JP3945003B2 - AGC circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an AGC circuit used for a radio receiver or the like.
[0002]
[Prior art]
The AGC circuit is provided in the radio receiver. The AGC circuit detects the level of the received signal and forms an AGC voltage, and the level of the received signal according to the AGC voltage. And a level control circuit to be controlled.
[0003]
FIG. 8 and FIG. 9 show examples of the level control circuit. In the circuit of FIG. 8, the level control circuit is constituted by a variable attenuator circuit. This circuit includes, for example, an antenna tuning circuit and a high frequency amplifier. Is provided on the signal line between the two. The signal from the antenna tuning circuit is divided by the resistor R1 and the emitter impedances of the transistors Q1 and Q2, and the emitter impedances of the transistors Q1 and Q2 are controlled by the AGC voltage. Therefore, the reception signal subjected to AGC is supplied to the next-stage high-frequency amplifier.
[0004]
In the circuit of FIG. 9, the level control circuit is configured by a variable gain amplifier (gain control amplifier), and this variable gain amplifier is used as an intermediate frequency amplifier. The intermediate frequency signal is supplied to the transistors Q5 to Q8 through the transistors Q3 and Q4. At this time, the ratio of the signal current supplied from the transistors Q3 and Q4 to the transistors Q5 and Q8 and the transistors Q6 and Q7 is AGC voltage. It depends on. Therefore, an intermediate frequency signal subjected to AGC is taken out from the transistors Q6 and Q7.
[0005]
[Problems to be solved by the invention]
However, in the circuit of FIG. 8, since the current-voltage characteristics of the emitter inputs of the transistors Q1 and Q2 are exponential functions, the linearity is poor and the signal level supplied to the transistors Q1 and Q2 needs to be several tens mV or less. . Therefore, the maximum allowable input level is small and the AGC control range cannot be widened.
[0006]
Also in the circuit of FIG. 9, the linearity of the differential amplifier formed by the transistors Q3 and Q4 is limited by the characteristics of the transistors Q3 and Q4. is there.
[0007]
For this reason, in some receivers, an attenuator circuit is configured by a resistor and a PIN diode for switching, and the attenuator circuit is provided in a signal line between the antenna tuning circuit and the high-frequency amplifier, and the PIN is manually operated. The signal level is switched by turning on and off the diode. That is, when receiving a broadcast near a broadcasting station, the radio wave is strong, so the attenuator circuit is switched effectively. When receiving a broadcast from a long-distance broadcasting station, the radio wave is weak, so the attenuator circuit is switched to invalid. It makes up for the characteristic.
[0008]
However, such a switching operation is complicated. Also, if the switching is mistaken or forgotten, the broadcast reception quality will be significantly deteriorated.
[0009]
Furthermore, when the circuit is made into an IC, the number of external parts increases. Further, it is not preferable in terms of uniform characteristics.
[0010]
The present invention is intended to solve such problems.
[0011]
[Means for Solving the Problems]
  For this reason, in the present invention,
  High frequency provided on the signal line between the tuning circuit and the mixer circuitAn amplifier,
  For intermediate frequency amplification provided after the mixer circuitAn amplifier,
  Based on the intermediate frequency signal obtained from this amplifier for intermediate frequency amplificationA circuit for forming an AGC voltage;
  AGC voltage magnitudeWhen the value is less than the predetermined value, the first level is obtained.A circuit for forming a switching control signal;
  A circuit for forming a combined signal of the AGC voltage and the switching control signal;
Have
  The high frequency amplifier
The first differential amplifier is configured by connecting the emitters of the first and second transistors to the first constant current source,
The emitters of the third and fourth transistors are connected to the second constant current source to form a second differential amplifier,
The bases of the first and third transistors are commonly connected to the tuning circuit through first and second resistors;
The collectors of the first and third transistors and the collectors of the second and fourth transistors are connected to a load;
By connecting this load to the mixer circuit through an output transistor,
An output having a phase opposite to the base inputs of the first and third transistors is supplied to the mixer circuit, and
Between the input terminal of the mixer circuit and the bases of the first and third transistors,
Third and fourth resistors for negative feedback are connected,
The resistance ratio between the first resistor and the third resistor is set to a value that reduces the gain of the high-frequency amplifier.
The resistance ratio between the second resistor and the fourth resistor is such that the gain of the high-frequency amplifier is larger than the resistance ratio between the first resistor and the third resistor. Set to the value
The intermediate frequency amplifying amplifier is configured to continuously change its gain,
When the switching control signal is at the first level by the switching control signal,
When the first constant current source is turned off, the second constant current source is turned on, and when the switching control signal is at the second level, the first constant current source is turned on. And turning on and off the first and second constant current sources so that the second constant current source is turned off.
  By the above composite signalFor intermediate frequency amplificationControl the gain of the amplifier
  AGC circuit
It is what.
  Therefore, the total gain of the front-stage amplifier and the rear-stage amplifier continuously changes depending on the AGC voltage.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
In FIG. 1, a reception signal SRX having a target frequency is extracted from the antenna tuning circuit 11, and this signal SRX is supplied to the mixer circuit 13 through the high-frequency amplifier 12 and a local oscillation signal having a predetermined frequency is supplied from the local oscillation circuit 14. Is supplied to the mixer circuit 13, and the signal SRX from the amplifier 12 is frequency-converted to an intermediate frequency signal SIF having a predetermined frequency. Then, the signal SIF is supplied to the AM detection circuit 17 through the intermediate frequency filter 15 and the intermediate frequency amplification amplifier 16 to be AM detected in the audio signal, and this audio signal is taken out to the terminal 18.
[0013]
Further, the AGC circuit 20 is configured as follows. That is, the high frequency amplifier 12 is a gain switching amplifier capable of switching the gain G12 in two stages, and the amplifier 16 is a variable gain amplifier capable of continuously changing the gain G16.
[0014]
The detection output of the detection circuit 17 is supplied to the low-pass filter 21 to form a DC voltage Va having a level corresponding to the level of the intermediate frequency signal SIF, that is, the AGC voltage Va, and this AGC voltage Va is supplied to the voltage comparison circuit 24. For example, as shown in FIG. 2A, a comparison output voltage V24 that is “L” when Va <VTH and “H” when Va ≧ VTH is extracted.
[0015]
The output voltage V24 is supplied to the high-frequency amplifier 12 as a switching signal for the gain G12. As shown in FIG. 2B, the gain G12 of the amplifier 12 is set to the gain GHI when V24 = "L", and V24 = "H". "", The gain GLW = (GHI−ΔG), which is smaller than the gain GHI by a predetermined value ΔG.
[0016]
Further, the AGC voltage Va from the low-pass filter 21 is supplied to the subtraction circuit 23 through the amplifier 22, and the output voltage V24 of the comparison circuit 24 is supplied to the subtraction circuit 23. From the subtraction circuit 23, a solid line is shown in FIG. 2C. like,
V23 = Va -k · V24
k: Subtraction ratio between the voltage Va and the voltage V24 in the subtraction circuit 23
Is output, and this output voltage V23 is supplied to the amplifier 16 as a control signal for gain G16. In this case, it is assumed that the gain G16 of the variable gain amplifier 16 decreases as the voltage V23 increases.
[0017]
According to such a configuration, the AGC voltage Va increases as the broadcast reception level increases. In the range Va <VTH, the gain G16 of the variable gain amplifier 16 increases as the AGC voltage Va increases. As shown by the solid line in 2D, it gets smaller.
[0018]
When Va = VTH, V24 = “H”, so G12 = GLW, and the gain G12 of the high-frequency amplifier 12 decreases by the value ΔG. However, at this time, since the voltage V23 is lowered by the value ΔV (the value ΔV is a difference voltage between the “H” level and the “L” level of the voltage V24), the gain G16 of the amplifier 16 is indicated by a solid line in FIG. 2D. Thus, the value ΔG increases from the previous value corresponding to k · ΔV.
[0019]
However, within the range of Va> VTH, the gain G16 of the variable gain amplifier 16 decreases as the AGC voltage Va increases, as shown by the solid line in FIG. 2D.
[0020]
Therefore, the decrease ΔG of the gain G12 in the high frequency amplifier 12 is compensated by the increase ΔG of the gain G16 of the amplifier 16, and the total gain G10 from the input terminal of the high frequency amplifier 12 to the output terminal of the variable gain amplifier 16 is compensated. Changes continuously from when the AGC voltage Va is small to when it is large as shown by the broken line in FIG. 2D (however, in FIG. 2D, in order to make the relationship between the gains G16 and G10 easy to understand, GHL = 0 dB).
[0021]
That is, with respect to the AGC voltage Va, the gain G12 of the high frequency amplifier 12 is switched as shown in FIG. 2A, and the gain G16 of the variable gain amplifier 16 is changed as shown by a solid line in FIG. 2D continuously changes as indicated by a broken line.
[0022]
In this way, according to the AGC circuit 20 of FIG. 1, AGC is performed, but the high-frequency amplifier 12 can appropriately process even a large level received signal because the gain G12 is only switched to two stages. . Further, as apparent from FIG. 2C, the control range of AGC can be widened corresponding to the value ΔG, compared to the case where only the variable gain amplifier 16 is provided.
[0023]
Further, the high-frequency amplifier 12 only needs to switch the gain G12 to two stages, and the control range of the gain G16 of the variable gain amplifier 16 is also reduced by a magnitude corresponding to the change width ΔG of the gain G12. AGC can be performed over a wide range.
[0024]
Furthermore, as will be described later, the high-frequency amplifier 12 and the gain control amplifier 16 can be configured by only transistors without using special elements such as FETs or PIN diodes, which is advantageous for IC implementation.
[0025]
Further, as shown in FIG. 3A, if a hysteresis characteristic is given to the voltage V24, the gains G12 and G16 of the gain switching amplifier 12 and the variable gain amplifier 16 are switched as shown in FIGS. 3B and C, and the switching becomes unstable. Never become.
[0026]
  4 shows a specific example of the amplifier 22 and the subtraction circuit 23, FIG. 5 shows a specific example of the voltage comparison circuit 24, and the symbols * 1 to * 5 in FIG. 4 are connected to the symbols * 1 to * 5 in FIG. The In these figures, the bias voltage V11 is converted into a constant current by the transistor Q11, and this current isPower lineIs supplied to the current mirror circuit 31 having the reference potential point as a reference potential point, and the transistor on the output side of the current mirror circuit 31 is used as a constant current source.
[0027]
In the voltage comparison circuit 24 of FIG. 5, the AGC voltage Va from the low pass filter 21 is supplied to the base of the transistor Q13 through the transistor Q12 of the emitter follower, and the transistor Q13 is connected to the transistor Q13 so that the differential amplifier is connected. 32 is configured. Transistors Q13 and Q14 are connected to transistors Q15 and Q16 constituting a current mirror circuit 33 as loads. The bias voltage V11 is divided by resistors R11 and R12 to form a reference voltage VTH, and this voltage VTH is supplied to the base of the transistor Q14 through the emitter-follower transistor Q17.
[0028]
Further, the collectors of the transistors Q13 and Q15 are connected to the base of the transistor Q18, the collector of the transistor Q18 is connected to the base of the transistor Q21 through the diode-connected transistor Q19, and the transistor Q21 is connected to the transistor Q22. The dynamic amplifier 33 is configured, and the collector of the transistor Q21 is connected to the base of the transistor Q14.
[0029]
Further, the base of the transistor Q21 is connected to the base of the transistor Q23, and the transistor Q23 is connected to the transistor Q23 to form a differential amplifier 34. The collector of the transistor Q23 is connected to the terminal T11 through the transistors Q25 and Q26 constituting the current mirror circuit 35, and the collector of the transistor Q24 is connected to the terminal T12 through the transistors Q27 and Q28 constituting the current mirror circuit 36.
[0030]
According to such a configuration, when Va = VTH, the collector current of the transistor Q13 and the collector current of the transistor Q15 have the same magnitude, so the current flowing into the base of the transistor Q18 is 0 and the transistor Q18 is off. is there. Therefore, the transistor Q21 is also off, and the differential amplifier 33 is not operating effectively with respect to the differential amplifier 32.
[0031]
When Va> VTH, the collector current of the transistor Q13 decreases, the collector current of the transistor Q14 increases, and the collector current of the transistor Q15 also increases. Therefore, the current flowing into the base of the transistor Q18 is still zero, and therefore The transistor Q21 is still off, and the differential amplifier 33 is still not operating effectively.
[0032]
However, when Va <VTH, the collector current of the transistor Q13 increases, the collector current of the transistor Q14 decreases, and the collector current of the transistor Q15 decreases, so that the collector current of the transistor Q13 flows into the base of the transistor Q18. As a result, the collector current of the transistor Q18 increases, the base potential of the transistor Q21 decreases, and the collector current increases, so the base current of the transistor Q14 decreases and the collector current also decreases.
[0033]
Therefore, although the collector current of the transistor Q13 increases, this is a positive feedback operation. As a result, the transistor Q13 is turned on and the transistor Q14 is turned off. At this time, the transistor Q21 is turned on.
[0034]
When the transistors Q13 to Q22 are on / off controlled by the AGC voltage Va as described above, the transistor Q23 is controlled similarly to the transistor Q21 by the collector output of the transistor Q18.
[0035]
Therefore, when Va ≧ VTH, the transistor Q23 is turned off and the transistor Q24 is turned on, so that the transistors Q25 and Q26 are turned off and the transistors Q27 and Q28 are turned on. When Va <VTH, the transistor Q23 is turned on and the transistor Q24 is turned off, so that the transistors Q25 and Q26 are turned on and the transistors Q27 and Q28 are turned off.
[0036]
Thus, the circuit of FIG. 5 operates as the voltage comparison circuit 24, and the terminals T11 and T12 have outputs that are turned on or off corresponding to the magnitude of the AGC voltage Va, that is, the gain G12 of the amplifier 12 in two stages. An output for switching (an output corresponding to the control voltage V24) is obtained.
[0037]
Further, in FIG. 4, the AGC voltage Va is supplied to the base of the transistor Q32 through the emitter-follower transistor Q31, and the transistor Q33 is connected to the transistor Q32 to constitute the differential amplifier 41. The transistors Q32 and Q33 are connected to the transistors Q34 and Q35 constituting the current mirror circuit 42 as loads, and the emitter voltage of the emitter-follower transistor Q36 is supplied to the transistor Q33 as a base bias voltage. Further, the collectors of the transistors Q33 and Q35 are connected to the bias power source V11 through a diode-connected transistor Q37.
[0038]
The collectors of the transistors Q33 and Q35 are connected to the bases of the transistors Q38 and Q39. Resistors R21 to R24 are connected to their emitters, and the voltage obtained at the voltage dividing point is supplied to the base of the transistor Q36. The collectors of the transistors Q38 and Q39 are connected to the terminals T21 and T22.
[0039]
Further, a differential amplifier 43 is constituted by the transistors Q41 and Q42. The base of transistor Q41 is connected to the base of transistor Q21, bias voltage V11 is supplied to the base of transistor Q42, and its collector is connected to the base of transistor Q36.
[0040]
According to such a configuration, when the AGC voltage Va becomes lower than the base potential of the transistor Q36 (approaching the ground potential), the collector current of the transistor Q32 decreases, the collector current of the transistor Q35 decreases, and the transistor Since the collector current of Q33 increases, the difference current between the collector current of transistor Q35 and the collector current of transistor Q33 flows from the bias power source V11 to the collector of transistor Q33 through transistor Q37.
[0041]
Conversely, when the AGC voltage Va becomes higher than the base potential of the transistor Q36, the collector current of the transistor Q32 increases, the collector current of the transistor Q35 increases, and the collector current of the transistor Q33 decreases. A difference current between the collector current and the collector current of the transistor Q3 flows from the collector of the transistor Q35 into the bias power source V11 through the transistor Q37.
[0042]
Since a voltage drop occurs in the transistor Q37 according to the current flowing therethrough, the base potentials of the transistors Q38 and Q39 change corresponding to the AGC voltage Va.
[0043]
However, at this time, as described above, the transistor Q21 is controlled to be turned on / off according to the magnitude of the AGC voltage Va, and the base of the transistor Q41 is connected to the base of the transistor Q21, so that the transistor Q41 is also the same as the transistor Q21. ON / OFF controlled. That is, the transistor Q41 is turned off when Va ≧ VTH, and turned on when Va <VTH.
[0044]
When the transistor Q41 is off, the transistor Q42 is on, so that the base current of the transistor Q36 becomes small corresponding to the collector current of the transistor Q42, and the collector current also becomes small. Conversely, when transistor Q41 is on, transistor Q42 is off, so that the base current of transistor Q36 increases and its collector current also increases.
[0045]
That is, the collector current of the transistor Q36 is switched between when Va ≧ VTH and when Va <VTH, and the collector current is larger when Va <VTH than when Va ≧ VTH.
[0046]
Therefore, when the base potentials of the transistors Q38 and Q39 change according to the AGC voltage Va as described above, the base potential changes in a sawtooth shape with Va = VTH as a boundary. When current flows, the collector current changes in a sawtooth shape with Va = VTH as a boundary.
[0047]
Thus, in the circuit of FIG. 4, the AGC voltage Va and the control voltage V24 are combined, and the output current that changes in a sawtooth shape corresponding to the magnitude of the AGC voltage Va at the terminals T21 and T22, that is, the amplifier 16 As shown in FIG. 2C, an output (an output corresponding to the control voltage V23) is obtained.
[0048]
  FIG.In this inventionThe gain switching amplifier 12One caseIndicates. That is, the differential amplifier 51 is configured by connecting the emitters of the transistors Q51 and Q52 to the collector of the transistor Q28 through the terminal T12, and the emitters of the transistors Q53 and Q54 are connected to the collector of the transistor Q26 through the terminal T11. Is configured. The output signal SRX of the tuning circuit 11 is supplied as an input signal to the differential amplifiers 51 and 52 through the resistors R51 and R53, and the differential amplifiers 51 and 52 are configured by transistors Q55 and Q56. The current mirror circuit 53 thus connected is connected as a common load.
[0049]
The collectors of the transistors Q51, Q53, and Q55 are connected to the bases of the SEPP-connected transistors Q57 and Q58, and the collectors of these transistors Q57 and Q58 are connected to the mixer circuit 13. The collectors of the transistors Q57 and Q58 are connected to the bases of the transistors Q51 and Q53 through resistors R52 and R54.
[0050]
According to such a configuration, when Va ≧ VTH, the transistor Q26 is off and the transistor Q28 is on, so that the differential amplifier 51 is in an operating state and the differential amplifier 52 is in an inoperative state. SRX is supplied to the transistors Q57 and Q58 through the differential amplifier 51 and the current mirror circuit 53, and is further supplied to the mixer circuit 13. Therefore, this circuit acts as an amplifier, and at this time, negative feedback is applied through the resistor R52, and the gain G12 of the amplifier 12 is obtained by the resistors R51 and R52.
G12 = R52 / R51 [times]
It becomes. For example, by setting R51 = R52, G12 = 1 times.
[0051]
When Va <VTH, the transistor Q26 is on and the transistor Q28 is off, so that the differential amplifier 51 is inactive and the differential amplifier 52 is in operation. The received signal SRX from the tuning circuit 11 is the differential amplifier 52. And supplied to the transistors Q57 and Q58 through the current mirror circuit 53 and further to the mixer circuit 13. Therefore, this circuit still acts as an amplifier, and at this time, negative feedback is applied through the resistor R54, and the gain G12 of the amplifier 12 is obtained by the resistors R53 and R54.
G12 = R54 / R53 [times]
It becomes. For example, by setting R54 = 10 · R53, G12 = 10 times.
[0052]
Therefore, the amplifier 12 operates as a gain switching amplifier in which the gain G12 is switched in two stages corresponding to the magnitude of the AGC voltage Va. In this case, since the gain switching amplifier 12 is based on a negative feedback amplifier, a large dynamic range can be achieved with low noise.
[0053]
In addition, the gain switching amplifier 12 does not require a special element such as an FET or a PIN diode for switching the gain, and can be configured with only a transistor, which is advantageous for IC implementation.
[0054]
FIG. 7 shows a specific example of the gain control amplifier 16. In this example, the variable gain amplifier 16 includes a variable attenuator circuit 161 whose gain (attenuation amount) changes as the impedance of the diode changes, and gain Is configured by an amplifier 162 having a variable gain and an amplifier 163 having a fixed gain.
[0055]
That is, the intermediate frequency signal SIF is extracted from the intermediate frequency filter 15 in opposite phases, and these signals SIF are supplied to the bases of the transistors Q71 and Q72 through the signal lines 61 and 62 having resistors R61 and R62, and the signal Between the lines 61 and 62, diode-connected transistors Q61 and Q62 are connected in series.
Reference sign V61 is a bias voltage.
[0056]
Transistors Q63 to Q65 having a power supply line as a reference potential point are provided, their bases are connected to the collector of the transistor Q39 through the terminal T22, and the collectors of the transistors Q64 and Q65 are connected to the signal lines 61 and 62. Further, the transistors Q66 to Q67 constitute a current mirror circuit 63 having the ground as a reference potential point, the collector of the transistor Q66 on the input side is connected to the collector of the transistor Q63, and the collector of the transistor Q67 on the output side is the transistor Q61. , Q62 is connected to the midpoint of connection.
[0057]
As described above, the collector current of the transistor Q39 changes according to the AGC voltage Va. When the collector current increases, the collector currents of the transistors Q64 and Q65 increase and the collector current of the transistor Q63 increases. Since the collector current of the transistor Q67 increases, the current flowing through the transistors Q61 and Q62 increases and the impedance decreases. If the impedance of the transistors Q61 and Q62 is reduced, the intermediate frequency signal SIF is canceled through the transistors Q61 and Q62 when the intermediate frequency signal SIF is supplied from the intermediate frequency filter 15 to the transistors Q71 and Q72 through the signal lines 61 and 62. Actually, the level of the intermediate frequency signal SIF supplied to the transistors Q71 and Q72 becomes small.
[0058]
Conversely, when the collector current of transistor Q39 decreases, the collector currents of transistors Q64 and Q65 decrease and the collector current of transistor Q63 decreases and the collector current of transistor Q67 decreases. The flowing current also decreases and its impedance increases. If the impedances of the transistors Q61 and Q62 are increased, the intermediate frequency signal SIF is not canceled through the transistors Q61 and Q62, so that the level of the intermediate frequency signal SIF supplied to the transistors Q71 and Q72 is increased.
[0059]
At this time, the magnitude of the collector current flowing out from the transistors Q64 and Q65 and the magnitude of the collector current flowing into the transistor Q67 are made equal so that the DC currents of the signal lines 61 and 62 can be changed even if these collector currents change. The order is fixed.
[0060]
Thus, the transistors Q61 to Q67 operate as a variable attenuator circuit 161 whose attenuation changes in accordance with the collector current of the transistor Q39, that is, the AGC voltage Va. The frequency signal SIF is supplied.
[0061]
The emitters of the transistors Q71 and Q72 are connected to the collectors of transistors Q76 and Q85 that operate as constant current sources, as will be described later, to form a differential amplifier 71. The collector output of the transistors Q71 and Q72 passes through capacitors C71 and C72. , Supplied to the base of Q74. At this time, the transistors Q73 and Q74 also have their emitters connected to the collectors of the transistors Q77 and Q86 that operate as constant current sources to form a differential amplifier 72, and the collector output is an amplifier 163 having a fixed gain. To be supplied.
[0062]
Further, a current mirror circuit 73 having the ground as a reference potential point is constituted by transistors Q75 to Q77. The bias voltage V61 causes a constant collector current to flow through the transistor Q75, and the transistors Q76 and Q77 are used as constant current sources for the differential amplifiers 71 and 72 as described above.
[0063]
A constant collector current is caused to flow through transistor Q81 by bias voltage V61, and this collector current is supplied to transistor Q82. This transistor Q82, together with the transistor Q83, constitutes a current mirror circuit 74 with the power supply line as a reference potential point, and the collector current of the transistor Q83 is supplied to the transistor Q84.
[0064]
The transistor Q84, together with the transistors Q85 to Q87, constitutes a current mirror circuit 75 with the ground as a reference potential point. Therefore, the transistors Q85 and Q86 are connected to the differential amplifiers 71 and 72 as described above. A constant current source.
[0065]
Further, at this time, the transistors Q88 and Q89 constitute a current mirror circuit 76 with the power supply line as a reference potential point. The collector current of the transistor Q38 is supplied to the input side transistor Q88 through the terminal T21, and the output side transistor Q89 The collector is connected to the base of transistor Q83.
[0066]
Accordingly, the intermediate frequency signal SIF from the signal lines 61 and 62 is sequentially amplified by the differential amplifiers 71 and 72, further amplified by the amplifier 163, and then supplied to the detection circuit 17.
[0067]
At this time, the collector current of the transistor Q38 changes according to the AGC voltage Va as described above. When this collector current increases, the collector current of the transistor Q88 increases and the impedance of the transistor Q89 decreases. The base current supplied to transistor Q83 by transistor Q82 is reduced. When the base current of the transistor Q83 is reduced, the collector current is reduced and the collector currents of the transistors Q76 and Q77 are also reduced, so that the gains of the differential amplifiers 71 and 72 are reduced.
[0068]
Conversely, when the collector current of transistor Q38 decreases, the collector current of transistor Q88 decreases and the impedance of transistor Q89 increases, so the base current supplied to transistor Q83 by transistor Q82 increases. When the base current of the transistor Q83 is increased, the collector current is increased and the collector currents of the transistors Q76 and Q77 are also increased, so that the gains of the differential amplifiers 71 and 72 are increased.
[0069]
Accordingly, the differential amplifiers 71 and 72 operate as a variable gain amplifier 162 whose gain changes according to the collector current of the transistor Q38, that is, the AGC voltage Va, and the amplifier 163 has an intermediate frequency whose level is controlled by the AGC voltage Va. The signal SIF will be supplied. Therefore, the circuit of FIG. 7 operates as the variable gain amplifier 16 that performs double gain control by the variable attenuation circuit 161 and the variable gain amplifier 162.
[0070]
The variable gain amplifier 16 does not require a special element such as an FET or a PIN diode for gain control, and can be configured with only a transistor.
[0071]
In the above description, the circuits 22 to 24 and the circuits 12 to 17 can be integrated into one chip. Further, depending on the polarities of the AGC voltage Va and the comparison output voltage V24, the voltages Va and V24 are synthesized by using the subtracting circuit 23 as an adding circuit.
[0072]
【The invention's effect】
According to the present invention, for example, a high-frequency amplifier can appropriately process even a high level received signal. Furthermore, the control range of AGC can be widened compared to the case where only the variable gain amplifier is used. In addition, AGC can be performed over a wide range with low noise. Furthermore, a special element such as an FET or a PIN diode is not required for AGC, and it can be configured with only a transistor, which is advantageous for IC.
[Brief description of the drawings]
FIG. 1 is a system diagram showing an embodiment of the present invention.
FIG. 2 is a waveform diagram for explaining the present invention.
FIG. 3 is a waveform diagram for explaining the present invention.
FIG. 4 is a connection diagram showing one embodiment of a part of the present invention.
FIG. 5 is a connection diagram showing one embodiment of a part of the present invention.
FIG. 6 is a connection diagram showing one embodiment of a part of the present invention.
FIG. 7 is a connection diagram showing one embodiment of a part of the present invention.
FIG. 8 is a connection diagram for explaining the present invention.
FIG. 9 is a connection diagram for explaining the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 ... Antenna tuning circuit, 12 ... High frequency amplifier, 13 ... Mixer circuit, 14 ... Local oscillation circuit, 15 ... Intermediate frequency filter, 16 ... Amplifier, 17 ... AM detection circuit, 20 ... AGC circuit, 21 ... Low pass filter, 22 ... Amplifier, 23 ... subtraction circuit, 24 ... voltage comparison circuit

Claims (1)

A high-frequency amplifier provided in a signal line between the tuning circuit and the mixer circuit ;
An intermediate frequency amplifying amplifier provided in a subsequent stage of the mixer circuit ;
A circuit for forming an AGC voltage based on an intermediate frequency signal obtained from the intermediate frequency amplifier ;
A circuit that forms a switching control signal that is a first level when the magnitude of the AGC voltage is less than a predetermined value, and that is a second level when the magnitude is greater than or equal to the predetermined value ;
A circuit for forming a combined signal of the AGC voltage and the switching control signal;
The high frequency amplifier
The first differential amplifier is configured by connecting the emitters of the first and second transistors to the first constant current source,
The emitters of the third and fourth transistors are connected to the second constant current source to form a second differential amplifier,
The bases of the first and third transistors are commonly connected to the tuning circuit through first and second resistors;
The collectors of the first and third transistors and the collectors of the second and fourth transistors are connected to a load;
By connecting this load to the mixer circuit through an output transistor,
An output having a phase opposite to the base inputs of the first and third transistors is supplied to the mixer circuit, and
Between the input terminal of the mixer circuit and the bases of the first and third transistors,
Third and fourth resistors for negative feedback are connected,
The resistance ratio between the first resistor and the third resistor is set to a value that reduces the gain of the high-frequency amplifier.
The resistance ratio between the second resistor and the fourth resistor is such that the gain of the high-frequency amplifier is larger than the resistance ratio between the first resistor and the third resistor. Set to the value
The intermediate frequency amplifying amplifier is configured to continuously change its gain,
When the switching control signal is at the first level by the switching control signal,
When the first constant current source is turned off, the second constant current source is turned on, and when the switching control signal is at the second level, the first constant current source is turned on. And turning on and off the first and second constant current sources so that the second constant current source is turned off.
An AGC circuit that controls the gain of the intermediate frequency amplifier by the synthesized signal.

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