JP3940409B2 - Memory controller, flash memory system, and control method - Google Patents

Description

  The present invention relates to a memory controller, a flash memory system, and a control method for controlling a data exchange operation between a host system and a flash memory.

  In recent years, flash memories have been widely adopted as semiconductor memories used in memory systems such as memory cards and silicon disks. A flash memory is a kind of nonvolatile memory. Data stored in the flash memory is required to be retained even when power is not supplied.

  A NAND flash memory is a type of flash memory that is particularly frequently used in the above memory system. Each of the plurality of memory cells included in the NAND flash memory receives a logical value “0” from an erased state in which data indicating a logical value “1” is stored, independently of the other memory cells. It is possible to change to a writing state in which the indicated data is stored.

  In contrast, when at least one of the plurality of memory cells must change from a written state to an erased state, each memory cell cannot change independently of the other memory cells. At this time, in a predetermined number of memory cells called blocks, all the memory cells must be simultaneously erased. This batch erase operation is generally called “block erase”. A block that has been subjected to block erase is referred to as an erased block.

  Due to the above characteristics, data cannot be overwritten in the NAND flash memory. In order to rewrite the stored data in the memory cell, after the block data including the new data is written into the erased block, the block erasure for the block storing the old data must be performed.

  The rewritten data is written in a block different from the previously stored block. Therefore, the correspondence between the logical block address specified by the address signal supplied from the host system and the physical block address indicating the actual block address in the flash memory is the same every time data is rewritten in the flash memory. Dynamically adjusted by the controller. For example, the correspondence between logical block addresses and physical block addresses is described in an address conversion table provided in the controller.

  When the correspondence between the logical block address and the physical block address is described in the address conversion table for all the blocks included in the flash memory, a large size address conversion table corresponding to the flash memory having a large data capacity is provided. Needed. In order to create a large size address translation table, large system resources and long processing time are consumed.

  In order to solve this problem, Patent Document 1 described later discloses a technique for dividing the memory space on the flash memory into a plurality of zones and creating an address conversion table for blocks allocated to each zone. ing. Further, Patent Document 2 discloses an address that prevents an increase in memory capacity required for using the address conversion table by copying a part of the address conversion table stored in the flash memory to a memory space on the RAM. A conversion method is disclosed.

  Furthermore, Patent Document 3 discloses a memory controller that can execute a series of data write operations in a flash memory in parallel. The memory controller disclosed in that document is designed to use a plurality of virtual blocks formed by virtually combining a plurality of physical blocks belonging to different groups.

In a flash memory having a memory space divided into a plurality of zones as disclosed in Patent Document 1, the existence of bad blocks should be considered in the allocation of each zone to the data area included in the host system. . In other words, it is preferable that the storage capacity of a zone allocated to a predetermined range of data area included in the host system is designed to be larger than the upper limit of data handled in the data area.
At this time, in each zone, at least one spare block (redundant block) is arranged so that the ratio of the spare block to the total number of blocks becomes a predetermined value.
JP 2000-284996 A JP 2002-73409 A JP 2003-15946 A

  However, when there are many bad blocks in a part of the flash memory, the bad blocks are concentrated in the zone to which the part is assigned. When the number of defective blocks included in one zone becomes larger than the number of preliminary blocks included in the zone, erased blocks cannot be secured and the operation stops.

  As described above, when many bad blocks are concentrated in a specific zone, there is a problem that data cannot be stored correctly even if the number of bad blocks in the entire flash memory does not exceed the allowable amount for normal operation. Sometimes.

  An object of the present invention is to suppress the occurrence of defects in a flash memory when there are many defective blocks in a part of the flash memory.

In order to achieve the above object, a memory controller of the present invention is a memory controller that controls access to a flash memory in which stored data is erased in units of physical blocks based on an address given from a host system.
Initial setting means for assigning a virtual block address to a physical block address attached to a physical block in the flash memory;
Logical zone forming means for forming a logical zone composed of areas of a plurality of blocks to which logical block addresses in the address space on the host system side are assigned;
Virtual zone forming means for forming a virtual zone composed of areas of a plurality of blocks to which the continuous virtual block addresses are assigned;
Zone management means for managing the correspondence between the logical zone and the virtual zone;
Address management means for managing a correspondence relationship between the logical block address included in the logical zone and the virtual block address included in the virtual zone corresponding to the logical zone;
Address conversion means for converting the virtual block address to the physical block address assigned to the virtual block address according to the assignment set by the initial setting means,
The initial setting means assigns the virtual block address to the physical block address so that the number of defective physical blocks assigned to each virtual zone is equalized .

For example, it comprises table storage means for storing a plurality of tables describing assignment of the virtual block addresses to the physical block addresses, and the initial setting means selects one table from the plurality of tables The address converting unit converts the virtual block address into the physical block address using the table selected by the initial setting unit .

  Function storage means storing a plurality of functions for generating a one-to-one mapping is arranged, the initial setting means selects one function from the plurality of functions, and the address conversion means The virtual block address may be converted into the physical block address using the function selected by the initial setting means.

For example, the address converting unit converts the virtual block address to the physical block address using a mapping function having a periodicity for generating a one-to-one mapping, and the initial setting unit is configured such that the address converting unit includes the mapping unit. The number of conversions when the virtual block address is converted into the physical block address using a function is set .

The mapping function is, for example, a mapping function that generates a tent map . For example, when the circulation cycle of the mapping function for generating the tent mapping is T and the number of physical blocks in the flash memory to which the virtual block address is assigned is N, T and N are
The relationship of N = 2 ^(T-1) is satisfied .

A flash memory system according to the present invention includes the above-described memory controller and a flash memory in which stored data is erased in units of physical blocks.

  The control method of the flash memory of the present invention is:
  A flash memory control method for controlling access to a flash memory in which stored data is erased in units of physical blocks based on an address given from a host system,
  An initial setting step of assigning a virtual block address to a physical block address attached to a physical block in the flash memory;
  An operation step of obtaining a logical block address corresponding to the access target area based on an address given from the host system;
  In accordance with the correspondence relationship between a logical zone composed of a plurality of block areas to which the logical block address is allocated and a virtual zone composed of a plurality of block areas to which the continuous virtual block address is allocated, A first conversion step of converting the logical block address included in the zone into the virtual block address included in the virtual zone corresponding to the logical zone;
  A second conversion step of converting the virtual block address to a physical block address assigned to the virtual block address according to the assignment set in the initial setting step;
  In the initial setting step, the virtual block address is allocated to the physical block address so that the number of defective physical blocks allocated to each virtual zone is equalized.

  For example, in the initial setting step, one table is selected from a plurality of tables describing assignment of the virtual block address to the physical block address, and in the second conversion step, the initial setting step The virtual block address is converted into the physical block address using the selected table.

  For example, in the initial setting step, one function is selected from a plurality of functions that generate a one-to-one mapping, and in the second conversion step, the function selected in the initial setting step is selected. Used to convert the virtual block address to the physical block address.

  For example, in the second conversion step, the virtual block address is converted into the physical block address using a mapping function having a periodicity for generating a one-to-one mapping, and in the initial setting step, the second conversion step is performed. In the conversion step, the number of conversions when the virtual block address is converted into the physical block address using the mapping function is set.

  For example, the mapping function is a mapping function that generates a tent map. For example, when the circulation cycle of the mapping function for generating the tent mapping is T and the number of physical blocks in the flash memory to which the virtual block address is assigned is N, T and N are N = 2 ^(T-1)   Satisfy the relationship.

  According to the present invention, when there are many defective blocks in a part of the flash memory, it is possible to suppress the occurrence of problems in the flash memory.

FIG. 1 is a block diagram schematically showing a flash memory system 1 according to the present invention.
The flash memory system 1 includes a flash memory 2 and a controller 3. The flash memory system 1 can be attached to a memory interface included in the host system 4.

  By attaching the flash memory system 1 to the host system 4, the host system 4 can operate the flash memory system 1 as an external storage device.

  The host system 4 may be a personal computer for processing various information such as character information, voice information, or image information, an information processing system represented by a digital camera, or the like. For example, the host system 4 may include a main processor such as a CPU (Central Processing Unit).

  The flash memory 2 shown in FIG. 1 is a nonvolatile memory. In the flash memory 2, both the data read operation and the data write operation are performed in so-called page units. On the other hand, the data stored in the flash memory 2 is erased in so-called block units. For example, one block includes 32 pages. One page includes a 512-byte user area 25 (shown in FIG. 4) and a 16-byte redundant area 26 (shown in FIG. 4).

  In FIG. 1, the controller 3 includes a host interface control block 5, a microprocessor 6, a host interface block 7, a work area 8, a buffer 9, a flash memory interface block 10, an ECC block 11, and a flash sequencer block. 12. For example, the controller 3 is integrated on one semiconductor chip. Below, the function of each part of the controller 3 will be described.

  The host interface control block 5 is a functional block for controlling the operation of the host interface block 7. The host interface control block 5 has a plurality of registers (not shown). The host interface control block 5 controls the operation of the host interface block 7 based on information set in each register.

The microprocessor 6 is a functional block for controlling the operation of the entire controller 3.
The host interface block 7 is a functional block for exchanging information indicating data, addresses, statuses, external commands and the like with the host system 4 under the control of the microprocessor 6. When the flash memory system 1 is mounted on the host system 4, the flash memory system 1 and the host system 4 are connected to each other via the external bus 13. Information supplied from the host system 4 to the flash memory system 1 is taken into the controller 3 through the host interface block 7. Information supplied from the flash memory system 1 to the host system 4 is output to the host system 4 through the host interface block 7.

  The work area 8 is a memory module for temporarily storing data used for controlling the flash memory 2. For example, the work area 8 includes a plurality of SRAM (Static Random Access Memory) cells.

  The buffer 9 is a functional block for holding data read from the flash memory 2 and data to be written to the flash memory 2. Data read from the flash memory 2 is held in the buffer 9 until it is output to the host system 4. Data to be written to the flash memory 2 is held in the buffer 9 until the data write operation of the flash memory 2 is ready.

The flash memory interface block 10 is a functional block for exchanging information indicating data, address, status, internal command and the like with the flash memory 2 via the internal bus 14.
The internal command is a command given from the controller 3 to the flash memory 2 and is distinguished from an external command given from the host system 4 to the flash memory system 1.

  The ECC block 11 is a functional block for generating an error correction code to be added to write data to the flash memory 2. In addition, the ECC block 11 detects and corrects an error included in the read data based on an error correction code included in the data read from the flash memory 2.

  The flash sequencer block 12 is a functional block for controlling the operation of the flash memory 2 based on an internal command. The flash sequencer block 12 has a plurality of registers (not shown). The flash sequencer block 12 sets information used when an internal command is executed in a plurality of registers under the control of the microprocessor 6. After setting information in a plurality of registers, the flash sequencer block 12 performs an operation according to an internal command based on the information set in each register. In addition, the flash sequencer block 12 executes a distributed process for distributing a plurality of blocks allocated to one block in the flash memory 2.

  The structure of the memory cell 16 included in the flash memory 2 will be described below with reference to FIGS. 2 and 3 are cross-sectional views schematically showing the structure of one memory cell 16 included in the flash memory 2. In FIG. 2, no data is written in the memory cell 16. In FIG. 3, data is written in the memory cell 16.

  As shown in FIGS. 2 and 3, the memory cell 16 includes a P-type semiconductor substrate 17, an N-type source diffusion region 18, an N-type drain diffusion region 19, a tunnel oxide film 20, and a floating gate electrode. 21, an insulating film 22, and a control gate electrode 23.

  Both the source diffusion region 18 and the drain diffusion region 19 are formed on the P-type semiconductor substrate 17. The tunnel oxide film 20 covers the P-type semiconductor substrate 17 between the source diffusion region 18 and the drain diffusion region 19. The floating gate electrode 21 is formed on the tunnel oxide film 20. The insulating film 22 is formed on the floating gate electrode 21. The control gate electrode 23 is formed on the insulating film 22. In the flash memory 2, a plurality of memory cells 16 are connected in series. One memory cell 16 stores 1-bit data.

  As shown in FIG. 2, when no electrons are stored in the floating gate electrode 21, the memory cell 16 is in an erased state. On the other hand, when electrons are accumulated in the floating gate electrode 21, the memory cell 16 is in a write state. The memory cell 16 in the erased state stores data indicating a logical value “1”. The memory cell 16 in the written state stores data indicating a logical value “0”.

  When a predetermined read voltage for reading data stored in the memory cell 16 is not applied to the control gate electrode 23 of the memory cell 16 in the erased state, the source diffusion region 18 and the drain diffusion region 19 No channel is formed on the surface of the P-type semiconductor substrate 17 between the two. Accordingly, the source diffusion region 18 and the drain diffusion region 19 are electrically insulated from each other.

  On the other hand, when a read voltage is applied to the control gate electrode 23 of the memory cell 16 in the erased state, the surface of the P-type semiconductor substrate 17 between the source diffusion region 18 and the drain diffusion region 19 is applied. A channel (not shown) is formed. The source diffusion region 18 and the drain diffusion region 19 are electrically connected by the channel.

  As described above, when the read voltage is not applied to the control gate electrode 23 of the memory cell 16 in the erased state, the source diffusion region 18 and the drain diffusion region 19 are electrically insulated. When a read voltage is applied to the control gate electrode 23 of the memory cell 16 in the erased state, the source diffusion region 18 and the drain diffusion region 19 are electrically connected.

  As shown in FIG. 3, when electrons are accumulated in the floating gate electrode 21, the memory cell 16 is in a write state. The floating gate electrode 21 is sandwiched between the tunnel oxide film 20 and the insulating film 22. For this reason, once electrons are injected into the floating gate electrode 21, the electrons remain in the floating gate electrode 21 for a very long time due to the potential barrier.

  In the memory cell 16 which is in the write state by accumulating electrons in the floating gate electrode 21, the channel 24 is connected to the source diffusion region 18 and the drain regardless of whether or not the read voltage is applied to the control gate electrode 23. It is formed on the surface of P-type semiconductor substrate 17 between diffusion region 19. Therefore, when the memory cell 16 is in the write state, the source diffusion region 18 and the drain diffusion region 19 are electrically connected regardless of whether or not the read voltage is applied to the control gate electrode 23.

A data read operation for specifying whether memory cell 16 is in the erased state or the written state will be described below. In the flash memory 2, a plurality of memory cells 16 are connected in series. One of the plurality of memory cells 16 is selected by the controller 3 for reading stored data.
A predetermined low level voltage is applied to the control gate electrode 23 attached to the selected one memory cell 16. A predetermined high level voltage (read voltage) higher than the low level voltage is applied to the control gate electrode 23 attached to the other one of the plurality of memory cells 16. In this situation, it is detected by a predetermined detector whether or not a series of memory cells 16 are conductive. When the detector detects conduction, the selected memory cell 16 is in the write state. When the detector detects non-conduction, the selected memory cell 16 is in the erased state.

As described above, the flash memory 2 is designed to read stored data indicating a logical value “0” or “1” from any one of a series of memory cells 16 connected in series. .
When the state of the memory cell 16 is changed between the erased state and the written state, an erase voltage or a write voltage larger than the voltage used in the data read operation of the memory cell 16 is used.

  When the memory cell 16 in the erased state is changed to the written state, the write voltage is applied to the control gate electrode 23 so that the potential of the control gate electrode 23 is higher than the potential of the floating gate electrode 21. . By this write voltage, an FN (Fowler-Nordhaim) tunnel current flows between the P-type semiconductor substrate 17 and the floating gate electrode 21 via the tunnel oxide film 20. As a result, electrons are injected into the floating gate electrode 21.

  On the other hand, when the memory cell 16 in the write state is changed to the erase state, an erase voltage is applied to the control gate electrode 23 so that the potential of the control gate electrode 23 is lower than the potential of the floating gate electrode 21. The With this erase voltage, electrons accumulated in the floating gate electrode 21 are discharged to the P-type semiconductor substrate 17 through the tunnel oxide film 20.

  Hereinafter, a structure for storing data in the flash memory 2 will be described. FIG. 4 schematically shows the address space of the flash memory 2. In the structure shown in FIG. 4, the address space of the flash memory 2 is divided based on “page” and “block”. A page is a processing unit in a data read operation and a data write operation performed in the flash memory 2. A block is a processing unit in a data erasing operation performed in the flash memory 2.

  One page includes a 512-byte user area 25 and a 16-byte redundant area 26. The user area 25 stores user data supplied from the host system 4. The redundant area 26 stores additional information indicating an error correction code (ECC), a corresponding logical block address, a block status, or the like. The error collection code is used to correct an error included in the data stored in the user area 25. When the number of errors included in the data stored in the user area 25 is equal to or less than a predetermined threshold, the errors can be corrected by an error correction code. At this time, the data read from the user area 25 is corrected to correct data by the error collection code.

  The corresponding logical block address indicates the address of the logical block with which the block is associated when valid data is stored in at least one user area 25 included in one block. The logical block address is a block address determined based on the host address given from the host system 4. On the other hand, the actual block address in the flash memory 2 is referred to as a physical block address.

  When no valid data is stored in all user areas 25 included in one block, the corresponding logical block address is not stored in the redundant area 26 included in the block. Therefore, by determining whether or not the corresponding logical block address is stored in the redundant area 26, it is possible to determine whether or not the data has been erased in the block including the redundant area 26. When the corresponding logical block address is not stored in the redundant area 26, the block including the redundant area 26 is in a state where data has been erased.

  The block status indicates whether each block is a bad block that cannot normally store data. For example, when a certain block is a bad block, a block status flag provided corresponding to the block is set to an on state.

  In the flash memory 2, the state of the memory cell 16 cannot change from the written state to the erased state in cell units, and the state change can be performed only in block units. Therefore, in order to store new data on a page, after block data including the new data is written to the erased block, block erasure for the block storing old data must be performed. Don't be. Since block erasure is executed in units of blocks, the stored data of all pages is erased in a block including a page in which old data has been stored. Therefore, when the stored data of a page is rewritten, a process for transferring the stored data of another page in the block including the page to the erased block is required.

  The block that stores new data to be rewritten is different from the block that stores old data. Accordingly, the correspondence between the logical block address specified by the address signal given from the host system 4 and the physical block address which is the actual block address in the flash memory 2 is as follows each time data is rewritten in the flash memory 2. It must be adjusted dynamically by the controller 3.

  Based on such a viewpoint, the controller 3 writes additional information indicating a logical block address (corresponding logical block address) in response to a data write operation to the user area 25 in the redundant area 26, so that the logical block address and the physical block Address correspondences can be managed.

  In the address space of the flash memory 2, a plurality of blocks are classified into one of a plurality of zones. An example of zone allocation in the flash memory 2 to the logical block address space in the host system 4 will be described below.

  In the example shown in FIG. 5, one zone has 1024 blocks # 0 to # 1023. Each of the blocks # 0 to # 1023 has 32 pages P00 to P31. A block is a processing unit in the data erasing operation. A page is a processing unit in a data read operation and a data write operation. The zones shown in FIG. 5 are allocated to a predetermined range of logical block address spaces in the host system 4.

For example, a zone including 1024 blocks is allocated to a logical block address space having a data capacity corresponding to 1000 blocks. In this example, the storage capacity in one zone is larger than the data capacity of the corresponding logical block address space by the amount of data corresponding to 24 blocks. In this allocation, bad blocks are taken into account. When the stored data is rewritten in the flash memory 2, one preliminary block for writing new data is required. Therefore, substantially 23 blocks are treated as surplus blocks in one zone.
The number of blocks included in one zone may be appropriately set based on the usage of the flash memory system 1 or the specifications of the flash memory 2.

Hereinafter, an example of classification of a plurality of blocks in each zone will be described. A plurality of blocks in the flash memory 2 can be classified into zones in the order of physical block addresses. However, in this case, many bad blocks may be classified into a specific zone due to the bad blocks being unevenly distributed in a part of the flash memory 2.
On the other hand, in the flash memory system 1 according to the present invention, a plurality of blocks included in one zone are distributed in the flash memory 2 in order to prevent bad blocks from being concentrated in a specific zone.

  FIG. 6 is a schematic diagram showing a process for classifying a plurality of blocks included in the flash memory 2 into one of a plurality of zones. In FIG. 6, the logical block address LBA given from the host system 4 is converted into a virtual block address VBA by the address conversion table 31. For example, the address conversion table 31 is stored in the work area 8 and is referred to by the host interface control block 5. The virtual block address VBA is associated with the physical block address PBA by the distributed processing unit 32. For example, the flash sequencer block 12 preferably functions as the distributed processing unit 32 shown in FIG. 6 by executing a predetermined program.

The virtual block address VBA is given by adding serial numbers attached to a plurality of blocks included in one zone to an offset value corresponding to the zone. In the example shown in FIG. 7, 1024 blocks are classified for each zone. Therefore, in one zone, serial numbers from “0” to “1023” are assigned to each block. The offset values corresponding to each zone are as follows.
Zone # 0: 0
Zone # 1: 1024x1,
Zone # 2: 1024 × 2,
. . . . . .
Zone #N: 1024 × N.

  In the virtual block address space, all the blocks in the flash memory 2 are arranged so that the virtual block address VBA increases by one. When the block serial number and the virtual block address VBA are in the form of bit data (binary data), the zone number (binary data) assigned to each zone is inserted into the higher order bits than the block serial number, A virtual block address VBA is given. When each of the zones # 0 to # 7 includes 1024 blocks, the serial number of the block is displayed by 10-bit data (from “00 0000 0000” to “11 1111 1111”).

  Three bits of data (from “000” to “111”) are allocated to the eight zones # 0 to # 7 as zone numbers. In this case, a 13-bit virtual block address VBA is created by inserting a zone number into bits higher than the block serial number. For example, the virtual block address VBA of the block having the serial number “16” (“00 0001 0000” in binary format) in the zone # 4 having the zone number “100” is “1 0000 0001 0000” in binary format. "Become. The distributed processing unit 32 refers to a function or table prepared in advance in order to associate the virtual block address VBA with the physical block address PBA.

  FIG. 7 shows the correlation among the logical block address LBA, the virtual block address VBA, and the physical block address PBA. In FIG. 7, each of a plurality of logical block address spaces divided every 1000 blocks is assigned to each of a plurality of zones # 0 to #N including 1024 blocks. The minimum value of the virtual block address in the zone #K is 1 larger than the maximum value of the virtual block address VBA in the zone # (K−1) (1 ≦ K ≦ N).

  By setting the virtual block address VBA, in the virtual block address space, any two adjacent zones among the zones # 0 to #N are connected via the virtual block address VBA. The virtual block address VBA is associated with the physical block address PBA by the distributed processing unit 32 according to the function or table setting prepared in advance. The function or table referred to by the distributed processing unit 32 only needs to be designed to classify a plurality of blocks having greatly different physical block addresses PBA into one of zones # 0 to # 7. As a result, a zone including 1024 blocks distributed in the flash memory 2 can be allocated to the logical block address space divided every 1000 blocks.

  Hereinafter, distributed processing executed by the distributed processing unit 32 will be described. The plurality of blocks distributed in the flash memory 2 are classified into one of the plurality of zones by executing the distributed processing. In this distributed processing, the distributed processing unit 32 associates the virtual block address VBA with the physical block address PBA. In order to execute the distributed processing, the distributed processing unit 32 uses an address register 33 and a processing setting register 34 as shown in FIG. For example, the address register 33 and the process setting register 34 may be included in the flash sequencer block 12.

  The virtual block address VBA is included in each of a plurality of virtual page addresses assigned to each of a plurality of pages in the virtual address space of the flash memory 2. The virtual page address includes a virtual block address VBA and a 5-bit page number. The 5-bit page number is used to identify each of the 32 pages included in one block. The address register 33 temporarily stores the virtual page address. The process setting register 34 stores information indicating the correspondence between the virtual block address VBA and the physical block address PBA.

The distribution processing unit 32 reads the virtual block address VBA included in the virtual page address stored in the address register 33 in order to generate the physical block address PBA. Then, the distributed processing unit 32 replaces the virtual block address VBA stored in the address register 33 with the physical block address PBA based on the information stored in the process setting register 34.
A physical page address is created by adding the page number included in the virtual page address stored in the address register 33 to the physical block address PBA generated by the distributed processing unit 32. The physical page address is provided to the memory space 35 of the flash memory 2.

FIG. 9 shows an operation for creating a physical page address based on the virtual page address stored in the address register 33.
The virtual page address shown in FIG. 9 is divided into lower 5-bit data indicating the page number and upper 13-bit data indicating the virtual block address VBA.

The distributed processing unit 32 replaces the upper 13-bit data indicating the virtual block address VBA with another 13-bit data indicating the physical block address PBA. In the example shown in FIG. 9, the upper 13-bit data included in the virtual page address indicates “0 0001 0001 0001” as the virtual block address VBA. “0 0001 0001 0001” is replaced by “1 1001 1001 1001” as the physical block address PBA by the distributed processing unit 32.
In the distributed processing executed by the distributed processing unit 32, bit data indicating the virtual block address VBA is replaced with bit data indicating the physical block address PBA, but 5-bit data indicating the page number is not changed. The number of bits indicating the virtual block address VBA in the virtual page address is determined corresponding to the number of blocks provided in the flash memory 2.

  The number of bits indicating the page number in the virtual page address is determined corresponding to the number of pages included in one block. For example, in the flash memory 2, when the memory space is divided into 8192 blocks and one block has 32 pages, the virtual block address VBA is identified by 13-bit data, The page number is identified by 5-bit data.

Next, processing for setting the correspondence between the virtual block address VBA and the physical block address PBA will be described.
FIG. 10 shows the correspondence between the virtual block address VBA and the physical block address PBA when the virtual block address VBA is directly assigned to the physical block address PBA.
In the example illustrated in FIG. 10, the distributed processing unit 32 does not execute the distributed processing. In this case, the physical block address PBA of each block in the flash memory 2 matches the virtual block address VBA.

  Accordingly, each of the zones # 0 to # 7 in the virtual address space is allocated to each of a plurality of physical areas in the flash memory 2 according to the physical block address PBA. In this case, for example, there are 30 memory areas composed of 1024 memory cells 16 allocated from “0 0100 0000 0000 (1024)” to “0 0111 1111 1111 (2047)” as physical block addresses PBA. When bad blocks are included, the 30 bad blocks are classified into zone # 1.

  In this case, there is no guarantee that all data provided to the logical block address space corresponding to zone # 1 in the host system 4 is correctly stored in the flash memory 2. When the bad block is excluded from the valid blocks used for storing data, there are not enough blocks to be used as valid blocks in the zone # 1.

  When a bad block is assigned to a part of the logical block address space, the data provided by the host system 4 to that part cannot be properly stored in the flash memory 2. The flash memory system 1 according to the present invention sets the correspondence relationship between the virtual block address VBA and the physical block address PBA so that the number of bad blocks classified into each of a plurality of zones is averaged.

  For example, the flash memory system 1 includes a plurality of replacement tables that describe the correspondence between the virtual block address VBA and the physical block address PBA. The plurality of replacement tables may be stored in advance in a ROM (Read Only Memory) that stores fixed data and programs in the controller 3. Alternatively, the plurality of replacement tables may be stored in advance in a predetermined storage area in the flash memory 2 and read by the controller 3.

  FIG. 11 shows an example of the replacement table. The replacement table associates the virtual block address VBA with the physical block address PBA. The flash memory system 1 selects one of the replacement tables that minimizes the maximum number of bad blocks classified in each zone in order to execute distributed processing.

  In order to select one of the plurality of replacement tables, the controller 3 detects all bad blocks in the flash memory 2, and the virtual block address corresponding to each bad block according to one of the replacement tables Specify the VBA. Subsequently, the controller 3 counts the number of defective blocks included in each zone based on the virtual block address VBA corresponding to the defective blocks. The controller 3 detects a replacement table that minimizes the maximum number of defective blocks classified into each zone by referring to the aggregation result corresponding to each replacement table.

  In order to specify the zone in which the bad block is classified, the controller 3 searches the replacement table for the physical block address PBA assigned to the bad block. When the physical block address PBA assigned to the bad block is detected, the virtual block address VBA associated with the physical block address PBA in the replacement table is read. The virtual block address VBA is assigned to one of a plurality of zones every 1024. Accordingly, one zone is specified corresponding to one virtual block address VBA assigned to one bad block.

For example, the bad block detected by the controller 3 has a physical block address PBA as shown in FIG.
In the list of bad blocks shown in FIG. 12, “0 0100 0000 0001”, which is written at the top as the physical block address PBA of the bad block, describes the physical block address PBA in the replacement table shown in FIG. In the above column, it is described eighth from the top. Therefore, “0 0000 0000 0111” is specified as the virtual block address VBA of the defective block corresponding to “0 0100 0000 0001” as the physical block address PBA by the replacement table shown in FIG. “0 0100 0000 0001” in the physical block address PBA is included in a virtual address range from “0 0000 0000 0000” to “0 0011 1111 1111” assigned to the zone # 0. As described above, it is specified that the defective block shown at the top in FIG. 12 is classified into zone # 0.

  When 8192 blocks in the flash memory 2 are classified into 8 zones as shown in FIG. 13, the total number of defective blocks classified in each of the zones # 0 to # 7 is represented by variables Nb0 to Nb7. Each is calculated. The maximum value among the variables Nb0 to Nb7 indicates the maximum number of defective blocks classified into each zone.

For example, each of the variables Nb0 to Nb7 is calculated as follows.
Nb0 = 5
Nb1 = 3
Nb2 = 8,
Nb3 = 2
Nb4 = 6
Nb5 = 4
Nb6 = 9,
Nb7 = 7.
In this case, the variable Nb6 indicating the number of defective blocks classified into the zone # 6 is the maximum value among the variables Nb0 to Nb7. Therefore, “9” indicated by the variable Nb6 is the maximum number of defective blocks classified into each zone.

  Corresponding to each of the plurality of replacement tables, after the maximum number of bad blocks classified into each zone is identified, one of the replacement tables that minimizes the maximum number is selected to perform the distributed processing. The For example, the flash memory system 1 has five replacement tables Tb1 to Tb5. The maximum value of the variables Nb0 to Nb7 calculated corresponding to the replacement table Tb1 is Nb3 = 9. The maximum value of the variables Nb0 to Nb7 calculated corresponding to the replacement table Tb2 is Nb6 = 8. The maximum value of the variables Nb0 to Nb7 calculated corresponding to the replacement table Tb3 is Nb7 = 10. The maximum value of the variables Nb0 to Nb7 calculated corresponding to the replacement table Tb4 is Nb0 = 15. The maximum value of the variables Nb0 to Nb7 calculated corresponding to the replacement table Tb5 is Nb4 = 6. In this case, the replacement table Tb5 is selected as a table that minimizes the maximum number of defective blocks.

  The replacement table selected to execute the distributed processing is specified by the information stored in the processing setting register 34 shown in FIG. The replacement table selected as described above is referred to by the distributed processing unit 32 in order to replace the virtual block address VBA with the physical block address PBA.

  The correspondence relationship between the virtual block address (VBA) and the physical block address (PBA) may be set by a predetermined function. In this case, in the flash memory system 1, the controller 3 stores in advance information defining a plurality of types of functions.

  The controller 3 selects a function that minimizes the maximum number of bad blocks classified into each zone. The function defined in the controller 3 is for performing a one-to-one mapping between the virtual block address space and the physical block address space. The zone into which each bad block is classified can be specified by an inverse function with respect to a function used in distributed processing by the distributed processing unit 32.

  The map generated by the function defined in the controller 3 preferably draws a periodic trajectory. In other words, it is desirable that the function defined in the controller 3 is for generating a mapping cycle. As an example of a map for forming a periodic orbit, a tent map may be used. The tent mapping is performed by using the function F (x) defined by the following equations (1) and (2).

When variable x is 0 ≦ x <2 ⁽ⁿ⁻¹⁾ F (x) = 2x (1)
When variable x is 2 ^(n-1) ≤x < ²ⁿ F (x) =-2x + 2 ^{(n + 1)} -1 (2)

  Serial numbers are assigned in order from 0 to the blocks to be distributed. In equations (1) and (2), the variable n is assigned the number of digits necessary to display the serial number assigned to the block in the form of a binary code. For example, when 8192 blocks are to be distributed, the maximum serial number “8191” assigned to the block is “1 1111 1111 1111” in binary code format. At this time, “13” is assigned to the variable n.

The function value obtained by executing the conversion using the function F (x) represented by the equations (1) and (2) n + 1 times coincides with the original value. In other words, the mapping by the function F (x) shown in equations (1) and (2) has a circulation period T = n + 1. For example, when “4” is assigned to the variable n and “1” is assigned to the variable x as the original value, the function value obtained by executing the conversion using the function F (x) five times. Matches the original value “1” as follows:
F (1) = 2 × 1 = 2
F (2) = 2 × 2 = 4
F (4) = 2 × 4 = 8,
F (8) = − 2 × 8 + 32−1 = 15,
F (15) =-2 * 15 + 32-1 = 1.

Assume that the variables a and b indicating the number of executions of the conversion using the function F (x) have a relationship represented by the following equation (3).
a + b = n + 1 (3)
In this case, since the mapping by the function F (x) represented by the equations (1) and (2) has a circulation period T = n + 1, a conversion using the function F (x) is performed as follows: This is an inverse conversion of b conversions. For example, when “4” is assigned to the variable n and “1” is assigned to the variable x as the original value, the transformation using the function F (x) is executed twice, thereby obtaining the function value “ 4 "is obtained. On the other hand, when “4” is assigned to the variable n and “4” is assigned to the variable x as the original value, the conversion using the function F (x) is executed three times to obtain the function value “ 1 "is obtained. It is desirable that the mapping cycle T by the function F (x) and the total number M of blocks classified in each zone satisfy the relationship represented by the following equation (4).
M = 2 ^(T-1) (4)

FIG. 13 shows an example of mapping between the virtual block address space and the physical block address space using the function F (x) expressed by the above equations (1) and (2).
In FIG. 13, the physical block address space of the flash memory 2 is divided into 8192 blocks. In order to execute the distributed processing using the function F (x) represented by the equations (1) and (2), a monitor register 36 for checking the output from the distributed processing unit 32 as shown in FIG. 14 is applied. The The process setting register 34 stores information indicating the number of executions of conversion using the function F (x).

  When the flash memory 2 includes 8192 blocks, the variable n in the function F (x) is set to “13”. The number of conversions indicated by the information stored in the process setting register 34 is in the range from “0” to “13”. The number of executions of conversion is set to a numerical value that minimizes the maximum number of defective blocks classified into each zone.

  The number of conversions that minimizes the maximum number of bad blocks classified in each zone is determined as follows. First, the controller 3 detects all defective blocks in the flash memory 2. In this detection process, information indicating “0” is set in the process setting register 34 as the number of executions of conversion.

  That is, in a state where the virtual block address VBA is directly converted into the physical block address PBA, the controller 3 detects a defective block by erasing, writing, reading, or the like in the flash memory 2. Subsequently, the distribution processing unit 32 sets information indicating “1” as the number of executions of conversion in the processing setting register 34, and then the physical block address PBA assigned to the defective block detected in the detection processing described above. Is set to a variable x to generate a mapping of the function F (x).

  The monitor register 36 stores the conversion result obtained by the distributed processing unit 32. The value stored in the monitor register 36 is read as the virtual block address VBA of the bad block. The controller 3 totals the number of bad blocks included in each zone based on the virtual block address VBA of the bad block. The controller 3 updates the information stored in the process setting register 34 so that the number of conversion executions increases by one.

  Each time the distributed processing unit 32 generates a mapping group corresponding to the number of conversions indicated by the information stored in the processing setting register 34, the controller 3 counts the number of defective blocks included in each zone. . The controller 3 detects the number of conversion executions that minimizes the maximum number of defective blocks classified in each zone by referring to the total result corresponding to the number of conversion executions.

For example, it is assumed that the maximum number of defective blocks in each zone is specified as follows, corresponding to the number of times of conversion using the function F (x).
When the number of conversions is one, the maximum value among the variables Nb0 to Nb7 is Nb4 = 8.
When the conversion execution number is 2, the maximum value among the variables Nb0 to Nb7 is Nb6 = 10.
When the number of conversion executions is 3, the maximum value among the variables Nb0 to Nb7 is Nb1 = 9.
When the number of conversions is four, the maximum value among the variables Nb0 to Nb7 is Nb5 = 11.
When the number of executions of the conversion is 5, the maximum value among the variables Nb0 to Nb7 is Nb3 = 13.
When the number of conversion executions is 6, the maximum value among the variables Nb0 to Nb7 is Nb2 = 9.
When the conversion execution number is 7, the maximum value among the variables Nb0 to Nb7 is Nb0 = 8.
When the conversion execution number is 8, the maximum value among the variables Nb0 to Nb7 is Nb6 = 6.
When the conversion execution number is 9, the maximum value among the variables Nb0 to Nb7 is Nb4 = 8.
When the conversion execution number is 10, the maximum value among the variables Nb0 to Nb7 is Nb7 = 10.
When the conversion execution count is 11, the maximum value among the variables Nb0 to Nb7 is Nb2 = 7.
When the conversion execution count is 12, the maximum value among the variables Nb0 to Nb7 is Nb0 = 9.
When the number of conversions is 13, the maximum value among the variables Nb0 to Nb7 is Nb3 = 12.

  In this case, when the number of conversion executions is 8, the maximum number of defective blocks classified into each zone is minimized. When the number of bad blocks classified into each zone is counted, the physical block address PBA of the bad block is converted into a virtual block address VBA.

  On the contrary, when the virtual block address VBA is converted to the physical block address PBA, the reverse conversion corresponding to the number of executions as described above is executed. Based on the variables a and b satisfying equation (3), the mapping when the transformation by the function F (x) is repeated b times is the inverse of the transformation by the transformation by the function F (x) a times. It is a mapping.

Therefore, when the number of executions of conversion that minimizes the maximum number of defective blocks specified by conversion from the physical block address PBA to the virtual block address VBA is indicated by the variable a, the following equation (5) By repeating the conversion for the number of times corresponding to the specified variable b, the virtual block address VBA is converted to the physical block address PBA in order to minimize the maximum number of defective blocks.
b = n + 1−a (5)

  In the above example, the variable b is “6” corresponding to the variable n = 13 and the variable a = 8. Therefore, information indicating “6” is set in the process setting register 34 as the number of executions of conversion.

  When access to the flash memory 2 is requested from the host system 4, the controller 3 sets information indicating the number of executions of conversion in the processing setting register 34 and then indicates information indicating the virtual page address set in the address register 33. Based on the above, a data read operation, a data write operation, etc. are started.

  In response to the request from the host system 4, the distributed processing unit 32 replaces a part indicating the virtual block address VBA in the virtual page address with the physical block address PBA. The physical page address generated by the distributed processing unit 32 is supplied to the memory space 35 of the flash memory 2. When block erasure is executed, the physical block address PBA is supplied to the memory space 35 of the flash memory 2 by setting information indicating the virtual block address VBA in the address register 33.

  When the virtual block address space is divided into many zones, each zone may be classified into a plurality of groups. In this case, the distributed processing unit 32 may perform conversion between the virtual block address VBA and the physical block address PBA in units of groups.

  For example, when each of the 32 zones is classified into 4 groups, the distributed processing unit 32 performs conversion between the virtual block address VBA and the physical block address PBA for every 8 zones. When the flash memory 2 includes a plurality of memory chips, the distributed processing unit 32 may perform conversion between the virtual block address VBA and the physical block address PBA for each chip. Settings for the replacement table, function, number of executions of conversion, and the like may be different for each group or for each chip.

  A function that defines the correspondence between the virtual block address VBA and the physical block address PBA may be arbitrarily set. For example, the function may be any mapping function that forms a periodic orbit, such as Bernoulli mapping.

  When the data read operation or data write operation is performed based on the information stored in the address register 33 as shown in FIG. 15, the controller 3 determines the correspondence between the logical block address LBA and the virtual block address VBA. It is desirable to provide the host system 4 with access to the flash memory 2 by using the address translation table shown.

  The address conversion table is created by the controller 3 corresponding to each of the plurality of zones. For example, in the address conversion table, as shown in FIG. 15, serial numbers assigned to the respective blocks in the virtual block address space are described in the order of logical block addresses LBA. A serial number assigned to each block in the virtual block address space is converted into a virtual block address VBA by inserting a zone number into higher bits.

  For example, in zone # 0, a virtual block address VBA corresponding to zone # 0 is generated by inserting “000” in a higher-order bit than the serial number in the binary code format.

  The address conversion table also includes information indicating an empty flag. The empty flag makes it possible to identify whether data is stored in a block corresponding to the logical block address LBA. In the example shown in FIG. 15, when the empty flag indicates “1”, it is identified that there is no virtual block address VBA corresponding to the logical block address LBA. No data is stored in the logical block address LBA that does not have the virtual block address VBA associated in the address conversion table.

  When the controller 3 creates an address conversion table as shown in FIG. 15, first, an area for storing information indicating a serial number and an empty flag corresponding to 1000 blocks is secured in the work area 8. The At this time, all the stored data in the secured area is set to the logical value “1”. Subsequently, the stored data in the redundant area 26 of the block is read in the order of the virtual block address VBA within the range in which the address conversion table manages the correspondence relationship with the logical block address LBA.

  When the stored data in the redundant area 26 indicates a specific logical block address LBA as the corresponding logical block address, the block serial number is written in the row of the logical block address LBA in the address conversion table. Further, the empty flag corresponding to the logical block address LBA is set to the logical value “0”.

  The controller 3 can convert the virtual block address VBA into a block serial number by removing the bit indicating the zone number from the virtual block address VBA. In the address conversion table, in the row of the logical block address LBA which is not indicated by the data stored in the redundant area 26, the empty flag is held with the logical value “1” as the initial setting.

  When the data stored in the flash memory 2 is rewritten, an erased block for writing rewrite data including new data must be specified. In the following, a process for specifying an erased block will be described.

  In this process, a search table 40 as shown in FIG. 16A is used. In the search table 40, each of the plurality of bits is associated with each of the virtual block addresses VBA included in the plurality of blocks classified into the specific zone. A plurality of search tables 40 are preferably created by the controller 3 corresponding to a plurality of zones.

  In the example shown in FIG. 16A, the virtual block address VBA increases as the search table 40 advances from left to right and from top to bottom. For example, the upper left bit in the search table 40 shown in FIG. 16A is associated with the head virtual block address VBA in the zone corresponding to the search table 40.

  The lower right bit in the search table 40 shown in FIG. 16A is associated with the final virtual block address VBA in the zone corresponding to the search table 40. In the search table 40 shown in FIG. 16, the bit indicating the logical value “0” indicates whether the block having the associated virtual block address VBA stores data or is a bad block. It represents something. In the search table 40, the bit indicating the logical value “1” indicates that the block having the associated virtual block address VBA is in an erased state.

  The search table 40 can be created at the same time as the address conversion table is created. For example, in the search table 40, a logical value “0” is set for all bits as an initial state. Thereafter, the controller 3 determines whether or not a corresponding logical block address or a block status indicating a bad block is stored in the redundant area 26 in the block having the virtual block address VBA associated with each bit. To do.

  When the controller 3 determines that neither the corresponding logical block address nor the block status indicating a bad block is stored, the bit corresponding to the virtual block address VBA is set to the logical value “1”. Thus, in the search table 40, only the bit associated with the erased block is set to the logical value “1”, and the other bits are held with the logical value “0”.

  When data is written to an erased block after the search table 40 is created, the bit associated with the block in the search table 40 changes from a logical value “1” to a logical value “0”. Updated. When block erasure is performed on a block in which data is stored, the bit associated with the block is updated from the logical value “0” to the logical value “1” in the search table 40.

Hereinafter, processing for searching for an erased block by using the search table 40 will be described with reference to FIG.
In this process, the controller 3 moves the search table 40 from the upper left bit associated with the first virtual block address VBA in the specific zone to the lower right bit associated with the last virtual block address VBA. Scan in direction. For example, the controller 3 sequentially checks the bits from left to right in a certain row of the search table 40, and similarly checks the bits in the next lower row. The controller 3 detects a bit indicating a logical value “1” corresponding to the erased block.

  In the search table 40 shown in FIG. 16B, a bit indicating a logical value “1” is detected in the fourth row and the fifth column. The controller 3 ends the search in the search table 40 in response to detection of the bit indicating the logical value “1”. At this time, the controller 3 specifies the virtual block address VBA associated with the bit indicating the logical value “1”.

  The controller 3 writes rewrite data including new data in the block having the virtual block address VBA thus specified. The bit next to the end point of the search process may be the start point in the next search process. For example, in the search table 40 shown in FIG. 16B, the next search process is started with the fourth row and sixth column as the starting point. In the search process, after the lower right bit is checked, the check operation returns to the upper left bit.

  Hereinafter, a data read operation for reading data from the flash memory 2 in response to a request from the host system 4 will be described. In this data read operation, the logical block address LBA specified by the address signal output from the host system 4 to the controller 3 is changed to the virtual block address VBA by using the address conversion table shown in FIG. Converted. The following information is set in a plurality of registers included in the flash sequencer block 12. First, the internal read command is set as an internal command in a predetermined first register (not shown) in the flash sequencer block 12. Secondly, the virtual page address including the virtual block address VBA specified by the address conversion table and the 5-bit data indicating the page number (when one block includes 32 pages) is shown in FIGS. 14 is set in the address register 33 indicated by 14.

  Based on the information set for the data read operation as described above, the flash sequencer block 12 controls the flash memory interface block 10 according to the internal command. The flash memory interface block 10 provides information indicating an internal command, information indicating an address, and the like to the flash memory 2 via the internal bus 14.

  The virtual page address is converted into a physical page address by the distributed processing unit 32 shown in FIGS. 8 and 14, for example. Therefore, the information provided to the flash memory 2 indicates a physical page address. In the flash memory 2, the stored data is read from the data area corresponding to the physical page address specified by the information provided from the controller 3. Data read from the flash memory 2 is transferred to the buffer 9 via the internal bus 14. As a result, the data stored in the data area having the physical page address associated with the virtual page address set in the address register 33 is held by the buffer 9.

  Next, a data write operation for writing data to the flash memory 2 in response to a request from the host system 4 will be described. In this data write operation, the following information is set in a plurality of registers included in the flash sequencer block 12. First, the internal write command is written to the first register in the flash sequencer block 12 as an internal command. Second, the virtual page address VBA of the erased block specified by the search table 40 and the 5-bit data indicating the page number (when one block includes 32 pages) is The address register 33 shown in FIGS. 8 and 14 is set.

  Based on the information set for the data write operation as described above, the flash sequencer block 12 controls the flash memory interface block 10 according to the internal command. The flash memory interface block 10 provides information indicating an internal command, information indicating an address, and the like to the flash memory 2 via the internal bus 14.

  The virtual page address is converted into a physical page address by the distributed processing unit 32 shown in FIGS. 8 and 14, for example. Therefore, the information provided to the flash memory 2 indicates a physical page address. The flash memory interface block 10 transfers the data stored in the buffer 9 to the flash memory 2 via the internal bus 14. As a result, the data supplied from the controller 3 to the flash memory 2 is written into the data area having the physical page address associated with the virtual page address set in the address register 33.

  In the data write operation as described above, when old data to be erased is stored in the flash memory 2, a data erase operation is performed on the block in which the old data is stored following the data write operation. The The virtual block address VBA included in the block in which the old data is stored can be specified by using the address conversion table shown in FIG.

  In this data erasing operation, the following information is set in a plurality of registers included in the flash sequencer block 12. First, the internal erase command is written to the first register in the flash sequencer block 12 as an internal command. Secondly, a virtual page address VBA of a block storing old data and a virtual page address including 5-bit data indicating a page number (when one block includes 32 pages) is shown in FIG. And the address register 33 shown in FIG.

  Based on the information set for the data erasing operation as described above, the flash sequencer block 12 controls the flash memory interface block 10 according to the internal command. The flash memory interface block 10 provides information indicating an internal command corresponding to a data erasing operation, information indicating an address, and the like to the flash memory 2 via the internal bus 14.

  The virtual page address is converted into a physical page address by the distributed processing unit 32 shown in FIGS. Therefore, the information provided to the flash memory 2 indicates a physical page address. As a result, the controller 3 completes the data erasing operation for the block in which the old data is stored in the flash memory 2.

  The controller 3 executes a process for minimizing the maximum number of defective blocks classified into each zone by using a plurality of replacement tables or a plurality of functions. Thus, the controller 3 can appropriately store the data provided from the host system 4 in each of the plurality of zones even when there are many bad blocks in a part of the flash memory 2.

  The present invention can be variously modified and applied. For example, the distributed processing unit 32 illustrated in FIG. 6 may be provided in the flash memory 2. The controller 3 may control data exchange between the flash memory 2 and the host system 4 independently of the flash memory system 1. The controller 3 may be built in the host system 4. The address register 33 and the processing setting register 34 may be replaced with arbitrary memories such as SRAM and DRAM (Dynamic RAM).

1 is a block diagram of a flash memory system according to the present invention. It is sectional drawing which shows the structure of a memory cell roughly. It is sectional drawing of the memory cell which is in the writing state. It is the schematic of the address space in flash memory. It is the schematic of the example of allocation of the zone in flash memory. It is the schematic of the process for classifying a block. It is the schematic which shows an example of the correlation between a logical block address, a virtual block address, and a physical block address. It is a block diagram which shows a distributed processing part, an address register, a process setting register, etc. It is the schematic of the operation | movement for converting a virtual page address into a physical page address. It is the schematic when the virtual block address is directly assigned to the physical block address. It is the schematic which shows the structural example of a replacement table. It is the schematic which shows an example of the list | wrist of a bad block. It is the schematic of the operation | movement with which a virtual block address is linked | related with a physical block address by distributed processing. It is the schematic which shows the structural example provided with a monitor register. It is the schematic which shows the example of 1 structure of an address conversion table. It is the schematic which shows one structural example of the table for a search.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Flash memory system 2 Flash memory 3 Controller 4 Host system 5 Host interface control block 6 Microprocessor 7 Host interface block 8 Work area 9 Buffer 10 Flash memory interface block 11 ECC block 12 Flash sequencer block 13 External bus 14 Internal bus 16 Memory cell 17 P-type semiconductor substrate 18 Source diffusion region 19 Drain diffusion region 20 Tunnel oxide film 21 Floating gate electrode 22 Insulating film 23 Control gate electrode 24 Channel 25 User region 26 Redundant region 31 Address conversion table 32 Distribution processing unit 33 Address register 34 Processing setting Register 35 Memory space 36 Monitor register

Claims (13)

A memory controller that controls access to a flash memory in which stored data is erased in units of physical blocks based on an address given from a host system,
Initial setting means for assigning a virtual block address to a physical block address attached to a physical block in the flash memory;
Logical zone forming means for forming a logical zone composed of areas of a plurality of blocks to which logical block addresses in the address space on the host system side are assigned;
Virtual zone forming means for forming a virtual zone composed of areas of a plurality of blocks to which the continuous virtual block addresses are assigned;
Zone management means for managing the correspondence between the logical zone and the virtual zone;
Address management means for managing a correspondence relationship between the logical block address included in the logical zone and the virtual block address included in the virtual zone corresponding to the logical zone;
Address conversion means for converting the virtual block address to the physical block address to which the virtual block address is assigned according to the assignment set by the initial setting means,
The memory controller , wherein the initial setting means assigns the virtual block address to the physical block address so that the number of defective physical blocks assigned to the virtual zones is equalized . Table storage means for storing a plurality of tables describing assignment of the virtual block address to the physical block address;
The initial setting means selects one table from the plurality of tables,
2. The memory controller according to claim 1, wherein the address conversion unit converts the virtual block address into the physical block address using the table selected by the initial setting unit . A function storage means for storing a plurality of functions for generating a one-to-one mapping;
The initial setting means selects one function from the plurality of functions,
2. The memory controller according to claim 1 , wherein the address conversion unit converts the virtual block address to the physical block address using the function selected by the initial setting unit . The address conversion means converts the virtual block address to the physical block address using a mapping function having a periodicity that generates a one-to-one mapping,
The memory controller according to claim 1, wherein the initial setting unit sets the number of conversions when the address conversion unit converts the virtual block address to the physical block address using the mapping function . The memory controller according to claim 4, wherein the mapping function is a mapping function that generates a tent map . When the cycle period of the mapping function for generating the tent map is T and the number of physical blocks in the flash memory to which the virtual block address is assigned is N, T and N are
N = 2 ^(T-1)
Satisfy the relationship
The memory controller according to claim 5.   A flash memory system comprising: the memory controller according to claim 1; and a flash memory in which stored data is erased in units of physical blocks.   A flash memory control method for controlling access to a flash memory in which stored data is erased in units of physical blocks based on an address given from a host system,
  An initial setting step of assigning a virtual block address to a physical block address attached to a physical block in the flash memory;
  An operation step of obtaining a logical block address corresponding to the access target area based on an address given from the host system;
  In accordance with the correspondence relationship between a logical zone composed of a plurality of block areas to which the logical block address is allocated and a virtual zone composed of a plurality of block areas to which the continuous virtual block address is allocated, A first conversion step of converting the logical block address included in the zone into the virtual block address included in the virtual zone corresponding to the logical zone;
  A second conversion step of converting the virtual block address to a physical block address to which the virtual block address is assigned according to the assignment set in the initial setting step;
  In the initial setting step, the virtual block address is allocated to the physical block address so that the number of defective physical blocks allocated to each virtual zone is equalized.   In the initial setting step, one table is selected from a plurality of tables describing assignment of the virtual block address to the physical block address,
  9. The flash memory control method according to claim 8, wherein, in the second conversion step, the virtual block address is converted into the physical block address using the table selected in the initial setting step.   In the initial setting step, one function is selected from a plurality of functions that generate a one-to-one mapping,
  9. The method of controlling a flash memory according to claim 8, wherein, in the second conversion step, the virtual block address is converted to the physical block address using the function selected in the initial setting step.   In the second conversion step, the virtual block address is converted into the physical block address using a mapping function having a periodicity that generates a one-to-one mapping,
  9. The flash according to claim 8, wherein in the initial setting step, the number of conversions when the virtual block address is converted into the physical block address is set using the mapping function in the second conversion step. Memory control method.   12. The flash memory control method according to claim 11, wherein the mapping function is a mapping function for generating a tent map.   When the cycle period of the mapping function for generating the tent map is T and the number of physical blocks in the flash memory to which the virtual block address is assigned is N, T and N are
  N = 2 ^(T-1)
Satisfy the relationship
  The flash memory control method according to claim 12.

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