JP2023044518A - Memory system and method - Google Patents

Abstract

To assign a plurality of blocks to match storage area units.SOLUTION: Memory chips operable in parallel each include first storage areas. A memory controller generates first groups, each of which is a group of first storage areas selected from corresponding different memory chips of the plurality of memory chips. The memory controller generates second groups each of which is constituted of a minimum number of first storage areas obtained by excluding one or more first storage areas from corresponding one of the first groups. The minimum number of first storage areas are capable of storing at least a first amount of data from the host. The memory controller executes writing of the data to all the first storage areas constituting one second group.SELECTED DRAWING: Figure 12

Description

The present embodiments relate to memory systems and methods.

In recent years, a type of SSD called ZNS (Zoned Namespace) SSD (Solid State Drive) has been proposed. A ZNS SSD presents one or more storage units to the host. A storage area unit is also called a zone. The host can write data to each zone up to a specified capacity common to all zones.

In ZNS SSDs, the memory controller assigns groups of physical blocks to each zone. A group of physical blocks assigned to each zone is referred to as a superblock. The memory controller writes the data received from the host with one storage area unit (that is, zone) as the write destination to the superblock assigned to the zone.

U.S. Patent Application Publication No. 2020/0133838 Japanese Patent Application Publication No. 2012-519900 U.S. Pat. No. 8,832,507

One embodiment aims at obtaining a memory system and method that can allocate multiple blocks to fit a storage area unit.

According to one embodiment, the memory system is connectable to a host. A memory system includes a plurality of memory chips that can operate in parallel and a memory controller. Each of the plurality of memory chips has a plurality of first storage areas. The memory controller generates a plurality of first groups, which are groups of first storage areas selected from different memory chips of the plurality of memory chips. The memory controller is configured with a minimum number of first storage areas each capable of storing at least a first amount of data from the host by removing one or more first storage areas from each of the plurality of first groups. Generate a plurality of second groups. The memory controller writes data to all the first memory areas that constitute one second group.

1 is a diagram showing a configuration example of a memory system according to an embodiment; FIG. 4 is a schematic diagram showing an example of the configuration of each memory chip according to the embodiment; FIG. 4 is a diagram showing a configuration example of each physical block according to the embodiment; FIG. 4A and 4B are schematic diagrams for explaining a method of creating a candidate configuration according to the embodiment; FIG. 1 is a schematic diagram showing one candidate configuration according to an embodiment; FIG. FIG. 4 is a schematic diagram showing an example of superblocks generated by a memory controller according to an embodiment; FIG. 4 is a schematic diagram illustrating another example superblock generated by a memory controller according to an embodiment; FIG. 4 is a schematic diagram illustrating yet another example superblock generated by a memory controller according to an embodiment; 4 is a schematic diagram for explaining two physical pages written in parallel in the block unit according to the embodiment; FIG. 4A and 4B are schematic diagrams for explaining data written to the page unit according to the embodiment; FIG. FIG. 4 is a schematic diagram showing a group of page units that can be written in parallel to a superblock at a first timing when user data is written for the first time after shipment of the memory system; FIG. 4 is a schematic diagram for explaining the state of each superpage of a superblock at a second timing when write/erase cycles are executed several times after the first timing; FIG. 11 is a schematic diagram for explaining the state of each super page of the super block at the third timing when write/erase cycles are executed several more times after the second timing; FIG. 12 is a schematic diagram for explaining the state of each super page of the super block at the fourth timing when the shortfall is compensated after the third timing; FIG. 11 is a schematic diagram for explaining the state of each super page of super blocks at the fifth timing when one block unit is deleted after the fourth timing; 4 is a schematic diagram for explaining an example of management information stored in a RAM according to the embodiment; FIG. 4 is a schematic diagram showing an example of the data structure of reserved block management information according to the embodiment; FIG. 4 is a flowchart for explaining an example of the operation of the memory system according to the embodiment regarding generation of superblocks; 4 is a flowchart for explaining an example of a write operation to a super block of the memory system according to the embodiment;

Memory systems and methods according to embodiments are described in detail below with reference to the accompanying drawings. It should be noted that the present invention is not limited by this embodiment.

(embodiment)
FIG. 1 is a diagram illustrating a configuration example of a memory system according to an embodiment;

A memory system 1 according to the embodiment can be connected to a host 2 via a communication path 3 . Host 2 is a computer. Computers include, for example, personal computers, portable computers, servers, or mobile communication devices. The memory system 1 functions as an external storage device for the host 2 .

The memory system 1 is a type of SSD called ZNS SSD. A ZNS SSD is an SSD that can execute each command included in the ZNS command set defined by NVM Express (TM). The ZNS command set includes, for example, ZONE CREATE COMMAND. A zone creation command is a command for causing the memory system 1 to set a new zone. Memory system 1 as a ZNS SSD provides host 2 with one or more zones indicated by zone creation commands. A zone is a logical storage area to which the host 2 can write a certain unit of data. A plurality of zones share a capacity for storing data from the host 2 . The capacity for storing data from the host 2 per zone is referred to as zone capacity. Hereinafter, data transferred from the host 2 to the memory system 1 will be referred to as user data.

In ZNS SSDs, there is a constraint that the host 2 must write user data sequentially in terms of logical address for each zone. Also, the ZNS SSD has a limitation that all data stored in one zone is erased at once.

The memory system 1 includes a memory controller 10 , a NAND flash memory (NAND memory) 20 , and a RAM (Random Access Memory) 30 . The NAND memory 20 is nonvolatile memory used as storage. The type of nonvolatile memory used as storage is not limited to NAND flash memory. For example, a NOR flash memory or the like can be used as the storage.

The RAM 30 is a volatile memory that stores various information for the memory controller 10 to control the NAND memory 20 . Details of various information stored in the RAM 30 will be described later. RAM 30 may also be used by memory controller 10 as a buffer for data transfers between host 2 and NAND memory 20 . RAM 30 may also be used as a buffer into which firmware programs are loaded. Any type of memory can be applied as the RAM 30 . For example, DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), or a combination thereof can be applied as RAM 30 . Also, instead of the RAM 30, a volatile or non-volatile memory that is faster than storage can be applied. The RAM 30 may be built in the memory controller 10 .

The memory controller 10 includes a CPU (Central Processing Unit) 11 , a host interface (host I/F) 12 , a RAM controller (RAMC) 13 , a NAND controller (NANDC) 14 and an ECC (Error Correction Checking) circuit 15 . The CPU 11, host I/F 12, RAMC 13, NANDC 14, and ECC circuit 15 are electrically connected via a bus.

The memory controller 10 can be configured as a SoC (System-on-a-Chip). Alternatively, the memory controller 10 can be composed of multiple chips. Memory controller 10 may be configured as a single SoC including RAM 30 .

The host I/F 12 controls signals transferred via the communication path 3 . The host I/F 12 receives various commands from the host 2 . The host I/F 12 executes data transfer between the host 2 and the RAM 30, for example. RAMC13 controls RAM30. NANDC 14 controls NAND memory 20 . NANDC 14 performs data transfer between RAM 30 and NAND memory 20, for example.

The CPU 11 is a processor that controls the entire memory controller 10 . The CPU 11 executes the control based on the firmware program.

A part or all of the control executed by the CPU 11 as a processor may be executed by a hardware circuit. A part or all of the control executed by the CPU 11 as a processor may be executed by an FPGA (Field-Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit).

The ECC circuit 15 encodes the data written to the NAND memory 20 for error correction, and decodes the data read from the NAND memory 20 . That is, the ECC circuit 15 is a circuit that executes processing related to data error correction.

As an encoding method used by the ECC circuit 15, an encoding method with a variable code rate is adopted. The code rate is numerical information obtained by dividing the size of data before encoding by the size of data after encoding. The smaller the code rate, the larger the amount of redundant data included in the encoded data. Therefore, the smaller the code rate, the higher the error correction capability.

As the number of write/erase cycles performed on NAND memory 20 increases, the data stored in NAND memory 20 is more likely to contain erroneous bits. That is, the reliability of stored data decreases as the number of write/erase cycles increases. If the number of erroneous bits contained in the data exceeds the number that can be corrected by the ECC circuit 15, the data cannot be read correctly. The CPU 11 reduces the code rate before it becomes impossible to read data correctly, thereby preventing it from becoming impossible to read data correctly.

Triggering code rate reduction is optional. For example, the CPU 11 may reduce the code rate according to the number of write/erase cycles for the NAND memory 20 . Alternatively, the memory controller 10 has an error correction function or circuit that is executed when the error correction by the ECC circuit 15 fails and has a higher error correction capability than the ECC circuit 15, and the CPU 11 has this error correction function or circuit. Code rate reduction may be performed depending on the use of .

It should be noted that code rate reduction is executed in a predetermined unit of storage area. In the embodiment, the unit of code rate reduction is the block unit BU. The details of the block unit BU will be described later, but in brief, the NAND memory 20 comprises a plurality of block units BU. The CPU 11 records the code rate for each block unit BU. Then, when the memory controller 10 writes the user data to the NAND memory 20, the CPU 11 causes the ECC circuit 15 to encode the user data at the code rate applied to the write destination block unit BU.

An upper limit value and a lower limit value are provided for the code rate. For example, when the memory system 1 is used for the first time after shipment, the CPU 11 causes the ECC circuit 15 to execute encoding at the upper limit code rate. Then, the CPU 11 reduces the code rate step by step according to the deterioration of the reliability of the stored data for each block unit BU. When the code rate of a certain block unit BU is reduced to the lower limit and the reliability of stored data does not meet the requirements even at the lower limit code rate, the CPU 11 prohibits the use of that block unit BU. . A block unit BU whose use is prohibited is called a defective block.

It should be noted that bad blocks are not always generated according to code rate reduction. A block unit BU determined to be faulty is also set as a bad block.

The NAND memory 20 includes multiple memory chips 21 . In FIG. 1, the memory chip 21 is simply written as a chip 21 in order to avoid complication of the drawing.

FIG. 2 is a schematic diagram showing an example of the configuration of each memory chip 21 according to the embodiment. Each memory chip 21 has a memory cell array 23 respectively. Memory cell array 23 has a configuration in which a plurality of memory cells are arranged two-dimensionally or three-dimensionally. A memory cell array 23 is divided into two regions 24 . Each area 24 includes multiple physical blocks 25 . Each region 24 is also called a plane.

The memory chip 21 has an independent peripheral circuit (for example, row decoder, column decoder, page buffer, data cache, etc.) for each area 24 . Therefore, the memory chip 21 can access the two areas 24 at the same time. An example of access is write, read, and erase.

Each of the two areas 24 of each memory chip 21 is given a plane number. That is, one of the two regions 24 is a plane identified by plane number 0, and the other of the two regions 24 is a plane identified by plane number 1. FIG. Hereinafter, plane #0 refers to the area 24 identified by plane number 0, and plane #1 refers to the area 24 identified by plane number 1. FIG.

The number of regions 24 included in the memory cell array 23 may be "1" or may be "3" or more.

A physical block 25 is an erase unit in each area 24 . FIG. 3 is a diagram showing a configuration example of each physical block 25. As shown in FIG. Each physical block 25 comprises multiple physical pages 26 . A physical page 26 is a unit of write and read in each area 24 . Each physical page 26 is given a page number. In FIG. 3, six physical pages 26 given page numbers 0 to 5 are denoted as page #0 to page #5, respectively.

As shown in FIG. 1, a plurality of memory chips 21 constituting the NAND memory 20 are each connected to the memory controller 10 via one of 16 channels ch (ch.0 to ch.15). . Here, it is assumed that eight memory chips 21 are connected to each channel ch.

Each memory chip 21 is connected to only one of the 16 channels ch. Each channel ch is configured by a wiring group including an I/O signal line and a control signal line group conforming to a certain standard. I/O signal lines are signal lines for transferring data, addresses, and commands. Note that the bit width of the I/O signal line is not limited to 1 bit. The control signal lines are a signal line for transferring a WE (write enable) signal, a signal line for transferring an RE (read enable) signal, a signal line for transferring a CLE (command latch enable) signal, and an ALE (address latch enable) signal. It is a group of signal lines for transferring, signal lines for transferring WP (write protect) signals, and the like. The memory controller 10 can individually control each channel ch. The memory controller 10 can simultaneously and individually control a plurality of channels ch to operate a plurality of memory chips 21 connected to different channels ch in parallel.

Also, multiple banks 22 are defined for the NAND memory 20 . Each bank 22 is composed of 16 memory chips 21 each connected to a different channel ch. Eight memory chips 21 connected to one channel ch belong to different banks 22 respectively. Therefore, the NAND memory 20 has eight banks 22 as the plurality of banks 22 . Each bank 22 is given a unique bank number (bank #0 to bank #7).

Memory controller 10 uses multiple banks 22 to perform bank interleaving. Bank interleaving is one of the parallel operations. In bank interleaving, while a plurality of (eg, 16) memory chips 21 belonging to one bank 22 are accessing data, the memory controller 10 controls a plurality of (eg, 16) memory chips belonging to another bank 22 to access data. An access instruction is issued to the chip 21 . This shortens the total time required for data transfer between the NAND memory 20 and the memory controller 10 . The access instructions include write instructions, read instructions, and erase instructions.

Thus, the memory controller 10 simultaneously operates 16 channels ch and performs bank interleaving using 8 banks 22, thereby allowing a total of 128 memory chips 21 to operate in parallel. can.

Furthermore, the memory controller 10 can simultaneously access two regions (ie, planes) 24 for each memory chip 21 . Therefore, the memory controller 10 can write data in parallel to the physical blocks 25 included in a total of 256 areas 24 . Each physical block 25 that constitutes a group of physical blocks 25 that can be written in parallel may be referred to as a parallel write element.

Memory controller 10 allocates a group of physical blocks 25 to each zone. A group of physical blocks 25 assigned to one zone is referred to as a superblock. The method of allocating superblocks is described below.

A superblock is composed of a group of parallel write elements. The memory controller 10 first generates super-block configuration candidates from groups of parallel write elements. A candidate configuration of the superblock is denoted as a candidate configuration.

In the example shown in FIG. 1, the NAND memory 20 is connected to the controller 10 by 16 channels ch, and 8 banks 22 are defined for the NAND memory 20 . The number of channels ch connecting the NAND memory 20 and the controller 10 is not limited to sixteen. Also, the number of banks 22 defined for the NAND memory 20 is not limited to eight.

FIG. 4 is a schematic diagram for explaining a method of generating a candidate configuration according to the embodiment; The memory controller 10 selects one or more banks 22 from a plurality of banks 22 (bank #0 to bank #7). The memory controller 10 then selects multiple parallel write elements from the selected one or more banks 22 .

In the example shown in FIG. 4, memory controller 10 selects bank #K and bank #K+1. Here, K is an integer of 0 or more and 6 or less. Note that when a plurality of banks 22 are selected, the bank numbers of the plurality of banks 22 do not necessarily have to be consecutive as in this example. Memory controller 10 selects a total of 32 to 64 parallel write elements belonging to the two selected banks, bank #K or bank #K+1. That is, the memory controller 10 selects 64 physical blocks 25 that differ from each other in at least one of the channel number of the connected channel ch, the bank number of the bank 22 to which it belongs, and the plane number of the region 24 included. Each physical block 25 hatched in FIG. 4 is an example of the physical block 25 selected as a parallel write element. Memory controller 10 considers the selected group of 64 physical blocks 25 as candidate configurations.

In the embodiment, as an example, the memory controller 10 manages a plurality of physical blocks 25 included in the same memory chip 21 and included in different areas 24 as one unit. This unit is written as a block unit BU. In the embodiment, one memory chip 21 includes two areas 24 . Therefore, in one memory chip 21, a pair of one physical block 25 included in plane #0 and one physical block 25 included in plane #1 is managed as one block unit BU.

That is, the memory controller 10 selects 32 block units BU in units of block units BU, and sets a group of 64 physical blocks 25 constituted by the selected 32 block units BU as a candidate configuration.

FIG. 5 is a schematic diagram illustrating one candidate configuration according to an embodiment; As shown in this figure, the memory controller 10 sets a group of total 32 block units BU as one candidate configuration 101 .

Note that one memory chip 21 includes a plurality of block units BU. That is, the memory controller 10 generates a plurality of block units BU for each memory chip 21. FIG. The number of generated block units BU may differ for each memory chip 21 . For example, when a plurality of physical blocks 25 included in one area 24 of a certain memory chip 21 includes a defective block, the memory controller 10 generates a block unit BU using the physical blocks 25 remaining after excluding the defective block. .

To simplify the explanation, it is assumed that one area 24 has N physical blocks 25 and M block units BU are generated for each memory chip 21 . Note that N is an integer of 2 or more. M is an integer of 2 or more and N or less.

For example, the memory controller 10 selects one of M block units BU from each of a total of 32 memory chips 21 belonging to either bank #K or bank #K+1. The memory controller 10 then sets the selected group of 32 block units BU as one candidate configuration 101 .

Subsequently, the memory controller 10 selects one or more unselected block units out of the M block units BU from each of a total of 32 memory chips 21 belonging to either bank #K or bank #K+1. Select a new one from BU. The memory controller 10 then sets the newly selected group of 32 block units BU to another candidate configuration 101 .

Thus, the memory controller 10 sets a plurality of candidate configurations 101 from a total of 32 memory chips 21 belonging to either bank #K or bank #K+1. That is, the memory controller 10 sets multiple candidate configurations 101 shown in FIG.

Note that the block unit BU is an example of a first storage area. The candidate configuration 101 is an example of a first group, which is a group of first storage areas selected from different memory chips 21 among the plurality of memory chips 21 capable of parallel operation.

The memory controller 10 does not necessarily have to manage a plurality of physical blocks 25 as block units BU. Memory controller 10 may perform various management for each physical block 25 . Various management includes code rate management, bad block management, management of candidate structures 101 and superblocks (described in detail below) as minimal components, and the like. That is, the physical block 25 may be the first storage area.

After generating a plurality of candidate configurations 101, the memory controller 10 deletes one or more block units BU from each candidate configuration 101, and sets each candidate configuration 101 after deletion as a superblock. Note that removing the block unit BU from the candidate configuration 101 means excluding the block unit BU from the candidate configuration 101 . The block units BU removed from the candidate structure 101 are eliminated from the candidate superblock constituents. The number of block units BU to be deleted from one candidate configuration 101 is obtained by subtracting the minimum number of block units BU required to store user data for the zone capacity from the number of block units BU included in one candidate configuration 101. is the number obtained by Therefore, one super block is composed of the minimum number of block units BU required to store user data for the zone capacity. In other words, one super block consists of the minimum number of block units BU capable of storing data from the host 2 up to at least the zone capacity.

The superblock stores not only user data but also redundant data such as error correction codes. Therefore, a storage area with a capacity exceeding the zone capacity is required to store user data corresponding to the zone capacity. The memory controller 10 calculates the minimum number of block units BU for obtaining the total capacity of the zone capacity plus the capacity required for storing redundant data. Then, the memory controller 10 obtains the number of block units BU to be deleted by subtracting the calculated minimum number of block units BU from the number of block units BU included in one candidate configuration 101 .

When deleting one or more block units BU from each of the plurality of candidate configurations 101, the memory controller 10 makes the number of deleted block units BU as uniform as possible among the 16 channels.

Each of FIGS. 6A-6C is a schematic diagram showing an example of a superblock generated by the memory controller 10 according to the embodiment.

For example, memory controller 10 selects channel ch. 7 and block unit BU selected from memory chip 21 connected to channel ch. 12 of the memory chips 21 connected to channel ch. 6 and the block unit BU selected from the memory chip 21 connected to channel ch. The block unit BU selected from the memory chip 21 connected to 10 is deleted. The memory controller 10 sets the remaining group of 28 block units BU as a superblock 102 (see superblock 102a in FIG. 6A).

Also, the memory controller 10 selects from another candidate configuration 101 channel ch. 8 and block unit BU selected from memory chip 21 connected to channel ch. 13 of the memory chips 21 connected to channel ch. 7 and block unit BU selected from memory chip 21 connected to channel ch. The block unit BU selected from the memory chip 21 connected to 11 is deleted. The memory controller 10 sets the remaining group of 28 block units BU as a superblock 102 (see superblock 102b in FIG. 6B).

In addition, the memory controller 10 selects from still another candidate configuration 101 channel ch. 9 and block unit BU selected from memory chip 21 connected to channel ch. 14 of the memory chips 21 connected to channel ch. 8 and block unit BU selected from memory chip 21 connected to channel ch. The block unit BU selected from the memory chip 21 connected to 12 is deleted. The memory controller 10 sets the remaining group of 28 block units BU as a superblock 102 (see superblock 102c in FIG. 6C).

In this way, the memory controller 10 changes (for example, shifts) the channel ch of the block unit BU to be deleted for each candidate configuration 101, thereby reducing the number of block units BU to be deleted as much as possible with 16 channels ch. make it uniform. Note that the number of block units BU to be deleted for each channel ch may not be uniform among the 16 channels ch.

Note that the superblock 102 is an example of the second group.

When writing data to each superblock 102, the memory controller 10 writes data in parallel to a plurality of block units BU that constitute the superblock 102 of the write destination. Also, the memory controller 10 controls each memory chip 21 to write data in parallel to two physical blocks 25 forming each block unit BU.

FIG. 7 is a schematic diagram for explaining two physical pages 26 written in parallel in the block unit BU according to the embodiment. The memory chip 21 simultaneously writes data to two physical pages 26 included in different physical blocks 25 forming one block unit BU. A group of two physical pages 26 included in one block unit BU and to which data is written at the same time is referred to as a page unit PU.

In the example shown in FIG. 7, two physical pages 26 selected from different physical blocks 25 and given the same page number form one page unit PU.

For example, one page unit PU is composed of two physical pages 26 given a page number of page #i. Another page unit PU is composed of two physical pages 26 given a page number of page #i+1. Another page unit PU is composed of two physical pages 26 given a page number of page #i+2. FIG. 7 shows, as an example, a page unit PU composed of two physical pages 26 given a page number of page #i.

Note that the page numbers of the plurality of physical pages 26 forming one page unit PU may not be the same. One page unit PU may be composed of a plurality of physical pages 26 given different page numbers.

FIG. 8 is a schematic diagram for explaining data written to the page unit PU according to the embodiment. The memory controller 10 manages data stored in the NAND memory 20 in units of clusters 27 . The size of cluster 27 is smaller than the size of physical page 26 . All clusters 27 have a common size.

More specifically, the memory controller 10 uses physical addresses to manage locations where data is stored in the NAND memory 20 . As described above, when user data is transferred from the host 2 to the memory system 1, a logical address is transferred corresponding to the user data. When writing user data to the NAND memory 20, the memory controller 10 associates a physical address value indicating a write destination position of the user data in the NAND memory 20 with a logical address value received corresponding to the user data. Remember. A cluster 27 is the smallest unit of data that can be specified by a physical address value. When reading data from the memory chip 21 , the memory controller 10 can indicate to the memory chip 21 the location where the data to be read is stored with a physical address value in units of clusters 27 .

In the example shown in FIG. 8, one physical page 26 stores four clusters 27 . Therefore, eight clusters 27 are stored in one page unit PU.

In addition to the eight clusters 27, one page unit PU has an area (not shown) in which an error correction code generated by encoding at the maximum code rate can be stored. That is, when the code rate is the maximum value, one page unit PU contains user data for eight clusters 27 and user data for eight clusters 27 generated by encoding the code rate of the maximum value. and an error correction code for correcting errors in .

FIG. 9A is a schematic diagram showing a group of page units PU that can be written in parallel to the superblock 102a at the first timing shortly after the memory system 1 is first used after shipment. According to the example shown in this figure, data can be written in parallel to 28 page units PU in the superblock 102a. A group of page units PU that can be written in parallel to one superblock 102 in this way is referred to as a superpage. Memory controller 10 performs parallel writes on a superpage-by-superpage basis.

As described above, the superblock 102 is composed of the minimum number of block units BU required to store user data for the zone capacity. However, since the capacity of each superblock 102 that can store user data is adjusted in units of block units BU, the amount of user data that can be stored in one superblock 102 may slightly exceed the zone capacity. be. If there is an extra area in the super block 102 where no data has been written after the user data has been written for the zone capacity, the memory controller 10 pads the extra area, that is, it is meaningless. data write. As a result, data is written until all block units BU constituting the super block 102 have no free space.

In the example shown in FIG. 9A, each superpage provided in the superblock 102a is composed of 28 page units PU, and one page unit PU can store user data for eight clusters 27. In the example shown in FIG. Therefore, each super page has a capacity capable of storing user data for 224 clusters 27 .

On the other hand, the amount obtained by dividing the zone capacity by the number of superpages included in the superblock 102a, that is, the amount obtained by converting the zone capacity into the capacity per superpage, is 218 clusters 27. It is assumed that it corresponds to the capacity of one minute.

In this case, superblock 102a has extra space for six clusters 27 per superpage.

As described above, if the super block 102 has an extra area to which no data has been written after the user data has been written for the zone capacity, the memory controller 10 Perform padding that writes meaningless data to the region. For example, in the example shown in FIG. 9A, memory controller 10 writes meaningless data to six clusters 27a per superpage.

It should be noted that the area in which meaningless data is written does not necessarily have to be provided uniformly in each super page. Memory controller 10 may collect areas where meaningless data is written to any superpage.

Zone capacity is an example of a first quantity. A capacity that can store user data in one superblock is an example of the second amount.

Note that the trigger for executing padding is not limited to the completion of writing of user data for the zone capacity to one super block 102 . When it is determined that the writing of user data to one zone has been completed, the memory controller 10 performs padding even if the amount of user data written to that zone does not reach the zone capacity. good.

Hereinafter, the extra area means the area obtained by subtracting the area in which the user data for the zone capacity is written from the area in which the user data of one super block 102 can be stored.

FIG. 9B is a schematic diagram for explaining the state of each superpage of superblock 102a at the second timing when several write/erase cycles are executed after the first timing. After the first timing, several write/erase cycles have been performed on the superblock 102a, resulting in reduced data reliability in some block units BU. Then, the memory controller 10 reduces the code rate of the block unit BU whose data reliability has deteriorated.

In the example shown in FIG. 9B, among 14 block units BU belonging to bank #K+1, channel ch. 0, the block unit BU selected from the memory chip 21 connected to channel ch. 1, block unit BU selected from memory chip 21 connected to channel ch. 2, block unit BU selected from memory chip 21 connected to channel ch. block unit BU selected from memory chip 21 connected to channel ch. 4 and block unit BU selected from memory chip 21 connected to channel ch. For each block unit BU selected from the memory chip 21 connected to 8, the code rate is reduced by one step. This reduces the capacity for storing user data by 6 clusters 27 per superpage. For example, six clusters 27b shown in the drawing represent clusters 27 in which user data cannot be stored due to code rate reduction. The six clusters 27b can store, for example, error correction codes for correcting errors in user data whose code rate has been reduced by one step.

In the example shown in FIG. 9B, the capacity for storing user data is reduced by 6 clusters 27b per superpage. As a result, the capacity for storing user data per superpage is equal to the capacity obtained by converting the zone capacity into the capacity per superpage. That is, at the second timing, superblock 102a has no extra area. In such a case, no padding apart from writing user data for the zone capacity is required.

FIG. 9C is a schematic diagram for explaining the state of each superpage of superblock 102a at a third timing in which write/erase cycles are executed several more times after the second timing.

In the example shown in FIG. 9C, channel ch. In the block unit BU selected from the memory chip 21 connected to 13, the code rate is reduced by one step. This leaves the amount of user data that can be stored in superblock 102a short of the zone capacity by one cluster 27 per superpage. For example, one cluster 27c shown in the drawing represents a cluster 27 in which user data cannot be stored due to code rate reduction.

If the amount of user data that can be stored in the superblock 102 falls below the zone capacity, the memory controller 10 replaces the deficit, that is, the capacity obtained by subtracting the amount of user data that can be stored in the superblock 102 from the zone capacity. , are supplemented with the block units BU deleted from the candidate configuration 101 .

That is, the memory controller 10 reserves all block units BU deleted from the multiple candidate configurations 101 . Then, if a super block 102 suffers from a shortage of capacity due to code rate reduction or the occurrence of defective blocks, the memory controller 10 reserves one or more block units BU out of the reserved block units BU and restores the capacity. is added to the superblock 102 where the shortfall of is generated.

FIG. 9D is a schematic diagram for explaining the state of each superpage of superblock 102a at the fourth timing when the shortfall is compensated after the third timing.

In the example shown in FIG. 9D, channel ch. One block unit BU selected from the memory chips 21 connected to 10 is added to the super block 102a. As a result, a page unit PUa capable of storing eight clusters 27 of user data is added to each superpage included in the superblock 102a. In other words, each super page is compensated for one missing cluster 27 by eight clusters 27 added. As a result, the lack of capacity is eliminated.

Note that the superblock 102a shown in FIG. 9D includes an amount of extra space equivalent to seven clusters 27 per superpage. In the embodiment, if the addition of the block unit BU results in extra space, the memory controller 10 removes one or more block units BU from the superblock 102 to reduce the capacity of the extra space as much as possible. is configured to allow

FIG. 9E is a schematic diagram for explaining the state of each superpage of the superblock 102a at the fifth timing when one block unit BU is deleted after the fourth timing.

In the example shown in FIG. 9E, from superblock 102a in the state shown in FIG. 9D, channel ch. The block unit BU selected from the memory chip 21 connected to 0 is deleted.

Superblock 102a shown in FIG. 9D contains an amount of extra space equivalent to seven clusters 27 per superpage. Channel ch. The block unit BU included in the memory chip 21 connected to 0 has a capacity capable of storing user data for seven clusters 27 per page unit PU. Then, from the super block 102a including an extra area corresponding to the amount of seven clusters 27 per super page, one page unit PU can store user data for seven clusters 27. is deleted. As a result, the capacity for storing user data per superpage becomes equal to the capacity obtained by converting the zone capacity into the capacity per superpage. In other words, superblock 102a has no extra area.

Note that the memory controller 10 operates on the channel ch. The block unit BU included in the memory chip 21 connected to 0 is reserved until it is added to some super block 102 again.

In the example illustrated with FIGS. 9A-9E, the reduction in the capacity of superblock 102 to store user data was caused by code rate reduction. A reduction in the capacity of the superblock 102 that can store user data can also be caused by the block unit BU included in the superblock 102 being set as a bad block. When the block unit BU is set as a bad block and the super block 102 has a capacity shortage, the memory controller 10 performs the same operation as when the super block 102 has a capacity shortage due to code rate reduction. , make up for the shortage from the block unit BU previously reserved.

In this way, the memory controller 10 configures each superblock 102 with the minimum number of block units BU that can obtain the zone capacity. Then, the memory controller 10 adds block units BU reserved in advance to the super block 102 when a certain super block 102 has insufficient capacity due to code rate reduction or occurrence of defective blocks. This allows the extra space in each superblock 102 to be minimized.

Note that in the example described with reference to FIGS. 9A to 9E, one block unit BU was added to the superblock 102 or one block unit BU was deleted from the superblock 102. FIG. The number of block units BU added to the superblock 102 at one time may be two or more. The number of block units BU deleted from the superblock 102 at one time may be two or more. For example, the memory controller 10 adds three block units BU to the super block 102 and removes two block units BU from the super block 102 to eliminate the shortage and minimize the excess capacity. may

Also, in the example described using FIGS. 9A to 9E, after one block unit BU was added to the superblock 102, another one block unit BU was deleted from the superblock 102. FIG. The execution order of addition of block units BU and deletion of block units BU is not limited to this.

Here, a technique to be compared with the embodiment will be described. A technique compared with the embodiment is referred to as a comparative example. According to a comparative example, the memory controller generates multiple superblocks of uniform size. Then, after the memory system starts operating, the memory controller neither adds physical blocks to nor deletes physical blocks from one superblock. Therefore, when generating each superblock, the memory controller can store at least the zone capacity of user data even if the code rate is reduced or a bad block occurs in a certain superblock. causes each superblock to have a lot of extra space upfront.

As described above, padding is performed when there is an extra area in one superblock when user data for the zone capacity has been written to the superblock. In the comparative example, there is a lot of extra capacity in each superblock, so the amount of meaningless data written by padding is very high. Therefore, according to the comparative example, the write amplification factor (hereinafter referred to as WAF) is poor, and the period during which the memory system operates reliably decreases. In addition, hardware resources of the NAND memory (for example, the bandwidth of the channel connecting the NAND memory and the memory controller) are occupied by meaningless data writes, which slows down the speed of writing user data. That is, according to the comparative example, the performance of the memory system deteriorates.

In contrast, according to the embodiment, the extra area included in each superblock 102 can be reduced as much as possible. Therefore, deterioration of WAF caused by padding is suppressed. As a result, compared to the comparative example, the period during which the memory system 1 operates with reliability can be lengthened, and a decrease in the write speed of user data can be suppressed. In other words, the memory controller 10 of the embodiment can generate super blocks with higher performance than the comparative example.

The CPU 11 stores, for example, the RAM 30 various kinds of management information for realizing the operations described above. FIG. 10 is a schematic diagram for explaining an example of management information stored in the RAM 30 according to the embodiment. As shown in the figure, the RAM 30 stores super block management information 201, reserved block management information 202, bad block management information 203, and zone allocation information 204. FIG.

The superblock management information 201 is information in which identification information of a plurality of block units BU constituting the superblock 102 is recorded for each superblock 102 . When a certain super block 102 is set, the CPU 11 records identification information of the super block 102 and identification information of a plurality of block units BU forming the super block 102 in association with each other. Further, when the CPU 11 deletes a block unit BU from a certain super block 102 or adds a block unit BU to a certain super block 102, the super block management information 201 to update.

The zone allocation information 204 is information that associates the identification information of a zone with the identification information of the superblock 102 allocated to the zone.

The bad block management information 203 is a list of identification information of block units BU whose use is prohibited. For example, if the code rate of a certain block unit BU is reduced to the lower limit value and data reliability cannot be ensured even at the lower limit code rate, the CPU 11 stores the identification information of this block unit BU in the bad block management information 203. register. As a result, the block unit BU is set as a bad block. The CPU 11 does not use the block unit BU registered in the bad block management information 203 thereafter.

The reserved block management information 202 is information in which identification information of block units BU that can be added to the super block 102 is recorded.

FIG. 11 is a schematic diagram showing an example of the data structure of the reserved block management information 202 according to the embodiment. As shown in this figure, the reserved block management information 202 includes three sublists for each pair of channel and bank (in other words, for each memory chip 21). The three sub-lists are the first BU list, the second BU list, and the third BU list.

The first BU list is a list of identification information of block units BU whose code rate is set to the upper limit. The block units BU registered in the first BU list can store user data for eight clusters 27 per page unit PU.

The second BU list is a list of identification information of block units BU whose code rate is reduced by one step from the upper limit. The block units BU registered in the second BU list can store user data for seven clusters 27 per page unit PU.

The third BU list is a list of identification information of block units BU whose code rate is reduced by two stages from the upper limit. The block units BU registered in the third BU list can store user data for six clusters 27 per page unit PU.

Regarding the code rate, the lower limit is assumed to be a value that is reduced by two steps from the upper limit. The code rate lower limit is not limited to this.

In this way, the block units BU that can be added to the super block 102 are classified and managed according to channels, banks, and set code rates.

The memory controller 10 can add block units BU managed by the reserved block management information 202 to the super block 102 . In the example described with reference to FIGS. 9A to 9E, the memory controller 10 added to the super block 102 a block unit BU with a code rate managed by the first BU list set to the upper limit. The memory controller 10 can add to the super unit 102 a block unit BU in which the code rate managed by the second BU list is reduced by one step from the upper limit. Also, the memory controller 10 can add to the super unit 102 a block unit BU in which the code rate managed by the third BU list is reduced by two stages from the upper limit.

Next, operation of the memory system 1 according to the embodiment will be described.

FIG. 12 is a flowchart for explaining an example of the operation of the memory system 1 according to the embodiment regarding generation of the superblock 102. As shown in FIG.

First, the memory controller 10 generates a plurality of candidate configurations 101 (S101). The memory controller 10 selects one block unit BU from each of a plurality of memory chips 21 capable of parallel operation, and sets a group of block units BU selected from different memory chips 21 as one candidate configuration 101. do.

For example, memory controller 10 selects one or more banks from bank #0 to bank #7, as described with reference to FIGS. Memory controller 10 then selects a plurality of parallel write elements from the selected one or more banks. The memory controller 10 then sets the selected group of parallel write elements as one candidate configuration 101 .

Following S101, the memory controller 10 deletes one or more block units BU from each candidate configuration 101, and sets each candidate configuration 101 after deletion as a super block 102 (S102). At S<b>102 , the memory controller 10 adds information about each superblock 102 to the superblock management information 201 .

The memory controller 10 registers the block unit BU deleted in S102 in the reserved block management information 202 (S103).

When the memory system 1 receives a zone creation command from the host 2 (S104), the memory controller 10 defines a new zone and allocates any superblock 102 to the defined zone (S105). In S<b>105 , the memory controller 10 records information about the newly defined zone in the zone allocation information 204 .

A series of operations relating to the setting of the superblock 102 is then completed.

FIG. 13 is a flowchart for explaining an example of a write operation to the superblock 102 of the memory system 1 according to the embodiment. Here, a series of operations started by the memory system 1 according to the embodiment when the host 2 requests to write to a certain zone will be described.

First, the memory controller 10 identifies the super block 102 allocated to the write destination zone by referring to the zone allocation information 204 (S201). The identified superblock 102 is denoted as the target superblock 102 .

Subsequently, the memory controller 10 determines whether a bad block has occurred (S202).

In S202, the memory controller 10 determines whether or not each block unit BU constituting the target super block 102 can continue to be used. If there is a block unit BU whose code rate is set to the lower limit and the reliability of stored data does not satisfy the standard, the memory controller 10 determines that the block unit BU has become a defective block. Also, if there is a failed block unit BU, the memory controller 10 determines that the block unit BU has become a defective block.

If any of the block units BU forming the target super block 102 becomes a defective block, the memory controller 10 deletes the block unit BU from the target super block 102 and registers it in the defective block management information 203 . If none of the block units BU forming the target super block 102 are defective blocks, the memory controller 10 does not change the configuration of the target super block 102 .

Subsequently, the memory controller 10 determines reduction of the code rate (S203).

In S204, the memory controller 10 determines whether or not to reduce the code rate for each block unit BU that constitutes the super block 102 of interest. If there is a block unit BU for which code rate reduction is to be performed, the memory controller 10 executes code rate reduction for that block unit BU.

Subsequently, the memory controller 10 determines whether or not the amount of user data that can be stored in the target superblock 102 is less than the zone capacity (S204). If the amount of user data that can be stored in the target super block 102 is less than the zone capacity (S204: Yes), the memory controller 10 determines the amount of user data that can be stored in the target super block 102 from the lack of capacity, that is, the zone capacity. It is determined whether or not the capacity obtained by subtracting the amount of data can be compensated (S205). By referring to the reserved block management information 202, the memory controller 10 determines whether the capacity shortage can be compensated based on whether there is a block unit BU that can be used to compensate for the capacity shortage. judge.

If the capacity shortage cannot be compensated for (S205: No), the memory controller 10 dismantles the target super block 102 (S206).

In S<b>206 , the memory controller 10 registers all block units BU forming the target super block 102 in the reserved block management information 202 . Also, the memory controller 10 deletes the information about the target superblock 102 from the superblock management information 201 .

Following S206, the memory controller 10 allocates another super block 102 to the write destination zone (S207). Through S207, the superblock 102 assigned to the write destination zone, that is, the target superblock 102 is switched to the new superblock 102. FIG.

After S207, the control shifts to S202, and the memory controller 10 determines whether or not the new superblock 102 that has become the target superblock 102 has a bad block.

If the capacity shortage can be compensated for (S205: Yes), the memory controller 10 compensates for the capacity shortage using one or more block units BU registered in the reserved block management information 202 (S208). .

In S208, the memory controller 10 adds one or more block units BU to the target superblock 102 or removes one or more block units BU from the target superblock 102 so that the capacity of the extra area is minimized. can be deleted. The memory controller 10 can select block units BU to be added from the first BU list, the second BU list, and the third BU list. The memory controller 10 updates the super block management information 201 when adding a block unit BU to the target super block 102 or deleting a block unit BU from the target super block 102 . When the block unit BU is deleted from the target superblock 102 , the memory controller 10 registers the block unit BU in the reserved block management information 202 .

After S208, or if the amount of user data that can be stored in the target superblock 102 is greater than or equal to the zone capacity (S204: No), the memory controller 10 erases the data in the target superblock 102. (S209).

In S209, the memory controller 10 collectively erases data for all block units BU that constitute the super block 102 of interest. As a result, the target superblock 102 becomes ready for data writing.

After S209, the memory controller 10 writes data to the target superblock 102 (S210).

In S210, the host 2 writes user data corresponding to the zone capacity to the super block 102 assigned to the write destination zone. The memory controller 10 writes user data corresponding to the zone capacity received from the host 2 to the target super block 102 together with redundant data such as an error correction code.

When the memory controller 10 writes the zone capacity of user data together with redundant data to the target super block 102, it determines whether or not there is an extra area in the target super block 102 (S211). If there is an extra area in the target superblock 102 (S211: Yes), the memory controller 10 performs padding to write meaningless data in the extra area (S212). The write operation to superblock 102 is then completed.

If there is no extra area in the target superblock 102 (S211: No), the memory controller 10 skips the processing of S213 and the write operation to the superblock 102 is completed.

Thus, according to the embodiment, the memory controller 10 generates a plurality of candidate configurations 101 that are groups of block units BU selected from different memory chips 21 of the plurality of memory chips 21 capable of parallel operation. By deleting one or more block units BU from each of the plurality of candidate configurations 101, the memory controller 10 is configured with a minimum number of block units BU, each of which can store user data up to at least the zone capacity. generates a superblock 102 of The memory controller 10 writes data until all block units BU forming one super block 102 have no free space. In addition, the memory controller 10 erases data collectively for all block units BU forming one super block 102 .

Therefore, deterioration of WAF due to padding is suppressed as compared with the comparative example. As a result, compared to the comparative example, the period during which the memory system 1 operates with reliability can be lengthened, and a decrease in the write speed of user data can be suppressed. That is, the memory controller 10 of the embodiment can generate the super block 102 with higher performance than the comparative example.

Further, according to the embodiment, the memory controller 10 is deleted from the plurality of candidate configurations 101 when the user data storage capacity of one super block 102 becomes smaller than the zone capacity due to code rate reduction. At least one of the plurality of block units BU is added to the super block 102 .

Therefore, it is possible to enhance the error correction capability in accordance with the decrease in the reliability of the data stored in the NAND memory 20 while maintaining the user data storable capacity of each super block 102 equal to or greater than the zone capacity. .

Further, according to the embodiment, when the capacity of one super block 102 that can store user data becomes smaller than the zone capacity due to the occurrence of bad blocks, the memory controller 10 removes the super block from the plurality of candidate configurations 101 . At least one of the plurality of block units BU is added to the superblock 102 .

Therefore, even if a bad block occurs, it is possible to maintain the user data storage capacity of each super block 102 equal to or greater than the zone capacity.

Further, according to the embodiment, when the capacity of one super block 102 that can store user data becomes larger than the zone capacity due to the addition of the block unit BU to one super block 102, the super block 102 increases the code rate. The extra capacity of the superblock 102 is reduced by deleting the block unit BU on which the reduction has been performed.

Therefore, during the operation of the memory system 1, it is possible to constantly suppress deterioration of the WAF caused by padding.

In the above description, the memory system 1 is assumed to be a type of SSD called ZNS SSD. The technology according to the embodiment can be applied to other than ZNS SSD. For example, the technology according to the embodiment can also be applied to a stream-specification SSD.

While several embodiments of the invention have been described, these embodiments have been presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and modifications can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the scope of the invention described in the claims and equivalents thereof.

1 memory system, 2 host, 3 communication path, 10 memory controller, 11 CPU, 12 host I/F, 13 RAM controller, 14 NAND controller 15 ECC circuit, 20 NAND memory, 21 memory chip, 22 bank, 23 memory cell array, 24 area, 25 physical block, 26 physical page, 27, 27a, 27b cluster, 101 candidate configuration, 102, 102a, 102b, 102c super block, 201 super block management information, 202 reserved block management information, 203 bad block management information , 204 Zone allocation information, BU block unit.

Claims (8)

A memory system connectable to a host,
a plurality of memory chips each having a plurality of first storage areas and capable of operating in parallel;
generating a plurality of first groups, which are groups of the first storage areas selected from different memory chips among the plurality of memory chips;
removing one or more of the first storage areas from each of the plurality of generated first groups, each configured with a minimum number of first storage areas capable of storing at least a first amount of data from the host; Generate a plurality of second groups with
executing the data write to all the first storage areas that constitute one second group;
a memory controller;
memory system. A circuit that performs error correction by encoding data written to each of the second groups by an encoding method with a variable code rate and decoding data read from each of the second groups. further comprising
The memory controller
reducing the code rate of data written to a first second group of the plurality of second groups;
When the second amount, which is the capacity of the first second group capable of storing data from the host, becomes smaller than the first amount due to the reduction of the code rate, each of the plurality of first groups adding at least one of a plurality of second storage areas, which is the first storage area removed from any of them, to the first second group;
2. The memory system of claim 1. The memory controller
setting one or more first storage areas included in a first second group out of the plurality of second groups to be unusable;
A second amount, which is the capacity of the first second group capable of storing data from the host, has become smaller than the first amount due to the one or more first storage areas being disabled. adding at least one of a plurality of second storage areas, each of which is a first storage area deleted from any of the plurality of first groups, to the second group;
2. The memory system of claim 1. The memory controller
performing the code rate reduction individually for each first storage area;
reducing the code rate of all the first storage areas constituting the first second group if the addition of the at least one second storage area causes the second amount to be greater than the first amount; reducing the third amount obtained by subtracting the first amount from the second amount by removing from the second group the third storage area in which
3. The memory system of claim 2. A circuit for executing error correction by encoding data written to each second group by an encoding system with a variable code rate and decoding data read from each second group. further prepared,
The memory controller
performing the code rate reduction individually for each first storage area;
reducing the code rate of all the first storage areas constituting the first second group if the addition of the at least one second storage area causes the second amount to be greater than the first amount; reducing the third amount obtained by subtracting the first amount from the second amount by removing from the second group the third storage area in which
4. The memory system of claim 3. After writing the first amount of data to one second group, if a surplus area in which data can be written remains in the second group, the memory controller pads the surplus area. do,
6. The memory system according to any one of claims 1-5. The memory system is a ZNS (Zoned Namespace) SSD (Solid State Drive),
the memory controller assigning one of the plurality of second groups to one zone;
the first amount is the total amount of data that the host can write to the one zone;
7. The memory system according to any one of claims 1-6. A method of controlling a memory system comprising a plurality of memory chips each comprising a plurality of first storage areas and operable in parallel, comprising:
generating a plurality of first groups, which are groups of the first storage areas selected from different memory chips among the plurality of memory chips;
removing one or more of the first storage areas from each of the plurality of generated first groups, each configured with a minimum number of first storage areas capable of storing up to at least a first amount of data from a host; generating a plurality of second groups;
executing the data write to all the first storage areas that constitute one second group;
How to prepare.

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