JP3939888B2 - Nonlinear distortion compensation power amplifier - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a power amplifier useful for mobile radio communication such as an automobile phone or a mobile phone, and more particularly to a nonlinear distortion compensation amplifier suitable for amplifying a linear modulation signal or a plurality of modulation signals in a base station in common. It is.
[0002]
[Prior art]
In power amplifiers that amplify linear modulated waves or multiple modulated waves, nonlinear distortion must be minimized as much as possible to suppress unnecessary radio wave (spurious) radiation and increase power efficiency. Conventionally, a negative feedback method, a feed forward method, and a predistorter method are known as methods for compensating for nonlinear distortion of an amplifier.
[0003]
The negative feedback system is less likely to be used in a base station radio because an oscillation phenomenon is likely to occur when the signal has a wide band and operation instability increases.
[0004]
The feedforward method is used in many base station radios at present because it does not cause unstable operation in principle. However, the feed-forward method requires a configuration in which an error component is extracted and amplified separately by a sub-amplifier and then subtracted from the output signal of the main amplifier. There is a problem that decreases.
[0005]
On the other hand, the predistorter method is attracting attention as an alternative to the feedforward method because a sub-amplifier is not required, and research and development are underway. For example, Y. In the method described in Nagata, “Linear Amplification Technology for Digital Mobile Communication” (see Reference 1), a predistorter amplifier using a digital signal processing technology is introduced. Since this method detects an error between the input modulation signal and the output signal, a demodulator is required, and there is a disadvantage that the circuit becomes complicated. F. The method described in Antonio et al., “New Technology for Adaptive Predistortion for Power Amplifiers” (see Reference 2) eliminates the need for a demodulator and other error detection circuits by detecting out-of-band power due to nonlinear distortion. ing. However, in this method, since the in-band to out-of-band power ratio is calculated by the fast Fourier transform, the amount of digital signal processing increases. In addition, in order to add distortion to the complex baseband signal, it is necessary to configure a circuit across the high-frequency power amplification unit and the baseband unit. In other words, there is a restriction that each device cannot be designed independently. Furthermore, since the contents of the memory circuit are updated for each address, there is a disadvantage that the time until the distortion compensation operation converges becomes longer.
[0006]
Reference 1: Y.Nagata, 'Linear Amplification Technique for Digital
Mobile Communication ', Proceedings of IEEE Vehicular
Technology Conference, pp. 159-164, 1989.
Reference 2: F. Antonio et al., 'A Novel Adaptive Predistortion
Technique for Power Amplifiers', Proceedings of IEEE
Vehicurlar Technology Conference, pp.1505-1509, 1999.
[0007]
[Problems to be solved by the invention]
None of the conventional nonlinear distortion compensating power amplifiers described above is insufficient in terms of power efficiency and ease of circuit implementation. In the future, radio signals that need to be amplified include, for example, a wideband code division multiple access (CDMA) system signal of a plurality of carriers, and it is expected that signals with complicated configurations need to be amplified in a lump. The For such signals, it is difficult to calculate the in-band to out-of-band power ratio as in the prior art.
[0008]
An object of the present invention is to provide a nonlinear distortion compensation power amplifier that can improve power efficiency and circuit feasibility, shorten the convergence time of distortion compensation operation, and flexibly cope with the configuration of a radio signal to be amplified. is there.
[0009]
[Means for Solving the Problems]
The present invention aims to solve the above problems by improving the predistorter method, and corrects the amplitude and / or phase of the input signal by a control circuit provided in the preceding stage of the power amplifier to achieve an optimal nonlinearity. Perform distortion compensation. The correction characteristics of the amplitude and phase of the input signal in the control circuit are corrected by trial and error little by little as the out-of-band signal component power included in the output signal of the power amplifier increases and decreases. The correction is finished when it no longer decreases. The correction characteristics of the amplitude and phase of the input signal are stored as a table in which correction values are set for each power level of the input signal. The value is calculated and updated.
[0010]
Such a configuration of the nonlinear distortion compensating power amplifier according to the present invention includes an amplitude / phase control circuit that corrects an input signal based on a control signal, a first power meter that detects the power of the input signal, and a detected signal. A storage circuit that stores a table that gives a corresponding control signal value that is referred to by the power value of the input signal, a control signal generation circuit that supplies the control signal to the amplitude / phase control circuit, and the amplitude / phase control circuit comprising of the connected power amplifier output, a filter for extracting an effective out-of-band signal components from the output signal of the power amplifier, and a second power measuring device for detecting the power of the signal components outside the useful band taken the control signal generating circuit, based on the power values of the detected outside the effective band of the signal component, the contents of the table stored, so that the effective band of the signal component power has been reduced A nonlinear distortion compensating power amplifier that have a algorithm for updating, the algorithm of positive and negative, a plurality of correction function patterns and different lines and triangles height, stepwise added to the initial value In other words, the power of the signal component outside the effective band is checked at each stage of the addition, and only the signal component that reduces the power of the signal component outside the effective band is left .
[0011]
FIG. 1 shows a specific example of the principle configuration of the present invention. In the figure, 10 is an input terminal, 11 is a delay circuit, 12 is an amplitude / phase control circuit, 13 is a power amplifier, 14 is a directional coupler, 15 is an output terminal, 16 is a first power meter, and 17 is a control. Signal generating circuit, 18 is a second power meter, 19 is a band pass filter, 20 is a frequency conversion circuit, 120 is a gain control circuit, 121 is a phase control circuit, 170 is a gain control signal, 171 is a phase control signal, 172 Is a storage circuit, 173 is a calculation circuit, 200 is a local signal generator, and 201 is a multiplication circuit.
[0012]
The radio signal input to the input terminal 10 is delayed by Δt time by the delay circuit 11 and then input to the amplitude / phase control circuit 12, where the gain control signal 170 and the phase control output from the control signal generation circuit 17 are input. After the amplitude and phase are controlled according to the signal 171, the signal is amplified by the power amplifier 13 and output to the output terminal 15. A part of the output signal is taken out by the directional coupler 14, frequency-converted by the frequency conversion circuit 20, and only unnecessary signal components within the frequency range to be observed are taken out by the band-pass filter 19, and the second power meter 18 to measure the power.
[0013]
On the other hand, a part of the input signal to the input terminal 10 is input to the first power meter 16 to measure the power, and the address of the memory circuit 172 is referred to by the value. The table contents of the storage circuit 172 are determined by the calculation circuit 173. Here, the calculation circuit 173 operates according to an algorithm that determines the table contents of the storage circuit 172 so that the output of the second power meter 18 is minimized. This algorithm can be trial and error. The control signal generation circuit 17 is realized by digital signal processing, and although not shown, an input signal to the circuit is analog / digital converted and an output signal is digital / analog converted.
[0014]
An example of the operation of the frequency conversion circuit 20 and the band pass filter 19 will be described with reference to FIG. FIG. 2A shows the power spectrum of the output signal extracted from the directional coupler 14. The solid line in the figure corresponds to the power spectrum of the input signal, and the broken line portion corresponds to the out-of-band spectral component generated by the odd-order nonlinear distortion of the power amplifier 13. The frequency f ₀ ′ generated by the local signal generator 200 of the frequency conversion circuit 20 is made the same as the center frequency f _{0 of the} signal (f ₀ ′ = f ₀ ), and the pass band of the band pass filter 19 is Δf ₁ to Δf ₂ . By setting the range, the power of the out-of-band spectral component indicated by the broken line in FIG. 2A is obtained at the output of the second power meter 18. By correcting the input signal through the control signal generation circuit 17 and the amplitude / phase control circuit 12 so as to minimize the out-of-band power, the nonlinear distortion of the power amplifier 13 can be compensated. In the nonlinear distortion compensation operation of the present invention, the operation of minimizing the out-of-band power is made possible by the algorithm of the calculation circuit 173 in the control signal generation circuit 17, and details will be described later in the description of the embodiment. .
[0015]
The operation principle of the predistorter constituted by the amplitude / phase control circuit 12 and the control signal generation circuit 17 in the present invention will be described with reference to FIG. In the figure, the horizontal axis represents the input level, the left vertical axis represents the output level, and the right vertical axis represents the output phase. Nonlinear distortion has a linear relationship between input and output level, and becomes zero if the output phase does not change with the input level. The characteristics of the power amplification circuit of the amplitude characteristic curve and the phase characteristic curve indicated by solid lines in the figure are converged like a downward arrow by connecting a predistorter to the input, and the overall characteristic is improved. .
[0016]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 3 is a diagram showing a signal power spectrum of the first embodiment of the present invention, FIG. 4 is a configuration example of a control signal generation circuit, and FIG. 5 is a configuration example of a control circuit. The overall configuration is the same as in FIG.
[0017]
In this embodiment, it is assumed that two radio signals having adjacent frequencies are amplified simultaneously as shown in FIG. The signal bandwidth is 2 W _s and the out-of-band power bandwidth is 2 W ₀ . The local oscillation frequency f ₀ ^′ of the frequency conversion circuit is set to f ₀ ^′ = f _0, and the pass band of the band pass filter is set to 2 (W ₀ −W _s ). As a result, the out-of-band power indicated by the broken line in FIG. 3 can be measured.
[0018]
In the configuration example of FIG. 4, the output of the first power meter input to the input terminal 40 passes through the logarithmic amplifier 41, and then the first A / D converter 42 performs sampling and analog− at the sampling frequency f _s. It is digitally converted and quantized to an N-bit value. Here, the logarithmic amplifier 41 is used for the purpose of reducing the number of quantization bits of the A / D converter 42. The address of the random storage circuit (RAM) 43 is determined by the quantized N-bit digital signal. The number of addresses M bits (2 ^M ways) of the memory circuit 43 is equal to or less than N bits (M ≦ N). When M <N, the control signal is determined by referring to the two nearest addresses corresponding to the value quantized to N bits and interpolating the two outputs of the storage circuit 43 in the level interpolation circuit 440. To do. The storage circuit 43 stores a table of values for controlling the gain and phase specified by the calculation circuit 47 by digital signal processing corresponding to each address. The value of the storage circuit 43 is digital-to-analog converted by the first and second D / A converters 441 and 442, and analog control signals for gain and phase are supplied to the gain control signal output terminal 443 and the phase control signal output terminal 444, respectively. Is output.
[0019]
An embodiment of the control circuit will be described with reference to FIG. When the output signal of the delay circuit 11 of FIG. 1 is input to the input terminal 51, the gain and phase are controlled by the gain control circuit 52 and the phase control circuit 53, respectively. Here, the gain control signal input terminal 524 and the phase control signal input terminal 533 correspond to the gain and phase control signal output terminals 443 and 444, respectively, in FIG. In the gain control, the amount of attenuation can be determined in consideration of the value of the resistor 523 by changing the resistance value according to the signal applied to the pin diodes 521 and 522. Further, the phase appearing at the output terminal 54 of the circulator 531 can be controlled by changing the bias voltage of the variable capacitance diode 532 with the phase control signal from the phase control input terminal 533. The method of gain control and phase control is not limited to the illustrated method, and any other method may be used. Further, when the phase distortion is small, the phase control can be omitted.
[0020]
Next, the calculation algorithm of the calculation circuit and the table content update processing of the storage circuit in the embodiment of the present invention will be described with reference to FIGS. The basic idea of the algorithm of the calculation circuit is to determine the table contents of the storage circuit by trial and error so as to minimize the out-of-band radiation power output from the second power meter.
[0021]
Assume that the address numbers of the memory circuit are k = 1 to K (that is, K = 2 ^M ). Here, the address number K is an address corresponding to a preset maximum output of the amplifier. Assume that as the value of k decreases, the output of the amplifier, and hence the input level of the amplifier, decreases. The table contents of the storage circuit are standardized so that the gain at k = K is 1 and the phase is 0 °, and this value is fixed through subsequent calculations. In the following description, the gain update algorithm will be described, but the same applies to the phase. The table contents are updated by simultaneously adding a small correction value given by a function (referred to as a correction function) illustrated in FIG. 6 to a table value corresponding to a plurality of addresses as follows. . FIG. 7 shows a flow of table update processing according to the embodiment of the present invention. The initial values of the table are assumed to be gain 1 and phase 0 ° for all addresses.
[0022]
In the calculation of the first stage, the half line a ₁ of the triangle corresponding to the address k = K / 2 to K of the memory circuit, the triangle b ₁ corresponding to k = _{1 to} K, and k = _{1 to} K / The height corresponding to each address of the straight line c ₁ corresponding to 2 is added to the initial value of the RAM contents. Here, the triangle height Δ ₁ is a small value arbitrarily selected. Δ ₁ assumes a positive or negative value. First, let Δ ₁ = | Δ ₁ | be added to the RAM contents f (k) (k = K / 2 to K−1) for the straight line a ₁ . At this time, the output power of the second power meter is P _{a + 1} . Next, the straight line a ₁ is added to the initial value as Δ ₁ = − | Δ ₁ |. The output power of the second power meter at this time is set to Pa _-1 . If P _{a + 1} > P _a−1 , it is determined that the contents of the RAM at this time are obtained by adding the value of the straight line a ₁ corresponding to Δ ₁ = − | Δ ₁ | to the initial value. This is the initial value for each calculation. Next, the same operation is performed for the phase. Also in the next round, performed on the same operation, so that the output power of the second power meter is reduced, g _a in the RAM contents f (k) (k = K / 2~K-1) Update by adding (k). Thereafter, the update is continued in the same manner. When the contents of the RAM are not substantially changed, the update relating to the straight line a ₁ is terminated.
[0023]
Next, with respect to the triangle b ₁ , the same update as that performed for the straight line a ₁ is continued with the contents f (k) (k = 1 to K−1) of the RAM so far as initial values. When this update is completed, the straight line c ₁ is similarly updated. When the update for the straight line c ₁ is completed, the same processing is performed from the beginning with the values given so far as initial values. When this is done a given number of times, the first stage update is completed.
[0024]
In the second stage update, the address area is divided into two parts, and the same update as in the first stage is continued for each of the areas. When the predetermined number of stages is reached, or when the area cannot be divided any more, the update procedure is finished.
[0025]
Thus, by simultaneously changing the table contents corresponding to a plurality of addresses of the storage circuit, the convergence time of the table contents can be shortened. The weighting method is not limited to a straight line, and for example, a quadratic curve or a Gaussian curve may be used.
[0026]
FIG. 8 shows a second embodiment of the memory circuit and the calculation circuit in the present invention. In this embodiment, a time adjustment circuit 745 is added to the configuration of the first embodiment shown in FIG. 4, and the other circuit portions are the same as those of the first embodiment. Therefore, the description here is limited to only the portion related to the time adjustment circuit 745.
[0027]
The purpose of the time adjustment circuit 745 is to appropriately set the timing of the control signal output from the control signal generation circuit 17 with respect to the time delay in the delay circuit 11 shown in FIG. The operation of the time adjustment circuit 745 in FIG. 8 will be described with reference to FIG. A portion of the control signal circuit that processes a digital signal (between the A / D converter 76 and the D / A converters 741 and 742 in FIG. 8) operates in the clock cycle T _s. . A control signal is output from the level interpolation circuit 740 every clock cycle T _s . When this signal is output as it is by the D / A converters 741 and 742, the control signal from the gain control signal output terminal 743 (170 in FIG. 1) and the phase control signal output terminal 744 (171 in FIG. 1) and the delay circuit 11 There may be a timing error between the output signals. Now, it is assumed that the optimal timing is shifted by Δτ from the clock time, and Δτ <T _S is assumed. If the clock cycle is sufficiently short, the control signal V _{opt at the} time shifted by Δτ is obtained by linear interpolation.
V _opt = V _n-1 + (V _n −V _n-1 ) × Δτ / T _S
Given in. By the way, the value of Δτ cannot actually be known. Therefore, this is determined by trial and error. For example, as Δτ = nΔT (ΔT is a sufficiently small time), n = 0, 1, 2,... Is changed, and the calculation circuit described so far is executed for each value of n, and the target out-of-band. It is possible to obtain n that minimizes the power.
[0028]
Here, if the time delay in the gain control circuit 120 cannot be ignored, the above operation may be performed separately in order to give a time difference to the gain and phase control signals.
[0029]
A third embodiment of the control signal generating circuit according to the present invention is shown in FIG. This embodiment shows another method for performing the time adjustment described above. The principle idea is that the timing of the clock signal of the calculation circuit and the storage circuit is changed relative to the time of the output signal of the first power meter (16 in FIG. 1), and the gain control signal output The signal output time of the terminal 991 and the phase control signal output terminal 992 is controlled.
[0030]
The output signal of the first power meter (not shown in FIG. 10) is input from the input terminal 91 to the sample and hold circuit 92. The sample hold circuit 92 takes in the value of the input signal at the time given by the clock signal 942 and temporarily holds it. The output of the sample hold circuit 92 is input to the A / D converter 93, and the output signal after A / D conversion gives the address of the storage circuit 96. The timing of the A / D converter 93 is determined by the clock signal 941. The clock signal 942 is given by inputting the clock signal 941 to the variable delay circuit 94. The variable delay circuit 94 changes the time delay amount by the control signal 943. The control signal 943 is output from the calculation circuit 95. The generation algorithm can be a trial and error method, for example, as in the second embodiment, so as to minimize the output of the second power meter (18 in FIG. 1). The detailed explanation is omitted. Other circuit portions of the present embodiment are the same as those of the above-described embodiment, so that no further description will be given.
[0031]
FIG. 11 shows an embodiment of the variable delay circuit 94 in the third embodiment. A clock signal 941 output from the calculation circuit 95 in FIG. 10 is input to the variable phase circuit 103 from the input terminal 104. The variable phase circuit 103 changes the phase by a control signal 943 input from the calculation circuit 95 via the control input terminal 105. Here, the circuit may have any configuration, and can be the same as the phase control circuit 53 shown in FIG. 5, for example.
[0032]
Since the output of the variable phase circuit 103 is normally sinusoidal, it is pulse-shaped by inputting it to the limiter circuit 102, and the clock signal 942 in the normal digital circuit is obtained at the output terminal 101. Here, the reason why the time delay can be changed by changing the phase is that the target signal is a periodic signal. This embodiment is particularly effective when the delay time is changed minutely.
[0033]
【The invention's effect】
The effect of improving the out-of-band power spectrum according to the present invention is shown in FIG. 12A shows an output signal spectrum before distortion correction, and FIG. 12B shows an output signal spectrum after distortion correction. INDUSTRIAL APPLICABILITY The present invention is excellent in power efficiency and circuit feasibility in a power amplifier, and has an effect of automatically performing nonlinear distortion compensation with a short convergence time. Further, according to the present invention, based on the principle of performing control so as to reduce the out-of-band power spectrum, errors in the first power measuring device, the gain control circuit, and the phase control circuit automatically change as the contents of the storage circuit. Since it is absorbed, there is an effect that these circuits can be easily realized. By these, it can contribute to the cost reduction of the base station radio | wireless machine of a motor vehicle and a mobile telephone system.
[Brief description of the drawings]
FIG. 1 is a principle configuration diagram of a nonlinear distortion compensating power amplifier according to the present invention.
FIG. 2 is a diagram illustrating the principle of a predistorter that compensates for nonlinear distortion according to the present invention.
FIG. 3 is an explanatory diagram of a signal power spectrum in the first embodiment of the present invention.
FIG. 4 is a configuration diagram of a first embodiment of a control signal generating circuit according to the present invention.
FIG. 5 is a configuration diagram of an embodiment of a control circuit according to the present invention.
FIG. 6 is an explanatory diagram of an algorithm of an embodiment of a calculation circuit according to the present invention.
FIG. 7 is a processing flow for updating table contents in the embodiment of the storage circuit according to the present invention;
FIG. 8 is a configuration diagram of a second embodiment of the control signal generating circuit according to the present invention.
FIG. 9 is an explanatory diagram of the operation principle of the time adjustment circuit.
FIG. 10 is a configuration diagram of a third embodiment of the control signal generating circuit according to the present invention.
FIG. 11 is a configuration diagram of an embodiment of a variable delay circuit in a third embodiment of the control signal generating circuit.
FIG. 12 is an explanatory diagram of an output signal spectrum showing the effect of nonlinear distortion compensation according to the present invention.
[Explanation of symbols]
10: input terminal 11: delay circuit 12: amplitude / phase control circuit 13: power amplifier 14: directional coupler 15: output terminal 16: first power meter 17: control signal generator circuit 18: second power measurement Unit 19: Band pass filter 20: Frequency conversion circuit 170: Gain control signal 171: Phase control signal 172: Storage circuit 173: Calculation circuit 200: Local signal generator 201: Multiplication circuit

Claims (8)

An amplitude / phase control circuit that corrects the input signal based on the control signal, a first power measuring device that detects the power of the input signal, and a corresponding control signal that is referred to by the detected power value of the input signal A storage circuit for storing a table for giving values; a control signal generating circuit for supplying a control signal to the amplitude / phase control circuit; a power amplifier connected to the output of the amplitude / phase control circuit; and an output signal of the power amplifier And a second power measuring device for detecting the power of the extracted signal component outside the effective band, and the control signal generation circuit includes a filter outside the effective band detected. based on the power values of the signal components, stores the contents of the table are at the effective out-of-band signal components of the nonlinear distortion compensating power amplifier that have a algorithm for updating such power is reduced I,
The algorithm adds a plurality of correction functions of positive and negative patterns having different heights, such as straight lines and triangles, to the initial value step by step, and the signal component outside the effective band for each step of the addition. A non-linear distortion compensating power amplifier characterized in that the power of the signal component of the signal component outside the effective band is reduced, and the power of the signal component is reduced . According to claim 1, before Symbol storage circuit, signals obtained samples and analog at a predetermined sampling frequency from the output of the first power meter - it is accessed by an address which is determined based on the value obtained by digital conversion A non-linear distortion compensation power amplifier characterized in that a value of a table read from the address is given as a control signal to the control signal generation circuit. 3. The nonlinear distortion compensating power amplifier according to claim 1, wherein a delay circuit is provided between the input terminal and the control circuit. 4. The nonlinear distortion compensation power amplifier according to claim 1, wherein when the contents of the table of the storage circuit are updated, contents corresponding to a plurality of addresses are simultaneously updated. 5. The nonlinear distortion compensating power amplifier according to claim 4, wherein the number of the plurality of addresses updated simultaneously is gradually decreased with time. 6. The time between the timing at which the storage circuit is accessed and the timing at which the control signal read from the storage circuit is supplied to the control signal generation circuit is optimally set. A non-linear distortion compensating power amplifier, characterized in that a time adjustment circuit is provided . 7. The nonlinear distortion compensating power amplifier according to claim 6, wherein the timing at which the time adjusting circuit gives the control signal to the control signal generating circuit is automatically set to an optimum by trial and error . 8. The control signal generation circuit according to claim 1, wherein the control signal generation circuit controls both the amplitude and the phase of the input signal, and separately performs the amplitude control operation and the phase control operation. A non-linear distortion compensating power amplifier characterized in that a time difference can be given between the control signal and the phase control signal .

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