JP3936681B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP3936681B2
JP3936681B2 JP2003208555A JP2003208555A JP3936681B2 JP 3936681 B2 JP3936681 B2 JP 3936681B2 JP 2003208555 A JP2003208555 A JP 2003208555A JP 2003208555 A JP2003208555 A JP 2003208555A JP 3936681 B2 JP3936681 B2 JP 3936681B2
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Prior art keywords
substrate
wire bonding
electrode pad
semiconductor device
bonding pad
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JP2004056137A (en
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茂 山田
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Oki Electric Industry Co Ltd
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Oki Electric Industry Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To improve the degree of freedom in the arrangement of a through-hole that passes through front and back sides of a substrate on which a semiconductor device is mounted. <P>SOLUTION: In a substrate 1 on which a semiconductor device 5 is mounted wherein a wire bonding pad 2 and an external electrode 10 are formed, respectively, on its front and back sides. These are electrically connected via a through-hole 3. By arranging the wire bonding pad 2 on the front side of the substrate 1 which corresponds to a region defined by the external electrode pad 10, the degree of freedom in the arrangement of the through-hole 3 is improved. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
この発明は、半導体装置、特に基板上に半導体素子の搭載される半導体装置に関する。
【従来の技術】
【０００２】
従来このような分野の技術としては、以下の構成の半導体装置がある。
すなわち、ガラスエポキシなどからなる基板上に半導体素子を搭載し、その半導体素子の電極と基板上に形成された内部電極とをワイヤを用いて接続されている。基板の裏面には外部電極用パッドおよびその上には外部電極が形成されている。この外部電極と配線とは基板に形成されたスルーホールを介して接続されている。
このような技術は特開平１０−２０９３２１号公報に開示されている。
【０００３】
【発明が解決しようとする課題】
しかしながら、上記文献に示されるような半導体装置においては、基板の表裏を電気的に接続するためのスルーホールは外部電極用パッドの部分には形成することができない。このため、内部電極の配置される位置によって、スルーホールを形成する位置が制約され、配線の引き回しが困難になるという課題がある。
【０００４】
また、半導体素子の大きさにあわせて基板を作らなければならず、基板の汎用性がなく、開発費用が高くなるという課題がある。
また、半導体素子と内部電極との距離が近いため半導体素子を基板に固定する際の接着剤が染み出し、内部電極を汚染してしまうという課題がある。
【０００５】
【課題を解決するための手段】
上記課題を解決するために本発明の半導体装置では、第１の表面と、この第１の表面と反対側の第２の表面とを有する基板と、第１の表面上に形成された外部電極パッドと、第２の表面上に形成され、基板の外周辺と実質的に平行に配置される第１の内部電極パッド群と、第１の内部電極パッド群よりも内側に配置される第２の内部電極パッド群と、基板の第２の表面に搭載され、第１あるいは第２の内部電極パッド群と電気的に接続される電極をその表面に備えた半導体素子とを備えた構成としている。
【０００６】
また、本願の他の発明によれば、第１の表面と、この第１の表面と反対側の第２の表面とを有する基板と、第１の表面上に形成された外部電極パッドと、第２の表面上に形成された内部電極パッド群と、第２の表面上に搭載され、内部電極パッド群と電気的に接続される電極を有する半導体素子と、半導体素子と前記内部電極パッド群との間に設けられたレジスト層とを有する構成としている。
【０００７】
【発明の実施の形態】
以下、本発明の第１の実施形態について図１〜図４を参照しながら説明する。図１は本発明の半導体装置の断面図、図２は図１に示される半導体装置の基板部分の透視図、図３は図２の部分拡大図、図４は図１の部分拡大図である。
【０００８】
図１、図２に示されるように、本実施形態の半導体装置は、基板１の表面にワイヤボンディングパッド２が形成されている。このワイヤボンディングパッド２は、基板１表面に銅箔を貼付け、パターニングすることにより形成される。このワイヤボンディングパッドは図示しない配線を介して基板の表裏を貫通するスルーホール３に接続される。基板１表面のワイヤボンディングパッドを除く領域はレジスト４で覆われている。
【０００９】
基板１表面の中央部には、半導体素子５が接着剤６により固定されている。この半導体素子５は、その表面に複数の電極パッド７を有している。半導体素子５の電極パッド７とワイヤボンディングパッド２とは金などからなるワイヤ８により接続される。
半導体素子５、ワイヤ８、ワイヤボンディングパッド２は、樹脂９により封止される。
【００１０】
一方、基板１の裏面には外部電極パッド１０が形成されている。この外部電極パッド１０は基板裏面に形成された配線１１、スルーホール３、基板４表面に形成された図示しない配線を介してワイヤボンディングパッド２と電気的に接続される。この外部電極パッド１０上には、はんだなどの電極１２が形成される。
【００１１】
この外部電極パッド１０は、基板１の外周辺に沿って列状に形成されている。図２においては、３列に形成されている。第１の実施形態では、この３列に配列された最外周の外部電極により定義される領域、すなわち、図２において破線で囲まれた領域１３に対応する基板４表面の領域にワイヤボンディングパッド２が配置されている。
【００１２】
その詳細が図３、図４に示される。図３は図１におけるａで囲まれる部分の拡大図である。図４は図２におけるｂで囲まれる部分の拡大図である。これらの図では、外部電極パッド１０により定義される領域の長さをＡ、ワイヤボンディングパッド２の長さをＢとして示されている。このように、ワイヤボンディングパッド２は、外部電極パッド１０により定義される領域に対応する基板１表面の領域内に形成されている。
【００１３】
このため、スルーホール３は、外部電極パッド１０により定義される領域１３と、この領域１３の内側に形成されている外部電極パッド１０により定義される領域を除く全ての領域に形成することが可能となる。
ワイヤボンディングパッド２を外部電極パッド１０により定義される領域に対応させて配置しているため、スルーホール３を形成できる範囲が広がり、配線の引き回しが行いやすくなる。このため、無理な配線を行うことも無くなり、基板の歩留りが向上する。
【００１４】
次に、図５〜図７を用いて本発明の第２の実施形態について説明する。
図５は本発明の第２の実施形態における半導体装置における基板を半導体素子搭載面側から見た上面図である。
【００１５】
この第２の実施形態では、基板２０上にワイヤボンディングパッド２１および２２が形成されている。ワイヤボンディングパッド２１は基板１の外周に沿って形成され、ワイヤボンディングパッド２２はワイヤボンディングパッド２１の内側に形成される。これらワイヤボンディングパッド２１とワイヤボンディングパッド２２とはそれぞれ配線２３により互いに接続されている。これらワイヤボンディングパッド２１、２２、配線２３は、基板２０表面に銅箔を貼付け、パターニングすることにより形成される。
【００１６】
このような基板２０を用いて製造した半導体装置の例が図６に示される。
図６において、半導体素子２５は内側のワイヤボンディングパッド２２上にレジスト２６を介して搭載されている。この半導体素子２５には複数の電極パッド２７が形成されていて、この電極パッド２７と外側のワイヤボンディングパッド２３とがワイヤ２８により電気的に接続されている。
【００１７】
また、図７では、内側のワイヤボンディングパッド２２の内側に半導体素子３０が搭載されている。この半導体素子３０の電極パッド３１と内側のワイヤボンディングパッド２２とがワイヤ３２により接続される。これにより、ワイヤの長さを必要以上に長くすることなく半導体素子３０の電極パッド３１をワイヤボンディングパッドに接続することができる。
【００１８】
このように、複数列に配置され、互いに電気的に接続されているワイヤボンディングパッド２１、２２を備えた基板１を用いることにより、半導体素子が大きい場合は外側のワイヤボンディングパッドを用い、半導体素子が小さい場合は内側のワイヤボンディングパッドを利用することができる。
【００１９】
これにより、基板の汎用性が向上し、開発コストを削減することが可能となる。
ここで、第２の実施形態においても第１の実施形態と同様に、外部電極パッド１０によって定義される領域に対応する基板２０表面の領域にワイヤボンディングパッド２１、２２を配置することが好ましい。このようにワイヤボンディングパッドを配置すると、スルーホール３を形成できる範囲が広がり、配線の引き回しが行いやすくなる。このため、無理な配線を行うことも無くなり、基板の歩留りが向上する。
【００２０】
次に、本発明の第３の実施形態について図８〜図９を参照しながら説明する。
図８に示されるように、本実施形態の半導体装置は、基板４０の表面にワイヤボンディングパッド４１が形成されている。このワイヤボンディングパッド４１は、基板４０表面に銅箔を貼付け、パターニングすることにより形成される。このワイヤボンディングパッドは図示しない配線を介して基板の表裏を貫通するスルーホール４２に接続される。基板４０表面のワイヤボンディングパッドを除く領域はレジスト４３で覆われている。
【００２１】
半導体素子４４とワイヤボンディングパッド４１との間のレジスト４３上には第２のレジスト４３’が形成されている。この第２のレジスト４３’は、半導体素子を取り囲むように形成される。
基板１表面の中央部には、半導体素子４４が接着剤４５により固定されている。この半導体素子４４は、その表面に複数の電極パッド４６を有している。半導体素子４４の電極パッド４６とワイヤボンディングパッド４１とは金などからなるワイヤ４７により接続される。
【００２２】
半導体素子４４、ワイヤ４７、ワイヤボンディングパッド４１は、樹脂４８により封止される。
一方、基板４０の裏面には外部電極パッド４９が形成されている。この外部電極パッド４９は基板裏面に形成された配線、スルーホール４２、基板４０表面に形成された図示しない配線を介してワイヤボンディングパッド４１と電気的に接続される。この外部電極パッド４９上には、はんだなどの電極５０が形成される。
【００２３】
このように、第２のレジスト４３’を形成することにより、接着剤４５が流れ出したり、染み出したりしてワイヤボンディングパッド４１を汚染することがなく、安定したワイヤ４７とワイヤボンディングパッド４１との接合が得られる。
また、組立工程で、ワイヤボンド前にワイヤボンディングパッド４１洗浄工程を入れる必要がないため、工程の簡略化、コスト削減も期待できる。さらに、段差がついているため、ワイヤ４７が垂れ下がることによる不良も低減することができる。
【００２４】
また、図９に示す半導体装置では、半導体素子４４とワイヤボンディングパッド４１との間のレジスト４３上には第２のレジスト５１が形成されている。また、ワイヤボンディングパッド４１の外側にも第２のレジスト５１が形成されている。これら第２のレジストは封止樹脂４８との密着性のよいエポキシ系の樹脂を用いる。
【００２５】
一般的にレジストは封止樹脂との密着性がよくない。このため、第２のレジストとして封止樹脂との密着性のよいエポキシ系の樹脂５１をレジストとして用いることにより、封止樹脂４８と基板４０との間の剥離を抑制することができる。
【発明の効果】
【００２６】
本発明の第１の実施形態によれば、ワイヤボンディングパッドを外部電極パッドにより定義される領域に対応させて配置しているため、スルーホールを形成できる範囲が広がり、配線の引き回しが行いやすくなる。このため、無理な配線を行うことも無くなり、基板の歩留りが向上する。
【００２７】
また、本発明の第２の実施形態によれば、複数列に配置され、互いに電気的に接続されているワイヤボンディングパッドを備えた基板を用いることにより、半導体素子が大きい場合は外側のワイヤボンディングパッドを用い、半導体素子が小さい場合は内側のワイヤボンディングパッドを利用することができる。これにより、基板の汎用性が向上し、開発コストを削減することが可能となる。
【００２８】
また、本発明の第３の実施形態によれば、接着剤が流れ出したり、染み出したりしてワイヤボンディングパッドを汚染することがなく、安定したワイヤとワイヤボンディングパッドとの接合が得られる。
【００２９】
また、組立工程で、ワイヤボンド前にワイヤボンディングパッド洗浄工程を入れる必要がないため、工程の簡略化、コスト削減も期待できる。さらに、段差がついているため、ワイヤが垂れ下がることによる不良も低減することができる。
【図面の簡単な説明】
【図１】本発明の第１の実施形態を示す図である。
【図２】本発明の第１の実施形態を示す図である。
【図３】本発明の第１の実施形態を示す図である。
【図４】本発明の第１の実施形態を示す図である。
【図５】本発明の第２の実施形態を示す図である。
【図６】本発明の第２の実施形態を示す図である。
【図７】本発明の第２の実施形態を示す図である。
【図８】本発明の第３の実施形態を示す図である。
【図９】本発明の第３の実施形態を示す図である。
【符号の説明】
１ 基板
２ ワイヤボンディングパッド
３ スルーホール
４ レジスト
５ 半導体素子
６ 接着剤
７ 電極パッド
８ ワイヤ
９ 樹脂
１０ 外部電極パッド
１１ 配線
１２ 電極[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a semiconductor element is mounted on a substrate.
[Prior art]
[0002]
Conventionally, as a technology in such a field, there is a semiconductor device having the following configuration.
That is, a semiconductor element is mounted on a substrate made of glass epoxy or the like, and an electrode of the semiconductor element and an internal electrode formed on the substrate are connected using a wire. An external electrode pad and an external electrode are formed on the back surface of the substrate. The external electrode and the wiring are connected through a through hole formed in the substrate.
Such a technique is disclosed in Japanese Patent Laid-Open No. 10-209321.
[0003]
[Problems to be solved by the invention]
However, in the semiconductor device as shown in the above document, a through hole for electrically connecting the front and back of the substrate cannot be formed in the external electrode pad portion. For this reason, the position where the through hole is formed is restricted by the position where the internal electrode is arranged, and there is a problem that it is difficult to route the wiring.
[0004]
Further, there is a problem that the substrate must be made in accordance with the size of the semiconductor element, the substrate is not versatile, and the development cost is high.
Further, since the distance between the semiconductor element and the internal electrode is short, there is a problem that the adhesive for fixing the semiconductor element to the substrate oozes out and contaminates the internal electrode.
[0005]
[Means for Solving the Problems]
In order to solve the above problems, in a semiconductor device of the present invention, a substrate having a first surface, a second surface opposite to the first surface, and an external electrode formed on the first surface A first internal electrode pad group formed on the second surface and disposed substantially parallel to the outer periphery of the substrate; and a second internal electrode pad group disposed on the inner side of the first internal electrode pad group. The internal electrode pad group and a semiconductor element mounted on the second surface of the substrate and having an electrode electrically connected to the first or second internal electrode pad group on the surface are provided. .
[0006]
According to another invention of the present application, a substrate having a first surface, a second surface opposite to the first surface, an external electrode pad formed on the first surface, An internal electrode pad group formed on the second surface; a semiconductor element having an electrode mounted on the second surface and electrically connected to the internal electrode pad group; and the semiconductor element and the internal electrode pad group And a resist layer provided between the two.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. 1 is a sectional view of a semiconductor device according to the present invention, FIG. 2 is a perspective view of a substrate portion of the semiconductor device shown in FIG. 1, FIG. 3 is a partially enlarged view of FIG. 2, and FIG. .
[0008]
As shown in FIGS. 1 and 2, in the semiconductor device of this embodiment, a wire bonding pad 2 is formed on the surface of a substrate 1. The wire bonding pad 2 is formed by attaching a copper foil to the surface of the substrate 1 and patterning it. This wire bonding pad is connected to a through hole 3 penetrating the front and back of the substrate through a wiring (not shown). The region excluding the wire bonding pad on the surface of the substrate 1 is covered with a resist 4.
[0009]
A semiconductor element 5 is fixed with an adhesive 6 at the center of the surface of the substrate 1. The semiconductor element 5 has a plurality of electrode pads 7 on its surface. The electrode pad 7 of the semiconductor element 5 and the wire bonding pad 2 are connected by a wire 8 made of gold or the like.
The semiconductor element 5, the wire 8, and the wire bonding pad 2 are sealed with a resin 9.
[0010]
On the other hand, external electrode pads 10 are formed on the back surface of the substrate 1. The external electrode pad 10 is electrically connected to the wire bonding pad 2 through the wiring 11 formed on the back surface of the substrate, the through hole 3, and the wiring (not shown) formed on the surface of the substrate 4. An electrode 12 such as solder is formed on the external electrode pad 10.
[0011]
The external electrode pads 10 are formed in a row along the outer periphery of the substrate 1. In FIG. 2, it is formed in three rows. In the first embodiment, the wire bonding pad 2 is formed on the region defined by the outermost outer electrodes arranged in the three rows, that is, on the surface of the substrate 4 corresponding to the region 13 surrounded by the broken line in FIG. Is arranged.
[0012]
The details are shown in FIGS. FIG. 3 is an enlarged view of a portion surrounded by a in FIG. FIG. 4 is an enlarged view of a portion surrounded by b in FIG. In these drawings, the length of the region defined by the external electrode pad 10 is shown as A, and the length of the wire bonding pad 2 is shown as B. Thus, the wire bonding pad 2 is formed in a region on the surface of the substrate 1 corresponding to a region defined by the external electrode pad 10.
[0013]
Therefore, the through hole 3 can be formed in all regions except the region 13 defined by the external electrode pad 10 and the region defined by the external electrode pad 10 formed inside the region 13. It becomes.
Since the wire bonding pad 2 is disposed in correspondence with the region defined by the external electrode pad 10, the range in which the through hole 3 can be formed is widened, and the wiring can be easily routed. This eliminates excessive wiring and improves the yield of the substrate.
[0014]
Next, a second embodiment of the present invention will be described with reference to FIGS.
FIG. 5 is a top view of the substrate in the semiconductor device according to the second embodiment of the present invention as viewed from the semiconductor element mounting surface side.
[0015]
In the second embodiment, wire bonding pads 21 and 22 are formed on the substrate 20. The wire bonding pad 21 is formed along the outer periphery of the substrate 1, and the wire bonding pad 22 is formed inside the wire bonding pad 21. The wire bonding pad 21 and the wire bonding pad 22 are connected to each other by a wiring 23. The wire bonding pads 21 and 22 and the wiring 23 are formed by attaching a copper foil to the surface of the substrate 20 and patterning it.
[0016]
An example of a semiconductor device manufactured using such a substrate 20 is shown in FIG.
In FIG. 6, the semiconductor element 25 is mounted on the inner wire bonding pad 22 via a resist 26. A plurality of electrode pads 27 are formed on the semiconductor element 25, and the electrode pads 27 and the outer wire bonding pads 23 are electrically connected by wires 28.
[0017]
In FIG. 7, the semiconductor element 30 is mounted inside the inner wire bonding pad 22. The electrode pad 31 of the semiconductor element 30 and the inner wire bonding pad 22 are connected by a wire 32. Thereby, the electrode pad 31 of the semiconductor element 30 can be connected to the wire bonding pad without making the length of the wire longer than necessary.
[0018]
In this way, by using the substrate 1 provided with the wire bonding pads 21 and 22 arranged in a plurality of rows and electrically connected to each other, the outer wire bonding pad is used when the semiconductor element is large. If is small, the inner wire bonding pad can be used.
[0019]
Thereby, the versatility of the substrate is improved, and the development cost can be reduced.
Here, also in the second embodiment, it is preferable to arrange the wire bonding pads 21 and 22 in the region of the surface of the substrate 20 corresponding to the region defined by the external electrode pad 10 as in the first embodiment. When the wire bonding pads are arranged in this way, the range in which the through hole 3 can be formed is widened, and the wiring can be easily routed. This eliminates excessive wiring and improves the yield of the substrate.
[0020]
Next, a third embodiment of the present invention will be described with reference to FIGS.
As shown in FIG. 8, in the semiconductor device of this embodiment, a wire bonding pad 41 is formed on the surface of the substrate 40. The wire bonding pad 41 is formed by attaching a copper foil to the surface of the substrate 40 and patterning it. This wire bonding pad is connected to a through hole 42 penetrating the front and back of the substrate through a wiring (not shown). A region excluding the wire bonding pad on the surface of the substrate 40 is covered with a resist 43.
[0021]
A second resist 43 ′ is formed on the resist 43 between the semiconductor element 44 and the wire bonding pad 41. The second resist 43 ′ is formed so as to surround the semiconductor element.
A semiconductor element 44 is fixed by an adhesive 45 at the center of the surface of the substrate 1. The semiconductor element 44 has a plurality of electrode pads 46 on its surface. The electrode pad 46 of the semiconductor element 44 and the wire bonding pad 41 are connected by a wire 47 made of gold or the like.
[0022]
The semiconductor element 44, the wire 47, and the wire bonding pad 41 are sealed with a resin 48.
On the other hand, external electrode pads 49 are formed on the back surface of the substrate 40. The external electrode pad 49 is electrically connected to the wire bonding pad 41 via a wiring formed on the back surface of the substrate, a through hole 42, and a wiring (not shown) formed on the surface of the substrate 40. An electrode 50 such as solder is formed on the external electrode pad 49.
[0023]
In this way, by forming the second resist 43 ′, the adhesive 45 does not flow out or ooze out to contaminate the wire bonding pad 41, and the stable wire 47 and the wire bonding pad 41 can be formed. Bonding is obtained.
In addition, since it is not necessary to insert a wire bonding pad 41 cleaning process before wire bonding in the assembly process, the process can be simplified and cost can be reduced. Furthermore, since there is a step, defects due to the wire 47 hanging down can be reduced.
[0024]
In the semiconductor device shown in FIG. 9, a second resist 51 is formed on the resist 43 between the semiconductor element 44 and the wire bonding pad 41. A second resist 51 is also formed outside the wire bonding pad 41. For these second resists, an epoxy resin having good adhesion to the sealing resin 48 is used.
[0025]
In general, the resist does not have good adhesion to the sealing resin. For this reason, peeling between the sealing resin 48 and the substrate 40 can be suppressed by using, as the resist, the epoxy resin 51 having good adhesion to the sealing resin as the second resist.
【The invention's effect】
[0026]
According to the first embodiment of the present invention, since the wire bonding pads are arranged so as to correspond to the regions defined by the external electrode pads, the range in which the through holes can be formed is widened, and the wiring can be easily routed. . This eliminates excessive wiring and improves the yield of the substrate.
[0027]
In addition, according to the second embodiment of the present invention, by using a substrate having wire bonding pads arranged in a plurality of rows and electrically connected to each other, the outer wire bonding is performed when the semiconductor element is large. If a pad is used and the semiconductor element is small, an inner wire bonding pad can be used. Thereby, the versatility of the substrate is improved, and the development cost can be reduced.
[0028]
Further, according to the third embodiment of the present invention, a stable bonding between the wire and the wire bonding pad can be obtained without causing the adhesive to flow out or ooze out and contaminate the wire bonding pad.
[0029]
Further, since it is not necessary to perform a wire bonding pad cleaning process before wire bonding in the assembly process, it is possible to expect simplification of the process and cost reduction. Furthermore, since there is a step, defects due to the wire hanging down can be reduced.
[Brief description of the drawings]
FIG. 1 is a diagram showing a first embodiment of the present invention.
FIG. 2 is a diagram showing a first embodiment of the present invention.
FIG. 3 is a diagram showing a first embodiment of the present invention.
FIG. 4 is a diagram showing a first embodiment of the present invention.
FIG. 5 is a diagram showing a second embodiment of the present invention.
FIG. 6 is a diagram showing a second embodiment of the present invention.
FIG. 7 is a diagram showing a second embodiment of the present invention.
FIG. 8 is a diagram showing a third embodiment of the present invention.
FIG. 9 is a diagram showing a third embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Substrate 2 Wire bonding pad 3 Through hole 4 Resist 5 Semiconductor element 6 Adhesive 7 Electrode pad 8 Wire 9 Resin 10 External electrode pad 11 Wiring 12 Electrode

Claims (3)

第１の表面と、この第１の表面と反対側の第２の表面とを有する基板と、
前記第１の表面上に形成され、この基板の外周辺に沿って配置された第１の外部電極パッド群と、前記第１の外部電極パッド群よりも内側に配置された第２の外部電極パッド群と、
前記第２の表面上に形成され、前記基板の外周辺に沿って配置された第１の内部電極パッド群と、前記第１の内部電極パッド群よりも内側に配置された第２の電極パッド群と、
前記基板の前記第２の表面に搭載され、前記第１あるいは第２の内部電極パッド群と電気的に接続される電極をその表面に備えた半導体素子とを備え、
前記複数の第１の内部電極パッド群の全てが、前記第１の外部電極パッド群により前記第１の表面上に規定される第１の領域に対応するように前記第２の表面に規定される第２の領域内に配置され、
前記複数の第２の内部電極パッド群の全てが、前記第２の外部電極パッド群により前記第１の表面上に規定される第３の領域に対応するように前記第２の表面に規定される第４の領域内に配置されることを特徴とする半導体装置。A substrate having a first surface and a second surface opposite the first surface;
A first external electrode pad group formed on the first surface and disposed along the outer periphery of the substrate, and a second external electrode disposed on the inner side of the first external electrode pad group A group of pads;
A first internal electrode pad group formed on the second surface and disposed along the outer periphery of the substrate, and a second electrode pad disposed on the inner side of the first internal electrode pad group Group,
A semiconductor element mounted on the second surface of the substrate and having an electrode electrically connected to the first or second internal electrode pad group on the surface;
All of the plurality of first internal electrode pad groups are defined on the second surface so as to correspond to a first region defined on the first surface by the first external electrode pad group. In the second region,
All of the plurality of second internal electrode pad groups are defined on the second surface so as to correspond to a third region defined on the first surface by the second external electrode pad group. The semiconductor device is arranged in a fourth region. 前記半導体装置は前記第２の内部電極パッド群の内側に配置され、前記半導体装置の前記電極は、前記第２の内部電極パッド群に接続されることを特徴とする請求項１記載の半導体装置。  2. The semiconductor device according to claim 1, wherein the semiconductor device is disposed inside the second internal electrode pad group, and the electrode of the semiconductor device is connected to the second internal electrode pad group. . 前記半導体装置は前記第２の内部電極パッド群上に絶縁層を介して搭載され、前記半導体装置の前記電極は前記第１の内部電極パッド群に接続されることを特徴とする請求項１記載の半導体装置。  2. The semiconductor device is mounted on the second internal electrode pad group via an insulating layer, and the electrode of the semiconductor device is connected to the first internal electrode pad group. Semiconductor device.
JP2003208555A 2003-08-25 2003-08-25 Semiconductor device Expired - Fee Related JP3936681B2 (en)

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