JP3934919B2 - Mask blank selection method, exposure mask formation method, and semiconductor device manufacturing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for selecting a mask blank for manufacturing a semiconductor, a method for forming an exposure mask, and a method for manufacturing a semiconductor device.
[0002]
[Prior art]
Conventionally, mask blanks (hereinafter simply referred to as “blanks”) used when producing exposure masks of the same standard are the same standard. The defect standard of blanks is loose compared to the defect standard required for the exposure mask, and even if the blanks are within the same defect standard, the variation of the defect is large.
[0003]
Such blank defect variations cause an increase in the defect yield variation of the exposure mask. For example, the latter exposure mask is used between an exposure mask for a pattern having a relatively small processing area, such as a CH mask, and an exposure mask for a pattern having a relatively large processing area, such as an L / S mask. However, the variation in defect yield increases.
[0004]
Such an increase in the variation in the defect yield of the exposure mask causes an increase in manufacturing cost. Therefore, in recent years, there is a strong demand for suppressing an increase in manufacturing costs caused by blanks. In particular, since it is more difficult to reduce defects in halftone blanks than in Cr blanks, an increase in the variation in the defect yield of the exposure mask is remarkable.
[0005]
[Problems to be solved by the invention]
As described above, even if the conventional blanks are within the same defect standard, the variation in defects is large, leading to an increase in the variation in the defect yield of the exposure mask, and as a result, there is a mask with a significantly low defect yield. There's a problem.
[0006]
The present invention has been made in view of the above circumstances, and the object of the present invention is to provide a mask blank selection method and exposure mask formation that can suppress an increase in the variation in the exposure yield of the exposure mask due to the mask blanks. A method and a method for manufacturing a semiconductor device are provided.
[0007]
[Means for Solving the Problems]
Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows. That is, in order to achieve the above object, a mask blank selection method according to the present invention includes a step of preparing a plurality of mask blanks and defect information of the plurality of mask blanks, pattern data of a given semiconductor device, A step of selecting a mask blank to form a pattern corresponding to the given pattern data of the semiconductor device from the plurality of mask blanks based on defect information, and each of the plurality of mask blanks The yield of an exposure mask obtained by forming a pattern corresponding to the pattern data of the given semiconductor device on the mask blanks is calculated based on the defect information and the pattern data of the given semiconductor device, The calculated yield value is a desired value. The upper mask blank is selected, and the relationship between the defect size and the number of defects that can occur on the mask blank and the relationship between the defect size and the defect correction rate are obtained in advance for each of a plurality of semiconductor device patterns. And determining the number of uncorrectable defects of the semiconductor device pattern corresponding to the given semiconductor device pattern data based on the relationship, and calculating the yield based on the determined number of defects. It is characterized by having.
[0008]
Here, the pattern data of the semiconductor device includes pattern data of a structure that does not constitute a direct element such as an element isolation trench in addition to pattern data of an element such as a MOS transistor.
[0009]
A method for forming an exposure mask according to the present invention is characterized in that a mask blank is selected by the mask blank selection method according to the present invention, and a pattern is formed on the selected mask blank.
[0010]
A method for manufacturing a semiconductor device according to the present invention is characterized in that a pattern is formed on a semiconductor substrate using the method for forming an exposure mask according to the present invention.
[0011]
According to the present invention, a mask blank suitable for a pattern to be formed can be selected from a plurality of mask blanks that have been treated as having the same standard. As a result, it is possible to reduce the influence of variations in defects of a plurality of mask blanks treated as having the same standard. Therefore, according to the present invention, it is possible to realize a mask blank selection method, an exposure mask forming method, and a semiconductor device manufacturing method capable of suppressing an increase in variation in the defect yield of the exposure mask due to the mask blank.
[0012]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings.
[0014]
(First embodiment)
FIG. 1 is a diagram showing a flow from ordering to completion of an exposure mask (hereinafter simply referred to as a mask) according to the first embodiment of the present invention.
[0015]
The mask orderer 1 orders a mask from the mask manufacturer 2 (step S1). At this time, the mask orderer 1 provides the mask manufacturer 2 with information necessary for mask creation such as mask drawing data.
[0016]
The mask manufacturer 2 places an order for blanks necessary for creating the mask from the blank manufacturer 3 (step S2).
[0017]
The blanks maker 3 creates a plurality of blanks of the same standard for creating the mask, and inspects the size, size, and position of the defect for each of these blanks (step S3). And based on the inspection result, a plurality of blanks are classified according to defect rank. The defects are particles and pinholes. The ranking is performed based on the defect size and the number of defects. The blanks may have a resist or may have no resist.
[0018]
The blanks maker 3 delivers the ranked blanks (blanks and defect information) to the mask maker 2 (step S4).
[0019]
The mask manufacturer 2 selects blanks having a defect rank (quality rank) necessary for creating a mask ordered from the mask orderer 1 from among the ranked blanks (step S5). Here, blanks are divided into the following four defect ranks A, B, C, and D.
[0020]
Defect rank A: S ≦ 10, M = 0, L = 0 Defect rank B: S ≦ 20, M = 0, L = 0 Defect rank C: S ≦ 30, M ≦ 10 L ≦ 5 defect rank D: S ≦ 40, M ≦ 10, L ≦ 5 S is a defect having a size of 0.3 μm or more and less than 1 μm,
M is a defect having a size of 1 μm or more and less than 2 μm,
L is a defect of size: 2 μm or more and less than 4 μm.
[0021]
The blanks with defect rank A have the fewest defects, the blanks with defect rank D have the most defects, and some of the defects have a larger size than the blanks with defect rank A. However, even if blanks with defect rank D are used, it is possible to create a pattern having a necessary standard.
[0022]
Therefore, the defect ranks A to D are associated with patterns that can be created. An example of the result is shown in the lower part of FIG. The association is performed based on experiments or a database. The above association is performed by the mask manufacturer 2 or the blanks manufacturer 3. When the blanks maker 3 performs, the above correspondence is also delivered to the mask maker 2. Furthermore, it is possible for the mask manufacturer 2 to acquire defect information. In this case, the blanks maker 3 only delivers the blanks to the mask maker 2 as in the prior art.
[0023]
The pattern of the semiconductor device to be formed is known from the mask drawing data provided from the mask orderer 1. The mask maker 2 selects blanks corresponding to the pattern. For example, if the pattern to be formed is a memory LSI and is a dense line & space pattern, blanks with defect rank A are selected.
[0024]
Thereafter, a pattern is drawn on the selected blank based on the mask drawing data to create a mask (step S6). The mask created in this way is delivered to the mask orderer 1. Then, the mask orderer 1 forms a semiconductor device pattern on the semiconductor substrate using the mask.
[0025]
Conventionally, all blanks having defect ranks A to D are selected. This is because blanks with defect ranks A to D are treated as being within the same standard. Therefore, for example, when a dense line & space pattern is formed by a memory LSI, blanks having defect ranks B to D that do not reach the required defect level (quality level) are also selected, so that variations in the defect yield of the mask can be achieved. Will increase.
[0026]
On the other hand, in the case of the present embodiment, since only blanks that have reached the required defect level (quality level) are selected, the variation in the defect yield of the mask is reduced. Thereby, the raise of the manufacturing cost resulting from blanks can be suppressed. Further, TAT (Turn Around Time) can be shortened.
[0027]
Furthermore, in the above example, blanks of defect ranks B to D that are not selected are not wasted by being used when creating a mask having a pattern corresponding to these.
[0028]
In the present embodiment, the defect levels of blanks are classified into four types, but may be classified into two or more types for each defect level and each drawing pattern.
[0029]
(Second Embodiment)
FIG. 2 is a diagram showing a flow from ordering to completion of a mask according to the second embodiment of the present invention. 1 corresponding to those in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and detailed description thereof is omitted.
[0030]
This embodiment is different from the first embodiment in that the mask orderer on the blanks delivered from the blanks manufacturer 3 based on the blanks delivered from the blanks manufacturer 3 and the defect information (defect size, defect coordinates). The mask yield (defect yield) when a pattern corresponding to the mask drawing data provided from 1 is formed is calculated, and only those whose values are greater than or equal to a predetermined value (here, 50% or more) are selected. .
[0031]
Here, 50% is selected as the predetermined value, but any value that can improve variation in the defect yield of the mask may be used. Further, the defect information may be acquired by the mask manufacturer 3.
[0032]
Also in this embodiment, since only blanks that have reached the required defect level can be selected, variation in the defect yield of the mask can be prevented and the manufacturing cost due to blanks can be increased, as in the first embodiment. Can be suppressed. Also, blanks that are not selected can be used to create masks of other patterns with a lower required defect level, and therefore are not wasted.
[0033]
(Third embodiment)
In the present embodiment, an example of a defect yield calculation method will be described. FIGS. 3 and 4 show examples of classification of black defects and white defects in a mask on which an L / S pattern (L: S = 1: 1, line width on mask is 0.64 μm) is formed. 3 and 4, the black defect and the white defect are classified into four types, respectively.
[0034]
FIG. 5 shows the relationship between the size of each black defect and the defect occurrence rate, and FIG. 6 shows the size of each black defect and the corrected NG rate (the number of black defects that failed to be corrected / number of corrected black defects). The relationship is shown respectively. FIG. 7 shows the relationship between the size of various white defects and the defect occurrence rate, and FIG. 8 shows the size of various white defects and the corrected NG rate. The defect occurrence rate and the corrected NG rate are obtained by calculation, database, experiment, or a combination thereof.
[0035]
The defect killer rate can be derived by multiplying the defect occurrence probability (FIGS. 5 and 7) and the corrected NG rate (FIGS. 6 and 8). FIG. 9 and FIG. 10 show the relationship between the defect size of the black defect and the white defect and the defect killer rate in the 1: 1 L / S (dense L / S) pattern, respectively.
[0036]
In addition to the 1: 1 L / S pattern, black defects and white defects in a mask in which a 1: 3 L / S pattern (line width on the mask: 0.64 μm) and an isolated CH pattern (diameter: 1 μm, pitch: 10 μm) are formed. The defect killer rate is shown in FIG. 11 and FIG. The defect occurrence rate and the corrected NG rate are obtained by calculation, database, experiment, or a combination thereof.
[0037]
Next, in order to express the difference in the pattern in the mask surface, specifically, the difference in the local processing area, for example, a mask with a side of 152 mm is divided into a 1000 μm mesh, Obtain the in-plane distribution of the white area ratio.
[0038]
An example is shown in FIG. Here, a black (white isolated) region (isolated CH region) having a white area ratio of 0% to 30%, a dense region (dense L / S region) from 30% to 70%, and from 70% to 100% The white (black isolated) region (isolated L / S region) was classified into three types. FIG. 13 also shows defect coordinate distribution by size of blanks defects (particles, pinholes) (particles 2.0 μm, particles 1.5 μm, pinholes 0.5 μm, pinholes 0.3 μm). Here, only the pinhole 0.3 μm exists outside the main body pattern region.
[0039]
Next, from FIG. 11 and FIG. 12, the defect killer rate of each of the above defects is obtained. In the example of FIG. 13, since the particle 2.0 μm exists in the isolated L / S region, the defect killer rate is 0.02 from FIG. 11, and the particle 1.5 μm exists in the dense L / S region. The defect killer rate is 0.40 from FIG. 11 and the pinhole 0.5 μm exists in the isolated L / S region. Therefore, the defect killer rate is 0.25 from FIG. 12, and the pinhole 0.3 μm is the main body pattern region. Since it exists outside, the defect killer rate becomes zero. Therefore, the sum of the defect killer rates (number of killer defects) λ of each defect is 0.02 + 0.40 + 0.25 + 0 = 0.67.
[0040]
From the relationship between the number of killer defects λ and the defect-free yield Y shown in FIG. 14, it can be seen that Y = 51% when λ = 0.67. That is, when λ = 0.67, the defect-free yield of the mask is 51%.
[0041]
In the present embodiment, the resolution of the defect coordinates is 1000 μm, and the mask mesh division size for representing the difference in the pattern in the mask plane is 1000 μm from the relationship between the alignment accuracy of the blanks defect inspection coordinates and the mask drawing coordinates. However, the mask division mesh may be changed to an arbitrary value equal to or less than the length of one side of the blanks in accordance with the defect coordinate distribution resolution and the alignment accuracy by size.
[0042]
In the present embodiment, the white area ratio per unit area is calculated in order to express the difference in the pattern in the mask plane. However, the white area ratio per unit area may be calculated in consideration of the length of the side. This makes it possible to distinguish between an isolated monochrome pattern (a pattern in which one of the left and right is entirely white and the other is entirely black) and a dense monochrome pattern (a pattern in which white and black are arranged alternately) in the same white area ratio. Yield calculation with high accuracy is possible.
[0043]
In this embodiment, the area is classified into three types (isolated L / S area, dense L / S area, and isolated CH area), but may be classified into two or more types.
[0044]
In the present embodiment, the defect sizes are classified into four types (2.0 μm, 1.5 μm, 0.5 μm, and 0.3 μm), but may be classified into two or more arbitrary sizes.
[0045]
Further, in this embodiment, the probability of defect-free yield (when the number of defects after correction is zero) is obtained. However, when there are a certain number of defects or less from the Poisson distribution (there is a defect that cannot be corrected, or correction). If there is a defect that has failed, the probability may be obtained.
[0046]
The above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, if the problem described in the column of the problem to be solved by the invention can be solved, the configuration in which this constituent requirement is deleted Can be extracted as an invention. Further, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.
[0047]
【The invention's effect】
As described above in detail, according to the present invention, it is possible to realize a mask blank selection method, a mask manufacturing method, and a semiconductor device manufacturing method capable of suppressing an increase in the defect yield of an exposure mask due to mask blanks.
[Brief description of the drawings]
FIG. 1 is a diagram showing a flow from ordering to completion of a mask according to a first embodiment of the present invention. FIG. 2 is a diagram showing a flow from ordering to completion of a mask according to a second embodiment of the present invention. FIG. 3 is a diagram showing an example of classification of black defects. FIG. 4 is a diagram showing an example of classification of white defects. FIG. 5 is a diagram showing the relationship between the size of various black defects and the defect occurrence rate in the L / S pattern. FIG. 7 is a diagram showing the relationship between the size of various black defects in the L / S pattern and the corrected NG rate. FIG. 7 is a diagram showing the relationship between the size of various white defects and the defect occurrence rate in the L / S pattern. FIG. 9 is a diagram showing the relationship between the size of various white defects in the S pattern and the corrected NG rate. FIG. 9 is a diagram showing the relationship between the size of various black defects and the defect killer rate in the L / S pattern. Showing the relationship between the size of various white defects and the defect killer rate FIG. 11 is a diagram showing the relationship between black defect size and defect killer rate in various patterns. FIG. 12 is a diagram showing the relationship between white defect size and defect killer rate in various patterns. FIG. FIG. 14 is a diagram showing the in-plane distribution, defect distribution, and defect size of the white area ratio in the mesh region. FIG. 14 is a diagram showing the relationship between the number of killer defects and the defect-free yield.
1 ... Mask orderer 2 ... Mask manufacturer 3 ... Blanks manufacturer

Claims (3)

Preparing a plurality of mask blanks and defect information of the plurality of mask blanks;
The step of selecting a mask blank for forming a pattern corresponding to the given pattern data of the semiconductor device from the plurality of mask blanks based on the given pattern data of the semiconductor device and the defect information. Then, for each of the plurality of mask blanks, the yield of the exposure mask obtained by forming a pattern corresponding to the pattern data of the given semiconductor device on the mask blanks, the defect information, and the given semiconductor Calculated based on device pattern data, selects a mask blank whose calculated yield value is equal to or greater than a desired value, and a defect size that can occur on the mask blank for each of a plurality of semiconductor device patterns Relationship with the number of defects and defect support The number of defects in the semiconductor device pattern corresponding to the given semiconductor device pattern data is determined based on the relationship and the defect correction rate. And a step of calculating the yield based on the method. A method for selecting mask blanks, comprising: A mask blank is selected by the mask blank selection method according to claim 1, and a pattern is formed on the selected mask blank. An exposure mask is formed by the exposure mask forming method according to claim 2, and a pattern is formed on a semiconductor substrate using the exposure mask.

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