JP3934494B2 - Delay line - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a delay line that is used in an optical module, a digital communication device, or the like and delays signal transmission.
[0002]
[Prior art]
Conventionally, a delay line used in an optical module, a digital communication device, or the like has a configuration in which a coaxial line is wound in a coil shape, and a signal transmission delay time is obtained by its total length.
[0003]
In this case, since the coaxial line is wound in a coil shape, its diameter and length are relatively large, which is an obstacle to high integration.
[0004]
Therefore, conventionally, as a delay line, for example, a ground electrode is formed almost entirely on the lower surface of a low dielectric constant substrate such as an alumina substrate, and a linear strip line or a meander-shaped strip is formed on the upper surface of the substrate. Lines have been proposed (see JP-A-1-143403, JP-A-2937421, JP-A-3072845, JP-A-4-46405).
[0005]
According to the delay line using the strip line, the delay line can be made smaller than the delay line using the coaxial line, the length of the delay line can be formed with high accuracy, and the delay time of signal transmission can be increased with high accuracy. Can be adjusted.
[0006]
[Problems to be solved by the invention]
Incidentally, the delay time T of signal transmission by the delay line is determined by the line length L and the dielectric constant ε, as is apparent from the following relational expression.
T = √ε · L / c (speed of light)
[0007]
Therefore, in order to realize a delay time of 1 nsec using, for example, a low dielectric constant substrate having a dielectric constant ε = 7 in the delay line by the above-described stripline, a stripline length of 100 mm is necessary, and the size is inevitably increased. There's a problem.
[0008]
Therefore, in order to achieve the miniaturization of the delay line by the strip line, it can be considered that (1): a dielectric substrate having a high dielectric constant is used, and (2): the strip lines are stacked in multiple layers.
[0009]
Simply stacking strip lines in multiple layers is disadvantageous for miniaturization because the size increases in the vertical direction, and there is a problem that loss due to conductor loss must be considered. There is a possibility that significant miniaturization can be realized by using a substrate together.
[0010]
However, when a dielectric substrate having a high dielectric constant is used, there is a new problem that electromagnetic coupling between strip lines becomes strong and a desired delay time cannot be obtained.
[0011]
In this case, it is conceivable to increase the distance between the strip lines, but the size increases in the vertical direction, which is disadvantageous in miniaturization.
[0012]
The present invention has been made in view of such problems, and an object thereof is to provide a delay line that can achieve both low loss and downsizing.
[0013]
[Means for Solving the Problems]
In the delay line according to the present invention, a ground electrode is formed on a dielectric substrate formed by laminating a plurality of dielectric layers, and the strip lines are electrically connected to the strip lines in the dielectric substrate. Among the plurality of strip lines, the dielectric constant between the strip line adjacent to the ground electrode and the ground electrode is εa, and the via hole is coupled, and the ground electrode is not sandwiched therebetween. When the dielectric constant between strip lines is εb, εa ≧ εb is satisfied.
[0014]
First, in the relational expression T = √ε · L / c (speed of light) that determines the signal transmission delay time T, one of the variables, the dielectric constant ε is the dielectric constant between the stripline and the ground electrode.
[0015]
When an earth electrode is formed on at least one surface of the dielectric substrate and a plurality of strip lines are arranged in the dielectric substrate, the effective dielectric constant substantially relating to the signal transmission delay time is the dielectric constant described above. It is determined by the rate εa.
[0016]
In the present invention, since the dielectric constant εa substantially relating to the delay time of signal transmission can be set high, when obtaining a desired delay time, the effective dielectric constant is compared with the conventional one using a low dielectric constant substrate. Will increase.
[0017]
Therefore, in comparison with a conventional delay line using a low dielectric constant substrate, when a strip line having the same line width is considered, the present invention can be realized with a short strip line, which contributes to miniaturization. Become. Further, the conductor loss is reduced by shortening the strip line, and signal attenuation on the delay line can be suppressed.
[0018]
In addition, since the dielectric constant εb between the strip lines coupled by the via hole can be set lower than the above-mentioned dielectric constant εa, it becomes possible to suppress interference (electromagnetic coupling) between the strip lines. This eliminates the need to increase the distance between strip lines. This is advantageous for downsizing.
[0019]
Thus, in the present invention, both low loss and downsizing can be achieved.
[0020]
And in the said structure, an earth electrode is each formed in the at least 2 surface inside and outside of the said dielectric substrate, It has two strip lines between these earth electrodes, and the via hole which electrically connects these strip lines. The dielectric constant of the dielectric layer between the one stripline and the ground electrode adjacent to the one stripline is εa1, and the dielectric constant of the dielectric layer between the other stripline and the ground electrode adjacent to the other stripline is If the dielectric constant is εa2, and the dielectric constant between strip lines connected by the via hole is εb, εa1 ≧ εb and εa2 ≧ εb may be satisfied.
[0021]
In this case, when an earth electrode is formed on each of at least two surfaces of the dielectric substrate and two strip lines are arranged between the earth electrodes, the effective dielectric constant substantially related to the signal transmission delay time is as described above. It is determined by dielectric constants εa1 and εa2.
[0022]
In the present invention, the dielectric constants εa1 and εa2 that are substantially related to the delay time of signal transmission can be set high. Therefore, when obtaining a desired delay time, it is more effective than the conventional one using a low dielectric constant substrate. The dielectric constant increases, and the area of the entire delay line can be reduced accordingly. In this case, εa1 = εa2 ≧ εb may be satisfied.
[0023]
In the delay line according to the prior art, the strip line formed in the dielectric substrate is formed so as to be sandwiched between a plurality of ground electrodes. In the delay line, crosstalk between strip lines can be reduced, but the ground electrode is close to the strip line. For this reason, the characteristic impedance of the strip line is reduced, and the width of the strip line needs to be reduced in design. Therefore, when the width of the stripline is narrowed, there is a possibility that loss due to the conductor loss of the stripline increases.
[0024]
Therefore, a delay line according to the present invention includes a plurality of ground electrodes formed in a dielectric substrate formed by laminating a plurality of dielectric layers, and a plurality of strip lines formed in the dielectric substrate. Each of the strip lines is composed of a strip line not sandwiched between the ground electrodes and a strip line sandwiched between at least two ground electrodes. It is characterized by having.
[0025]
In this case, the cross line between the strip lines is reduced by the strip line sandwiched between the two ground electrodes.
[0026]
The width of the strip line not sandwiched between the ground electrodes may be greater than the width of the strip line sandwiched between the ground electrodes.
[0027]
Accordingly, since the width of the strip line not sandwiched between the ground electrodes is larger than the width of the strip line sandwiched between the ground electrodes, the strip line not sandwiched between the ground electrodes reduces the delay line. Loss can be achieved.
[0028]
In addition, since the number of ground electrodes can be reduced as compared with the delay line according to the prior art, the height of the delay line according to the present invention can be reduced.
[0029]
Further, in the delay line according to the present invention, since the number of ground electrodes is reduced, the number of ground electrode patterns necessary for manufacturing the delay line can be reduced, and the manufacturing cost of the delay line is reduced. It becomes possible to do.
[0030]
The plurality of strip lines may be formed in a meander shape, a spiral shape, or a combination of a meander shape and a spiral shape.
[0031]
In the case of a combination of a meander shape and a spiral shape, electromagnetic coupling between adjacent strip lines can be weakened, and a desired delay time can be easily obtained.
[0032]
In particular, the signal direction of the adjacent strip line or the adjacent strip line via each ground electrode may be reversed. Thereby, interference between strip lines can be further reduced.
[0033]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the delay line according to the present invention will be described with reference to FIGS.
[0034]
First, as shown in FIG. 1, the delay line 10 </ b> A according to the first embodiment includes a plurality of dielectric layers (S <b> 1 to S <b> 10: see FIG. 2) that are laminated and baked and integrated. Ground electrodes (first and second ground electrodes 12a and 12b: see FIGS. 2 and 3) are respectively formed on one main surface of the first dielectric layer S1 and one main surface of the tenth dielectric layer S10. The dielectric substrate 14 is provided.
[0035]
In the dielectric substrate 14, as shown in FIG. 2, two strip lines (first and second strip lines 16a and 16b) and a via hole 18 electrically connecting the strip lines 16a and 16b are formed. Has been.
[0036]
Further, in the delay line 10A, as shown in FIG. 1, an input terminal 20 and an output terminal 22 are formed on one side surface of the outer peripheral surface of the dielectric substrate 14, and the input terminal 20 and the output terminal 22 are A region for insulation is secured between the first and second ground electrodes 12a and 12b.
[0037]
Specifically, referring to FIGS. 1 and 2, the dielectric substrate 14 is configured by stacking first to tenth dielectric layers S1 to S10. These first to tenth dielectric layers S1 to S10 are composed of one or a plurality of layers.
[0038]
A first strip line 16a having one end connected to the output terminal 22 and the other end connected to the via hole 18 is formed on one main surface of the fourth dielectric layer S4. On one main surface of S7, a second strip line 16b having one end connected to the input terminal 20 and the other end connected to the via hole 18 is formed.
[0039]
Here, the first and second strip lines 16a and 16b are both formed in a spiral shape of one turn or more, and the spiral direction from the input terminal 20 to the connection portion of the via hole 18 in the second strip line 16b, The spiral direction from the connection portion of the via hole 18 to the output terminal 22 in the first strip line 16a is opposite to each other.
[0040]
Furthermore, the delay line 10A according to the first embodiment includes the first to third dielectric layers between the first strip line 16a and the first ground electrode 12a adjacent to the first strip line 16a. For example, a dielectric layer having a dielectric constant of 25 is used as S1 to S3, and the seventh to ninth dielectrics between the second strip line 16b and the second ground electrode 12b adjacent to the second strip line 16b. For example, a dielectric layer having a dielectric constant of 25 is used as the layers S7 to S9. For example, a dielectric constant of 7 is used as the fourth to sixth dielectric layers S4 to S6 between the first and second strip lines 16a and 16b. A dielectric layer is used.
[0041]
That is, the dielectric constant of the first to third dielectric layers S1 to S3 is εa1, the dielectric constant of the seventh to ninth dielectric layers S7 to S9 is εa2, and the fourth to sixth dielectric layers S4 to S6. Is set to satisfy εa1 = εa2 ≧ εb. Of course, εa1 ≧ εb and εa2 ≧ εb may be satisfied.
[0042]
As described above, in the delay line 10A according to the first embodiment, the dielectric constants εa1 and εa2 that are substantially related to the delay time of the signal transmission can be set high, so that a desired delay time can be obtained. The effective dielectric constant is increased as compared with the conventional low dielectric constant substrate.
[0043]
Therefore, in comparison with a conventional delay line using a low dielectric constant substrate, when a strip line having the same line width is considered, in this embodiment, the first and second strip lines 16a and 16b are used. This contributes to downsizing. Further, the conductor loss is reduced by the amount that the first and second strip lines 16a and 16b can be shortened, and the signal attenuation in the delay line 10A can be suppressed.
[0044]
In addition, since the dielectric constant εb between the first and second strip lines 16a and 16b can be set lower than the above-described dielectric constants εa1 and εa2, the gap between the first and second strip lines 16a and 16b can be set. Interference (electromagnetic coupling) can be kept small, and there is no need to increase the distance between the first and second strip lines 16a and 16b. This is advantageous for downsizing.
[0045]
Thus, in the delay line 10A according to the first embodiment, both low loss and downsizing can be achieved.
[0046]
Here, two experimental examples (referred to as first and second experimental examples for convenience) are shown. In the first experimental example, as shown in FIG. 4, a width w from a lower surface to a surface (formation surface) having a height h or a depth b is formed in a dielectric substrate 32 having a ground electrode 30 formed on the lower surface. A sample 36 having a strip line 34 was prepared. In Comparative Example 1, the dielectric constant of the entire dielectric substrate 32 is 7, and in Example 1, the dielectric constant of the part from the lower surface to the height h is 25, and the dielectric constant of the part from the upper surface to the depth b is It was set to 7.
[0047]
In Comparative Example 1 and Example 1, the width w of the strip line 34 is 100 μm, and the relationship between the width w and the height h is w / h = 4.0, w / h = 1.0, and w / In the case of three types of h = 0.2, the characteristic impedance when b / h was changed was measured, and the effective dielectric constant at that time was further measured.
[0048]
The measurement result of the characteristic impedance is shown in FIG. 5, and the measurement result of the effective dielectric constant is shown in FIG. In these FIG. 5 and FIG. 6, the plot of w / h = 4.0 in Comparative Example 1 is shown by ◆, the plot of w / h = 1.0 is shown by ■, and the plot of w / h = 0.2 is shown by ▲. In Example 1, a plot of w / h = 4.0 is indicated by ◇, a plot of w / h = 1.0 is indicated by □, and a plot of w / h = 0.2 is indicated by Δ.
[0049]
In order to realize, for example, 50Ω as the characteristic impedance, in Example 1, it is necessary to set w / h = 0.2 when b / h = 1.0. It turns out that it is 6 to 16. In Comparative Example 1, it is necessary that w / h = 1.0 when b / h = 0.11. In this case, the effective dielectric constant is 5.
[0050]
From this, it can be seen that the effective dielectric constant of Example 1 is three times that of Comparative Example 1, and the effective dielectric constant is increased.
[0051]
As a result, the area of Example 1 can be reduced to about ３ compared to Comparative Example 1, and when a delay line having the same line width, for example, a delay time of 5 nsec, is created, the length of the strip line is short. Accordingly, there is an effect that the loss due to the conductor loss is reduced accordingly.
[0052]
In the second experimental example, the change in attenuation with respect to the frequency was measured in Example 2 and Comparative Example 2 shown below in which the delay time was set to 5 nsec.
[0053]
In Example 2, in the delay line 10A according to the first embodiment, the dielectric constant between the first strip line 16a and the first ground electrode 12a and the distance between the second strip line 16b and the second ground electrode 12b are used. The dielectric constant is 25, and the dielectric constant between the first and second strip lines 16a and 16b is 7.
[0054]
The comparative example 2 has a configuration in which a dielectric layer having a dielectric constant of 7 is used as the first to tenth dielectric layers S1 to S10 in the delay line 10A according to the first embodiment.
[0055]
The result of this second experimental example is shown in FIG. In FIG. 7, a curve A shows the characteristics of Example 2, and a curve B shows the characteristics of Comparative Example 2. From this experimental result, it can be seen that the attenuation of the signal in Example 2 is reduced over 1 GHz to 10 GHz as compared with Comparative Example 2. This confirms that the conductor loss is reduced by the amount that the second embodiment can shorten the strip line compared to the second comparative example, and the signal attenuation in the delay line 10A is suppressed.
[0056]
In the above-described example, the case where the first ground electrode 12a is formed on the upper surface of the dielectric substrate 14 has been shown. In addition, as shown by the two-dot chain line in FIG. 3, the dielectric is formed on the first ground electrode 12a. The form in which the body layer 50 was formed may be sufficient.
[0057]
In the above-described first embodiment, the first and second strip lines 16a and 16b are formed in a spiral shape of one turn or more. In addition, the delay according to the modified example of FIG. As shown in the line 10Aa, both the first and second strip lines 16a and 16b may have a meander shape. Although not shown, one of the first and second strip lines 16a and 16b is a meander. You may make it a shape and you may make any other spiral shape. In this case, the electromagnetic coupling between the first and second strip lines 16a and 16b can be weakened, and a desired delay time can be easily obtained. In particular, if the first and second strip lines 16a and 16b are formed so that the signal directions of the adjacent first and second strip lines 16a and 16b are reversed, the first and second strip lines are formed. Interference between the lines 16a and 16b can be further reduced.
[0058]
Next, a delay line 10B according to a second embodiment will be described with reference to FIGS.
[0059]
As shown in FIG. 9, the delay line 10B according to the second embodiment has a configuration in which two delay lines 10A according to the first embodiment are stacked with the inner layer ground electrode 12c interposed therebetween. Have
[0060]
Specifically, as shown in FIG. 10, the dielectric substrate 14 is configured by stacking first to fifteenth dielectric layers S1 to S15. These first to fifteenth dielectric layers S1 to S15 are composed of one or a plurality of layers.
[0061]
10 and 11, the input terminal 20 and the output terminal 22 are formed on one side surface of the outer peripheral surface of the dielectric substrate 14, and the input terminal 20, the output terminal 22, and the ground electrode 12a, A region for insulation is secured between 12b, 12c and 12.
[0062]
Then, the first ground electrode 12a is formed on one main surface of the first dielectric layer S1, the inner layer ground electrode 12c is formed on one main surface of the eighth dielectric layer S8, and the fifteenth dielectric layer A second ground electrode 12b is formed on one main surface of S15.
[0063]
Further, a first strip line 16a having one end connected to the input terminal 20 and the other end connected to the first via hole 18a is formed on one main surface of the third dielectric layer S3. On one main surface of the dielectric layer S6, there is formed a second strip line 16b having one end connected to the first via hole 18a and the other end connected to the second via hole 18b.
[0064]
Here, the first and second strip lines 16a and 16b are both formed in a spiral shape of one turn or more, and the spiral from the input terminal 20 to the connection portion of the first via hole 18a in the first strip line 16a. The direction and the spiral direction from the connection portion of the first via hole 18a to the connection portion of the second via hole 18b in the second strip line 16b are opposite to each other. A region for insulation (region where no electrode film is formed) is secured between the second via hole 18b and the inner layer ground electrode 12c.
[0065]
Furthermore, a third strip line 16c having one end connected to the second via hole 18b and the other end connected to the third via hole 18c is formed on one main surface of the tenth dielectric layer S10. On one main surface of the thirteenth dielectric layer S13, a fourth strip line 16d having one end connected to the output terminal 22 and the other end connected to the third via hole 18c is formed.
[0066]
Also in this case, the third and fourth strip lines 16c and 16d are both formed in a spiral shape having one or more turns, and the third via hole 18c is connected to the second via hole 18b in the third strip line 16c. The spiral direction to the connection portion is opposite to the spiral direction from the connection portion of the third via hole 18c to the output terminal 22 in the fourth strip line 16d.
[0067]
In the delay line 10B according to the second embodiment, the first and second dielectric layers S1 and S2 between the first strip line 16a and the first ground electrode 12a have a dielectric constant of 25, for example. For example, dielectric layers having a dielectric constant of 25 are used as the sixth and seventh dielectric layers S6 and S7 between the second strip line 16b and the inner layer ground electrode 12c. For example, a dielectric layer having a dielectric constant of 7 is used as the third to fifth dielectric layers S3 to S5 between the second strip lines 16a and 16b.
[0068]
Further, for example, dielectric layers having a dielectric constant of 25 are used as the eighth and ninth dielectric layers S8 and S9 between the third strip line 16c and the inner layer ground electrode 12c, and the fourth strip line 16d and the second dielectric layer For example, a dielectric layer having a dielectric constant of 25 is used as the thirteenth and fourteenth dielectric layers S13 and S14 between the ground electrodes 12b, and the tenth to twelfth layers between the third and fourth striplines 16c and 16d. As the dielectric layers S10 to S12, for example, a dielectric layer having a dielectric constant of 7 is used.
[0069]
In the delay line 10B according to the second embodiment, both low loss and downsizing can be achieved, similarly to the delay line 10A according to the first embodiment described above.
[0070]
In the above example, the case where the first ground electrode 12a is formed on the upper surface of the dielectric substrate 14 has been shown, but in addition, as shown by the two-dot chain line in FIG. 9, the dielectric is formed on the first ground electrode 12a. The form in which the body layer 50 was formed may be sufficient.
[0071]
Further, in the above-described embodiment, the case where the ground electrodes are formed on the six surfaces of the dielectric substrate 14 has been shown. However, it is not necessary to form the ground electrodes on all the surfaces, and a plurality of components constituting the dielectric substrate 14 are formed. Of these dielectric layers, it may be formed on each main surface of at least two dielectric layers, or a ground electrode may be formed between the input terminal 20 and the output terminal 22 together.
[0072]
Next, a delay line 10C according to a third embodiment will be described with reference to FIGS.
[0073]
As shown in FIG. 12, the delay line 10C according to the third embodiment has a plurality of dielectric layers (S1 to S13) stacked and baked and integrated, and the appearance is the second one shown in FIG. Similar to the delay line 10 </ b> B according to the embodiment, the input terminal 20, the output terminal 22, and the ground electrode 12 are formed on one side surface of the outer peripheral surface of the dielectric substrate 14.
[0074]
Specifically, as shown in FIG. 12, the dielectric substrate 14 is configured by stacking first to thirteenth dielectric layers S1 to S13. These first to thirteenth dielectric layers S1 to S13 are composed of one or a plurality of layers.
[0075]
In addition, a first strip line 16a having one end connected to the input terminal 20 and the other end connected to the first via hole 18a is formed on one main surface of the second dielectric layer S2. On one main surface of the dielectric layer S6, a second strip line 16b having one end connected to the first via hole 18a and the other end connected to the second via hole 18b is formed. The tenth dielectric layer On one main surface of S10, a third strip line 16c having one end connected to the second via hole 18b and the other end connected to the output terminal 22 is formed.
[0076]
Further, there is a relationship of w1> w2 = w3 among the width w1 of the first strip line 16a, the width w2 of the second strip line 16b, and the width w3 of the third strip line 16c.
[0077]
Furthermore, an inner layer ground electrode 12d connected to the ground electrode 12 is formed on one main surface of the fourth dielectric layer S4, and connected to the ground electrode 12 on one main surface of the eighth dielectric layer S8. The inner layer ground electrode 12e is formed, and an inner layer ground electrode 12f connected to the ground electrode 12 is formed on one main surface of the twelfth dielectric layer S12.
[0078]
Therefore, the second strip line 16b layer The fourth dielectric layer S4 and the fifth dielectric layer S5 having the ground electrode 12d, the seventh dielectric layer S7 and the inner layer It is sandwiched between eighth dielectric layers S8 having a ground electrode 12e. The third strip line 16c layer The dielectric layer S8 and the ninth dielectric layer S9 having the ground electrode 12e, the eleventh dielectric layer S11 and the inner layer layer A first electrode having a ground electrode 12f. 12 Dielectric layer S 12 It is sandwiched between.
[0079]
It should be noted that a region for insulation (a region where no electrode film is formed) is secured between the first via hole 18a and the inner layer ground electrode 12d and between the second via hole 18b and the inner layer ground electrode 12e. Has been.
[0080]
Here, the first, second, and third strip lines 16a, 16b, and 16c are both formed in a meander shape, and from the input terminal 20 to the connection portion of the first via hole 18a in the first strip line 16a. The meander direction and the meander direction from the connection portion of the first via hole 18a to the connection portion of the second via hole 18b in the second strip line 16b are opposite to each other. Further, the meander direction from the connection portion of the first via hole 18a to the connection portion of the second via hole 18b in the second strip line 16b and the connection portion of the second via hole 18b in the third strip line 16c. The meander directions to the output terminal 22 are opposite to each other.
[0081]
Here, one experimental example (referred to as a third experimental example for convenience) is shown. The third experimental example has the same delay time T and meander-shaped strip line, and the transmission characteristics of three types of delay lines with different inner-layer ground electrode formation locations and strip line widths w, that is, The pulse response characteristics and frequency characteristics of the delay line are examined.
[0082]
This third experimental example is shown in FIG. 14 which is a modification of the delay line 10C (Example 3) according to the third embodiment shown in FIG. 13 and the delay line 10A according to the first embodiment. A delay line 10D (Example 4) and a delay line 10E according to the prior art shown in FIG. 15 (Comparative Example 3) were prepared. Each of the above-described three types of delay lines 10C, 10D, and 10E has a delay time of T = 2 μs and a meander-shaped three stripline pattern.
[0083]
In the delay line 10C (Example 3), as shown in FIG. 13, the width w1 of the first strip line 16a, the width w2 of the second strip line 16b, and the width w3 of the third strip line 16c are respectively set. w1 = 120 μm, w2 = w3 = 70 μm, and the dielectric constants of the plurality of dielectric layers constituting the dielectric substrate 14 are the same.
[0084]
As shown in FIG. 14, the delay line 10D (Embodiment 4) is a dielectric substrate in which a plurality of dielectric layers are laminated and integrated by firing, and inner ground electrodes 12g and 12h are formed on both main surfaces, respectively. 14 In the dielectric substrate 14, a first strip line 16a not sandwiched between the inner layer ground electrodes 12g and 12h, and second and third strip lines 16b and 16c sandwiched between the inner layer ground electrodes 12g and 12h, A via hole 18a that electrically connects the first and second strip lines 16a and 16b and a via hole 18b that electrically connects the second and third strip lines 16b and 16c are formed.
[0085]
In this case, in the dielectric substrate 14, the dielectric constant between the inner layer ground electrode 12g and the second strip line 16b is εa1, the dielectric constant between the second and third strip lines 16b and 16c is εb, and the third strip. When the dielectric constant between the line 16c and the inner layer ground electrode 12h is εa2, εa1 = εa2 ≧ εb or εa1 ≧ εb and εa2 ≧ εb are satisfied.
[0086]
In the delay line 10D (Embodiment 4), the widths of the first, second and third strip lines 16a, 16b and 16c are w1, and w1 = 120 μm. Further, the dielectric constants εa1, εa2, and εb of the plurality of dielectric layers constituting the dielectric substrate 14 are set to εa1 = εa2 = εb, respectively.
[0087]
In the delay line 10E (Comparative Example 3), as shown in FIG. 15, a plurality of dielectric layers are laminated and fired and integrated, and inner ground electrodes 12i, 12j, 12k and 12l are formed on both main surfaces, respectively. And a dielectric substrate 14. In the dielectric substrate 14, first, second and third strip lines 16a, 16b and 16c sandwiched between inner layer ground electrodes 12i, 12j, 12k and 12l, first and second strip lines 16a and A via hole 18a that electrically connects 16b and a via hole 18b that electrically connects the second and third strip lines 16b and 16c are formed.
[0088]
In the delay line 10E (Comparative Example 3), the width of the first, second, and third strip lines 16a, 16b, and 16c is w3, and w3 = 70 μm. The dielectric constant of the plurality of dielectric layers constituting the dielectric substrate 14 is εb.
[0089]
Output when a pulse input signal of a step pulse having a rise time of 17 ns and an amplitude of 225 mV is input to the input terminal 20 of the above-described three types of delay lines 10C, 10D and 10E (Examples 3, 4 and Comparative Example 3). The pulse output signal output from the terminal 22 was measured with a spectrum analyzer. The rise time is a time when the level of the pulse input signal or pulse output signal is 20% to 80% with respect to the amplitude of the pulse input signal or pulse output signal at the rise of the pulse input signal or pulse output signal. Say.
[0090]
As shown in FIG. 16, the pulse response characteristic indicating the rising portion of the pulse output signal has delay lines 10C, 10D and 10E (Examples 3 and 4) after about 2 ns have elapsed from the rising of the pulse input signal (input waveform). And the characteristic is that the pulse output signal of Comparative Example 3) rises. That is, the time when the pulse input signal (input waveform) is 50% (112.5 mV) of the amplitude of the pulse input signal (input waveform), and the pulse output signal is 50% of the amplitude of the pulse output signal (112. If the time difference from the time of 5 mV) is defined as the delay time T, the delay time T of Comparative Example 3, Example 3 and Example 4 is T = about 2 ns.
[0091]
Further, in the pulse response characteristics of the delay line 10D (Embodiment 4), the rise time is smaller than the pulse response characteristics of the delay lines 10C and 10E (Embodiment 3 and Comparative Example 3), but overshoot occurs. ing.
[0092]
On the other hand, the pulse response characteristic of the delay line 10E (Comparative Example 3) is lower than the pulse response characteristic of the delay line C (Example 3), and the level of the pulse output signal at the rise is small. It takes a long time to reach the amplitude of the pulse input signal (input waveform). That is, the delay line 10E (Comparative Example 3) has a larger loss due to conductor loss and a longer rise time than the delay line C (Example 3).
[0093]
As described above, the delay line 10C (Embodiment 3) is more responsive to the pulse input signal than the delay lines 10D and 10E (Embodiment 4 and Comparative Example 3) and does not cause overshoot. It can be seen that this is a good delay line that can quickly reach the amplitude of the pulse input signal (input waveform).
[0094]
As shown in FIG. 17, the frequency characteristics of the delay lines 10C, 10D, and 10E (Examples 3 and 4 and Comparative Example 3) have an insertion loss of the delay line 10D (Example 4) in the region where the frequency is 1 GHz or less. The insertion loss of the delay lines C and E (Example 3 and Comparative Example 3) is smaller. Further, in the region where the frequency is 1 GHz or more, the insertion loss of the delay line 10C (Example 3) is smaller than the insertion loss of the delay lines D and E (Example 4 and Comparative Example 3). The above insertion loss includes a loss due to a conductor loss, a dielectric loss, and the like.
[0095]
In particular, the delay line 10C (Embodiment 3) is suitable as a delay line that can cope with a high-frequency region because a sudden increase in loss due to discontinuities does not occur in a frequency region of about 3 GHz or less.
[0096]
As described above, in the delay line 10C according to the third embodiment, the width w1 of the first strip line 16a not sandwiched between the inner layer ground electrodes 12d, 12e, and 12f is equal to the inner layer ground electrodes 12d, 12e. Since the widths w2 and w3 of the second and third strip lines 16b and 16c sandwiched between the second and third strip lines 16f are larger than those of the second and third strip lines 16f, the loss due to the conductor loss of the delay line 10C can be reduced.
[0097]
Furthermore, since the delay line 10C according to the third embodiment does not have the inner layer ground electrode 12i of the delay line 10E according to the related art (Comparative Example 3), the height of the delay line 10C is reduced. Is possible. Further, when the delay line 10C according to the third embodiment is manufactured, the pattern of the inner layer ground electrode 12i is not necessary, so that the manufacturing cost of the delay line 10C can be reduced.
[0098]
Since the first, second and third strip lines 16a, 16b and 16c are formed in the dielectric substrate 14 via the inner layer ground electrodes 12d, 12e and 12f, the crosstalk between the strip lines. Can be reduced.
[0099]
Furthermore, the insertion loss of the delay line 10C is reduced by reducing the crosstalk. In addition, due to the reduction of the crosstalk, a sharp increase in insertion loss at a discontinuous point occurring in a high frequency region of 1 GHz or higher is greatly suppressed. Therefore, the delay line 10C is a delay line that can be used even in a high frequency region of 1 GHz or more.
[0100]
It should be noted that the delay line according to the present invention is not limited to the above-described embodiment, and various configurations can be adopted without departing from the gist of the present invention.
[0101]
【The invention's effect】
As described above, the delay line according to the present invention can achieve both low loss and downsizing.
[Brief description of the drawings]
FIG. 1 is a perspective view showing a delay line according to a first embodiment.
FIG. 2 is an exploded perspective view showing a delay line according to the first embodiment.
FIG. 3 is a longitudinal sectional view showing a delay line according to the first embodiment.
FIG. 4 is a cross-sectional view showing a sample used in a first experimental example.
5 is a characteristic diagram showing a change in characteristic impedance with respect to b (depth) / h (height) in Comparative Example 1 and Example 1. FIG.
6 is a characteristic diagram showing a change in effective dielectric constant with respect to b (depth) / h (height) in Comparative Example 1 and Example 1. FIG.
FIG. 7 is a characteristic diagram showing a change in attenuation with respect to frequency in the second experimental example.
FIG. 8 is an exploded perspective view showing a modified example of the delay line according to the first embodiment.
FIG. 9 is a longitudinal sectional view showing a delay line according to a second embodiment.
FIG. 10 is an exploded perspective view showing a delay line according to a second embodiment.
FIG. 11 is a perspective view showing a delay line according to a second embodiment.
FIG. 12 is an exploded perspective view showing a delay line according to a third embodiment.
FIG. 13 is a longitudinal sectional view showing a delay line according to a third embodiment.
14 is a longitudinal sectional view showing Example 4 (modified example of the delay line according to the first embodiment) used in Experimental Example 3. FIG.
15 is a longitudinal sectional view showing a delay line according to Comparative Example 3. FIG.
FIG. 16 is a characteristic diagram showing pulse response characteristics in delay lines according to Examples 3 and 4 and Comparative Example 3;
FIG. 17 is a characteristic diagram showing frequency characteristics in delay lines according to Examples 3 and 4 and Comparative Example 3;
[Explanation of symbols]
10A, 10Aa, 10B, 10C, 10D, 10E ... Delay line
12 ... Earth electrode 12a ... First earth electrode
12b ... Second earth electrode 12c-12l ... Inner layer earth electrode
14, 32 ... Dielectric substrate
16a to 16d: first to fourth strip lines
18, 18a to 18c ... via hole 20 ... input terminal
22 ... Output terminal 30 ... Ground electrode
34 ... Stripline 36 ... Sample
A, B ... Curve b ... Depth
h ... Height S1-S15 ... Dielectric layer
w, w1-w3 ... width
ε, εa, εa1, εa2, εb ... dielectric constant

Claims (4)

Two ground electrodes formed in a dielectric substrate formed by laminating a plurality of dielectric layers, a first strip line not sandwiched between the ground electrodes in the dielectric substrate, and the dielectric A second and a third strip line formed between the ground electrodes in the body substrate, and a via hole for electrically connecting the first to third strip lines,
The two ground electrodes and the first to third strip lines are respectively formed on one main surface of each dielectric layer,
The first to third strip lines are both formed in a meander shape, or a spiral shape, or a combination of a meander shape and a spiral shape,
Ground electrode adjacent the dielectric constant of the dielectric layer between the ground electrode adjacent to the second strip line and the second strip line .epsilon.a 1, the third strip line and the third strip line when the Ipushironbi the dielectric constant of the dielectric layer between the dielectric constant of the dielectric layer Ipushiron'ei2, the second strip line and the third strip line between, εa 1> εb and,, εa2 > Delay line characterized by satisfying εb. The delay line according to claim 1 ,
A delay line satisfying εa1 = εa2 > εb. Three ground electrodes formed in a dielectric substrate formed by laminating a plurality of dielectric layers, a first strip line not sandwiched between the ground electrodes in the dielectric substrate, and the dielectric A second strip line formed between two ground electrodes on the first strip line side of the three ground electrodes in the body substrate, and the first of the three ground electrodes in the dielectric substrate. A third strip line formed between two ground electrodes spaced from one strip line, and a via hole for electrically connecting the first to third strip lines,
The three ground electrodes and the first to third strip lines are respectively formed on one main surface of each dielectric layer;
The first to third strip lines are both formed in a meander shape, or a spiral shape, or a combination of a meander shape and a spiral shape,
The delay line according to claim 1 , wherein a width of the first strip line is larger than a width of the second and third strip lines. In the delay line according to any one of claims 1 to 3 ,
The delay line is characterized in that the signal direction of the adjacent strip line or the adjacent strip line via each ground electrode is reversed.

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