JPH0458602A - Delay line device - Google Patents

Delay line device

Info

Publication number
JPH0458602A
JPH0458602A JP17116790A JP17116790A JPH0458602A JP H0458602 A JPH0458602 A JP H0458602A JP 17116790 A JP17116790 A JP 17116790A JP 17116790 A JP17116790 A JP 17116790A JP H0458602 A JPH0458602 A JP H0458602A
Authority
JP
Japan
Prior art keywords
delay
delay line
line
microwave integrated
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17116790A
Other languages
Japanese (ja)
Inventor
Hiroaki Izumi
和泉 裕昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP17116790A priority Critical patent/JPH0458602A/en
Publication of JPH0458602A publication Critical patent/JPH0458602A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0296Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298Multilayer circuits

Abstract

PURPOSE:To make the device small by overlapping microwave integrated circuits to form a delay line and forming a characteristic deterioration compensating circuit integrally. CONSTITUTION:Plural microwave integrated circuit boards 1a-1c each having a signal strip signal line for delay purpose on other side and insulation boards 2a-2c are overlapped alternately and another insulation board 5 is overlapped at the outside and they are integrated to form a delay circuit. The board 5 is integrated with a compensation circuit 7 compensating the deterioration in the electric characteristic due to delay. The delay line circuit device is made small through the adoption of the integral configuration of employment of the strip line and the plural overlapped boards.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、マイクロ波通信装置等に使用される遅延線路
に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a delay line used in microwave communication devices and the like.

[従来の技術] 従来、マイクロ波通信装置等に使用される遅延線路は1
例えば、第3図に示すように、同軸線路14をコイル状
に巻いた構成を基本とし、その組合長により所望の遅延
時間を得る構造となっていた。また、その発展した形態
として、第4図に示すように、マイクロ波集積回路15
を適用し、ストリップ線路16の組合長により所望の遅
延時間を得る構造も近年多く適用されている。
[Prior art] Conventionally, the delay line used in microwave communication equipment, etc.
For example, as shown in FIG. 3, the structure is based on a coaxial line 14 wound into a coil, and a desired delay time can be obtained by adjusting the length of the union. In addition, as an advanced form of the microwave integrated circuit 15, as shown in FIG.
In recent years, a structure in which a desired delay time can be obtained by adjusting the combination length of the strip lines 16 has been widely applied.

[発明が解決しようとする課Ma1 ところで、上記従来のストリップ線路歴遅延線路は、平
面上にしか形成できないため、より多くの遅延時間を必
要とする場合には、絶縁基板を挿入しながらストリップ
線路を1M数枚重ね、各基板に設けたスルーホールを通
して、各ストリップ線路の接地面と信号線路とを各々電
気接続し、接続された信号線路の合計長でより多くの遅
延時間を得ることができる。しかし、ストリップ線路は
同軸線路に比較し、導体抵抗が大きく、そのため通過損
失が大きく、かつ周波数特性において高周波になるに従
って通過損失が大きくなり、−次傾斜の振幅特性となる
[Problem to be solved by the invention Ma1 By the way, since the above-mentioned conventional strip line history delay line can only be formed on a flat surface, if a longer delay time is required, the strip line can be formed while inserting an insulating substrate. By stacking several 1M sheets and electrically connecting the ground plane of each strip line and the signal line through the through holes provided on each board, it is possible to obtain more delay time with the total length of the connected signal lines. . However, a strip line has a larger conductor resistance than a coaxial line, and therefore has a large passing loss, and in terms of frequency characteristics, the passing loss increases as the frequency becomes higher, resulting in an amplitude characteristic with a -th order slope.

したがって、前記多層型ストリップ線路状遅延線路をマ
イクロ波通信装置に適用する場合、外部回路に通過損失
を補償する増幅回路と一次傾斜を補償する振幅等化回路
が必要になり、これら周一回路を刷部に設けなければな
らないので、それだけ、大きなスペースが必要となり高
集積化の障害となっているという問題があった。
Therefore, when applying the multilayer stripline delay line to a microwave communication device, an amplifier circuit to compensate for the passing loss and an amplitude equalization circuit to compensate for the primary slope are required as external circuits, and these circuits are printed separately. Since it has to be installed in a large area, a large space is required, which is an obstacle to high integration.

本発明は、上記の問題点にかんがみてなされたもので、
より小型化が図れ′遅延線部装置の提供を目的とする。
The present invention has been made in view of the above problems, and
The purpose of this invention is to provide a delay line device that can be made more compact.

[!!WJを解決するための手段] このような課題を解決するため、本発明の遅延線路装置
は、板状をした絶縁基板の一方の面に全面導体からなる
接地面を有し2他方の面にストリップ線路からなる信号
線路を設けたマイクロ波集積回路基板と、表裏面が絶縁
された絶縁基板とを交互に複数枚重ねて列設し、かつ前
記各基板に設けたスルーホールを通して、前記各マイク
ロ波集積回路基板の接地面と信号線路とをそれぞれ電気
接続し、接続された信号線路の合計長で所望の遅延時間
を得る遅延線路を構成した遅延線路装置てあって、上記
列設された基板の外側に別の絶縁基板を付設し、この絶
縁基板上に遅延線路の電気的特性の劣化を補償する増幅
および振幅等化回路を形成した構成としである。
[! ! Means for Solving WJ] In order to solve such problems, the delay line device of the present invention has a ground plane made of a full conductor on one side of a plate-shaped insulating substrate, and a ground plane made of a conductor on the other side. A microwave integrated circuit board provided with a signal line consisting of a strip line and a plurality of insulating substrates whose front and back sides are insulated are stacked alternately and arranged in a row, and each of the micro-waves is connected through a through hole provided in each substrate. a delay line device configured to electrically connect the ground plane of a wave integrated circuit board and a signal line to obtain a desired delay time with the total length of the connected signal lines, Another insulating substrate is attached to the outside of the delay line, and an amplification and amplitude equalization circuit for compensating for deterioration of the electrical characteristics of the delay line is formed on this insulating substrate.

また、上記別の絶縁基板には、スルーホールを通して各
マイクロ波集積回路基板の接地面および信号線路に接続
される、接地端子および入出力端子をそれぞれ設けると
ともに、上記増幅および振幅等化回路のバイアス端子を
設けたことが有効である。
Further, the above-mentioned separate insulating substrate is provided with a ground terminal and an input/output terminal, which are connected to the ground plane and signal line of each microwave integrated circuit board through through holes. Providing a terminal is effective.

[作用] 本発明の遅延線路装置によれば、マイクロ波集積回路が
列設されて所望の遅延時間を得る遅延線路が形成される
とともに、この遅延線路の電気特性の劣化を補償する増
幅および振幅等化回路が一体形成され、装置の小型化が
図られる。
[Function] According to the delay line device of the present invention, a delay line is formed in which microwave integrated circuits are arranged in a row to obtain a desired delay time, and amplification and amplitude compensation are performed to compensate for deterioration of the electrical characteristics of this delay line. The equalization circuit is integrally formed, and the device can be made smaller.

[実施例] 以下、本発明の実施例に係る遅延線路装置について図面
を参照して説明する。
[Example] Hereinafter, a delay line device according to an example of the present invention will be described with reference to the drawings.

第1図および第2図は本発明の一実施例を示している。1 and 2 show one embodiment of the invention.

第1図は全体構成の斜視図、第2図は部分分解斜視図で
ある。
FIG. 1 is a perspective view of the overall configuration, and FIG. 2 is a partially exploded perspective view.

これらの図において、遅延線路装置は、複数枚(ここで
は3枚)のマイクロ波集積回路((MIC)基板1a〜
lcと、3枚の絶縁基板2 a S2 cとを有してお
り、これらの基板を交互に重ねて列設し、さらに、外側
にもう1枚の別の絶縁基板5を重ねて一体化した構成に
なっている。
In these figures, the delay line device includes a plurality of (here, three) microwave integrated circuit (MIC) substrates 1a to 1.
lc and three insulating substrates 2 a S 2 c, these substrates are stacked alternately and arranged in a row, and another insulating substrate 5 is stacked on the outside to integrate them. It is configured.

マイクロ波集積回路基板1a−1cは、一方の面に全面
導体からなる接地面11a〜llcを有し、他方の面に
信号線路としてのストリップ線路10 a = 10 
cを形成しである。また、前記絶縁基板2a〜2Cに設
けたスルーホール9a〜9fを通して各マイクロ波集積
回路基板1 a −1cのストリップ線路10 a =
 10 cを電気的に接続し、接続したストリップ線路
10 a−10cの合計長で所望の遅延時間を得る遅延
線路を構成している。
The microwave integrated circuit boards 1a-1c have ground planes 11a-11c made of conductors all over the surface on one surface, and strip lines 10a=10 as signal lines on the other surface.
It forms c. Further, the strip lines 10a of each microwave integrated circuit board 1a-1c are passed through the through holes 9a to 9f provided in the insulating substrates 2a to 2C.
10c are electrically connected, and the total length of the connected strip lines 10a to 10c constitutes a delay line that obtains a desired delay time.

また、同様に絶縁基板28〜2Cに設けたスルーホール
8a〜8gを通して各接地面11a〜11cft接続し
ている。さらに、絶縁基板5に最も近いマイクロ波集積
回路基板1cのストリップ線路10cは、スルーホール
9dを通して絶縁基板5上の厚鮫回路13へ接続される
Further, the respective ground planes 11a to 11cft are connected through through holes 8a to 8g similarly provided in the insulating substrates 28 to 2C. Further, the strip line 10c of the microwave integrated circuit board 1c closest to the insulating substrate 5 is connected to the thick circuit 13 on the insulating substrate 5 through the through hole 9d.

絶縁基板5上には、電気特性を補償する補償回路7が形
成されている。この補償回12!7は、遅延線路の電気
的特性の劣化を補償する増Ilaおよび振幅等化回路を
構成している。
A compensation circuit 7 is formed on the insulating substrate 5 to compensate for electrical characteristics. This compensation circuit 12!7 constitutes an amplifier Ila and an amplitude equalization circuit for compensating for deterioration of the electrical characteristics of the delay line.

これらのマイクロ波集積回路基板1a〜lcおよび絶縁
基板2a〜2Cは、例えば、セラミック等を用いて構成
し、これを焼成等することにより一体化を行なうことが
望ましい。
These microwave integrated circuit boards 1a to lc and insulating substrates 2a to 2C are desirably made of, for example, ceramic, and are integrated by firing or the like.

そして、スルーホール8a〜8g、9a〜9fを通して
マイクロ波11槍回路基板1aおよび絶縁基板5に導か
れた適宜の部位に、短冊状をした接続片を接続し入出力
端子3a、3bとして構成しているとともに、接続片を
接続し接地端子4a。
Then, strip-shaped connection pieces are connected to appropriate parts guided to the microwave 11 spear circuit board 1a and the insulating board 5 through the through holes 8a to 8g and 9a to 9f to form input/output terminals 3a and 3b. At the same time, connect the connecting piece to the ground terminal 4a.

4bとしている。さらに、絶縁基板5に接続片6を接続
し、補償回路7のバイアス端子として構成している。
It is set as 4b. Further, a connecting piece 6 is connected to the insulating substrate 5, and is configured as a bias terminal of a compensation circuit 7.

したがって、この構成の遅延線路装置によれば、複数枚
の基板を重ねて一体化し、さらに電気特性の劣化を補償
する補償回路7を付加した構成であるため、小型で小ス
ペースの遅延回路装置となり、しかも、特性の劣化が少
ないものとなる。
Therefore, according to the delay line device having this configuration, since the multiple boards are stacked and integrated, and the compensation circuit 7 is added to compensate for the deterioration of the electrical characteristics, the delay line device is small and takes up little space. , moreover, there is less deterioration of characteristics.

また、ストリップ線路10 a = l Ocは、印刷
等により形成できるので2その長さを高精度で管理でき
、遅延時間の調整を精度良く行なうことができる。
Further, since the strip line 10 a = l Oc can be formed by printing or the like, its length can be controlled with high precision, and the delay time can be adjusted with high precision.

[発明の効果] 以、1−説IJJ L、たように本発明の遅延線路装置
によれば、マイクロ波集積回路基板と絶縁基板とを交互
に複数枚重ねて列設して、各マイクロ波集積回路基板の
接地面と信号線路とをそれぞれ電気接続し、接続された
信号線路の合計長で所望の遅延線路を構成し、さらに、
itt気特性の劣化を補償する補償回路を一体的に付加
したので、特性劣化のない遅延線路を小型に形成できる
とともに、遅延線路の長さを高精度に形成することかで
き、′M延待時間調整を精度良く行なうことがてきる。
[Effects of the Invention] Hereinafter, according to the delay line device of the present invention, a plurality of microwave integrated circuit boards and insulating substrates are alternately stacked and arranged in a row, so that each microwave The ground plane of the integrated circuit board and the signal line are each electrically connected, the total length of the connected signal lines constitutes a desired delay line, and further,
Since a compensation circuit that compensates for the deterioration of the characteristic characteristics is integrally added, it is possible to form a compact delay line without deterioration of the characteristics, and the length of the delay line can be formed with high precision, reducing the delay time. Time adjustment can be made with high precision.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例に係る′N遅延線路装置示す斜
視図、第2図は実施例に係る遅延線貼装との分解斜視図
、第3図および第4図は従来の遅延線路装置の一例を示
す斜視図である。 la〜1c:マイクロ波集積回路基板 2a〜2c:絶縁基板 3a、3b:入出力端子 4a、4b:接地端子 5:絶縁基板 6:バイアス端子 7:補償回路 8a 〜8g、9a 〜9f ニスルーホール10a〜
10Cニストリツプ線路 11a 〜llc:按地面 第1図
FIG. 1 is a perspective view showing a 'N delay line device according to an embodiment of the present invention, FIG. 2 is an exploded perspective view of a delay line pasted according to an embodiment, and FIGS. 3 and 4 are conventional delay lines. It is a perspective view showing an example of a device. la-1c: Microwave integrated circuit board 2a-2c: Insulating substrate 3a, 3b: Input/output terminal 4a, 4b: Ground terminal 5: Insulating substrate 6: Bias terminal 7: Compensation circuit 8a-8g, 9a-9f Varnished through hole 10a~
10C strip line 11a ~ llc: Laying ground Figure 1

Claims (2)

【特許請求の範囲】[Claims] (1)板状をした絶縁基板の一方の面に全面導体からな
る接地面を有し、他方の面にストリップ線路からなる信
号線路を設けたマイクロ波集積回路基板と、表裏面が絶
縁された絶縁基板とを交互に複数枚重ねて列設し、かつ
前記各基板に設けたスルーホールを通して、前記各マイ
クロ波集積回路基板の接地面と信号線路とをそれぞれ電
気接続し、接続された信号線路の合計長で所望の遅延時
間を得る遅延線路を構成した遅延線路装置であって、上
記列設された基板の外側に別の絶縁基板を付設し、この
絶縁基板上に遅延線路の電気的特性の劣化を補償する増
幅および振幅等化回路を形成したことを特徴とする遅延
線路装置。
(1) A microwave integrated circuit board that has a ground plane made of a full conductor on one side of a plate-shaped insulating substrate and a signal line made of a strip line on the other side, and the front and back sides are insulated. A plurality of insulating substrates are alternately stacked and arranged in a row, and the ground plane of each of the microwave integrated circuit boards and the signal line are electrically connected through through holes provided in each of the substrates, and the connected signal line is formed. A delay line device comprising a delay line that obtains a desired delay time with a total length of 1. A delay line device comprising an amplification and amplitude equalization circuit that compensates for deterioration of the signal.
(2)上記別の絶縁基板に、スルーホールを通して各マ
イクロ波集積回路基板の接地面に接続される接続端子お
よび信号線路に接続される入出力端子をそれぞれ設ける
とともに、上記増幅および振幅等化回路のバイアス端子
を設けたことを特徴とする請求項1記載の遅延線路装置
(2) A connection terminal connected to the ground plane of each microwave integrated circuit board through a through hole and an input/output terminal connected to a signal line are provided on the above-mentioned separate insulating substrate, and the above-mentioned amplification and amplitude equalization circuit are provided. 2. The delay line device according to claim 1, further comprising a bias terminal.
JP17116790A 1990-06-28 1990-06-28 Delay line device Pending JPH0458602A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17116790A JPH0458602A (en) 1990-06-28 1990-06-28 Delay line device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17116790A JPH0458602A (en) 1990-06-28 1990-06-28 Delay line device

Publications (1)

Publication Number Publication Date
JPH0458602A true JPH0458602A (en) 1992-02-25

Family

ID=15918242

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17116790A Pending JPH0458602A (en) 1990-06-28 1990-06-28 Delay line device

Country Status (1)

Country Link
JP (1) JPH0458602A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003133821A (en) * 2001-08-13 2003-05-09 Soshin Electric Co Ltd Delay line
JP2006270026A (en) * 2005-02-28 2006-10-05 Tokyo Univ Of Science Wiring structure, printed wiring board, integrated circuit, and electronic device
JP2007001282A (en) * 2005-05-26 2007-01-11 Fujifilm Holdings Corp Molding die and its manufacturing method
JP2009133420A (en) * 2007-11-30 2009-06-18 Ckd Corp Actuator with rod

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003133821A (en) * 2001-08-13 2003-05-09 Soshin Electric Co Ltd Delay line
JP2006270026A (en) * 2005-02-28 2006-10-05 Tokyo Univ Of Science Wiring structure, printed wiring board, integrated circuit, and electronic device
JP4660738B2 (en) * 2005-02-28 2011-03-30 学校法人東京理科大学 Printed wiring board and electronic device
JP2007001282A (en) * 2005-05-26 2007-01-11 Fujifilm Holdings Corp Molding die and its manufacturing method
JP2009133420A (en) * 2007-11-30 2009-06-18 Ckd Corp Actuator with rod

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