JP3927576B2 - I / O interface and semiconductor integrated circuit - Google Patents

Description

  The present invention relates to an input / output interface for transmitting and receiving signals between semiconductor integrated circuits or within a semiconductor integrated circuit.

In a conventional input / output interface, signals are transmitted and received by changing a signal line to a high level or a low level corresponding to a binary number. In this case, 1-bit data is transmitted through one signal line. Japanese Patent Application Laid-Open No. 5-227035 describes a technique for setting a logical value of a signal in accordance with an interval between rising edges of the signal.
Japanese Patent Laid-Open No. 5-227035

  In this type of input / output interface, the number of signal lines increases according to the number of bits of a signal to be transmitted. Therefore, as the amount of transmission increases, the chip size of the semiconductor integrated circuit increases or the area of the system board increases. There was a problem. An input / output circuit for inputting / outputting data to / from the signal line is necessary for each bit. For this reason, when the number of signal lines increases, the number of input / output circuits increases, and there is a problem that charge / discharge current due to switching increases. That is, the current consumption increases as the data bit width increases. In particular, the amount of data handled in mobile devices such as mobile phones that use a battery as a power source has increased significantly. An increase in the amount of data is a big problem because it greatly affects the operation time of these portable devices.

  Japanese Patent Laid-Open Nos. 5-227035 and 10-107684 are disclosed as techniques for transmitting data of a plurality of bits to one signal line. In JP-A-5-227035, a logical value is expressed by a combination of the pulse width of a pulse signal and the timing of a transition edge. However, since the four parameters T1-T4 are required to express 2-bit data, the configurations of the transmission circuit and the reception circuit are complicated. Further, since a timing margin is required for each parameter T1-T4, it is difficult to design the timing of the transmission circuit and the reception circuit. For this reason, it is necessary to increase the cycle time of the pulse signal.

  In Japanese Patent Application Laid-Open No. 10-107684, digital data is represented by a time difference generated between temporally adjacent frame signals in a spread spectrum communication system. In general, this type of transmission system has a complicated transmission / reception circuit and consumes a large amount of power.

  An object of the present invention is to provide an input / output interface and a semiconductor integrated circuit capable of transmitting a large amount of data with a small number of signal lines.

  Another object of the present invention is to reduce the number of signal lines without reducing the data transfer rate, thereby reducing the number of input circuits and output circuits and reducing power consumption.

  Still another object of the present invention is to reduce the wiring area of signal lines by reducing the number of signal lines without lowering the data transfer rate.

In one form of the input / output interface of the present invention, the logical value is expressed by the time difference between the transition edge of the signal transmitted on the signal line and the transition edge of the reference timing signal. Therefore, a plurality of bits of logical values can be transmitted with one signal line. That is, a large amount of data can be transmitted with a small number of signal lines. Since a large amount of data can be transmitted with one signal transmission, the data transfer rate can be greatly improved. Therefore, the number of signal lines can be reduced as compared with the prior art. Since the number of signal lines is small, the number of signal output circuits (output buffers) and the number of input circuits (input buffers) can be reduced. Since fewer circuits operate, power consumption can be reduced on both the signal transmission side and the signal reception side. In addition, since the number of signal lines is small, the wiring area of the signal lines can be reduced.

  In a preferable example in one form of the input / output interface of the present invention and one form of the semiconductor integrated circuit of the present invention, the transmission circuit converts each logical value expressed by a plurality of bits into a predetermined delay time. The logical value is output to the signal line as a signal delayed by a delay time with respect to the reference timing signal. The receiving circuit detects a delay time with respect to the reference timing signal at the transition edge of the signal transmitted via the signal line, and generates a logical value according to the delay time. The transmission circuit may delay the signal by a delay time according to the logical value. The receiving circuit can generate a logical value only by detecting a delay time of the signal with respect to the reference timing signal. Therefore, a simple transmission circuit can convert a logical value into a signal, and a simple reception circuit can convert a signal into a logical value. The receiving circuit may restore the original logical value transferred by the transmitting circuit, or may generate a logical value (for example, inverted logic) different from the logical value transferred by the transmitting circuit. In particular, when the present invention is applied to a signal having a large number of bits, such as data or an address, the number of bus lines can be greatly reduced, so that the power consumption is greatly reduced and the apparatus is downsized. Is achieved.

  For example, a variable delay circuit may be formed in the transmission circuit, and the signal to be transmitted may be generated by changing the delay time of the variable delay circuit according to the logical value. In the receiving circuit, the delay circuit that generates multiple timing signals with different phases from the reference timing signal is compared with the phase of the received signal and the timing signal, respectively, and the delay time of the signal relative to the reference timing signal is detected. By forming the comparison circuit, it is possible to easily generate a logical value. At this time, by forming a plurality of latch circuits that respectively latch the signal with the timing signal in the comparison circuit, the phase of the signal can be expressed by the logic level latched by the latch circuit. Furthermore, by forming a simple encoder in the comparison circuit, a logic value can be generated based on the logic level latched in the latch circuit.

  By forming the transmission circuit and the reception circuit on different semiconductor chips, the number of signal lines wired between the semiconductor chips can be reduced. For example, when a semiconductor chip is mounted on a printed board, the signal line area of the printed board can be reduced. As a result, since the printed circuit board becomes small, the system can be downsized and the cost of the system can be reduced.

  By forming the transmission circuit and the reception circuit on the same semiconductor chip, the wiring area in the semiconductor chip can be reduced. As a result, the chip size of the semiconductor chip is reduced, and the chip cost can be reduced.

  In a preferred example of one mode of the input / output interface of the present invention, the transmission circuit and the reception circuit are formed on a plurality of semiconductor chips, respectively, so that data can be transmitted and received with a small number of signal lines. At this time, each semiconductor chip is formed with, for example, a first input circuit and a second input circuit for receiving signals output from other semiconductor chips and a reference timing signal, respectively, for signal reception. As described above, a first output circuit that outputs a signal, a signal generation circuit that generates a reference timing signal based on an external clock signal, and a second output circuit that outputs the reference timing signal to the outside are formed.

At this time, the number of signal lines can be further reduced by connecting the input of the first input circuit and the output of the first output circuit to a common external terminal and making the signal lines bidirectional. Similarly, the number of signal lines can be further reduced by connecting the input of the second input circuit and the output of the second output circuit to a common external terminal and making the signal line of the reference timing signal bidirectional.

  In the input / output interface of the present invention, a logical value of a plurality of bits can be transmitted through one signal line. Therefore, the number of signal lines can be reduced as compared with the prior art. Since the number of signal lines is small, the number of output circuits and input circuits can be reduced, and power consumption can be reduced. Since a large amount of data can be transmitted with one signal transmission, the data transfer rate can be greatly improved. In addition, the wiring area of the signal line can be reduced.

  In the input / output interface of the present invention and the semiconductor integrated circuit of the present invention, a simple transmission circuit can convert a logical value into a signal, and a simple reception circuit can convert a signal into a logical value.

  With the input / output interface of the present invention, data can be transmitted and received with a small number of signal lines.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows a technique related to the present invention. Here, an example in which data is transmitted from the device 10 to the device 12 using four data bus lines (signal lines) DA, DB, DC, and DD will be described.

  The data transmission circuit 14 of the apparatus 10 outputs a low level pulse (hereinafter referred to as L pulse) to the data bus lines DA, DB, DC, DD. The logical value of the data is expressed in the order of the transition edge timing in the L pulse. That is, 24 kinds of logic are expressed by the combination of the leading edge (down edge) of the L pulse, and 24 kinds of logic are expressed by the combination of the trailing edge (up edge) of the L pulse. By combining the front and rear edges, 576 logics can be expressed. This is more than 9 bits (512 patterns) of binary data. In other words, in this example, data of 9 bits or more can be transmitted only by using the four data bus lines DA, DB, DC, and DD.

  The minimum interval between the leading and trailing edges of the signal output to the data bus line DA-DD is set to tD1, and the interval between the closest leading and trailing edges is set to tD2. . As described above, the front edges and rear edges of the signal output to the data bus line DA-DD do not coincide with each other, and the nearest front edge and the nearest rear edge each have the interval tD1. is doing. The interval tD1 is set to a value that can determine the order of transition edges, and the interval tD2 is set to a value that can identify the leading edge and the trailing edge even in a signal having the smallest pulse width. Specifically, the intervals tD1 and tD2 are set according to the characteristics of the transmission circuit 114, the reception circuit 16, and the transmission path (in this example, the data bus line DA-DD).

  On the other hand, the data receiving circuit 16 of the device 12 determines the order of the timings of the leading and trailing edges of the signals transferred via the data bus lines DA, DB, DC, DD, and generates a logical value. Here, the reception circuit 16 may restore the logical value (original logical value) handled by the device 10 and generates a unique logical value (eg, inverted data of the original logical value) handled by the device 12. May be.

  Since the logic is expressed in the relative order of the transition edges of the signal, it is not necessary to synchronize the signal transmitted using the reference signal or the like between the devices 10 and 12. Therefore, the timing design of the data transmission circuit 14 of the device 10 and the data reception circuit 16 of the device 12 is facilitated. The problem of skew of signals transmitted on the data bus line can be easily solved by making the wiring lengths of the data bus lines uniform. As a result, a large amount of data can be reliably transmitted with a simple transmission circuit 14 and reception circuit.

When logic is expressed in the order of the leading edge and trailing edge of the pulse signal, 14400 ((5 × 4 × 3 × 2) ² ) logic can be expressed by using five data bus lines. . This exceeds 13 bits (8192 patterns) of binary data.

  2 to 12 show an input / output interface and a semiconductor integrated circuit related to the present invention. In the figure, a plurality of signal lines are indicated by thick lines.

  The input / output interface includes the data transmission circuit 14 of the device 10 shown in FIG. 1, the data reception circuit 16 of the device 12, and data buses DA, DB, DC, and DD that transfer data from the device 10 to the device 12. Yes. For example, the device 10 is a microcomputer, and the device 12 is a semiconductor memory device such as a DRAM. That is, the devices 10 and 12 are mounted on a system board or the like as another semiconductor chip. In addition to the devices shown in FIG. 1, signal lines for transmitting control signals and address signals are wired between the devices 10 and 12.

  FIG. 2 shows details of the transmission circuit 14 of the device 10. The transmission circuit 14 includes a predecoder 18, a delay circuit 20, selection circuits 22 and 24, and an edge generation circuit 26.

  The predecoder 18 decodes the 9-bit logical values D8 to D0 and outputs a decoded signal.

  The delay circuit 20 has seven delay stages 20a connected in cascade. The first delay stage 20a receives the reference signal STD. The reference signal STD is a high level pulse signal. Each delay stage 20a sequentially delays the reference signal STD and outputs it as timing signals N2-N8. The delay circuit 20 outputs the reference signal STD as the timing signal N1. That is, the delay circuit 20 operates as a timing signal generation circuit that generates a plurality of timing signals N1-N8 having different transition edges. Symbols tD1 and tD2 in the delay stage 20a indicate the intervals (delay time of the delay stage 20a) in FIG. 1, respectively.

  The selection circuit 22 is a circuit that sets the timing of the leading edge of the L pulse signal output from the transmission circuit 14. The selection circuit 22 includes decoders DEC1-DEC4 and selectors SEL1-SEL4. The decoders DEC1-DEC4 generate selection signals for operating the selectors SEL1-SEL4 using the decoded signals. The logic of the decoders DEC1-DEC4 is determined according to a conversion table described later. Each selector SEL1-SEL4 outputs a timing signal N1-N4 to any one of the nodes NDD, NCD, NBD, and NAD according to the selection signal.

  The selection circuit 24 is a circuit that sets the timing of the trailing edge of the L pulse signal output from the transmission circuit 14. The selection circuit 24 includes decoders DEC5-DEC8 and selectors SEL5-SEL8. The decoders DEC5-DEC8 generate selection signals for operating the selectors SEL5-SEL8 using the decoded signals. The logic of the decoders DEC5-DEC8 is determined according to a conversion table described later. Each selector SEL5-SEL8 outputs a timing signal N5-N8 to any one of the nodes NDD, NCD, NBD, and NAD according to the selection signal. Nodes NDD, NCD, NBD, and NAD are nodes corresponding to the data bus lines DD, DC, DB, and DA, respectively.

  The edge generation circuit 26 has four edge generation units 26a corresponding to the nodes NDD, NCD, NBD, and NAD, respectively. The edge generator 26a generates the leading edge of the L pulse signal output to the data bus lines DD, DC, DB, DA in synchronization with the timing signals N1-N4 transmitted to the nodes NDD, NCD, NBD, NAD, respectively. To do. The edge generation unit 26a generates the trailing edge of the L pulse signal output to the data bus lines DD, DC, DB, DA using the timing signals N5-N8 transmitted to the nodes NDD, NCD, NBD, NAD. .

  FIG. 3 shows details of the predecoder 18 of FIG. The predecoder 18 includes a decode circuit that generates four decode signals in accordance with the logical values D8 to D7, a decode circuit that generates four decode signals in accordance with the logical values D6 to D5, and 2 in accordance with the logical value D4. A decoding circuit that generates two decoding signals, a decoding circuit that generates two decoding signals according to the logical value D3, a decoding circuit that generates four decoding signals according to the logical values D2-D1, and a logical value D0. Correspondingly, it has a decode circuit for generating two decode signals. The symbol “/” in the figure indicates negative logic. Each decode circuit sets the corresponding decode signal to a high level when the logical value (for example, D8-D7) is the logic shown in the frame in the figure.

  FIG. 4 shows a conversion table for converting 9-bit logical values D8-D0 into L pulse signals to be output to the data bus line DA-DD. “Order of edges” indicates the order of the timing of the leading edge or trailing edge of the L pulse signal output to the data bus line DA-DD. For example, “ABCD” with the number 0 indicates that the front edge (or rear edge) of the L pulse signal changes in the order of the data bus lines DA, DB, DC, DD, and “BADC” with the number 7 indicates the data bus It shows that the leading edge (or trailing edge) of the L pulse signal changes in the order of lines DB, DA, DD, and DC.

 In this example, as described with reference to FIG. 1, data is transferred using four data bus lines DA-DD. For this reason, there are 24 combinations of the leading edge and trailing edge of the L pulse signal from number 0 to number 23, respectively. With the four L pulse signals, 576 logical values can be expressed. However, this value cannot be expressed in binary numbers. Since the data to be actually transferred is 512 (9 bits), using the logic L1 and logic L2 shown in the figure, control signals for operating the selectors SEL1-SEL8 according to the logic values D8-D0 Is generated. “11bar” in the figure indicates that the logical values D8 to D7 are other than “11”.

  The logical L1 is used when the logical values D8-D0 are "000000000"-"101111111", and the logical L2 is used when the logical values D8-D0 are "110000000"-"111111111". For example, the logical value D8-D0 “001011000” is included in the logical L1. For this reason, as indicated by a thick solid line in the figure, the order of the leading edge is “ADCB” of number 5 and the order of the trailing edge is “BCAD” of number 8. On the other hand, the logic value D8-D0 “111010011” is included in the logic L2. As indicated by a thick broken line in the figure, the order of the leading edge is “ADCB” of number 5 and the order of the trailing edge is “DACB” of number 19. The conversion table is not limited to FIG. Another conversion table may be formed by changing the correspondence between the logical values D8-D0 and the order of the edges.

  FIG. 5 shows details of the decoder DEC1 and the selector SEL1 of FIG. The decoder DEC1 sets any one of the four outputs to a high level according to the logical values D8 to D0 to be transferred. The selector SEL1 turns on one of the four CMOS transmission gates respectively connecting the signal line of the timing signal N1 and the node NAD-NDD according to the output signal of the decoder DEC1. As a result, the timing signal N1 is output to one of the nodes NAD-NDD according to the conversion table shown in FIG. The decoder DEC1 shown in FIG. 5 is only an example for realizing the logic of the conversion table of FIG. 4 with a relatively small number of elements. There are many other circuits for implementing the same logic. Although not particularly illustrated, the decoder DEC2-DEC4 and the selector SEL2-SEL4 are configured in the same manner as the decoder DEC1 and the selector SEL1.

  FIG. 6 shows details of the decoder DEC5 and the selector SEL5 of FIG. The decoder DEC5 sets one of the four outputs to a high level according to the logical values D8 to D0 to be transferred. The selector SEL5 turns on one of the four CMOS transmission gates respectively connecting the signal line of the timing signal N5 and the node NAU-NDU in accordance with the output signal of the decoder DEC5. As a result, the timing signal N5 is output to one of the nodes NAU-NDU according to the conversion table shown in FIG.

  FIG. 7 shows details of the edge generation unit 26a in the edge generation circuit 26 of FIG. The edge generation unit 26a includes an L pulse generation circuit that generates an L pulse in synchronization with any rising edge of the timing signal N1-N4 transmitted to the node NAD (or NBD, NCD, NCD), and a node NAU (or (NBU, NCU, NCU) are connected in series between an H pulse generation circuit that generates an H pulse signal in synchronization with a rising edge of any one of the timing signals N5-N8 and a power line and a ground line pMOS transistor (controlled by the output of the L pulse generating circuit) and nMOS transistor (controlled by the output of the H pulse generating circuit), a latch circuit for latching the outputs of the pMOS transistor and the nMOS transistor, and the pMOS transistor and the nMOS transistor And an open drain type output transistor (output circuit) controlled by the output. The output of the output transistor is connected to a data bus line DA (or DB, DC, DD) connected to a power supply line through a 50Ω termination resistor, for example.

  The data bus line DA (or DB, DC, DD) changes to low level in synchronization with any rising edge of the timing signal N1-N4, and in synchronization with any rising edge of the timing signal N5-N8. Change to high level. That is, an L pulse signal having a front edge and a rear edge synchronized with the selected timing signal is output to the data bus line DA-DD. As a result, 512 logical values D8-D0 can be transmitted only by using the four data bus lines DA-DD.

  FIG. 8 shows details of the receiving circuit 16 in the device 12. The receiving circuit 16 includes an input circuit 28, comparison circuits 30 and 32, transfer circuits 34 and 36, and a decoder 38.

  The input circuit 28 has four input buffers that receive the L pulse signal transmitted via the data bus line DA-DD. The input buffer is composed of a differential amplifier, and receives an L pulse signal at one input and a reference voltage VREF at the other input. The input buffer outputs the received signals as positive logic positive signals PA2, PB2, PC2, and PD2, respectively. The positive signals PA2, PB2, PC2, and PD2 are inverted by an inverter and output as negative logic negative signals NA2, NB2, NC2, and ND2.

  The comparison circuit 30 includes six comparators 30b (second comparators) that compare the timing order of the trailing edges (up edges) of the two L pulse signals. “(CD)” or the like described in the comparator 30b indicates a symbol of a data bus line that transmits an L pulse signal to be compared by the comparator 30b. The comparator 30b outputs the comparison result as a complementary signal.

  The comparison circuit 32 includes six comparators 32b (first comparators) that compare the timing order of the leading edges (down edges) of the two L pulse signals. “(CD)” or the like described in the comparator 32b indicates a symbol of a data bus line that transmits an L pulse signal to be compared by the comparator 32b. The comparator 32b outputs the comparison result as a complementary signal.

  The transfer circuit 34 transfers the complementary signal output from the comparator 30b to the decoder 38 in synchronization with the transfer signal TR2. The transfer signal TR2 is generated by AND logic of the positive signals PA2, PB2, PC2, and PD2. That is, the transfer signal TR2 is output in accordance with the rear edge having the latest timing among the four L pulse signals.

  The transfer circuit 36 transfers the complementary signal output from the comparator 32b to the decoder 38 in synchronization with the transfer signal TR1. The transfer signal TR1 is generated by AND logic of the negative signals NA2, NB2, NC2, and ND2. That is, the transfer signal TR1 is output in accordance with the front edge having the latest timing among the four L pulse signals.

For example, the complementary transfer signals S2-6X and S2-6Z output from the transfer circuit 34 are transmitted from the corresponding comparator 30a at the trailing edge of the L pulse signal on the data bus line DC by the L pulse on the data bus line DD. When it is determined that the timing is earlier than the trailing edge of the signal, the level becomes low level and high level, respectively. The same applies to the complementary transfer signal output from the transfer circuit 36. In addition, the symbols A, B, C, and D shown in the frame of the decoder 38 have a fast transition edge timing of the L pulse signal corresponding to the symbol when the transfer signal from the transfer circuit indicating the symbol is at a high level. It is shown that. Here, the symbols A, B, C, and D correspond to L pulse signals transmitted through the data bus lines DA, DB, DC, and DD, respectively.

  The decoder 38 restores the logic sent from the transmission circuit 14 in accordance with the comparison result (transfer signal) output from the comparators 30b and 32b, and outputs it as logic values D8-D0.

  FIG. 9 shows details of the comparators 30b and 23b of FIG. The comparators 30b and 32b are configured by RS flip-flops that connect the input and output of a two-input NAND gate. The output of the NAND gate is connected to the output terminal via an inverter. For example, when the input IN1 first changes to high level, the outputs OUT1 and OUT2 become high level and low level, respectively, and when the input IN2 changes first to high level, the outputs OUT1 and OUT2 become low level and rear level, respectively.

  FIG. 10 shows a conversion table for restoring the L pulse signal received via the data bus line DA-DD to the original logical values D8-D0. "Number", "Edge order", "Logic L1", and "Logic L2" are the same as those in the conversion table shown in FIG.

  For example, when the “edge order” of the front edge and the rear edge is “ADCB (number 5)” and “BCAD (number 8)”, the outputs of the comparators 32b and 30b are “111000” and “001111”, respectively. become. Here, the output “111000” of the comparator 32b indicates the logic levels of the positive logic transfer signals S1-1Z, S1-2Z, S1-3Z, S1-4Z, S1-5Z, and S1-6Z shown in FIG. Show. Similarly, the output “001111” of the comparator 30b indicates the logic level of the positive logic transfer signals S2-1Z, S2-2Z, S2-3Z, S2-4Z, S2-5Z, and S2-6Z shown in FIG. Show. Then, as indicated by a thick solid line in the figure, the original logical value D8-D0 = “001011000” is restored by the decoder 38.

  When the “edge order” of the front edge and the rear edge is “ADCB (number 5)” and “DACB (number 19)”, respectively, the outputs of the comparators 32b and 30b are “111000” and “110000”. become. At this time, the original logical value D8-D0 = “111010011” is restored by the decoder 38 as indicated by the thick broken line in the figure.

  11 and 12 show details of the decoder 38 of FIG. FIG. 11 shows a logic circuit for restoring the logic values D4-D8. FIG. 12 shows a logic circuit for restoring the logic values D0-D3. These logic circuits are configured according to the conversion table of FIG. The logic circuits shown in FIGS. 11 and 12 are merely examples for realizing the logic with a relatively small number of elements in the conversion table of FIG. There are many other circuits for implementing the same logic.

  In the above example, the logical value is expressed by the order of the transition edge timings of the plurality of signals transmitted respectively on the plurality of data bus lines DA-DD. Therefore, a large amount of data can be transmitted with a small number of signal lines. Since a large amount of data can be transmitted by one signal transmission, the data transfer rate can be greatly improved. Specifically, the logical value is expressed by using the timing order of the leading edge and the trailing edge (a plurality of transition edges) of the pulse signal. For this reason, 576 logics can be expressed by four signal lines. This is more than 9 bits (512 patterns) of binary data.

Since the number of data bus lines DA-DD can be reduced, the number of signal output circuits (output buffers) and the number of input circuits (input buffers) can be reduced. Since fewer circuits operate, power consumption can be reduced on both the signal transmission side and the signal reception side. Further, since the number of data bus lines DA-DD can be reduced, the wiring area can be reduced.

  Since the logic can be expressed by the difference (relative value) of the timing of the transition edge, the reference signal is not necessary. That is, it is not necessary to synchronize the reference signal on the signal transmission side and the signal reception side. For this reason, the configuration of the transmission circuit 14 and the reception circuit 16 can be simplified.

  Further, the transmission circuit 14 and the reception circuit 16 are formed on different semiconductor chips. When the semiconductor chip is mounted on the printed board, the signal line area of the printed board can be reduced. As a result, since the printed circuit board becomes small, the system can be downsized and the cost of the system can be reduced.

  Since the logical value can be expressed by the order of the timing of the transition edge of the signal, both the transmission circuit 14 and the reception circuit 16 can transmit a large amount of data by configuring a simple logic circuit. Specifically, the data transmission circuit 14 of the apparatus 10 may generate an L pulse according to the logical value of the data to be transferred. Therefore, the transmission circuit 14 can be configured with a simple logic circuit. The receiving circuit 16 of the device 12 may compare the edges of the received signals with each other and determine which edge is earlier. Therefore, the de-receiving circuit 16 can also be configured with a simple logic circuit. Since the circuit scale of the transmission circuit 14 and the reception circuit 16 can be reduced, the chip size of the semiconductor integrated circuit on which these circuits are mounted can be reduced.

  Since an open drain type output transistor is formed in the edge generation circuit 26, a plurality of transmission circuits 14 can be connected to the data bus line DA-DD.

  FIG. 13 shows the basic principle of the present invention. In this example, data is transferred from the transmission circuit 40 to the reception circuit 42 using the clock signal line (CLK) for transmitting the reference timing signal CLK (clock signal) and one data bus line (signal line) DATA. explain.

  The transmission circuit 40 outputs a signal SIG delayed by a predetermined time with respect to the up edge of the reference timing signal CLK. The logical value of the data is expressed by the delay time (time difference) of the transition edge of the signal SIG with respect to the transition edge of the reference timing signal CLK. In this example, 2-bit data can be transferred by one signal line by setting four delay times.

  The timing difference of the transition edge of the signal SIG is set to 4 ns. This difference is set according to the characteristics of the transmission circuit 40, the reception circuit 42, and the transmission path (in this example, the data bus line DATA). The reference timing signal CLK and the signal SIG are generated by delaying the reference timing signal CLK itself for a predetermined time according to the logical value. For example, the transition edge of the signal SIG is delayed by 6 ns, 10 ns, 14 ns, and 18 ns, respectively, with respect to the transition edge of the reference timing signal CLK.

  On the other hand, the receiving circuit 42 receives the reference timing signal CLK and the signal SIG, and detects a time difference (delay time) between the transition edge of the signal SIG and the transition edge of the reference timing signal CLK. Then, a logical value is generated according to this difference. Here, the reception circuit 42 may restore the logical value (original logical value) handled by the transmission circuit 40, and a unique logical value (for example, inverted data of the original logical value) handled by the reception circuit 42. It may be generated.

As described above, a plurality of bits of data are transmitted / received through one data bus line DATA. Since the number of data bus lines wired between the transmission circuit 40 and the reception circuit 42 can be reduced, the number of data input circuits and output circuits can be reduced. As a result, power consumption can be reduced. Since the number of input circuits and output circuits is reduced, the chip size of a semiconductor integrated circuit on which these circuits are mounted can be reduced. Since the number of data bus lines is reduced, the wiring area can be reduced.

  In the example described above, the case of transferring 2-bit data has been described, but the present invention can be easily applied to the case of transferring data of 3 bits or more by increasing the set number of delay times. In the case of transferring 3-bit data, eight types of delay times may be set.

  FIG. 14 shows a first embodiment of the input / output interface and semiconductor integrated circuit of the present invention. In the figure, a plurality of signal lines are indicated by thick lines.

  The input / output interface includes the transmission circuit 40, the reception circuit 42, and the data bus DATA shown in FIG. For example, the transmission circuit 40 and the reception circuit 42 are formed in the same clock synchronous semiconductor memory device (semiconductor integrated circuit). The receiving circuit 42 is arranged near the data output pad. The transmission circuit 40 receives multiple bits of data DT0 and DT1 read from a memory core (not shown) and outputs a signal SIG corresponding to the logic to the data bus line DATA. The receiving circuit 42 restores the signal SIG received via the data bus line DATA to the original 2-bit data and outputs it to a data output circuit (peripheral circuit) or the like. The data bus line DATA is wired from the end of the memory core to the vicinity of the output pad, and the wiring length is long.

  The transmission circuit 40 includes a decoder 44, a variable delay circuit 46, and an output unit 48. The decoder 44 decodes the data DT0 and DT1 read from the memory core, and outputs a decoding result (corresponding to a logical value) to the variable delay circuit 46. The variable delay circuit 46 delays the reference timing signal TZ for a predetermined time according to the decoding result, and outputs the delayed signal to the output unit 48. The output unit 48 outputs the received signal as a signal SIG to the data bus line DATA. The reference timing signal TZ is, for example, an internal clock signal synchronized with a clock signal supplied from the outside.

  The reception circuit 42 includes a delay circuit 50, latches 52a, 52b, and 52c, and an encoder 54. The delay circuit 50 receives the reference timing signal TZ, and generates four timing signals TDZ1, TDZ2, TDZ3, and TDZ4 having different phases from the reference timing signal TZ. The latches 52a, 52b, and 52c latch the signal SIG in synchronization with the timing signals TDZ1, TDZ2, and TDZ3, respectively. The encoder 54 generates 2-bit logical values RDT0 and RDT1 based on the logical level of the signal SIG latched in the latches 52a, 52b and 52c. In this embodiment, the logical values RDT1 and RDT2 are the same as the logical values DT0 and DT1. That is, the receiving circuit 42 restores the original data read from the memory core. The logical values RDT0 and RDT1 generated by the receiving circuit 42 may be different from the original logical values DT0 and DT1. For example, the receiving circuit 42 may generate an inverted logic of the original logic value.

  As described above, the latches 52a, 52b, 52c and the encoder 54 compare the phase of the signal SIG transmitted from the transmission circuit 40 and the timing signals TDZ1-TDZ4, respectively, and detect the delay time of the signal SIG with respect to the reference timing signal TZ. It operates as a comparison circuit. The reference timing signal TZ received by the receiving circuit 42 is supplied with a delay corresponding to the load of the data bus line DATA with respect to the reference timing signal TZ received by the transmitting circuit 40.

  FIG. 15 shows details of the transmission circuit 40 of FIG. The decoder 44 receives the logical values DT0 and DT1 read from the memory core via the read amplifier 40a, and decodes the received data. That is, one of the decode signals T0, T1, T2, and T3 changes to a low level according to the logical values DT0 and DT1.

  The variable delay circuit 46 has four delay stages 46a, 46b, 46c, 46d connected in cascade, and switch circuits 46e, 46f, 46g, 46h controlled by decode signals T0-T3, respectively. The delay stages 46a to 46d output delay signals DLY1, DLY2, DLY3, and DLY4 obtained by delaying the reference timing signal TZ by a predetermined time, respectively. The delay time of the delay stages 46a to 46d is set to approximately 4 ns. Therefore, the delay signals DLY1-DLY4 are output with a delay of 4 ns sequentially with respect to the reference timing signal TZ.

  The switch circuits 46e to 46h are composed of a CMOS transmission gate and an inverter that controls the CMOS transmission gate. The switch circuits 46e to 46h each receive the delay signals DLY1 to DLY4 at one terminal and connect the other terminal to the output unit 48. Any one of the delay signals DLY1-DLY4 is output to the output unit 48 in accordance with the decode signals T0-T3.

  The output unit 48 includes a latch circuit 48 a that latches a delay signal output from the variable delay circuit 46 and an output buffer 48 b. The signal SIG having the timing shown in FIG. 13 is latched by the latch circuit 48a and output from the output buffer 48b.

  FIG. 16 shows details of the delay circuit 50 and the latch circuits 52a, 52b, 52c in the receiving circuit 42 of FIG. The delay circuit 50 includes four delay stages 50a, 50b, 50c, and 50d connected in cascade. The delay stages 50a to 50d output timing signals TDZ1, TDZ2, TDZ3, and TDZ4 obtained by delaying the reference timing signal TZ by a predetermined time, respectively. The delay time of the delay stage 50a is set to approximately 8 ns, and the delay time of the delay stages 50b to 50d is set to approximately 4 ns. Therefore, the timing signals TDZ1, TDZ2, TDZ3, and TDZ4 are output with a delay of 8 ns, 12 ns, 16 ns, and 20 ns, respectively, with respect to the reference timing signal TZ.

  The latch circuits 52a, 52b, and 52c include a CMOS transmission gate, an inverter that controls the CMOS transmission gate, and a latch. The latch circuit 52a latches the logic level of the signal SIG in synchronization with the rising edge of the timing signal TDZ1. The latch circuit 52b latches the logic level of the signal SIG in synchronization with the rising edge of the timing signal TDZ2. The latch circuit 52c latches the logic level of the signal SIG in synchronization with the rising edge of the timing signal TDZ3. Therefore, when the rising edge of the signal SIG is earlier than the rising edge of the timing signal, a high level is latched in the latch circuit. When the rising edge of the signal SIG is later than the rising edge of the timing signal, a low level is latched in the latch circuit.

  As described above, the delay of the timing signals TDZ1 to TDZ3 with respect to the reference timing signal TZ is 8 ns, 12 ns, and 16 ns, respectively, and the delay of the signal SIG with respect to the reference timing signal TZ is 6 ns, 10 ns, 14 ns, or 18 ns. is there. That is, in this embodiment, the timing margin for correct operation of the latch circuits 52a-52c is set to 2 ns. The data latched by the latch circuits 52a-52c are output as latch signals L1, L2, L3 and their inverted signals / L1, / L2, / L3, respectively.

  FIG. 17 shows details of the encoder 54 in the receiving circuit 42 of FIG. The encoder 54 includes a decoder 56 that decodes the latch signals L1, L2, L3, / L1, / L2, and / L3, and a data generation circuit 58 that generates a 2-bit logical value according to the decoding result of the decoder 56. is doing.

  The decoder 56 sets any one of the decode signals T5, T6, T7, and T8 to a low level according to the logical values DT1 and DT0 transferred from the transmission circuit 40 of FIG. For example, as shown in parentheses in the figure, when the logic values DT1 and DT0 are "00", the decode signal T5 changes to a low level, and when the logic values DT1 and DT0 are "01", the decode signal T6 is low. Change to level.

  The data generation circuit 58 includes NAND circuits 58a, 58b, 58c, and 58d, CMOS transmission gates 58e, 58f, 58g, and 58h, latches 58i and 58j, switch circuits 58k and 58l, and latches 58m and 58n. ing.

  The NAND circuits 58a to 58d operate when the timing signal TDZ4 is at a low level to perform a logical operation of the decode signals T5-T8, and are deactivated when the timing signal TDZ4 is at a high level to output a low level. That is, data to be encoded is determined in synchronization with the rising edge of the timing signal TDZ4. The timing signal TDZ4 is a signal obtained by further delaying the latest timing signal TDZ3 as shown in FIG. Therefore, the data generation circuit 58 can encode the received data at high speed and reliably by using the timing signal TDZ4.

  The CMOS transmission gates 58e-58h are controlled by the outputs of the NAND circuits 58a-58d, respectively. The node ND0 changes to a high level when the CMOS transmission gate 58e is turned on, and changes to a low level when the CMOS transmission gate 58f is turned on. The node ND1 changes to a high level when the CMOS transmission gate 58g is turned on, and changes to a low level when the CMOS transmission gate 58h is turned on.

  The latches 58i and 58j hold values obtained by inverting the logic levels of the nodes ND0 and ND1, respectively. The switch circuits 58k and 58l are turned on when the timing signal TDZ4 is at a high level, and connect the latches 58i and 58m and the latches 58l and 58n, respectively. The latches 58m and 58n invert the latched values and output them as logic values RDT0 and RDT1. The logical values RDT0 and RDT1 are at the same logical level as the nodes ND0 and ND1.

  FIG. 18 shows operations of the transmission circuit 40 and the reception circuit 42. The transmission circuit 40 generates a reference timing signal TZ using an external clock signal CLK supplied from the outside of the chip. In order to simplify the description, the timings of the reference timing signals TZ used in the transmission circuit 40 and the reception circuit 42 are the same. Actually, the timing of the reference timing signal TZ used in the receiving circuit 42 is delayed in accordance with the load of the data bus line DATA.

  Data read from the memory core is transmitted to the receiving circuit 42 in synchronization with the external clock signal CLK, and output to the outside of the chip in synchronization with the next external clock signal CLK. In this example, data (logical values DT1, DT0) “00”, “01”, “10”, “11” are transmitted to the receiving circuit 42 in synchronization with the 0th to 3rd external clock signals CLK, respectively. The

  First, in the transmission circuit 40, the read amplifier 40a of FIG. 15 operates in synchronization with the rising edge of the 0th reference timing signal TZ, and amplifies the levels of the data DT0 and DT1. The decoder 44 decodes the amplified data DT0 and DT1 (= “00”), and changes only the decode signal T0 to a low level (FIG. 18A).

The variable delay circuit 46 in FIG. 15 sequentially outputs the delay signals DLY1-DLY4 (not shown) in synchronization with the reference timing signal TZ. The switch circuit 46e of the variable delay circuit 46 is turned on in response to the decode signal T0 and transmits the delay signal DLY1 to the output unit 48. Then, a signal SIG corresponding to the logical value is output from the transmission circuit 40 (FIG. 18B).
The delay circuit 50 in the receiving circuit 42 in FIG. 16 sequentially outputs the timing signals TDZ1 to TDZ4 in synchronization with the reference timing signal TZ (FIGS. 18C and 18D). The timing of the rising edge of the transmitted signal SIG is earlier than the timing of the rising edge of the timing signals TDZ1 to TDZ4. Therefore, the latch circuits 52a, 52b, and 52c each take in the high-level signal SIG and output the high-level latch signal L1-L3 and the low-level latch signal / L1- / L3 (not shown).

  The decoder 56 in the encoder 54 in FIG. 17 decodes the latch signals L1-L3 and / L1- / L3, and changes only the decode signal T5 to a low level (FIG. 18 (e)). Due to the change of the decode signal T5, the outputs of the NAND circuits 58b and 58d of the data generation circuit 58 change to a high level, and the CMOS transmission gates 58f and 58h are turned on. As a result, the nodes ND0 and ND1 both change to a low level, and the logical values RDT0 and RDT1 change to a low level (FIG. 18 (f)). That is, the data read from the memory core is restored by the receiving circuit 42. Thereafter, the logical values RDT0 and RDT1 are output to the outside as read data in synchronization with the first external clock signal CLK.

  Thereafter, similarly to the 0th clock cycle, the logical values “01”, “10”, and “11” are transmitted from the transmission circuit 40 to the reception circuit 42 in synchronization with the first to third external clock signals CLK. Is transmitted.

  As described above, in this embodiment, the logical value is expressed by the time difference between the transition edge of the signal SIG transmitted on the data bus line DATA and the transition edge of the reference timing signal TZ. Therefore, a plurality of bits of logical values can be transmitted with one signal line. Therefore, the number of signal lines can be reduced as compared with the prior art. Since the number of signal lines is small, the number of signal output circuits (output buffers) and the number of input circuits (input buffers) can be reduced. Since fewer circuits operate, power consumption can be reduced on both the signal transmission side and the signal reception side.

  Since the number of signal lines is small, the wiring area of the signal lines can be reduced. In particular, when the present invention is applied to a signal having a large number of bits, such as data or an address, a high effect can be obtained. A simple transmission circuit 40 can convert a logical value into a signal, and a simple reception circuit 42 can convert a signal into a logical value.

  The transmission circuit 40 and the reception circuit 42 are formed in the same semiconductor memory device, and the number of data bus lines DATA for data read from the memory core is reduced. For this reason, the wiring area | region in a semiconductor memory device can be made small. As a result, the chip size of the semiconductor memory device can be reduced, and the chip cost can be reduced.

  FIG. 19 shows a second embodiment of the input / output interface and semiconductor integrated circuit of the present invention. The same elements as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  In general, in a semiconductor memory device such as a DRAM, memory cells are formed in most of the chip. For this reason, the transmission circuit 40 for transmitting data read from the memory cell on one end side of the chip and the transmission circuit 40 for transmitting data read from the memory cell on the other end side of the chip are arranged at positions separated from each other. Often. When the distance between one transmission circuit 40, the other transmission circuit, and the reception circuit 42 is different, the lengths of the data bus lines DATA connecting the transmission circuit 40 and the reception circuit 42 are different. At this time, when the timings of the reference timing signal TZ input to the transmission circuit 40 are the same, the delay amount (relative amount) of the signal SIG with respect to the reference timing signal TZ corresponds to the position of the transmission circuit 40 on the reception circuit 42 side. And change. Therefore, it is necessary to adjust the timing of the reference timing signal TZ input to the reception circuit 42 according to the transmission circuit 40 that outputs the signal SIG.

  For example, using the block selection signals BK0Z and BK1Z and the resistors R1 and R2 for selecting the memory core and the transmission circuit 40, the delay amount of the signal SIG can be easily adjusted on the reception circuit 42 side. In the example shown in the figure, when the signal SIG is output from the lower transmission circuit 40 having a large wiring load, the reference timing signal TZ is delayed by R2 having a large resistance. When the signal SIG is output from the upper transmission circuit 40 having a small wiring load, the reference timing signal TZ is delayed by R1 having a small resistance.

  When the circuit that generates the reference timing signal TZ is arranged near the transmission circuit 40 on the lower side of the figure, the load of the signal line of the reference timing signal TZ between the two transmission circuits 40 and the data bus line The DATA load is almost equal. In this case, since the delay amount (relative amount) of the signal SIG with respect to the reference timing signal TZ is constant, it is not necessary to adjust the timing of the reference timing signal TZ input to the receiving circuit 42.

  Also in this embodiment, the same effect as that of the first embodiment described above can be obtained. Furthermore, it is possible to prevent a shift in reception data fetch timing due to a difference in load on the data bus line DATA wired between the plurality of transmission circuits 40 and the reception circuit in the semiconductor memory device.

  FIG. 20 shows a third embodiment of the input / output interface and semiconductor integrated circuit of the present invention. The same elements as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  In this embodiment, the semiconductor integrated circuits (semiconductor chips) 60 and 62 are formed with the transmission circuit 40 and the reception circuit 42 of the second embodiment. For example, the semiconductor integrated circuits 60 and 62 are mounted on a printed circuit board and connected via a system bus on the printed circuit board. The semiconductor integrated circuits 60 and 62 transmit / receive data to / from each other.

  Since the input / output interface circuits of the semiconductor integrated circuits 60 and 62 are the same, only the semiconductor integrated circuit 60 will be described below. The semiconductor integrated circuit 60 includes a SIG input buffer 64 (first input circuit), a SIG output buffer 66 (first output circuit), a TZ input buffer 68 (second input circuit), a TZ output buffer 70 (second output circuit), A TZ generation circuit (signal generation circuit) 72 and a clock input buffer 74 are provided.

  The SIG input buffer 64 outputs the signal SIG output from the semiconductor integrated circuit 62 to the receiving circuit 42. The SIG output buffer 66 outputs the signal SIG output from the transmission circuit 40 to the data bus line DATA. The TZ input buffer 68 outputs the reference timing signal TZ output from the semiconductor integrated circuit 62 to the receiving circuit 42. The TZ output buffer 70 outputs the reference timing signal TZOUT output from the TZ generation circuit 72 to the transmission circuit 40. That is, the reference timing signal TZOUT generated by the TZ generation circuit 72 is not output directly to the system bus but is output via the TZ output buffer 70. The TZ generation circuit 72 generates a reference timing signal TZOUT synchronized with the internal clock signal CLK1 output from the clock input buffer 74. The clock input buffer 74 receives an external clock signal CLK from the outside and outputs it as an internal clock signal CLK1.

  The input of the SIG input buffer 64 and the output of the SIG output buffer 66 are connected to the data bus line DATA via a common external terminal. Similarly, the TZ input buffer 68 and the TZ output buffer 70 are connected to the signal line of the reference timing signal TZ through a common external terminal. By making the data bus line DATA and the signal line of the reference timing signal TZ bidirectional, the wiring area of the signal line can be further reduced.

  The semiconductor integrated circuit 60 operates the SIG input buffer 64 and the TZ input buffer 68 when receiving the signal SIG, and when transmitting the signal SIG, the SIG output buffer 66, the TZ output buffer 70, and the TZ generation circuit 72. Work. Thus, by forming the transmission circuit 40 and the reception circuit 42 in the semiconductor integrated circuits 60 and 62, the signal SIG can be transmitted bidirectionally using a small number of data bus lines DATA.

  Also in this embodiment, the same effect as that of the first embodiment described above can be obtained. Furthermore, since the transmission circuit 40 and the reception circuit 42 are formed on a plurality of semiconductor integrated circuits, data can be transmitted and received with a small number of signal lines.

  Further, since the input of the SIG input buffer 64 and the output of the SIG output buffer 66 are connected to a common external terminal and the signal lines are bidirectional, the number of signal lines can be further reduced. Similarly, since the input of the TZ input buffer 68 and the output of the TZ output buffer 70 are connected to a common external terminal and the signal line of the reference timing signal TZ is bidirectional, the number of signal lines can be further reduced.

  FIG. 21 shows a fourth embodiment of the input / output interface and semiconductor integrated circuit of the present invention. The same elements as those in the first and third embodiments are denoted by the same reference numerals, and detailed description thereof is omitted. The invention of this embodiment is applied to the memory interface device 76 and the system bus. The memory interface device 76 connects the system bus and the semiconductor memory device 78. The semiconductor memory device 78 is, for example, a conventional SDRAM (general purpose memory).

  The memory interface device 76 includes the same reception circuit 42, transmission circuit 40, SIG input buffer 64, SIG output buffer 66, TZ input buffer 68, TZ output buffer 70, TZ generation circuit 72, and clock input buffer 74 as in FIG. is doing. Further, the memory interface device 76 includes an address input buffer 80, a command input buffer 82, and a receiving circuit 42 that receives the address signal AD. In this embodiment, the present invention is applied to a data bus and an address bus.

  The address input buffer 80 receives the address signal AD from the system bus in synchronization with the reference timing signal TZ, and outputs the received address to the address receiving circuit 42. The command input buffer 82 receives a command signal CMD from the system bus and outputs the received command to the semiconductor memory device 78. Data received by the data reception circuit 42 and data (input / output data) read from the semiconductor memory device 78 and supplied to the transmission circuit 40 are transmitted via a data bus line common to input and output.

  In this embodiment, data and addresses supplied via the system bus are converted into conventional multi-bit data and addresses by the memory interface device 76 and supplied to the semiconductor memory device 78. Then, a write operation or the like is executed. Further, data consisting of a plurality of bits read from the semiconductor memory device 78 by the read operation is converted into the interface of the present invention by the memory interface device 76 and output to the system bus.

  The command signal CMD and the external clock signal CLK may be supplied directly from the system bus to the semiconductor memory device 78 without going through the memory interface device 76. However, by using the command input buffer 82 and the clock input buffer 74, the optimum timing can be set for the data and the address.

  Also in this embodiment, the same effect as the first and third embodiments described above can be obtained. Further, since the present invention is applied not only to the data signal interface but also to the address signal interface, the number of signal lines of the system bus can be reduced as compared with the third embodiment, and the power consumption can be further reduced.

  In addition, since the present invention is applied to the memory interface device 76, a general-purpose memory that has been mass-produced in the past can be easily connected to a system bus employing the present invention.

  In the first embodiment described above, the example in which the present invention is applied to an interface for transmitting data read from a memory core to a peripheral circuit has been described. The present invention is not limited to such an embodiment. For example, the present invention may be applied to an interface for transmitting write data from a peripheral circuit to a memory core.

  In the above-described first embodiment, the example in which the transmission circuit 40 and the reception circuit 42 are formed in the same semiconductor memory device has been described. The present invention is not limited to such an embodiment. For example, by forming the transmission circuit 40 and the reception circuit 42 on different semiconductor chips, the number of signal lines wired between the semiconductor chips can be reduced. For example, when a semiconductor chip is mounted on a printed board, the signal line area of the printed board can be reduced. As a result, since the printed circuit board becomes small, the system can be downsized and the cost of the system can be reduced.

The invention described in the above embodiments is organized and disclosed as an appendix.
(Supplementary note 1) An input / output interface characterized in that a logical value is expressed by a time difference between a transition edge of a signal transmitted on a signal line and a transition edge of a reference timing signal.
(Appendix 2) In the input / output interface described in Appendix 1,
A transmission circuit that converts a logical value expressed by a plurality of bits into a predetermined delay time and outputs the signal delayed by the delay time with respect to a reference timing signal to the signal line;
A receiving circuit that detects a delay time of the transition edge of the signal transmitted through the signal line with respect to the reference timing signal and generates a logical value according to the delay time. Output interface.
(Appendix 3) In the input / output interface described in Appendix 2,
The input / output interface, wherein the transmission circuit includes a variable delay circuit that delays the reference timing signal according to the logical value and generates the signal.
(Appendix 4) In the input / output interface described in Appendix 2,
The receiver circuit generates a plurality of timing signals having different phases from the reference timing signal based on the reference timing signal;
An input / output interface comprising: a comparison circuit for comparing a phase of the signal with a phase of the timing signal and detecting a delay time of the signal with respect to the reference timing signal.
(Appendix 5) In the input / output interface described in Appendix 4,
The comparison circuit includes a plurality of latch circuits that respectively latch the signal with the timing signal;
An input / output interface comprising: an encoder that generates a logical value based on a logical level of a signal latched in each of the latch circuits.
(Appendix 6) In the input / output interface described in Appendix 2,
The input / output interface, wherein the signal is a signal representing at least one of data and an address.
(Appendix 7) In the input / output interface described in Appendix 2,
The input / output interface, wherein the logical value generated by the receiving circuit is an original logical value handled by a device that transmits the signal.
(Appendix 8) In the input / output interface described in Appendix 2,
The input / output interface, wherein the transmission circuit and the reception circuit are formed on different semiconductor chips, respectively.
(Appendix 9) In the input / output interface described in Appendix 2,
The input / output interface, wherein the transmission circuit and the reception circuit are formed on the same semiconductor chip.
(Appendix 10) In the input / output interface described in Appendix 2,
The transmission circuit and the reception circuit are respectively formed on a plurality of semiconductor chips,
Each of the semiconductor chips receives a first input circuit and a second input circuit that receive the signal output from the other semiconductor chip and the reference timing signal, respectively, and a signal that generates the reference timing signal based on an external clock signal An input / output interface comprising: a generation circuit; and a first output circuit that outputs the signal.
(Appendix 11) In the input / output interface described in Appendix 10,
Each of the semiconductor chips is provided with a second output circuit that outputs the reference timing signal to the outside.
(Appendix 12) In the input / output interface described in Appendix 11,
An input / output interface, wherein an input of the second input circuit and an output of the second output circuit are connected to a common external terminal.
(Appendix 13) In the input / output interface described in Appendix 10,
An input / output interface, wherein an input of the first input circuit and an output of the first output circuit are connected to a common external terminal.
(Additional remark 14) It is provided with the transmission circuit which converts the logical value expressed by a plurality of bits into a predetermined delay time and outputs the signal delayed by the delay time with respect to the reference timing signal to the signal line. A semiconductor integrated circuit.
(Supplementary Note 15) A semiconductor comprising a receiving circuit that detects a delay time with respect to a reference timing signal at a transition edge of a signal transmitted via a signal line, and generates a logical value according to the delay time. Integrated circuit.

  As mentioned above, although this invention was demonstrated in detail, said embodiment and its modification are only examples of this invention, and this invention is not limited to this. Obviously, modifications can be made without departing from the scope of the present invention.

  The present invention can be applied to a semiconductor integrated circuit that transmits and receives signals.

It is explanatory drawing which shows the technique relevant to this invention. It is a block diagram which shows the detail of the transmission circuit relevant to this invention. FIG. 3 is a block diagram showing details of the predecoder in FIG. 2. It is a conversion table for converting a logical value into a signal output to a data bus line. FIG. 2 is a circuit diagram showing details of a decoder DEC1 and a selector SEL1 in FIG. FIG. 2 is a circuit diagram showing details of a decoder DEC5 and a selector SEL5 in FIG. FIG. 2 is a circuit diagram illustrating details of an edge generation unit in the edge generation circuit of FIG. 1. It is a block diagram which shows the detail of the receiving circuit relevant to this invention. It is a circuit diagram which shows the detail of the comparator of FIG. It is a conversion table for restoring the signal received via the data bus line to the original logical value. It is a circuit diagram which shows the detail of the decoder of FIG. It is a circuit diagram which shows the detail of the decoder of FIG. It is explanatory drawing which shows the basic principle of this invention. It is a block diagram which shows 1st Embodiment. It is a circuit diagram which shows the detail of the transmission circuit of FIG. FIG. 15 is a circuit diagram illustrating details of a delay circuit and a latch circuit of the reception circuit of FIG. 14. FIG. 15 is a circuit diagram showing details of an encoder of the receiving circuit of FIG. 14. FIG. 3 is a timing diagram illustrating operations of a transmission circuit and a reception circuit in the first embodiment. It is a block diagram which shows 2nd Embodiment. It is a block diagram which shows 3rd Embodiment. It is a block diagram which shows 4th Embodiment.

Explanation of symbols

10 device 12 device 14 data transmission circuit 16 data reception circuit 18 predecoder 20 delay circuit 20a delay stage 22 selection circuit 23b comparator 24 selection circuit 26 edge generation circuit 26a edge generation unit 28 input circuit 30, 32 comparison circuit 30b comparator 34 36 Transfer circuit 38 Decoder 40 Transmit circuit 40a Read amplifier 42 Receive circuit 44 Decoder 46 Variable delay circuit 48 Output unit 50 Delay circuits 52a, 52b, 52c Latch 54 Encoder 56 Decoder 58 Data generation circuit 60, 62 Semiconductor integrated circuit 64 SIG input Buffer 66 SIG output buffer 68 TZ input buffer 70 TZ output buffer 72 TZ generation circuit 74 Clock input buffer 76 Memory interface device 78 Semiconductor memory device 80 Address input buffer 82 Command input buffer
CLK External clock signal
D0-D8 logical value
DA, DB, DC, DD Data bus
DATA Data bus line
DLY1, DLY2, DLY3, DLY4 Delay signal
DT0, DT1 logical value, data
N1-N8 timing signal
RDT0, RDT1 logical value
SIG signal
STD reference signal
T0, T1, T2, T3 decode signal
TDZ1, TDZ2, TDZ3, TDZ4 timing signals
TZ reference timing signal

Claims (8)

An input / output interface that represents a logical value by a time difference between a transition edge of a signal transmitted on a signal line and a transition edge of a reference timing signal ,
A transmission circuit that converts a logical value expressed by a plurality of bits into a predetermined delay time and outputs the signal delayed by the delay time with respect to a reference timing signal to the signal line;
A reception circuit that detects a delay time of the transition edge of the signal transmitted through the signal line with respect to the reference timing signal and generates a logical value according to the delay time;
The transmission circuit and the reception circuit are respectively formed on a plurality of semiconductor chips,
Each of the semiconductor chips generates the reference timing signal based on a common external clock signal and a first input circuit and a second input circuit that receive the signal output from the other semiconductor chip and the reference timing signal, respectively. An input / output interface comprising: a signal generation circuit that outputs the signal; and a first output circuit that outputs the signal. The input / output interface according to claim 1.
Each of the semiconductor chips includes a second output circuit that outputs the reference timing signal to the outside.
An input / output interface, wherein an input of the second input circuit and an output of the second output circuit are connected to a common external terminal . The input / output interface according to claim 1.
An input / output interface, wherein an input of the first input circuit and an output of the first output circuit are connected to a common external terminal .   The input / output interface according to claim 1.
  The receiver circuit generates a plurality of timing signals having different phases from the reference timing signal based on the reference timing signal;
  An input / output interface comprising: a comparison circuit for comparing a phase of the signal with a phase of the timing signal and detecting a delay time of the signal with respect to the reference timing signal.   The input / output interface according to claim 4,
  The comparison circuit includes a plurality of latch circuits that respectively latch the signal with the timing signal;
  An input / output interface comprising: an encoder that generates a logical value based on a logical level of a signal latched in each of the latch circuits.   A semiconductor integrated circuit that expresses a logical value by a time difference between a transition edge of a signal transmitted on a signal line and a transition edge of a reference timing signal,
  A transmission circuit that converts a logical value expressed by a plurality of bits into a predetermined delay time and outputs the signal delayed by the delay time with respect to a reference timing signal to the signal line;
  A receiving circuit that detects a delay time of the transition edge of the signal transmitted through the signal line with respect to the reference timing signal, and generates a logical value according to the delay time;
  A first input circuit and a second input circuit that respectively receive the signal and the reference timing signal supplied from outside; a signal generation circuit that generates the reference timing signal based on a common external clock signal; and A semiconductor integrated circuit comprising: a first output circuit that outputs to the outside.   The semiconductor integrated circuit according to claim 6.
  A second output circuit for outputting the reference timing signal to the outside;
  An input of the second input circuit and an output of the second output circuit are connected to a common external terminal.   The semiconductor integrated circuit according to claim 6.
  An input of the first input circuit and an output of the first output circuit are connected to a common external terminal.

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