JP3927180B2 - Semiconductor device manufacturing apparatus and manufacturing method - Google Patents

Semiconductor device manufacturing apparatus and manufacturing method Download PDF

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JP3927180B2
JP3927180B2 JP2004011032A JP2004011032A JP3927180B2 JP 3927180 B2 JP3927180 B2 JP 3927180B2 JP 2004011032 A JP2004011032 A JP 2004011032A JP 2004011032 A JP2004011032 A JP 2004011032A JP 3927180 B2 JP3927180 B2 JP 3927180B2
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process processing
semiconductor element
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JP2005203711A (en
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日出夫 南
英瑞 岩本
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Ueno Seiki Co Ltd
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本発明は、チップ部品等の半導体素子の製造装置およびその方法に関するものであり、詳しくは、複数の半導体素子を搭載しているリードフレーム、トレイ、粘着シートから個別に半導体素子を分離し、特性テスト、梱包(テーピング)処理等の各処理を行う製造装置において、複数の処理機構に半導体素子を搬送しながら処理を行う半導体素子製造装置および製造方法を提供するものである。   The present invention relates to an apparatus and method for manufacturing a semiconductor element such as a chip component, and more specifically, separates a semiconductor element from a lead frame, a tray, and an adhesive sheet on which a plurality of semiconductor elements are mounted. The present invention provides a semiconductor device manufacturing apparatus and a manufacturing method for performing a process while transporting a semiconductor element to a plurality of processing mechanisms in a manufacturing apparatus that performs each process such as a test and a packing (taping) process.

ミニモールドトランジスタ等の半導体素子を含む電子部品は、短冊状のリードフレームを用いて数多くの電子部品が一括して製造され、これを個々の電子部品に分けて出荷される。この場合、リードフレームから電子部品を取り出した後、搬送機構を用いて搬送し、この搬送過程で、外観の寸法や電気特性の測定、捺印など出荷に際して必要とされる一連の工程処理を経て、梱包テープに挿入される。   Electronic components including semiconductor elements such as mini-mold transistors are manufactured in a batch using a strip-shaped lead frame, and these are divided into individual electronic components before shipment. In this case, after taking out the electronic components from the lead frame, they are transported using a transport mechanism, and in this transport process, after undergoing a series of process processing required for shipping such as measurement of external dimensions and electrical characteristics, and stamping, Inserted into packing tape.

また、最近では、携帯型コンピュータの普及で需要が増大傾向にあるCSP(Chip Size Package )等のリードレス半導体素子についても、ブレージング工程で個々に分断されて製造されたリードレス半導体素子を特性測定や外観検査等の複合処理を行ってから品質ランク別にテーピング梱包して出荷している。すなわち、リードレス半導体素子Sのブレージング工程では、複数のリードレス半導体素子が高密度で一連に形成された薄板形状の樹脂モールド基板をウェーハシートに貼着した状態でブレージングソーによって個々のリードレス半導体素子に細分割しており、この工程でミリサイズに細分割されたリードレス半導体素子Sの個々が、次の複合工程処理に送られて、各処理がなされる。   In recent years, the characteristics of leadless semiconductor elements such as CSP (Chip Size Package), which are in increasing demand due to the spread of portable computers, are also measured in the brazing process. After performing combined processing such as visual inspection and taping, it is shipped by taping according to quality rank. That is, in the brazing process of the leadless semiconductor element S, individual leadless semiconductors are formed by a brazing saw in a state in which a thin resin-molded substrate in which a plurality of leadless semiconductor elements are formed in series at a high density is attached to a wafer sheet. The element is subdivided into elements, and each of the leadless semiconductor elements S subdivided into millimeter sizes in this process is sent to the next composite process, and each process is performed.

具体的には、半導体素子を保持した保持機構が、搬送機構の駆動によって、半導体素子製造装置上に配置した工程処理機構に順次搬送されながら、複数の工程処理を経ることとなる。このような半導体素子製造装置における保持機構としては、真空吸着式やチャック式のように何らかの保持手段を有するものがあり、また、工程処理機構は一般的にはターンテーブル型や直線搬送型の搬送ユニットを1つ、または複数の組合せで構成し、さらに、ターンテーブルや搬送ユニット上に複数の工程処理を備えるものが用いられている。そして、搬送機構は、上記のような保持機構を備え、工程処理機構に設けられた工程処理部を間欠的に回転することによって工程処理の間を搬送されながら、半導体素子を工程処理機構の工程処理位置ごとに停止し、半導体素子を工程処理機構に挿入して、電気特性や外観検査等の各工程処理を行う。工程処理完了後は、搬送機構は半導体素子を工程処理機構から引出し、再び駆動して次の工程処理へ半導体素子を搬送する(例えば、下記特許文献1、2)。
特許2531006号公報 特許2667712号公報
Specifically, the holding mechanism holding the semiconductor element is subjected to a plurality of process processes while being sequentially transferred to the process processing mechanism disposed on the semiconductor element manufacturing apparatus by driving of the transfer mechanism. As a holding mechanism in such a semiconductor element manufacturing apparatus, there is a holding mechanism such as a vacuum suction type or a chuck type, and a process processing mechanism is generally a turntable type or a linear conveyance type conveyance. A unit is composed of one or a plurality of combinations, and a unit having a plurality of process processes on a turntable or a transport unit is used. The transport mechanism includes the holding mechanism as described above, and intermittently rotates the process processing unit provided in the process processing mechanism, thereby transporting the semiconductor element between the process processes. The process is stopped for each processing position, and a semiconductor element is inserted into the process processing mechanism to perform each process such as electrical characteristics and appearance inspection. After the process processing is completed, the transport mechanism pulls out the semiconductor element from the process processing mechanism and is driven again to transport the semiconductor element to the next process process (for example, Patent Documents 1 and 2 below).
Japanese Patent No. 2531006 Japanese Patent No. 2667712

しかしながら、上記従来の半導体素子製造装置においては、以下のような課題があった。すなわち、ターンテーブル上にはその円周等配位置に外観検査や電気特性検査などの多数の工程処理を設けているが、工程処理機構の各工程ではそれぞれ目的に応じた別異の工程処理を行うため工程毎に処理時間に差がある。例えば、図7に示すように、ある停止位置において、電気特性測定、位置合わせ及び外観検査の各工程処理を同時に行った場合、外観検査は、その処理の特性上、電機特性検査の半分以下の時間で処理が終了するにもかかわらず、処理終了後も電機特性検査の処理が終了するのを待機していなければならない。すなわち、ターンテーブルを間欠回転させて全処理を一括して行うような搬送機構においては、ターンテーブルの停止時間を最も時間の要する工程に、他の工程の処理時間を合わせる必要がある。このため、実際には停止時間の半分以下の時間で終わっている作業を処理時間と同等時間さらに待機させなければならないこととなり、作業効率が悪く、結果として生産性の低下を招来するものとなっていた。   However, the conventional semiconductor element manufacturing apparatus has the following problems. That is, on the turntable, many process processes such as appearance inspection and electrical characteristic inspection are provided at the circumferentially equidistant positions, but each process of the process processing mechanism performs different process processes according to the purpose. Therefore, there is a difference in processing time for each process. For example, as shown in FIG. 7, when each process process of electrical characteristic measurement, alignment, and appearance inspection is performed at a certain stop position, the appearance inspection is less than half of the electrical characteristics inspection due to the characteristics of the process. In spite of the completion of the process in time, it is necessary to wait for the electrical characteristic inspection process to be completed even after the process is completed. That is, in a transport mechanism that performs intermittent rotation of the turntable and performs all processes at once, it is necessary to match the processing time of other processes with the process that requires the longest stoppage time. For this reason, in practice, work that has been completed in less than half of the stop time must be kept on standby for a time equivalent to the processing time, resulting in poor work efficiency and consequently reduced productivity. It was.

また、上記のような問題から処理効率の向上を図るべく、従来技術においては、工程処理機構に可能な限り多くの工程を設け、さらに搬送機構(ターンテーブル)を複数設ける構成としているが、この場合、工程処理機構及び搬送機構自体の大型化、複雑化あるいは高コスト化は免れず、これによる停止位置の精度低下と共に半導体素子の微小化への対応が困難となっていた。また、装置の大型化と相まって、出力の大きな駆動源や制動力の大きな停止機構が必要となるため、装置がさらに高重量化することとなり、これによる搬送機構のトラブル増加や装置全体の振動増加、さらには装置全体のトラブルの増加、装置設置床への要求強度の増加等も懸念されていた。   Further, in order to improve the processing efficiency due to the problems as described above, in the prior art, the process processing mechanism is provided with as many processes as possible, and a plurality of transfer mechanisms (turntables) are provided. In this case, the process processing mechanism and the conveyance mechanism itself are not enlarged, complicated, or expensive, and it is difficult to cope with the miniaturization of the semiconductor element as the stop position accuracy decreases. Also, coupled with the increase in size of the device, a drive source with a large output and a stop mechanism with a large braking force are required, which further increases the weight of the device, resulting in increased trouble in the transport mechanism and increased vibration of the entire device. Furthermore, there are concerns about an increase in troubles in the entire apparatus and an increase in required strength of the apparatus installation floor.

本発明は上記のような従来技術の問題点を解決するために提案されたものであり、その目的は、半導体素子に各工程処理を施す機構に半導体素子を搬送しながら工程処理を行う半導体素子の製造装置および製造方法において、半導体素子を搬送する搬送機構の一回の停止あたりの工程処理を増加させることによって、搬送機構の小型化、軽量化が図れ、半導体素子の微小化にも対応可能で、作業効率、生産性が高い半導体素子製造装置および製造方法を提供するものである。   The present invention has been proposed in order to solve the above-described problems of the prior art, and the object thereof is a semiconductor element that performs process processing while transporting the semiconductor element to a mechanism that performs each process process on the semiconductor element. By increasing the number of process steps per stop for the transport mechanism that transports semiconductor elements, the transport mechanism can be reduced in size and weight, and can be used for miniaturization of semiconductor elements. Thus, the present invention provides a semiconductor device manufacturing apparatus and a manufacturing method with high work efficiency and high productivity.

上記目的を達成するために、請求項1の発明は、間欠的に回転するターンテーブル式の搬送機構と、この搬送機構の円周等配位置に複数設けられ半導体素子を保持する保持機構と、この保持機構が間欠的に停止する停止位置と合致する位置に設けられ半導体素子に所定の工程処理を施す複数種の工程処理機構とを備え、前記搬送機構の間欠回転によって搬送される半導体素子に対して、前記保持機構が前記搬送機構の回転軸方向に移動して前記工程処理機構の工程処理部に半導体素子を供給することで半導体素子に所定の工程処理を施す半導体素子製造装置において、前記複数種の工程処理機構のうち少なくとも一つには、種類の異なる工程処理部が前記保持機構の移動方向に対して並んで設けられた工程処理群を備え、前記保持機構は、前記搬送機構の回転軸方向に移動して前記工程処理群を形成する複数の工程処理部に半導体素子を供給するものであることを特徴とする。 In order to achieve the above object, the invention of claim 1 includes a turntable type transport mechanism that rotates intermittently, a holding mechanism that holds a plurality of semiconductor elements provided at circumferentially equidistant positions of the transport mechanism, The holding mechanism is provided at a position that coincides with a stop position at which the holding mechanism is intermittently stopped, and includes a plurality of types of process processing mechanisms that perform predetermined process processing on the semiconductor element. On the other hand, in the semiconductor element manufacturing apparatus that performs a predetermined process on the semiconductor element by moving the holding mechanism in the direction of the rotation axis of the transport mechanism and supplying the semiconductor element to the process processing unit of the process processing mechanism, At least one of the plurality of types of process processing mechanisms includes a process processing group in which different types of process processing units are provided side by side with respect to the movement direction of the holding mechanism. Wherein the multiple step processing unit to move in the rotational axis direction of the transport mechanism forming the step treatment groups and supplies a semiconductor device.

請求項4の発明は、請求項1の発明を方法の観点から捉えたものであって、間欠的に回転するターンテーブル式の搬送機構と、この搬送機構の円周等配位置に複数設けられ半導体素子を保持する保持機構と、この保持機構が間欠的に停止する停止位置と合致する位置に設けられ半導体素子に所定の工程処理を施す複数種の工程処理機構とを制御装置により制御して、前記搬送機構の間欠回転によって搬送される半導体素子に対して、前記保持機構により前記搬送機構の回転軸方向に移動させて前記工程処理機構の工程処理部に半導体素子を供給することで半導体素子に所定の工程処理を施す半導体素子製造方法において、前記複数種の工程処理機構のうち少なくとも一つには、種類の異なる工程処理部が前記保持機構の移動方向に対して並んで設けられた工程処理群を備え、前記制御装置により、前記保持機構を、前記搬送機構の回転軸方向に移動させ前記工程処理群を形成する複数の工程処理部に半導体素子を供給させることを特徴とする。 The invention of claim 4 captures the invention of claim 1 from the viewpoint of the method, and a plurality of turntable transport mechanisms that rotate intermittently and a plurality of circumferentially equidistant positions of the transport mechanism are provided. A control device controls a holding mechanism that holds the semiconductor element and a plurality of process processing mechanisms that are provided at positions that coincide with a stop position at which the holding mechanism stops intermittently and that performs predetermined process processing on the semiconductor element. The semiconductor element is moved by the holding mechanism in the direction of the rotation axis of the transfer mechanism with respect to the semiconductor element transferred by the intermittent rotation of the transfer mechanism, and the semiconductor element is supplied to the process processing unit of the process processing mechanism. In the method of manufacturing a semiconductor device in which a predetermined process is performed, at least one of the plurality of types of process processing mechanisms includes different types of process processing units arranged in the moving direction of the holding mechanism. A plurality of process processing units that form the process processing group by moving the holding mechanism in the direction of the rotation axis of the transport mechanism by the control device. And

以上のような構成を有する請求項1または4の発明によれば、半導体素子に所定の工程処理を行う工程処理部を2ヵ所、またはそれ以上設けた工程処理群を形成することによって、半導体素子の搬送機構の一回の停止あたり、処理時間の短い処理工程を複数施すことができ、搬送機構の停止個所を減らすことが可能となる。また、処理時間の長い処理工程部を単独で設け、処理時間の短い処理工程部を複数組み合わせた処理工程群を設けることによって、作業効率、生産性の向上を図ることが可能となる。   According to the invention of claim 1 or 4 having the above-described configuration, a semiconductor element is formed by forming a process processing group in which two or more process processing parts for performing predetermined process processing are provided on the semiconductor element. A plurality of processing steps with a short processing time can be performed per one stop of the transport mechanism, and the number of stops of the transport mechanism can be reduced. Further, it is possible to improve work efficiency and productivity by providing a processing step unit having a long processing time and providing a processing step group in which a plurality of processing step units having a short processing time are combined.

また、搬送機構の停止位置の減少に伴い、搬送機構に設ける保持機構の数を減少させることができるので、搬送機構の小型化、軽量化が可能となる。これにより、搬送機構の停止位置の精度が向上し、それに伴う半導体素子微小化への対応が容易となる。さらに、搬送機構の駆動源の簡略化、停止機構の軽量化が可能で、装置全体のエネルギー消費量の低減および重量減による搬送機構のトラブル減少を図ることができ、ひいては、装置全体の振動減少やトラブル減少、装置設置床への要求強度減少を図ることが可能となる。   Further, since the number of holding mechanisms provided in the transport mechanism can be reduced as the stop position of the transport mechanism decreases, the transport mechanism can be reduced in size and weight. Thereby, the accuracy of the stop position of the transport mechanism is improved, and it becomes easy to cope with the miniaturization of the semiconductor element. Furthermore, the drive source of the transport mechanism can be simplified and the stop mechanism can be reduced in weight, so that the energy consumption of the entire device can be reduced and the trouble of the transport mechanism can be reduced by reducing the weight. It is possible to reduce the trouble and the required strength of the equipment installation floor.

請求項2の発明は、前記請求項1の発明において、前記複数種の工程処理機構は、各々処理時間の異なる工程処理を備え、単独の工程処理部を備えた工程処理機構と、前記工程処理群を備えた工程処理機構との処理時間が略同一となるように構成されていることを特徴とする。以上のような請求項2の発明では、複数の工程処理部をその処理時間に応じて組み合わせ、各工程処理群の処理時間あるいは単独の工程処理部の処理時間を略同一とすることによって、単独の工程処理部のみで構成した装置のように工程処理時間の長い工程に工程処理時間の短い工程が合わせなければならないような必要はなく、複数の工程処理部の処理時間の和によって各工程処理群の処理時間を調整することが可能となるので、著しい作業効率、生産性の向上を図ることが可能となる。 According to a second aspect of the present invention, in the first aspect of the invention, the plurality of types of process processing mechanisms include process processes each having a different processing time, and a process processing mechanism including a single process processing unit, and the process processing. The processing time of the process processing mechanism provided with the group is configured to be substantially the same. In the invention of claim 2 as described above, a plurality of process processing units are combined according to the processing time, and the processing time of each process processing group or the processing time of a single process processing unit is made substantially the same. There is no need for a process with a short process processing time to be combined with a process with a long process processing time as in the case of an apparatus constituted only by the process processing section. Since it becomes possible to adjust the processing time of the group, it is possible to significantly improve work efficiency and productivity.

請求項3の発明は、前記請求項1または2の発明において、前記複数の保持機構は、前記工程処理機構ごとに各々独立した移動タイミングで移動して前記工程処理機構の工程処理位置に半導体素子を供給するものであることを特徴とする。 According to a third aspect of the present invention, in the first or second aspect of the invention, the plurality of holding mechanisms are moved at independent movement timings for each of the process processing mechanisms, and are moved to the process processing position of the process processing mechanism. It is characterized by supplying.

以上のような請求項3の発明では、複数の保持機構は、前記工程処理機構ごとに各々独立した移動タイミングで移動させることによって、複数の工程処理部をその処理時間に応じて組み合わせ、各工程処理群の処理時間あるいは単独の工程処理部の処理時間を略同一とする制御が可能となり、著しい作業効率、生産性の向上を図ることが可能となる。 In the invention of claim 3 as described above , the plurality of holding mechanisms are combined with each other according to the processing time by moving each of the process processing mechanisms at an independent movement timing, and each process It is possible to control the processing time of the processing group or the processing time of the single process processing unit to be substantially the same, and it is possible to significantly improve work efficiency and productivity.

本発明の半導体素子製造装置によれば、半導体素子を搬送する搬送機構の一回の停止あたりの工程処理を増加させることによって、搬送機構の小型化、軽量化が図れ、半導体素子の微小化にも対応可能で、作業効率、生産性が高い半導体素子製造装置および製造方法を提供することが可能となる。   According to the semiconductor element manufacturing apparatus of the present invention, by increasing the number of process steps per stop of the transport mechanism that transports the semiconductor element, the transport mechanism can be reduced in size and weight, and the semiconductor element can be miniaturized. Therefore, it is possible to provide a semiconductor device manufacturing apparatus and a manufacturing method with high work efficiency and high productivity.

(1)本実施形態
以下、本発明を実施するための最良の形態(以下、本実施形態という)について図面に従って具体的に説明する。そこで、まず本実施形態に係る半導体素子Sを含む半導体素子製造装置D(以下、装置Dという)の全体構成について、図1及び図2を用いて示す。
(1) Present Embodiment Hereinafter, the best mode for carrying out the present invention (hereinafter referred to as the present embodiment) will be specifically described with reference to the drawings. First, the overall configuration of a semiconductor element manufacturing apparatus D (hereinafter referred to as apparatus D) including the semiconductor element S according to the present embodiment will be described with reference to FIGS.

[1.本実施形態の構成]
[1−1.全体構成]
図1は、この装置Dの全体構成を概略的に示した正面図及び側面図である。なお、図1においては、説明の便宜上、各部材の縮尺等は簡略化して表示しているものであって、実際の縮尺とは異なる。また、図1(b)では、便宜上一部の部材の記載を省略している。
[1. Configuration of this embodiment]
[1-1. overall structure]
FIG. 1 is a front view and a side view schematically showing the overall configuration of the apparatus D. In FIG. 1, for convenience of explanation, the scale of each member is shown in a simplified manner and is different from the actual scale. Further, in FIG. 1B, illustration of some members is omitted for convenience.

これらの図に示すように、本実施の形態における装置Dは、ターンテーブル式の搬送機構1と、この搬送機構1の円周等配位置に一定の間隔で配置された複数の保持機構部2とを備えている。また、搬送機構1の下部の保持機構部2と合致する位置には、半導体素子Sに位置補正、外観検査、電気特性検査、捺印、不良品排出、テーピング、残留素子検査等の各処理を行う工程処理部を備えた工程処理機構3を備えている。装置Dはさらに、搬送機構1の近傍に、半導体素子を自動的に整列させ搬送機構1側に送り出すパーツフィーダ4を備え、このパーツフィーダ4と搬送機構1との間には、パーツフィーダ4から送り出された半導体素子を搬送機構1の各保持機構部2に対して個別に供給する搬送路5を備えている。   As shown in these drawings, the device D in the present embodiment includes a turntable transport mechanism 1 and a plurality of holding mechanism sections 2 arranged at regular intervals at circumferentially equidistant positions of the transport mechanism 1. And. In addition, the semiconductor element S is subjected to processing such as position correction, appearance inspection, electrical characteristic inspection, stamping, defective product discharge, taping, and residual element inspection at a position that matches the holding mechanism portion 2 below the transport mechanism 1. A process processing mechanism 3 including a process processing unit is provided. The apparatus D further includes a parts feeder 4 in the vicinity of the transport mechanism 1 that automatically aligns the semiconductor elements and feeds them to the transport mechanism 1 side. Between the parts feeder 4 and the transport mechanism 1, the parts feeder 4 A transport path 5 is provided for individually feeding the sent semiconductor element to each holding mechanism section 2 of the transport mechanism 1.

搬送機構1は、上述のように、ターンテーブル式で、図示しない駆動モータの駆動力を図示しないタイミングベルトで伝達することにより、図中矢印方向に向かって一定間隔(ここでは、60°間隔)で時計回転方向に間欠回転するものである。そして、搬送機構1は、下部に設けられた工程処理機構3と搬送路5の半導体素子Sの受渡し位置を停止位置として回転するものである。ここで、本実施形態では、前記半導体素子Sの受渡し位置を停止位置Tとし、工程処理機構3に対応した停止位置を、回転方向に沿ってT〜Tと呼ぶこととする。 As described above, the transport mechanism 1 is a turntable type, and transmits a driving force of a driving motor (not shown) by a timing belt (not shown), whereby a constant interval (here, 60 ° interval) in the direction of the arrow in the drawing. And intermittently rotate in the clockwise direction. And the conveyance mechanism 1 rotates by setting the delivery position of the semiconductor element S of the process processing mechanism 3 and the conveyance path 5 provided in the lower part as a stop position. In the present embodiment, the passing position of the semiconductor element S and the stop position T 1, a stop position corresponding to the step processing mechanism 3, is referred to as T 2 through T 6 along the direction of rotation.

保持機構部2は、上記のように搬送機構1の円周等配位置に搬送機構1の間欠回転間隔に沿って、吊り下った状態で複数設けられ(ここでは、60°間隔で6つ)、吸着ノズルで真空吸着することによって半導体素子を保持するように構成されている。また、保持機構部2と搬送機構1との間には、この保持機構部2を上下に移動させる移動機構6が設けられている。この移動機構6は、搬送機構1の間欠回転に伴って、保持機構部2が工程処理機構3の工程処理部上に停止した場合において、保持機構部2を各工程処理部へ向けて下降させ、各工程処理部の各処理を行う位置に半導体素子を挿入し、工程処理終了後には再び上昇させるように構成されている。ここで、本実施形態では、搬送機構1の停止位置において、保持機構部2に吸着保持された半導体素子Sの水平方向における位置を搬送位置Hといい、保持機構部2の下降により各工程処理部に挿入され、各工程処理が行われる位置を処理位置Pという。   A plurality of holding mechanism sections 2 are provided in a suspended state along the intermittent rotation interval of the conveyance mechanism 1 at the circumferentially equidistant positions of the conveyance mechanism 1 as described above (here, six at 60 ° intervals). The semiconductor element is held by vacuum suction with a suction nozzle. In addition, a moving mechanism 6 that moves the holding mechanism unit 2 up and down is provided between the holding mechanism unit 2 and the transport mechanism 1. The moving mechanism 6 lowers the holding mechanism unit 2 toward each process processing unit when the holding mechanism unit 2 stops on the process processing unit of the process processing mechanism 3 due to the intermittent rotation of the transport mechanism 1. The semiconductor element is inserted into the position where each process in each process processing unit is performed, and is raised again after the process is completed. Here, in the present embodiment, the position in the horizontal direction of the semiconductor element S attracted and held by the holding mechanism unit 2 at the stop position of the transfer mechanism 1 is referred to as a transfer position H. The position where each process is performed is called a processing position P.

工程処理機構3は、上述の通り、搬送機構1下部の保持機構部2と合致する位置に設けられ、半導体素子Sの位置補正、外観検査、電気特性検査、捺印、不良品排出、テーピング、残留素子検査等の各処理を行うものである。具体的には、停止位置Tには、位置補正および外観検査を行う位置補正装置3aと外観検査装置3bが設けられ、停止位置Tには、半導体素子Sの電気特性検査を行う電気特性検査装置3cが設けられ、停止位置Tには捺印装置及び不良品排出装置が設けられ、停止位置Tにはテーピング装置が設けられている。また、停止位置Tは、半導体素子Sの残留を確認する残留素子検出装置が設けられている。 As described above, the process processing mechanism 3 is provided at a position that coincides with the holding mechanism portion 2 below the transport mechanism 1, and corrects the position of the semiconductor element S, appearance inspection, electrical characteristic inspection, stamping, defective product discharge, taping, residual Each process such as element inspection is performed. Electrical properties In particular, the stop position T 2, provided the position correction apparatus 3a and the appearance inspection device 3b to perform the position correction and visual inspection, the stop position T 3, to perform electrical testing of the semiconductor device S inspection device 3c is provided, marking devices and the defective discharge unit is provided in the stop position T 4, taping device is provided in the stop position T 5. Further, the stop position T 6, the residual element detecting device is provided to check the residual of the semiconductor element S.

パーツフィーダ4は、半導体素子を自動的に整列させ、搬送機構1側に送り出すものであり、搬送機構1の間欠回転における停止位置Tの近傍に設けられている。また、このパーツフィーダ4と搬送機構1との間には、パーツフィーダ4から送り出された半導体素子を搬送機構1の各保持機構部2に対して個別に供給する搬送路5が設けられている。そして、この搬送路5によって、搬送機構1の停止位置Tまで搬送された半導体素子Sは、この位置において保持機構部2の吸着ノズルによってピックアップされ、保持されるようになっている。 Parts feeders 4, the semiconductor element is automatically aligned, which feeds the transport mechanism 1 side, is provided in the vicinity of the stop position T 1 in the intermittent rotation of the conveyance mechanism 1. Further, between the parts feeder 4 and the transport mechanism 1, there is provided a transport path 5 for individually supplying the semiconductor elements sent from the parts feeder 4 to each holding mechanism section 2 of the transport mechanism 1. . Then, by the conveying path 5, the semiconductor device S conveyed to the stop position T 1 transport mechanism 1 is adapted to be picked up and held by the suction nozzle of the holding device 2 in this position.

[1−2.工程処理機構および保持機構の構成]
次に、本発明の保持機構部2、工程処理機構3および移動機構6の具体的な構成について、図2を用いて説明する。
[1-2. Configuration of process processing mechanism and holding mechanism]
Next, specific configurations of the holding mechanism unit 2, the process processing mechanism 3, and the moving mechanism 6 of the present invention will be described with reference to FIG.

上述のような構成からなる半導体素子製造装置Dにおける工程処理機構3のうち、その一部は複数の工程処理部を併せ持つ工程処理群が形成されている。具体的には、工程処理機構3における搬送機構1の停止位置の一つであるTに、図2(a)に示すように、位置補正装置3aと外観検査装置3bとの2つの工程処理部を備えた工程処理群が形成されている。一方、図2(b)に示すように、他の工程処理機構として、ここでは、一つの工程処理部である停止位置Tの電気特性検査装置3cを取り上げる。 Of the process processing mechanisms 3 in the semiconductor element manufacturing apparatus D having the above-described configuration, a part of the process processing mechanism 3 includes a process processing group having a plurality of process processing units. Specifically, T 2, which is one of the stop positions conveying mechanism 1 in the step processing mechanism 3, as shown in FIG. 2 (a), 2 two-step treatment with the position correction apparatus 3a and the appearance inspection device 3b The process process group provided with the part is formed. On the other hand, as shown in FIG. 2 (b), as another step processing mechanism, here, take up electrical characteristic test device 3c stop position T 3 which is one step processing unit.

工程処理機構3の停止位置Tには、上述の通り、位置補正装置3aと、外観検査装置3bとが設けられている。すなわち、一つの停止位置に、位置合わせおよび外観検査という2つの工程処理が設けられているのである。この位置補正装置3aは、パーツフィーダ4から搬送路5を介して保持機構部2に受け渡された半導体素子Sの吸着状態における前後左右方向の位置ずれを補正する装置であって、図2(a)に示すように、半導体素子Sの左右両側に、半導体素子Sの幅と略同一の間隔を以て補正部材X、Yを設け、その上部にはテーパ加工が施されている。そして、この位置補正装置3aに、上部から半導体素子Sを挿入することよって、半導体素子Sの位置補正をするように構成されている。 Of the stop position T 2 step processing mechanism 3, as described above, the position correcting unit 3a, and the appearance inspection apparatus 3b is provided. That is, two process processes of alignment and appearance inspection are provided at one stop position. The position correction device 3a is a device that corrects the positional deviation in the front-rear and left-right directions in the suction state of the semiconductor element S delivered from the parts feeder 4 to the holding mechanism unit 2 via the transport path 5, and is shown in FIG. As shown in a), correction members X and Y are provided on both the left and right sides of the semiconductor element S at substantially the same interval as the width of the semiconductor element S, and the upper portion thereof is tapered. The position of the semiconductor element S is corrected by inserting the semiconductor element S from above into the position correction device 3a.

なお、この位置補正の方法は、上記のように半導体素子Sを挿入する方法に限られず、例えば、図3(a)に示すように、位置補正装置3aの補正部材を左右方向に動かして、半導体素子を左右方向から挟み込むことによって位置補正する構成とすることもできる。また、位置補正方向も、左右の二方向からのものに限らず、例えば図3(b)に示すような四方から挟み込む方法、あるいは、図3(c)のように四方を囲まれ、上部がテーパ加工された方状凹部に挿入する方法等であってもよい。   The position correction method is not limited to the method of inserting the semiconductor element S as described above. For example, as shown in FIG. 3A, the correction member of the position correction device 3a is moved in the left-right direction, It is also possible to adopt a configuration in which the position is corrected by sandwiching the semiconductor element from the left and right directions. Also, the position correction direction is not limited to the left and right directions, for example, a method of sandwiching from four directions as shown in FIG. 3B, or the four sides are surrounded as shown in FIG. It may be a method of inserting into a tapered concave recess.

また、外観検査装置3bは、パーツフィーダ4から供給された半導体素子Sの外観上の欠陥、例えば破損、チップの有無、汚れ、封止樹脂のボイド等に起因したスリット抜けなどの有無を検査するものであって、外観をカメラによって画像として取り込んで検査するものや、光を照射することによって行う光学式検査、X線を照射して行うX線検査があるが、本実施の形態においては、いずれのものにおいて構成してもよい。   Further, the appearance inspection apparatus 3b inspects the appearance defects of the semiconductor element S supplied from the parts feeder 4, such as breakage, chip presence / absence, dirt, slit missing due to sealing resin voids, and the like. In this embodiment, there are an inspection of an external appearance taken as an image by a camera, an optical inspection performed by irradiating light, and an X-ray inspection performed by irradiating X-rays. You may comprise in any thing.

このような位置補正装置3aと外観検査装置3bとは、本実施形態における装置Dにおいては、図3(a)に示すように、上部と下部に重畳的に設置されて一つの工程処理群を形成しているのである。具体的には、位置補正装置3aが上部に設けられ、外観検査装置3bがその下部に設けられている。そして、保持機構部2を介して半導体素子を保持した搬送機構1が停止位置Tから間欠回転して、停止位置Tで止まった際には、移動機構6が保持機構部2を下降させ、まず、第1の停止位置である位置補正装置3aの位置で停止すると、位置補正が行われ、さらに下降し、第2の停止位置である外観検査装置3b上で停止して、外観検査が行われるように構成されている。 As shown in FIG. 3A, the position correction device 3a and the appearance inspection device 3b are installed in an upper portion and a lower portion in the device D in the present embodiment, so that one process processing group is formed. It is forming. Specifically, the position correction device 3a is provided in the upper part, and the appearance inspection device 3b is provided in the lower part. Then, the transport mechanism 1 holding the semiconductor element via a holding mechanism 2 is intermittently rotated from the stop position T 1, when stopped at the stop position T 2 are, the moving mechanism 6 lowers the holding mechanism 2 First, when stopping at the position of the position correction device 3a that is the first stop position, position correction is performed, and the position is further lowered and stopped on the appearance inspection device 3b that is the second stop position. Configured to be done.

一方、停止位置Tの電気特性検査装置3cでは、保持機構部2を介して半導体素子を保持した搬送機構1が停止位置Tから間欠回転して、第2の停止位置Tで止まった際には、移動機構6が保持機構部2を下降させ、電気特性検査装置3c上で停止すると、半導体素子Sの電気特性が検査されるように構成されている。 On the other hand, the electrical characteristic test device 3c stop position T 3, the transport mechanism 1 holding the semiconductor element via a holding mechanism 2 is intermittently rotated from the stop position T 2, stopped at the second stop position T 3 In this case, the electric characteristics of the semiconductor element S are inspected when the moving mechanism 6 lowers the holding mechanism portion 2 and stops on the electric characteristic inspection apparatus 3c.

ここで、停止位置Tにおける位置補正工程(第1の停止位置)および外観検査工程(第2の停止位置)と、停止位置Tにおける電気特性検査工程との処理に要する時間は、図4に示すように、位置補正工程および外観検査工程の処理時間の和が、電気特性検査工程の処理時間と略同一となるように構成されている。すなわち、搬送位置Hから位置補正装置への挿入、位置補正され、外観検査工程への下降、停止、検査、上昇して再び搬送位置Hへ戻るまでに要する時間と、搬送位置Hから電気特性検査装置へ挿入され、電気特性検査を終え、上昇して再び搬送位置Hへ戻るまでに要する時間が、いずれかが何らかの位置において停滞することなく、ほぼ同一となるように構成されている。 Here, the position correction process in the stop position T 2 (the first stop position) and appearance inspection step (the second stop position), the time required for processing the electrical characteristic inspection process in the stop position T 3, 4 As shown in FIG. 5, the sum of the processing times of the position correction process and the appearance inspection process is configured to be substantially the same as the processing time of the electrical characteristic inspection process. In other words, the time required for insertion from the transfer position H to the position correction device, position correction, descent to the appearance inspection process, stop, inspection, rise and return to the transfer position H, and electrical property inspection from the transfer position H The time required for insertion into the apparatus, completion of the electrical characteristic inspection, rising and returning to the transport position H again is substantially the same without any stagnation at any position.

[2.本実施形態の作用]
前記のような構成を有する本実施の形態の半導体素子製造装置Dは、具体的に以下のように作用する。
[2. Operation of this embodiment]
The semiconductor element manufacturing apparatus D of the present embodiment having the above-described configuration specifically operates as follows.

[2−1.半導体素子製造装置D全体の作用]
まず、半導体素子製造装置D全体の作用の概略について説明する。図1において、パーツフィーダ4から整列されて送り出された半導体素子Sは、搬送路5を介して間欠回転する搬送機構1に設けられた各保持機構部2に対して個別に供給される(停止位置TT)。保持機構部2に吸着保持された半導体素子Sは、搬送機構1によって停止位置T〜Tに設けられた複数の工程処理部からなる工程処理機構3上に搬送され、位置補正装置、外観検査装置、電気的特性検査装置、捺印装置および不良品排出機構等の各工程処理部において、各処理が行われる。また、これら各工程処理を終了した半導体素子Sは、停止位置Tに設けられたテーピング装置7によってテーピング梱包が行われ、一連の工程が終了することとなる。
[2-1. Operation of entire semiconductor element manufacturing apparatus D]
First, an outline of the operation of the entire semiconductor element manufacturing apparatus D will be described. In FIG. 1, the semiconductor elements S aligned and sent out from the parts feeder 4 are individually supplied to each holding mechanism portion 2 provided in the transport mechanism 1 that rotates intermittently via the transport path 5 (stop). Position TT 1 ). The semiconductor element S sucked and held by the holding mechanism unit 2 is transported by the transport mechanism 1 onto the process processing mechanism 3 including a plurality of process processing units provided at the stop positions T 2 to T 6. Each process is performed in each process processing unit such as an inspection device, an electrical characteristic inspection device, a stamping device, and a defective product discharge mechanism. Further, the semiconductor device S ended these steps process, taping is performed by taping device 7 provided at the stop position T 5, so that the series of processes are completed.

[2−2.工程処理機構および保持機構の作用]
次に、本発明の工程処理機構および保持機構の作用について、図1および図3を用いて具体的に説明する。上記のようにして、搬送機構1の保持機構部2によってパーツフィーダ4から排出され搬送路5からピックアップ、保持された半導体素子Sは、間欠的に回転しながら停止位置Tへと搬送されてくる。停止位置Tに停止すると、図2(a)に示すように、位置合わせを行う保持機構部2に設けられた移動機構6が保持機構部2を下降させ、半導体素子を第1の停止位置である位置補正装置3aの位置補正位置に挿入する。
[2-2. Action of process processing mechanism and holding mechanism]
Next, the operation of the process processing mechanism and the holding mechanism of the present invention will be specifically described with reference to FIGS. As described above, picked up from the conveying path 5 is discharged from the parts feeder 4 by the holding mechanism portion 2 of the transfer mechanism 1, the semiconductor device S held is conveyed to the stop position T 2 while intermittently rotated come. If you stop the stop position T 2, as shown in FIG. 2 (a), lowering the moving mechanism 6 is holding mechanism 2 provided on the holding mechanism 2 to perform alignment, the semiconductor element and the first stop position Is inserted into the position correction position of the position correction device 3a.

この位置補正装置3aにおいて、半導体素子Sは、上部がテーパ加工された補正板X及びYの上部から挿入され、補正板X、Yの下部まで挿入されることによって位置補正される。その後、さらに下降し、位置補正装置3aの下部に設けられた外観検査装置3b上の処理位置Pすなわち第2の停止位置において停止する。そして、この外観検査装置3bにおいて、半導体素子Sの外観上の欠陥等の有無が検査される。外観検査終了後は、移動機構6が保持機構部2を、位置補正装置3aの上部まで引き上げ、半導体素子Sは搬送位置Hまで戻される。   In this position correction device 3a, the position of the semiconductor element S is corrected by being inserted from above the correction plates X and Y whose upper portions are tapered and inserted to the lower portions of the correction plates X and Y. Then, it further descends and stops at the processing position P on the appearance inspection apparatus 3b provided at the lower part of the position correction apparatus 3a, that is, at the second stop position. Then, in this appearance inspection apparatus 3b, the presence or absence of defects on the appearance of the semiconductor element S is inspected. After the appearance inspection is completed, the moving mechanism 6 raises the holding mechanism unit 2 to the upper part of the position correction device 3a, and the semiconductor element S is returned to the transport position H.

一方、停止位置Tの電気特性検査装置3cでは、搬送機構1の間欠回転によって停止位置Tから搬送され停止した半導体素子Sは、移動機構6によって保持機構部2が下降し、電気特性検査装置口3dに挿入される。そして、半導体素子Sの電気特性が検査される。検査終了後は、上記同様、移動機構6が保持機構部2を、電気特性検査装置3cの上部まで引き上げ、半導体素子Sは搬送位置Hまで戻される。 On the other hand, the electrical characteristic test device 3c stop position T 3, the semiconductor device S has been stopped is conveyed from the stop position T 2 by intermittent rotation of the conveying mechanism 1, the holding mechanism 2 is lowered by the moving mechanism 6, the electrical characteristics test It is inserted into the device port 3d. Then, the electrical characteristics of the semiconductor element S are inspected. After completion of the inspection, the moving mechanism 6 pulls the holding mechanism portion 2 up to the upper part of the electrical characteristic inspection apparatus 3c and the semiconductor element S is returned to the transport position H as described above.

ここで、図4に示したように、停止位置Tにおける位置補正および外観検査と、停止位置Tにおける電気特性検査に要する処理時間は、略同一に構成され、また、その他の工程処理部における処理時間もほぼ同一に構成されている。したがって、工程処理部への半導体素子Sの挿入から引き上げ、そして次工程への搬送までの作業は、いずれの工程処理部においてもロスなく行われるようになっている。 Here, as shown in FIG. 4, the position correction and visual inspection at the stop position T 2, the processing time required for electrical testing at the stop position T 3, it is configured to be substantially the same, also, other steps processor The processing time is substantially the same. Therefore, the operations from insertion of the semiconductor element S to the process processing unit to pulling up and transfer to the next process are performed without any loss in any process processing unit.

[3.本実施形態の効果]
上記のように作用する本実施形態の半導体素子製造装置Dは、具体的に以下のような効果を奏する。すなわち、工程処理機構3の工程処理部のうち、位置補正装置3aと外観検査装置3bとを、一つの停止位置Tに工程処理群として構成して、当該停止位置において位置補正及び外観検査という2つの工程処理を行うことによって、半導体素子Sの搬送機構1の間欠回転動作の一回の停止で、半導体素子Sに複数の処理工程を施すことができる。したがって、搬送機構1の停止個所を減少させることが可能となる。また、処理時間の長い電気特性検査を行う電気特性検査装置3cを単独で設け、処理時間の短い処理工程である位置補正を行う位置補正装置3aと外観検査を行う外観検査装置3bとを組み合わせて設けることによって、全体として処理時間の短縮を図ることができるので、作業効率、生産性の向上を図ることが可能となる。
[3. Effects of this embodiment]
The semiconductor element manufacturing apparatus D of the present embodiment that operates as described above specifically has the following effects. That is, of the process unit step processing mechanism 3, and a position correcting unit 3a and the visual inspection apparatus 3b, constituting the one stop position T 2 as step treatment group, that the position correction and visual inspection in the stop position By performing the two process steps, the semiconductor element S can be subjected to a plurality of process steps by one stop of the intermittent rotation operation of the transport mechanism 1 of the semiconductor element S. Accordingly, it is possible to reduce the number of stops of the transport mechanism 1. Also, an electrical property inspection device 3c that performs electrical property inspection with a long processing time is provided alone, and a position correction device 3a that performs position correction, which is a processing step with a short processing time, is combined with an appearance inspection device 3b that performs visual inspection. By providing, it is possible to shorten the processing time as a whole, so that it is possible to improve work efficiency and productivity.

また、処理時間の短い処理工程である位置補正装置3aと外観検査装置3bとを組み合わせることによって、処理時間の長い電気特性検査装置3cの処理時間と上記組み合わせによる処理時間とを、ほぼ同一とすることができる。したがって、例えば、従来のように、単独の工程処理部のみで構成した装置の場合、長い工程処理が終わらなければ、搬送機構を回転させて次の工程へ進ませるようなことができず、処理時間の短い工程がその処理を終えているにもかかわらず、処理時間の長い工程の処理が終わるまで停留しなければならなかったが、本実施形態ではそのような必要がなく、処理時間の長い電気特性検査が終わるまでに、処理時間の短い位置補正と外観検査を行うことができるので、作業効率、生産性の著しい向上を図ることが可能となる。   Further, by combining the position correction device 3a and the appearance inspection device 3b, which are processing steps having a short processing time, the processing time of the electrical property inspection device 3c having a long processing time and the processing time by the above combination are made substantially the same. be able to. Therefore, for example, in the case of an apparatus composed of only a single process processing unit as in the prior art, unless a long process process is completed, the transport mechanism cannot be rotated to advance to the next process, Although the process having a short time has finished the process, the process has to be stopped until the process of the process having a long process time is completed. However, in this embodiment, such a process is not necessary and the process time is long. Since the position correction and the appearance inspection with a short processing time can be performed before the electrical characteristic inspection is completed, it is possible to significantly improve work efficiency and productivity.

また、上記のように、工程処理機構3の位置補正装置3aと外観検査装置3bとを組み合わせて設けることで、搬送機構1の停止位置が減少することに伴い、搬送機構1に設ける保持機構部2の数を減少させることが可能となるので、搬送機構1の小型化、軽量化および機構の簡略化が可能となる。これにより、搬送機構1の停止位置の精度を向上させることが可能となり、微小な半導体素子Sへの対応が容易となる。さらに、搬送機構1の駆動源の簡略化、停止機構の軽量化が可能で、装置D全体のエネルギー消費量の低減および重量減による搬送機構のトラブル減少を図ることができ、ひいては、装置全体の振動減少やトラブル減少、装置設置床への要求強度減少を図ることが可能となる。   In addition, as described above, the holding mechanism unit provided in the transport mechanism 1 is provided by reducing the stop position of the transport mechanism 1 by providing the position correction device 3a and the appearance inspection device 3b of the process processing mechanism 3 in combination. Since the number of 2 can be reduced, the transport mechanism 1 can be reduced in size and weight, and the mechanism can be simplified. This makes it possible to improve the accuracy of the stop position of the transport mechanism 1 and facilitate the handling of the minute semiconductor element S. Further, the drive source of the transport mechanism 1 can be simplified and the stop mechanism can be reduced in weight, so that the energy consumption of the entire apparatus D can be reduced and troubles in the transport mechanism can be reduced due to the weight reduction. It is possible to reduce vibrations and troubles, and to reduce the required strength of the equipment installation floor.

(2)他の実施形態
なお、本発明は上記実施の形態に限定されるものではなく、次のような実施の形態も包含するものである。
(2) Other Embodiments The present invention is not limited to the above-described embodiments, and includes the following embodiments.

本実施形態においては、工程処理機構3の電気特性検査装置3cにおける工程処理時間を基準として、位置補正装置3aと外観検査装置3bとを組み合わせて工程処理群を形成したが、本発明は、このような組み合わせに限られず、処理時間の異なる複数の工程処理をその目的あるいは処理時間によって、さまざまに組み合わせて工程処理群を形成することも可能である。これにより、さまざまな目的からなる半導体素子製造装置の有する工程処理部の目的や処理時間に応じて、その組み合わせを自在に行うことが可能で、さらに装置全体の処理時間の短縮化を図ることもできる。   In the present embodiment, the process processing group is formed by combining the position correction apparatus 3a and the appearance inspection apparatus 3b on the basis of the process processing time in the electrical property inspection apparatus 3c of the process processing mechanism 3. It is not limited to such a combination, and a plurality of process processes having different process times can be combined in various ways depending on the purpose or process time to form a process process group. This makes it possible to freely combine them according to the purpose and processing time of the process processing unit possessed by the semiconductor device manufacturing apparatus having various purposes, and also to shorten the processing time of the entire apparatus. it can.

例えば、図1に示す工程処理には含まれていないが、電気特性検査の処理時間を基準として、半導体パッケージ上に捺印された文字を外観検査する工程を行った場合にも上記同様、装置全体の処理時間の短縮を図る可能である。すなわち、半導体製造工程によっては、先に半導体素子に捺印を行ってから、各種検査やテーピング処理を行う本装置に半導体素子が供給される場合がある。このような場合、半導体素子の捺印は上面部に行われるが、上述の通り、吸着ノズルは、半導体素子の上面部を吸着し搬送するため、捺印文字が吸着ノズルで隠れて、そのままでは捺印された文字の外観検査を行うことができなかった。これを回避する方法としては、従来図6(a)あるいは(b)に示す通り、保持機構部2の吸着ノズルで保持した半導体装置Sをターンテーブル等の別の搬送機構Eに、解放位置Tで受渡し、その搬送機構Eが外観検査位置Tまで搬送して処理していた。つまり、この装置では、搬送装置Eを別個に設けるほか、搬送装置1においても半導体素子Sの解放位置T、受取位置Tの2つの停止位置が必要であった。 For example, although not included in the process shown in FIG. 1, the entire apparatus is the same as described above even when a step of visually inspecting characters stamped on a semiconductor package is performed on the basis of a processing time for electrical characteristic inspection. It is possible to shorten the processing time. That is, depending on the semiconductor manufacturing process, the semiconductor element may be supplied to this apparatus that performs various inspections and taping processes after the semiconductor element is first stamped. In such a case, the marking of the semiconductor element is performed on the upper surface portion. However, as described above, the suction nozzle sucks and conveys the upper surface portion of the semiconductor element, so that the stamp character is hidden by the suction nozzle and is printed as it is. The appearance inspection of the characters could not be performed. As a method of avoiding this, as shown in FIG. 6A or FIG. 6B, the semiconductor device S held by the suction nozzle of the holding mechanism unit 2 is transferred to another transfer mechanism E such as a turntable at the release position T. 4 , the transport mechanism E transported to the appearance inspection position T 6 for processing. That is, in this apparatus, in addition to providing the transport apparatus E separately, the transport apparatus 1 also requires two stop positions of the semiconductor element S release position T 4 and reception position T 7 .

しかしながら、本発明では、電気特性検査の処理時間を基準として、この処理時間に合わせて半導体素子Sに捺印された文字の外観検査を行うことによって、図5(a)に示すように一つの停止位置において処理を行うことが可能となる。つまり、外観カメラCを設置した文字検査停止位置にて、一旦、半導体素子Sを保持機構部2の吸着ノズルから解放し半導体素子S上面部を外観カメラCにて撮像できる状態にし検査を行い、検査終了後、再度保持機構部2の吸着ノズルが下降し、半導体素子Sを再吸着を行うことが可能となるのである。これにより、受取位置の削減と別の搬送機構の削減を図ることができ、全体としての生産効率の向上を図ることができるようになる。   However, according to the present invention, one stop as shown in FIG. 5A is performed by performing an appearance inspection of the characters stamped on the semiconductor element S in accordance with the processing time based on the processing time of the electrical characteristic inspection. Processing can be performed at the position. In other words, at the character inspection stop position where the appearance camera C is installed, the semiconductor element S is once released from the suction nozzle of the holding mechanism unit 2 and the upper surface portion of the semiconductor element S can be imaged by the appearance camera C for inspection. After the inspection is completed, the suction nozzle of the holding mechanism unit 2 is lowered again, and the semiconductor element S can be re-sucked. As a result, it is possible to reduce the receiving position and the separate transport mechanism, and to improve the overall production efficiency.

また、上記外観検査と同様、電気特性検査の処理時間を基準とすることにより、従来2つの停止位置を移動させながら行っていた捺印工程も、図1に示す処理位置Tの一箇所において処理することが可能となる。すなわち、従来の半導体素子製造装置おける捺印工程は、図6(a)あるいは(c)に示すように、搬送装置Eを別個に設け、その搬送機構Eが捺印処理位置Tまで搬送して処理を行う必要があり、半導体素子Sの解放位置Tと受取位置Tの2つの停止位置を設ける必要があった。 Also, similar to the above visual inspection, by the reference processing time of electric characteristic inspection, marking process has been performed while moving the conventional two stop positions also processed in one place of the processing position T 4 shown in FIG. 1 It becomes possible to do. That is, marking steps definitive conventional semiconductor device manufacturing apparatus, as shown in FIG. 6 (a) or (c), separately provided conveyance device E, and conveyed the conveying mechanism E until stamping processing position T 5 treatment There is a need to provide two stop positions, a release position T 4 of the semiconductor element S and a receiving position T 7 .

しかしながら本発明では、図5(b)に示すように、電気特性検査の処理時間を基準として、この処理時間に合わせて捺印処理を行うことによって、一つの停止位置において捺印処理を行うことができるようになる。すなわち、捺印装置Nを設置した捺印位置Tにおいて、半導体素子SをベッドB上で保持機構部2の吸着ノズルから解放し、このベッドBを捺印装置Nによって半導体素子S上面部に捺印できる位置まで動かして捺印処理を行う。そして、捺印終了後、再度保持機構部2の吸着ノズルが下降し、半導体素子Sを再吸着を行う。これにより、従来2つの停止位置を設けて行う必要があった捺印処理を、半導体素子Sの解放位置と受取位置を一つの停止位置Tにおいて行うことができるので、停止位置の削減と別の搬送機構の削減を図ることができ、全体としての生産効率の向上を図ることが可能となる。 However, in the present invention, as shown in FIG. 5 (b), the stamping process can be performed at one stop position by performing the stamping process in accordance with the processing time of the electrical characteristic inspection as a reference. It becomes like this. That is, at the marking position T 4 where the marking device N is installed, the semiconductor element S is released from the suction nozzle of the holding mechanism unit 2 on the bed B, and the bed B can be marked on the upper surface of the semiconductor element S by the marking device N. Move to the end and perform the marking process. Then, after the marking is completed, the suction nozzle of the holding mechanism unit 2 is lowered again to re-suck the semiconductor element S. As a result, the marking process, which has conventionally been required to be performed with two stop positions, can be performed at one stop position T 4 for the release position and the receiving position of the semiconductor element S. The number of transport mechanisms can be reduced, and the overall production efficiency can be improved.

このように、従来ターンテーブルで形成された搬送装置を複数設け、ターンテーブル間での受渡しを行う必要のあった処理を、この受渡し作業を伴うことなく一つの停止位置において行うことができる点は、従来技術に比して装置構成の簡略化において顕著な効果がある。なお、本発明においては、上述した方法で外観検査処理あるいは捺印処理を行うことによって、これらの処理時間を基準として、例えば上記実施形態で示した他の処理工程、例えば、位置補正装置3aと外観検査装置3bとを組み合わせた工程処理群において処理工程を行うことも可能である。これにより、上記実施形態において電気特性検査の処理時間を基準とした場合と同様の効果を奏することができることは言うまでもない。   In this way, a plurality of transfer devices conventionally formed by turntables are provided, and the processing that had to be delivered between turntables can be performed at one stop position without this delivery work. As compared with the prior art, there is a remarkable effect in simplifying the device configuration. In the present invention, by performing the appearance inspection process or the stamping process by the above-described method, for example, the other processing steps shown in the above embodiment, for example, the position correction device 3a and the appearance are performed on the basis of these processing times. It is also possible to perform a processing process in a process processing group combined with the inspection apparatus 3b. As a result, it goes without saying that the same effect as in the case where the processing time of the electrical characteristic inspection is used as a reference in the above embodiment can be obtained.

本実施形態において、搬送機構はターンテーブルを用いて構成したが、本発明は、かかる構成に限定されるものではなく、例えば、直線搬送、その他既知のいかなる搬送機構を用いても、ターンテーブルの場合と同様の作用効果を奏することができるものである。   In the present embodiment, the transport mechanism is configured using a turntable. However, the present invention is not limited to such a configuration, and for example, a linear transport or any other known transport mechanism may be used. The same effects as the case can be achieved.

また、本実施形態における半導体素子の保持方法としては、保持機構部に吸着ノズルを設け、真空吸着することによって保持する構成を採用しているが、本発明は、このような構成に限定されることはなく、例えば、機械的に挟持するチャッキングによるもの等、その他既知のいかなる保持方法を用いることもできる。   In addition, as a method for holding the semiconductor element in the present embodiment, a configuration is adopted in which a suction nozzle is provided in the holding mechanism and held by vacuum suction. However, the present invention is limited to such a configuration. However, any other known holding method can be used, for example, by chucking mechanically.

本実施形態においては、工程処理部に、位置補正、外観検査、電気特性検査、捺印、不良品排除、テーピングおよび残留検査等の処理を設けたが、これらは例示にすぎず、本発明では半導体素子製造工程で用いられるいかなる工程処理を用いても同様の作用効果を実現可能である。また、本実施形態では、位置補正及び外観検査を一つの工程処理群とし、他の工程処理として電気特性検査を取り上げ、その処理時間を同一にすることを示したが、本発明はかかる組み合わせに限定されず、他のいかなる工程処理を組み合わせて、処理時間の調整を行うことが可能である。例えば、捺印工程と不良品排除工程を組み合わせることによって、不良品として排除されなかった素子のみに捺印を押す処理を一つの停止位置で行うようにすることも可能である。   In this embodiment, processing such as position correction, appearance inspection, electrical property inspection, stamping, defective product elimination, taping, and residual inspection is provided in the process processing section, but these are merely examples, and in the present invention, a semiconductor is used. Similar effects can be realized by using any process used in the element manufacturing process. Further, in the present embodiment, the position correction and the appearance inspection are set as one process processing group, and the electrical characteristic inspection is taken up as the other process processing, and the processing time is made the same. Without limitation, it is possible to adjust the processing time by combining any other process. For example, by combining the stamping process and the defective product exclusion process, it is possible to perform the process of pressing the stamp only on the elements that are not excluded as defective products at one stop position.

本実施形態において、保持機構部は、半導体素子を保持した状態で、移動機構によって、上下動するように構成したが、本発明はこのような構成に限定されるものではなく、保持機構部を工程処理機構の配置に応じていかなる方向へも移動可能とすることもできる。例えば、本発明の工程処理群における工程処理部を搬送機構の中心から外側に向かって並列させ、保持機構を直径方向に移動させるように構成することも可能である。また、保持機構部の駆動源については、リニアモータ、回転モータ、ソレノイドコイル、シリンダ等既知のいかなる駆動手段で駆動して良い。さらに、ギア、レバー、カム、ベルト、ボールネジ等いかなる既知の駆動力伝達機構を組み合わせも良い。   In the present embodiment, the holding mechanism portion is configured to move up and down by the moving mechanism while holding the semiconductor element, but the present invention is not limited to such a configuration, and the holding mechanism portion is It can also be movable in any direction depending on the arrangement of the process processing mechanism. For example, the process processing units in the process processing group of the present invention can be arranged in parallel from the center of the transport mechanism toward the outside, and the holding mechanism can be moved in the diameter direction. Further, the drive source of the holding mechanism section may be driven by any known drive means such as a linear motor, a rotary motor, a solenoid coil, a cylinder or the like. Further, any known driving force transmission mechanism such as a gear, a lever, a cam, a belt, and a ball screw may be combined.

本発明の実施形態に係る半導体素子製造装置の全体構成を示す模式図(a)及び(b)。Schematic (a) and (b) which shows the whole structure of the semiconductor element manufacturing apparatus which concerns on embodiment of this invention. 本発明の実施形態に係る保持機構部及び工程処理機構の作用を示す模式図。The schematic diagram which shows the effect | action of the holding mechanism part and process processing mechanism which concern on embodiment of this invention. 本発明の実施形態に係る保持機構部及び工程処理機構の他の構成を示す正面図(a)、斜視図(b)及び(c)The front view (a), perspective view (b), and (c) which show other composition of the maintenance mechanism part and process processing mechanism concerning the embodiment of the present invention. 本発明の実施形態に係る半導体素子製造装置における工程処理及びその時間を示す図。The figure which shows the process process and its time in the semiconductor element manufacturing apparatus which concerns on embodiment of this invention. 本発明の他の実施形態に係る保持機構部及び工程処理機構の作用を示す模式図。The schematic diagram which shows the effect | action of the holding mechanism part and process processing mechanism which concern on other embodiment of this invention. 従来の半導体素子製造装置における工程処理の一例を示す模式図。The schematic diagram which shows an example of the process process in the conventional semiconductor element manufacturing apparatus. 従来の半導体素子製造装置における工程処理及びその時間を示す図。The figure which shows the process processing and its time in the conventional semiconductor element manufacturing apparatus.

符号の説明Explanation of symbols

1…搬送機構
2…保持機構部
3…工程処理機構
3a…位置補正装置
3b…外観検査装置
3c…電気特性検査装置
3d…電気特性検査装置口
4…パーツフィーダ
5…搬送路
6…移動機構
7…テーピング装置
B…ベッド
C…外観カメラ
D…半導体素子製造装置
E…搬送装置
N…捺印装置
S…半導体素子
X、Y…補正部材
DESCRIPTION OF SYMBOLS 1 ... Conveyance mechanism 2 ... Holding mechanism part 3 ... Process processing mechanism 3a ... Position correction apparatus 3b ... Appearance inspection apparatus 3c ... Electrical characteristic inspection apparatus 3d ... Electrical characteristic inspection apparatus port 4 ... Parts feeder 5 ... Conveyance path 6 ... Movement mechanism 7 ... Taping device B ... Bed C ... Appearance camera D ... Semiconductor element manufacturing device E ... Conveying device N ... Stamping device S ... Semiconductor element X, Y ... Correction member

Claims (4)

間欠的に回転するターンテーブル式の搬送機構と、この搬送機構の円周等配位置に複数設けられ半導体素子を保持する保持機構と、この保持機構が間欠的に停止する停止位置と合致する位置に設けられ半導体素子に所定の工程処理を施す複数種の工程処理機構とを備え、前記搬送機構の間欠回転によって搬送される半導体素子に対して、前記保持機構が前記搬送機構の回転軸方向に移動して前記工程処理機構の工程処理部に半導体素子を供給することで半導体素子に所定の工程処理を施す半導体素子製造装置において、A turntable transport mechanism that rotates intermittently, a holding mechanism that holds a plurality of semiconductor elements provided at circumferentially equidistant positions of the transport mechanism, and a position that matches a stop position at which the holding mechanism stops intermittently A plurality of types of process processing mechanisms that perform predetermined process processing on the semiconductor elements, and the holding mechanism is arranged in the direction of the rotation axis of the transport mechanism with respect to the semiconductor elements transported by the intermittent rotation of the transport mechanism. In a semiconductor device manufacturing apparatus that performs a predetermined process process on a semiconductor element by moving and supplying the semiconductor element to a process processing unit of the process processing mechanism,
前記複数種の工程処理機構のうち少なくとも一つには、種類の異なる工程処理部が前記保持機構の移動方向に対して並んで設けられた工程処理群を備え、At least one of the plurality of types of process processing mechanisms includes a process processing group in which different types of process processing units are provided side by side with respect to the movement direction of the holding mechanism,
前記保持機構は、前記搬送機構の回転軸方向に移動して前記工程処理群を形成する複数の工程処理部に半導体素子を供給するものであることを特徴とする半導体素子製造装置。The holding mechanism supplies a semiconductor element to a plurality of process processing units that move in the direction of the rotation axis of the transport mechanism to form the process processing group.
前記複数種の工程処理機構は、各々処理時間の異なる工程処理を備え、The plurality of types of process processing mechanisms each include process processes with different processing times,
単独の工程処理部を備えた工程処理機構と、前記工程処理群を備えた工程処理機構との処理時間が略同一となるように構成されていることを特徴とする請求項1記載の半導体素子製造装置。2. The semiconductor device according to claim 1, wherein a processing time of a process processing mechanism including a single process processing unit and a process processing mechanism including the process processing group are substantially the same. Manufacturing equipment.
前記複数の保持機構は、前記工程処理機構ごとに各々独立した移動タイミングで移動して前記工程処理機構の工程処理位置に半導体素子を供給するものであることを特徴とする請求項1又は2記載の半導体素子製造装置。3. The plurality of holding mechanisms move at an independent movement timing for each of the process processing mechanisms and supply semiconductor elements to a process processing position of the process processing mechanism. Semiconductor device manufacturing equipment. 間欠的に回転するターンテーブル式の搬送機構と、この搬送機構の円周等配位置に複数設けられ半導体素子を保持する保持機構と、この保持機構が間欠的に停止する停止位置と合致する位置に設けられ半導体素子に所定の工程処理を施す複数種の工程処理機構と、を制御装置により制御して、前記搬送機構の間欠回転によって搬送される半導体素子に対して、前記保持機構により前記搬送機構の回転軸方向に移動させて前記工程処理機構の工程処理部に半導体素子を供給することで半導体素子に所定の工程処理を施す半導体素子製造方法において、A turntable transport mechanism that rotates intermittently, a holding mechanism that holds a plurality of semiconductor elements provided at circumferentially equidistant positions of the transport mechanism, and a position that matches a stop position at which the holding mechanism stops intermittently And a plurality of types of process processing mechanisms that perform predetermined process processing on the semiconductor element, and are controlled by the control device, and the semiconductor element transported by intermittent rotation of the transport mechanism is transported by the holding mechanism In a semiconductor element manufacturing method for performing a predetermined process on a semiconductor element by moving the mechanism in a rotational axis direction and supplying the semiconductor element to a process processing unit of the process processing mechanism,
前記複数種の工程処理機構のうち少なくとも一つには、種類の異なる工程処理部が前記保持機構の移動方向に対して並んで設けられた工程処理群を備え、At least one of the plurality of types of process processing mechanisms includes a process processing group in which different types of process processing units are provided side by side with respect to the movement direction of the holding mechanism,
前記制御装置により、前記保持機構を、前記搬送機構の回転軸方向に移動させ前記工程処理群を形成する複数の工程処理部に半導体素子を供給させることを特徴とする半導体素子製造方法。A method of manufacturing a semiconductor device, comprising: supplying a semiconductor element to a plurality of process processing units forming the process processing group by moving the holding mechanism in a direction of a rotation axis of the transport mechanism by the control device.
JP2004011032A 2004-01-19 2004-01-19 Semiconductor device manufacturing apparatus and manufacturing method Expired - Fee Related JP3927180B2 (en)

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