JP3924859B2 - Semiconductor laser and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor laser having a current confinement structure using an oxide and a manufacturing method thereof.
[0002]
At present, surface emitting semiconductor lasers with an extremely low threshold current using an oxide film for current confinement have been realized, and the technology will be applied to edge emission type semiconductor lasers. In the present invention, a technique for improving the manufacturing yield of the oxide current confinement structure is disclosed.
[0003]
[Prior art]
FIG. 5 is a front view of a principal part cutaway showing an edge emission type semiconductor laser for explaining the prior art of an oxide current confinement structure.
[0004]
In the figure, 1 is a substrate, 2 is a one-conductivity-type side cladding layer, 3 is an active layer, 4 is an oxide current confinement layer, 4A is a current injection region, 5 is an opposite-conductivity-type side cladding layer, and 6 is a contact layer. , 7 is the opposite conductivity type side electrode, 8 is the one conductivity type side electrode, and L _OX is the oxidation depth.
[0005]
In this semiconductor laser, a material that is easily oxidized is used as the oxide current confinement layer 4, and the width of the current injection region 4A is controlled depending on the oxidation time.
[0006]
By the way, the technology disclosed in the present invention can improve performance even when applied to other than the edge emission type semiconductor laser, and the surface emitting semiconductor laser is also targeted in the embodiment of the present invention. Here, a conventional surface emitting semiconductor laser will be described.
[0007]
FIG. 6 is a cut-away side view of a main part showing a surface emitting semiconductor laser having an oxide current confinement structure.
[0008]
In the figure, 11 is a substrate, 12 is a DBR (distributed Bragg reflector) layer, 13 is a resonator layer, 14 is a DBR layer, 15 and 16 are electrodes, and 12A and 14A are oxide current confinement layers. Yes.
[0009]
In the oxide current confinement layer 4 or the oxide current confinement layers 12A and 14A in the conventional semiconductor laser shown in FIGS. 5 and 6, the width and diameter of the current injection region, and accordingly, the oxide region Since the width and diameter are controlled depending on the oxidation time, the oxidation depth L _ox changes due to fluctuations in the oxidation temperature or the distribution of the oxidation temperature. There is a problem that device characteristics vary.
[0010]
[Problems to be solved by the invention]
In the present invention, when an oxide current confinement layer is formed in an edge emission type or surface emitting type semiconductor laser, the depth of oxidation, and hence the width and diameter of the current injection region, can be accurately and reliably ensured. try to.
[0011]
[Means for Solving the Problems]
In the present invention, when an easily oxidizable layer is oxidized by providing a hardly oxidizable region, i.e., an oxidation inhibiting region, at the edge of the portion that becomes the current injection region, the progress of oxidation is stopped at the oxidation inhibiting region, and the accurate A current injection region having a width or a diameter can be formed with good reproducibility.
[0012]
From the above, in the semiconductor laser of the present invention and the manufacturing method thereof,
(1)
A compound semiconductor layer (for example, an n-side cladding layer 22, an SCH layer 23, a strained quantum well active layer 24, an SCH layer 25, an easily oxidizable layer 26, p) including a semiconductor oxidizable layer (for example, an easily oxidizable layer 26). include side cladding layer 27, group III were introduced so as to extend along both sides of in the stripe current injection region and the like) contact layer 28 (e.g., a stripe current injection region 26A) impurities (e.g. Ga or in) An oxidation inhibition region (for example, an oxidation inhibition region 29), and extending from an outer edge of the semiconductor oxidizable layer toward the stripe current injection region and terminated at the oxidation inhibition region to define the stripe current injection region Or an insulating region made of a compound semiconductor oxide (for example, an insulating region 26), or
[0013]
(2)
Compound semiconductor layer (for example, n-side DBR layer 42, n-side cladding layer 43, cladding / impurity diffusion suppression layer 43A, strained quantum well active layer) including a semiconductor multilayer reflector (for example, p-side DBR layer 46) 44, p-side cladding layer 45, cladding / impurity diffusion suppression layer 45A, p-side DBR layer 46, DBR / contact layer 46A) extending along the periphery of a circular current injection region (for example, circular current injection region 46B). An oxidation-inhibiting region (for example, oxidation-inhibiting region 47) containing a Group III impurity (for example, Ga or In) introduced in such a manner, and a semiconductor easy oxidation layer (for example, an AlAs layer) included in the semiconductor multilayer reflector A compound semiconductor oxide extending from the outer edge of the semiconductor layer toward the circular current injection region and terminated at the oxidation inhibition region to define the circular current injection region That the insulating region (e.g. dielectric region 46C) and either characterized by including, or,
[0014]
(3)
One conductivity type cladding layer (for example, n-side cladding layer 22), an active layer (for example, strained quantum well active layer 24) and an opposite conductivity type semiconductor easy oxidation layer (for example, p) on one conductivity type semiconductor substrate (for example, n type substrate 21). A step of laminating an opposite conductivity type cladding layer (for example, the p-side cladding layer 27) and an opposite conductivity type contact layer (for example, the p-type contact layer 28), and then forming a stripe current injection region Introducing a group III impurity (eg, Ga or In) to extend along both sides of the portion to form an oxidation inhibition region (eg, oxidation inhibition region 29), and then forming the opposite conductivity type contact layer Performing mesa etching from the surface to at least the base surface of the opposite conductivity type semiconductor oxidizable layer, and then exposing the opposite conductivity type semiconductor oxide Or characterized by comprising contains a step of the outer edge of the layer to oxidize the until the oxidation inhibition zone defining a stripe current injection region (e.g. stripe current injection region 26A), or,
[0015]
(4)
A resonator (for example, a resonator) including a one-conductivity-type semiconductor multilayer film reflector (for example, an n-side DBR layer 42) and an active layer (for example, a strained quantum well layer 44B) on a one-conductivity-type semiconductor substrate (for example, an n-type substrate 41). 44) and a step of laminating an opposite conductivity type semiconductor multilayer mirror (eg, p-side DBR layer 46) and an opposite conductivity type contact layer (eg, DBR / contact layer 46A), and then a circular current injection region generation scheduled portion Introducing a group III impurity (for example, Ga or In) to extend along the periphery of the substrate to form an oxidation inhibiting region (for example), and then at least the opposite from the surface of the opposite conductivity type contact layer A step of performing mesa etching to reach the underlying surface of the conductive semiconductor multilayer mirror, and then the reverse conductivity included in the exposed reverse conductive semiconductor multilayer mirror Forming a circular current injection region (for example, a circular current injection region 46B) by oxidizing a region from an outer edge of a semiconductor easy oxidation layer (for example, an AlAs layer) to the oxidation inhibition region. To do.
[0016]
By adopting the above means, the oxidation to the semiconductor oxidizable layer is surely stopped in the oxidation inhibition region formed by the implantation of group III ions, and an oxidation inhibition region for controlling the oxidation is formed. The accuracy of ion implantation is greatly different in terms of accuracy as compared with the case where the oxidation of the oxide current confinement layer is controlled by time, the reproducibility is very good, and the manufacturing yield is improved.
[0017]
In addition, the width and diameter of the current injection region in the easy-to-oxidize layer of the semiconductor can be easily selected depending on the mask used for ion implantation to form the oxidation suppression region. Easy.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a cut-away front view of an essential part showing an edge emission type semiconductor laser according to an embodiment of the present invention.
[0019]
In the figure, 21 is a substrate, 22 is an n-side cladding layer, 23 is an SCH (separate confinement heterostructure) layer, 24 is a strained quantum well active layer, 24A is a barrier layer, 24B is a quantum well layer, 25 is an SCH layer, 26 is an easily oxidizable layer, 26A is a stripe current injection region, 26B is an insulating region, 27 is a p-side cladding layer, 28 is a contact layer, 29 is an oxidation-inhibiting region, 30 is a passivation film, 31 is a p-side electrode, and 32 is n Each side electrode is shown.
[0020]
Examples of main data regarding each component of the semiconductor laser shown in FIG. 1 are as follows.
[0021]
(1) About substrate 21 Material: n-GaAs
Impurity: Si
Impurity concentration: 2 × 10 ¹⁸ [cm ^-3 ]
Thickness: 100 [μm]
[0022]
(2) Material for n-side cladding layer 22: n-InGaP
Impurity: Si
Impurity concentration: 2 × 10 ¹⁸ [cm ^-3 ]
Thickness: 1 [μm]
[0023]
(3) Material for SCH layer 23: i-AlGaAs
Thickness: 100 [nm]
[0024]
(4) Strained quantum well active layer 24 ○ Barrier layer 24A
Material: i-GaAs
Thickness: 10 [nm]
○ Quantum well layer 24B
Material: i-InGaAs
Thickness: 8 [nm]
[0025]
(5) Material for SCH layer 25: i-AlGaAs
Thickness: 100 [nm]
[0026]
(6) Material for easy oxidation layer 26: p-AlAs
Impurity: Zn
Impurity concentration: 1 × 10 ¹⁸ [cm ⁻³ ]
Thickness: 10 [nm]
[0027]
(7) Material for p-side cladding layer 27: p-InGaP
Impurity: Zn
Impurity concentration: 1 × 10 ¹⁸ [cm ⁻³ ]
Thickness: 1 [μm]
[0028]
(8) Material for contact layer 28: p-GaAs
Impurity: Zn
Impurity concentration: 2 × 10 ¹⁹ [cm ⁻³ ]
Thickness: 0.3 [μm]
[0029]
(9) Implanted ions: Ga for the oxidation inhibition region 29
Acceleration voltage: 150 [kV]
Dose amount: 1 × 10 ¹³ [cm ^-2 ]
Width: 1 [μm]
Interval: 1 [μm]
[0030]
(10) About the passivation film 30 Material: SiO ₂
Thickness: 300 [nm]
[0031]
(11) Material for p-side electrode 31: Ti / Pt / Au
Thickness: 100 [nm] / 300 [nm] / 3 [μm]
[0032]
(12) Material for the n-side electrode 32: AuGe / Au / Au
Thickness: 30 [nm] / 150 [nm] / 3 [μm]
[0033]
FIG. 2 is a front sectional view showing a main part of the semiconductor laser in the main points of the process for explaining the process of manufacturing the semiconductor laser shown in FIG. 1. Next, FIG. 2 and FIG. An embodiment of the invention will be described.
[0034]
Refer to FIG. 2 (A) 2- (1)
By applying an MBE (molecular beam epitaxy) method, an n-side cladding layer 22, an SCH layer 23, a strained quantum well active layer 24, an SCH layer 25, an easy oxidation layer 26, a p-side cladding layer 27, Contact layer 28 is grown. Note that the MBE method applied here may be replaced with, for example, the MOVPE (Metalorganic Vapor Phase Epitaxy) method.
[0035]
2- (2)
By applying a resist process in the lithography technique, a resist film 33 having an opening 33A is formed in the two oxidation suppression region formation planned portions extending in the cavity length direction.
[0036]
Here, the width of the opening 33A is 1 [μm], and the interval between the two openings 33A is 1 [μm].
[0037]
2- (3)
By applying the ion implantation method, Ga ions are implanted to form an oxidation suppression region 29 that reaches the surface of the SCH layer 25 from the surface of the contact layer 28.
[0038]
Refer to FIG. 2 (B) 2- (4)
By removing the resist film 33 by immersing it in acetone solution and then applying the resist process again, the current injection region forming portion extending in the resonator length direction and the two oxidation inhibition regions 29 are formed. For example, a stripe resist film (not shown) having a width of, for example, about 10 [μm] is formed.
[0039]
2- (5)
By applying a wet etching method using an etchant as a Br-based etchant, mesa etching is performed from the surface of the contact layer 28 to at least the surface of the SCH layer 25 using the stripe resist film as a mask.
[0040]
2- (6)
The stripped resist film is removed by dipping in an acetone solution, and then the oxidizable layer 26 is oxidized in a water vapor atmosphere at a temperature of 400 ° C. supplied by nitrogen bubbling.
[0041]
This oxidation is abruptly delayed in the oxidation inhibition region 29 into which Ga is introduced, so that it can be almost stopped and the width of the current injection region 26A can be ensured accurately.
[0042]
See Fig. 1 1- (1)
The whole is covered with the passivation film 30 by applying the CVD method.
[0043]
1- (2)
By applying a resist process in the lithography technique and a wet etching method using a hydrofluoric acid-based etching solution, the passivation film 30 on the top surface of the mesa is etched to form a stripe having a width of 10 [μm]. Forming an opening.
[0044]
1- (3)
After removing the resist film used as an etching mask for the passivation film 30, the p-side electrode 31 is formed by applying a resist process, a vacuum deposition method, and a lift-off method in lithography technology.
[0045]
1- (4)
By applying a CMP (Chemical Mechanical Polishing) method, the back surface is polished so that the thickness of the substrate 21 becomes about 100 [μm], for example.
[0046]
1- (5)
The n-side electrode 32 is formed on the back surface of the substrate 21 by applying a vacuum deposition method.
[0047]
Thereafter, the device is cleaved to complete the device. In this semiconductor laser, as described above, the width of the current injection region 26A is ensured as designed, so that all devices have substantially uniform characteristics. .
[0048]
FIG. 3 is a cut-away side view of an essential part showing a surface emitting semiconductor laser according to an embodiment of the present invention. Here, a 0.98 [μm] band surface emitting semiconductor laser using a GaAs-based material is targeted.
[0049]
In the figure, 41 is a substrate, 42 is an n-side DBR layer, 43 is an n-side clad layer, 43A is a clad / impurity diffusion suppression layer, 44 is a resonator including an active layer, 44A is a barrier layer, and 44B is a strained quantum. Well layer, 45A is a clad / impurity diffusion suppression layer, 45 is a p-side clad layer, 46 is a p-side DBR layer, 46A is a DBR / contact layer, 46B is a circular current injection region, 46C is an insulating region, 47 is an oxidation suppression region , 48 are passivation films, 49 is a p-side electrode, 50 is a non-reflective film, and 51 is an n-side electrode.
[0050]
The main data regarding each component of the surface emitting semiconductor laser shown in FIG. 3 is exemplified as follows.
[0051]
(1) Material for substrate 41: n-GaAs
Impurity: Si
Impurity concentration: 2 × 10 ¹⁸ [cm ^-3 ]
Thickness: 100 [μm]
[0052]
(2) Material for the DBR layer 42: n-GaAs (λ / 4) / n-AlAs (λ / 4)
Impurity: Si
Impurity concentration: 2 × 10 ¹⁸ [cm ^-3 ]
Number of layers: 22.5 pairs
(3) Material for n-side cladding layer 43: n-AlGaAs
Impurity: Si
Impurity concentration: 1 × 10 ¹⁸ [cm ⁻³ ]
Thickness: 104.75 [nm]
[0054]
(4) Clad and impurity diffusion suppression layer 43A Material: i-AlGaAs
Thickness: 30 [nm]
[0055]
(5) Strained quantum well active layer 44 ○ Barrier layer 44A
Material: i-GaAs
Thickness: 10 [nm]
○ Quantum well layer 44B
Material: i-InGaAs
Thickness: 8 [nm]
[0056]
(6) Clad and impurity diffusion suppression layer 45A
Material: i-AlGaAs
Thickness: 30 [nm]
[0057]
(7) Material for the p-side cladding layer 45: p-AlGaAs
Impurity: Be
Impurity concentration: 1 × 10 ¹⁸ [cm ⁻³ ]
Thickness: 104.75 [μm]
[0058]
(8) Material for the DBR layer 46: p-GaAs (λ / 4) / p-AlAs (λ / 4)
Impurity: Be
Impurity concentration: 2 × 10 ¹⁸ [cm ^-3 ]
Number of layers: 25 pairs [0059]
(9) For the DBR / contact layer 46A, the material p ⁺ -GaAs
Impurity: Be
Impurity concentration: 2 × 10 ¹⁹ [cm ⁻³ ]
Thickness: 50 [nm]
[0060]
(10) Implantation ions: Ga for the oxidation inhibition region 47
Accelerating voltage: Changed from 50 [kV] to 300 [kV] Dose amount: 1 × 10 ¹³ [cm ⁻² ]
Inner diameter: 5 [μm]
Outer diameter: 7 [μm]
Width: 1 [μm]
[0061]
(11) Material for the passivation film 48: SiO ₂
Thickness: 300 [nm]
[0062]
(12) Material for p-side electrode 49: Ti / Pt / Au
Thickness: 100 [nm] / 300 [nm] / 3 [μm]
[0063]
(13) About the antireflective film 50: Material: SiN
Thickness: λ / 4
[0064]
(14) Material for n-side electrode 51: AuGe / Au / Au
Thickness: 30 [nm] / 150 [nm] / 3 [μm]
[0065]
FIG. 4 is a sectional front view showing a main part of the surface emitting semiconductor laser in the main points of the process for explaining the step of manufacturing the surface emitting semiconductor laser shown in FIG. 3. Next, FIG. 4 and FIG. Embodiments of the present invention will be described with reference to the drawings.
[0066]
Refer to FIG. 4 (A) 4- (1)
By applying the MBE method, the DBR layer 42, the n-side cladding layer 43, the cladding / impurity diffusion suppression layer 43A, the strained quantum well active layer 44, the cladding / impurity diffusion suppression layer 45A, the p-side cladding are formed on the substrate 41. A layer 45, a DBR layer 46, and a DBR / contact layer 46A are grown. The MBE method applied here may be replaced with, for example, the MOVPE method.
[0067]
4- (2)
By applying a resist process in lithography technology, a circular band-shaped opening corresponding to an area on which an oxidation suppression region is to be formed and having an inner diameter of 5 [μm] and an outer diameter of 7 [μm], and thus a width of 1 [μm]. A resist film 52 having 52A is formed.
[0068]
4- (3)
By applying the ion implantation method, using the resist film 52 as a mask, Ga ions are implanted in the entire depth direction of the DBR layer to form the oxidation suppression region 47.
[0069]
Refer to FIG. 4 (B) 4- (4)
By removing the resist film 52 by immersing it in acetone, and then applying the resist process again, the diameter that covers the current injection region formation planned portion and the oxidation inhibition region 47 and extends to the outside thereof, for example, A circular resist film (not shown) of about 20 [μm] is formed.
[0070]
4- (5)
By applying a wet etching method using an etchant as a Br-based etching solution, mesa etching is performed from the surface of the DBR / contact layer 46A to at least the surface of the p-side cladding layer 45 using the circular resist film as a mask.
[0071]
4- (6)
After removing the circular resist film by dipping in an acetone solution, the AlAs layer, which is an easily oxidized semiconductor layer in the DBR layer 46, is oxidized in a water vapor atmosphere at a temperature of 400 ° C. supplied by nitrogen bubbling.
[0072]
This oxidation is also slowed down rapidly in the oxidation inhibition region 47 into which Ga has been introduced, so that it can be almost stopped and the diameter of the current injection region 46A can be ensured accurately.
[0073]
See Fig. 3 3- (1)
By applying the CVD method, the whole is covered with a passivation film 48 made of SiO ₂ .
[0074]
3- (2)
By applying a resist process in the lithography technology and a wet etching method using a hydrofluoric acid-based etching solution, the passivation film 48 on the top surface of the mesa is etched to form a circular shape having a diameter of 10 μm. Form an opening.
[0075]
3- (3)
After removing the resist film used as an etching mask for the passivation film 48, the p-side electrode 49 is formed by applying a resist process, a vacuum deposition method, and a lift-off method in lithography technology.
[0076]
3- (4)
By applying the CMP method, the back surface is polished so that the thickness of the substrate 41 becomes, for example, about 100 [μm].
[0077]
3- (5)
By applying a resist process, a vacuum deposition method, and a lift-off method in lithography technology, the antireflection film 50 and the n-side electrode 51 having a thickness of λ / 4, and therefore 2450 [Å] are formed. To do.
[0078]
Thereafter, the element is cleaved to complete the element. In this surface emitting semiconductor laser, as described above, the diameter of the current injection region 46B is ensured as designed, and all elements have substantially uniform characteristics. .
[0079]
【The invention's effect】
In the semiconductor laser obtained according to the present invention, the group III introduced so as to extend along both sides of the stripe current injection region in the compound semiconductor layer formed to include the semiconductor easy oxidation layer. An oxidation inhibiting region made of impurities, and a compound semiconductor oxide extending from an outer edge of the semiconductor easy oxidation layer toward the stripe current injection region and terminated at the oxidation inhibition region to define the stripe current injection region Or a group III impurity introduced so as to extend along the peripheral edge of the circular current injection region in the compound semiconductor layer formed to include the semiconductor multilayer reflector. An oxidation inhibition region, and extends from an outer edge of a semiconductor oxidizable layer included in the semiconductor multilayer reflector toward the circular current injection region and terminates in the oxidation inhibition region It is in and a the circular current injection region defines a compound semiconductor oxide insulating regions.
[0080]
【The invention's effect】
In the semiconductor laser obtained according to the present invention, the group III introduced so as to extend along both sides of the stripe current injection region in the compound semiconductor layer formed to include the semiconductor easy oxidation layer. An oxidation inhibiting region comprising impurities , and a compound semiconductor oxide extending from an outer edge of the semiconductor easy oxidation layer toward the stripe current injection region and terminated at the oxidation inhibition region to define the stripe current injection region Or a group III impurity introduced so as to extend along the peripheral edge of the circular current injection region in the compound semiconductor layer formed to include a semiconductor multilayer reflector. and oxidation inhibition zone comprising the semiconductor multilayer film wherein the outer edge of the semiconductor oxide easily layer included in the reflector extending towards the circular current injection region and the oxide inhibiting territory In and a termination has been made of a compound semiconductor oxide defining said circular current injection region an insulating region.
[0081]
In addition, the width and diameter of the current injection region in the easy-to-oxidize semiconductor layer can be easily selected depending on the mask used when ion implantation is performed to form the oxidation-inhibiting region. It is.
[Brief description of the drawings]
FIG. 1 is a cutaway front view showing a main part of an edge emission type semiconductor laser according to an embodiment of the present invention.
FIG. 2 is a fragmentary front view showing a semiconductor laser in a process essential point for explaining a process of manufacturing the semiconductor laser shown in FIG. 1;
FIG. 3 is a cutaway side view showing a main part of a surface emitting semiconductor laser according to an embodiment of the present invention.
4 is a fragmentary front view showing a semiconductor laser in a process key point for explaining a process of manufacturing the semiconductor laser shown in FIG. 3; FIG.
FIG. 5 is a front view of a principal part showing an edge emission type semiconductor laser for explaining a conventional technique of an oxide current confinement structure.
FIG. 6 is a cutaway side view of a main part showing a surface emitting semiconductor laser having an oxide current confinement structure.
[Explanation of symbols]
21 substrate 22 n-side cladding layer 23 SCH layer 24 strained quantum well active layer 24A barrier layer 24B quantum well layer 25 SCH layer 26 easy oxidation layer 26A stripe current injection region 26B insulating region 27 p-side cladding layer 28 contact layer 29 oxidation inhibition region 30 Passivation film 31 P-side electrode 32 N-side electrode

Claims (4)

An oxidation inhibiting region comprising a group III impurity introduced so as to extend along both sides of the stripe current injection region in the compound semiconductor layer formed to include a semiconductor oxidizable layer; and
An insulating region made of a compound semiconductor oxide extending from an outer edge of the semiconductor easy oxidation layer toward the stripe current injection region and terminated at the oxidation suppression region to define the stripe current injection region. An edge emission type semiconductor laser. An oxidation inhibition region comprising a Group III impurity introduced so as to extend along the periphery of the circular current injection region in the compound semiconductor layer formed to include the semiconductor multilayer reflector;
From the compound semiconductor oxide extending from the outer edge of the semiconductor easy oxidation layer included in the semiconductor multilayer reflector to the circular current injection region and terminated at the oxidation inhibition region to define the circular current injection region A surface-emitting type semiconductor laser comprising an insulating region. A step of laminating a one-conductivity-type cladding layer, an active layer, an opposite-conductivity-type semiconductor easy-oxidation layer, an opposite-conductivity-type clad layer, and an opposite-conductivity-type contact layer on a one-conductivity-type semiconductor substrate;
Next, a step of introducing a Group III impurity so as to extend along both sides of the stripe current injection region generation scheduled portion to form an oxidation inhibition region;
Next, performing mesa etching from the surface of the opposite conductivity type contact layer to at least the underlying surface of the opposite conductivity type semiconductor easy oxidation layer;
And a step of oxidizing a region from the exposed outer edge of the opposite-conductivity-type semiconductor easy-oxidation layer to the oxidation-suppressing region to define a stripe current injection region. Manufacturing method of emission type semiconductor laser. A step of laminating a resonator including an one-conductivity-type semiconductor multilayer reflector and an active layer on a one-conductivity-type semiconductor substrate, an opposite-conductivity-type semiconductor multilayer reflector and an opposite-conductivity-type contact layer;
Next, a step of introducing a group III impurity so as to extend along the periphery of the circular current injection region generation scheduled portion to form an oxidation suppression region,
Next, performing mesa etching from the surface of the opposite conductivity type contact layer to reach at least the ground surface of the opposite conductivity type semiconductor multilayer reflector;
And forming a circular current injection region by oxidizing a region between the outer edge of the opposite conductivity type semiconductor easy-oxidation layer included in the exposed opposite conductivity type semiconductor multilayer film reflector and the oxidation inhibition region. A method of manufacturing a surface-emitting type semiconductor laser, comprising:

Images