JP3922527B2 - Semiconductor storage device control apparatus and semiconductor storage device control method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a control device for a semiconductor storage device and a control method for a semiconductor storage device. More particularly, the present invention relates to a control apparatus and control method for a nonvolatile semiconductor memory device (in an accurate expression, “electrically rewritable nonvolatile semiconductor memory device”) capable of electrically rewriting stored data, and is used particularly in a high temperature environment. The present invention relates to a control apparatus and control method for a semiconductor storage device.
[0002]
[Prior art]
Examples of the “electrically rewritable nonvolatile semiconductor storage device” include an EEPROM (Electrically Erasable Programmable Read Only Memory), an EPROM (Erasable Programmable Read Only Memory), and a flash memory. In this specification, these are collectively referred to as “EEPROM etc.”.
[0003]
An EEPROM or the like can write arbitrary data, and can overwrite the data with other data. In addition, the write data can be held even after the power is turned off. An EEPROM or the like is smaller and lighter than other storage devices having the same function, that is, data writing, data overwriting, and data retention after power-off, for example, a storage device such as a hard disk. It has many advantages such as easy mounting on the board, very low power consumption, no mechanical parts and shock resistance, and various controls used especially in small electronic devices and harsh environments. It is an indispensable data holding device for equipment.
[0004]
By the way, it is known that when an EEPROM or the like is used in a high temperature environment, it may be difficult to guarantee a stable holding operation of stored data. In general, a memory element (nonvolatile memory transistor) that constitutes an EEPROM or the like has a special control gate called a floating gate surrounded by an insulating film, and injects charges into the floating gate. By controlling the threshold voltage, either binary logic (logic 0 or logic 1) data is stored. However, when used in a high temperature environment, the charge in the floating gate is easily lost. This is because it has an undesirable characteristic.
[0005]
Data loss (in other words, destruction of retained data) is considered to be caused by leakage current such as Frenkel-Pool current that becomes prominent under high temperature environment. There are products for use (such as EEPROM for high temperature resistant versions with temperature resistance), but the price is high so that inexpensive general-purpose products (non-temperature resistant normal temperature compatible versions) can be used even in high temperature environments. It is requested to do.
[0006]
<First prior art>
In order to solve the above problems, there has conventionally been a countermeasure, for example, that data is rewritten before data is lost. However, such measures can avoid data loss, but EEPROM and the like have a certain limit (upper limit) on the number of writing, so the number of writable times decreases with rewriting. The cycle (lifetime) was short.
[0007]
<Second prior art>
Japanese Patent Application Laid-Open No. 10-21693 describes a “semiconductor memory device” intended to overcome the above-mentioned drawbacks. According to this, the use environment temperature of the EEPROM or the like is detected, and only when the detected temperature exceeds a predetermined temperature (that is, in a high temperature environment), the data is rewritten, thereby reducing the number of rewrites. Have achieved.
[0008]
That is, the “semiconductor memory device” described in the publication differs from the first prior art (rewriting data before data is lost regardless of temperature) only in a specific high temperature environment. The data is rewritten in the same manner. Therefore, for example, in an in-vehicle environment such as an automobile, it is not always used in a high temperature environment (that is, an application in which a high temperature environment often enters between room temperature environment and low temperature environment). Therefore, data is rewritten only occasionally, and as a result, the number of times of rewriting can be reduced, and the lifetime of the EEPROM or the like can be extended accordingly.
[0009]
[Problems to be solved by the invention]
However, both (first and second prior arts) are exactly the same when viewed in terms of “rewriting for avoiding data loss”. Therefore, the second prior art also has the same problem that the number of times “write” is possible in the EEPROM or the like is reduced by the number of times of rewriting, and the life is shortened accordingly.
[0010]
Accordingly, the present invention provides a control device for a semiconductor memory device that can avoid data loss in a high temperature environment without performing rewriting, and thus can extend the life by not performing rewriting. It is an object.
[0011]
[Means for Solving the Problems]
The present invention provides a temperature detection means for detecting the operating temperature of the semiconductor storage device itself or the ambient environment temperature of the semiconductor storage device;
Disabling means for disabling the semiconductor memory device when the temperature detected by the temperature detecting means exceeds a predetermined temperature;
Alternative storage means for storing data in place of the semiconductor storage device when data is to be written to the semiconductor storage device while the semiconductor storage device is disabled;
And writing means for writing the data into the semiconductor storage device when data is stored in the alternative storage means when the disabling of the semiconductor storage device is released or after the release. is there.
[0012]
Here, “immobilization” means that only the data holding function among the functions of the semiconductor memory device is utilized and the other functions (data writing function and reading function) are stopped. This disabling can be performed, for example, by shutting off the power supply to the semiconductor memory device. In this case, the operation of releasing the disabled state, in other words, releasing and activating the stopped state of other functions (data writing function and reading function) can be performed by resuming the power supply.
[0013]
A “semiconductor memory device” is a non-volatile semiconductor memory device in which stored data can be electrically rewritten. In particular, when used in a high temperature environment, it may be difficult to guarantee a stable operation of storing stored data. Some are, for example, EEPROM, EPROM or flash memory.
Further, the “alternative storage means” may be anything that can be used as a temporary storage area for data written to the semiconductor storage device. For example, the volatile semiconductor storage device itself such as a RAM or a part of the storage area is used. Can be used.
[0014]
According to the present invention, when the operating temperature of the semiconductor storage device itself or the ambient environment temperature of the semiconductor storage device is higher than the predetermined temperature, the semiconductor storage device is disabled. When data is to be written to the semiconductor storage device during the disabled period, the data is saved in the alternative storage means, and then the operating temperature of the semiconductor storage device itself or When the ambient environmental temperature of the semiconductor storage device does not exceed a predetermined temperature, the above-described disabling is canceled and data saved in the alternative storage means is written (written back) to the semiconductor storage device.
[0015]
Therefore, when the operating temperature of the semiconductor storage device itself or the ambient environment temperature of the semiconductor storage device is higher than a predetermined temperature, that is, in a high temperature environment, only the semiconductor storage device is disabled. In other words, since the “rewriting operation” as in the prior art is not performed at all, it is possible to avoid unnecessary consumption of the number of writable times. In addition, it is possible to provide a useful control device for a semiconductor storage device that can avoid data loss in a high-temperature environment and can extend the life by not performing rewriting.
[0016]
According to a more preferred configuration of the present invention, the disabling means disables the semiconductor memory device by cutting off power supply to the semiconductor memory device.
With such a configuration, data loss can be further suppressed by disabling the semiconductor storage device.
[0017]
According to a more preferred configuration of the present invention, the disabling means cuts off power supply to the semiconductor memory device and sets at least the data input / output terminal of the semiconductor memory device to an L logic level or a high impedance state. As a result, the semiconductor memory device is disabled.
With such a configuration, the signal current entering from the data input / output terminal can be cut off, and the heat generation of the chip accompanying the application of the signal current can be suppressed.
[0018]
Further, a more preferable configuration of the present invention is such that an external program stop signal or reset signal is not accepted while the semiconductor memory device is disabled.
With such a configuration, for example, when a volatile semiconductor storage device such as a RAM is used as a data save destination (alternate storage means), it is stored in the alternative storage means by an inadvertent program stop signal or reset signal. The saved data is not lost. Thereby, the stability of the system operation can be ensured.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings, taking as an example application to “EEPROM”. It should be noted that the specification or examples of various details and the illustrations of numerical values, character strings, and other symbols in the following description are only for reference in order to clarify the idea of the present invention, and all or part of them may Obviously, the idea of the invention is not limited. In addition, a well-known method, a well-known procedure, a well-known architecture, a well-known circuit configuration, and the like (hereinafter, “well-known matter”) are not described in detail, but this is also to simplify the description. Not all or part of the matter is intentionally excluded. Such well-known matters are known to those skilled in the art at the time of filing of the present invention, and are naturally included in the following description.
[0020]
FIG. 1 is a block diagram of the control device 1. This control device 1 may be used in a "high temperature environment", but not always, for example, various control units for vehicle use (engine control unit, electric power steering control unit, keyless entry system control unit, etc. The control unit can be a specific example.
[0021]
These vehicle-mounted control units may be exposed to considerable high temperatures, especially when parked under hot weather in summer, and by turning on the air conditioner or starting running, Or it is because it can escape from this high temperature environment by moving to an underground parking lot etc. In other words, these in-vehicle control units are only placed in a high temperature environment under certain conditions (such as when parked under hot weather in summer), and the particular conditions are not permanent and are sporadic ( "Rarely" or "sometimes" or "often").
[0022]
The technology of the present invention does not use such an exemplary control unit (for in-vehicle use) as the outer edge of the idea. Includes all types and applications of control units or the like that may be used sporadically in high temperature environments.
[0023]
In the following, for convenience of explanation, application to an in-vehicle keyless entry system control unit is taken as an example. That is, the control device 1 shown in the figure is a so-called biometric authentication system that performs personal authentication using biological features of the human body that cannot be arbitrarily changed (eg, facial features, fingerprints, retinal blood vessel patterns). It functions as a control unit for a keyless entry system that uses the.
[0024]
In this case, the control device 1 is, for example, an input / output interface 2 for inputting data from a fingerprint sensor or the like and outputting data indicating the result of personal authentication to a keyless entry system, and a central unit using a microcomputer or the like. A processing unit (hereinafter abbreviated as “CPU”) 3, a volatile semiconductor storage device (hereinafter abbreviated as “RAM”) 4, a nonvolatile semiconductor storage device (hereinafter abbreviated as “ROM”) 5, and a rewritable data holding unit 6, a bus 7 (including a data bus and a control bus) that connects these units, and a power supply unit 8 that supplies power to these units.
[0025]
The CPU 3 functions as “immobilization means” and “writing means” described in the gist of the invention, the RAM 4 functions as “alternative storage means” described in the gist, and the EEPROM 9 describes “semiconductor memory device” described in the gist. ”.
[0026]
The rewritable data holding unit 6 includes an electrically rewritable nonvolatile semiconductor memory device (hereinafter abbreviated as “EEPROM”) 9 corresponding to “EEPROM etc.” described at the beginning, and an operating temperature of the EEPROM 9 (EEPROM 9 itself) The operating temperature of the device itself, the temperature of the mounting substrate of the EEPROM 9, the internal temperature of the control device 1 or the ambient environment temperature of the control device 1; hereinafter, these are collectively referred to as “the operating temperature of the EEPROM 9”) are detected. And a temperature sensor 10 that generates and outputs an electrical signal Tmp having a correlated value. Further, according to a predetermined control signal Csw from the input / output interface 2, the electrical continuity of the power supply line of the EEPROM 9 is turned on / off (ON) Switch 11 for turning off / off).
[0027]
Hereinafter, the switch 11 is turned on as illustrated when the control signal Csw is “active”, and is turned off when the control signal Csw is “inactive”. The temperature sensor 10 functions as “temperature detection means” described in the gist of the invention, and the switch 11 functions as “immobilization means” described in the gist.
[0028]
The power supply unit 8 receives supply of an external power supply (in this case, a vehicle battery), generates at least two types of internal power supplies VCCa and VCCb from the external power supply, and supplies the internal power supplies VCCa and VCCb to each unit (input / output). The data is supplied to the interface 2, the RAM 4, the ROM 5, and the rewritable data holding unit 6).
[0029]
One of the features of this embodiment is that the internal power supply (VCCb in the figure) necessary for the operation of the EEPROM 9 of the rewritable data holding unit 6 and other parts (the input / output interface 2 other than the EEPROM 9, the RAM 4, The internal power supply (VCCa in the figure) necessary for the operation of the ROM 5 and the temperature sensor 10) is a separate system, and the switch 11 is inserted in the VCCb supply path.
[0030]
With this feature, for example, Csw is set to “inactive”, the switch 11 is turned off, and the internal power supply VCCb necessary for the operation of the EEPROM 9 can be cut off. As a result, the state in which only the data holding function of the EEPROM 9 is allowed, that is, the state of “disabled” in which the data reading function and the overwriting function are stopped can be achieved.
[0031]
Note that the roles of the CPU 3, RAM 4, ROM 5, and EEPROM 9 are generally as follows. The ROM 5 semi-permanently holds electronic data such as control programs and fixed data necessary for the control device 1. Normally, electronic data is written only once when the control device 1 is shipped from the factory, and the data written in the ROM 5 cannot be changed. The RAM 4 operates as a work memory for the CPU 3. The CPU 3 reads required electronic data (such as a control program) from the ROM 5 via the bus 7, expands (loads) it to the RAM 4, and executes it.
[0032]
In the course of executing various processes by the CPU 3, variable electronic data may be generated. In some cases, the variable data must be stored until it becomes necessary after the fact. For example, in the case of a keyless entry system, the collation information (fingerprint information etc.) of the person registered in advance in the system corresponds to the variable data. The EEPROM 9 is a component for storing such variable data. Whenever variable data is generated, the CPU 3 accesses the EEPROM 9 via the bus 7 and writes the variable data in the EEPROM 9.
[0033]
As described above, since the EEPROM 9 keeps the stored data even after the power is turned off, the variable data written in the EEPROM 9 is not lost over a long period of time. As a result, the keyless entry system stores the collation information written in the EEPROM 9 for a long period of time, and matches the fingerprint reading information of the person to be collated with the collation information read from the EEPROM 9 as necessary, and is registered in the system. It is possible to determine whether or not the person himself / herself is.
[0034]
FIG. 2A is a terminal arrangement diagram of the EEPROM 9. This terminal arrangement shows only a part of the actual arrangement. That is, address terminals and other control terminals (such as terminals for mode designation) are omitted. Needless to say, this terminal arrangement is just one example for convenience of explanation.
[0035]
In the figure, the EEPROM 9 includes a chip select terminal CS, a system clock terminal SK, a data input terminal DI, a data output terminal DO, a power supply terminal VCC, a common potential terminal GND, and the like. The capacitor 12 inserted between the power supply terminal VCC and the common potential terminal GND is a bypass capacitor for removing a pulse-like noise component that enters through the power supply wiring (or outputs to the outside from itself).
[0036]
Now, when the switch 11 is turned on as shown in the figure, the internal power supply VCCb from the power supply unit 8 is applied to the VCC terminal. For this reason, the EEPROM 9 is in an “activated” state in which any function of data writing, data reading and data holding is not limited.
[0037]
When the CPU 3 uses (accesses) the EEPROM 9 in this activated state, first, the chip select terminal CS is activated via the bus 7. When the chip select terminal CS is changed from inactive to active, the EEPROM 9 changes the state of the data input / output terminals DI and DO to the floating state (the state in which the electrical connection with the bus 7 is cut off, or Transition from a high impedance state to a data input / output enabled state. As a result, the EEPROM 9 takes in the write data transmitted via the bus 7 from the input terminal DI (in the write mode), or takes out the data stored therein to the bus 7 from the output terminal DO (in the read mode). time). Note that the description of address designation is omitted.
[0038]
FIG. 2B is an example circuit diagram of the temperature sensor 10. In the case of this example, the temperature sensor 10 includes a first resistance element 10a having temperature dependency and a second resistance having non-temperature dependency (or may have negligible weak temperature dependency). The element 10b is configured to be connected in series between the internal power supply VCCa and the common potential. This temperature sensor 10 is an electric signal obtained by dividing the potential of the internal power supply VCCa by two resistance values (resistance values of the first resistance element 10a and the second resistance element 10b) when the ground potential is set to 0V for convenience. Tmp (voltage across the second resistance element 10b) is output. Now, assuming that the temperature dependency of the first resistance element 10a is, for example, “negative temperature dependency” in which the resistance value decreases as the temperature increases, the temperature of the first resistance element 10a increases as the temperature increases. Since the voltage drop decreases and the voltage (Tmp) across the second resistance element 10b increases by the decrease, the value of the electrical signal Tmp eventually has a correlation that changes in proportion to the temperature.
[0039]
Next, an algorithm for taking measures against data loss of the EEPROM 9 under a high temperature environment while using the electric signal Tmp and the switch 11 will be described.
[0040]
FIG. 3 is a flowchart of the program including the algorithm. This flowchart shows a part of a control program (a control program stored in advance in the ROM 5) executed by the CPU 3 of the control device 1. The initialization process (step S10) and the normal process (step S11) are essentially functional parts of the control program, for example, a keyless entry system, for example, a system initialization process or a pre-registration process for personal authentication, And it is a core part for performing the personal authentication process etc. based on the registration information periodically. On the other hand, a portion surrounded by a wavy line is a sub-portion for taking measures against data loss of the EEPROM 9, and this sub-portion includes the features of the present invention.
[0041]
The branch from the core part to the sub part may be performed in response to an access request to the EEPROM 9, for example. Alternatively, it may be performed in response to an interrupt. When execution of the process moves from the core part to the sub part, the CPU 3 first takes in the electric signal Tmp from the input / output interface 2 (step S12). Next, Tmp is compared with a predetermined determination reference value SL to determine whether Tmp exceeds SL (step S13).
[0042]
As described above, the value of Tmp changes in proportion to the temperature. Now, the value of Tmp at the lower limit temperature (for example, about 85 degrees) that may adversely affect the operation of the EEPROM 9 will be referred to as “TmpHi” for convenience, and the above-described determination reference value SL Will be adjusted to TmpHi. TmpHi corresponds to the predetermined temperature described in the gist of the invention.
[0043]
In this case, if the operating temperature of the EEPROM 9 does not exceed SL (= TmpHi), that is, in a non-high temperature environment, the determination result in step S13 is “Yes” (YES), while the operating temperature of the EEPROM 9 is If it exceeds SL (= TmpHi), that is, in a high temperature environment, the determination result in step S13 is “No” (NO). Hereinafter, processing for each determination result will be described.
[0044]
<Treatment in a high temperature environment>
First, the control signal Csw output from the input / output interface 2 to the switch 11 is set to “inactive”, and the switch 11 is turned off to cut off the supply of the internal power supply VCCb to the EEPROM 9 (step S14). As a result, the EEPROM 9 becomes disabled and makes its own power consumption zero, and at least suppresses heat generation corresponding to the power consumption to avoid data loss. By the way, while the EEPROM 9 is disabled, no data can be written to the EEPROM 9. Therefore, in this algorithm, when data is written to the EEPROM 9 during the immobilization period, the written data is saved in a temporary area (described later) of the RAM 4 (step S15).
[0045]
<Treatment in non-high temperature environment>
On the other hand, when the determination result in step S13 is “No” (NO), that is, in a non-high temperature environment (room temperature or low temperature environment) lower than TmpHi, first, the control signal Csw is set to “active”, Switch 11 is turned on to allow supply of internal power supply VCCb to EEPROM 9 (step S16). As a result, the EEPROM 9 is brought into an activated state in which the immobilization is canceled and data can be read, written, and stored. Next, the temporary area of the RAM 4 is examined, and it is determined whether save data is stored there (step S17). If there is saved data, the data is written in the EEPROM 9 (step S18). Finally, the EEPROM 9 is accessed (step S19).
[0046]
FIG. 4 is a diagram schematically illustrating the processing under the high temperature environment and the processing under the non-high temperature environment. In the case of a non-high temperature environment, as shown in FIG. 6A, the write data from the CPU 3 to the EEPROM 9 is written as it is in the EEPROM 9 as it is, but in the case of a high temperature environment, FIG. As shown in FIG. 5, the write data from the CPU 3 to the EEPROM 9 is not written to the disabled EEPROM 9, but is written to the temporary area 4a of the RAM 4 (data saving). After that, when the temperature decreases and returns to the non-high temperature environment, (c) the data written in the temporary area 4a of the RAM 4 is read and written into the EEPROM 9 in the activated state. Become.
[0047]
As described above, according to the present embodiment, (A) data loss can be avoided by disabling the EEPROM 9 in a high temperature environment. In addition, (B) the effect of avoiding data loss eliminates the need to rewrite data as in the prior art, so the number of times of writing can be reduced and the life of the EEPROM 9 can be extended. Moreover, (C) Since an inexpensive general-purpose product can be used for the EEPROM 9, the system cost can be reduced. Further, (D) if data writing to the EEPROM 9 occurs while the EEPROM 9 is disabled, the data is saved in the RAM 4, and then the RAM 4 is transferred to the EEPROM 9 when returning to the non-high temperature environment. Since the data is written back, the data holding operation is not impaired.
[0048]
In addition, this invention is not limited to said embodiment, In the range of the technical idea of invention, the deformation | transformation to various aspects is possible. For example, the disabling of the EEPROM 9 is not only performed by cutting off the power supply voltage, but may also be combined with the floating state (high impedance state) of the input / output terminals DI and DO. In this way, in addition to the power supply current, the signal current flowing through the input / output terminals DI and DO can be cut off. Alternatively, the input / output terminals DI and DO may be set to the L logic level instead of the floating state, or not only the input / output terminals DI and DO but also other terminals (address terminal, control terminal, etc.) are in the floating state. Or an L logic level.
[0049]
In the above embodiment, the save destination of the data written to the EEPROM 9 in the high temperature environment is the temporary area 4a secured in the RAM 4, but may be a storage area other than the temporary area 4a, or The storage area is not limited to the RAM 4 and may be a storage area of another storage device (of course, a temperature-resistant device).
[0050]
Further, for example, when the CPU 3 executes the initialization process (step S10 in FIG. 3), the volatile storage device such as the RAM 4 may lose the stored data (evacuation data) depending on the contents of the initialization process. There is. Therefore, in this case, the save data cannot be written to the EEPROM 9 after the fact. Therefore, when the save destination is the RAM 4, it is desirable to take some measures to ensure a stable operation. As a countermeasure, for example, while saving data is stored in the RAM 4, it is possible to prevent an external signal (in particular, a program stop signal or a reset signal) that may execute an initialization process from being accepted. .
[0051]
Moreover, although the application to the keyless entry system was illustrated as an application of the control apparatus 1 in the above embodiment, the application to an electric power steering control system other than this is also possible. Especially in this application (electric power steering control system), there is a heat generation part (power steering motor drive circuit; specifically, a bridge circuit for PWM control) in the system control unit, and the temperature for monitoring the heat generation state originally. Since a detection element (such as a thermistor) is provided, a detection signal from the temperature detection element can be used as a substitute for Tmp in the above embodiment.
[0052]
【The invention's effect】
According to the present invention, when the operating temperature of the semiconductor storage device itself or the ambient environment temperature of the semiconductor storage device is higher than the predetermined temperature, the semiconductor storage device is disabled. When data is to be written to the semiconductor storage device during the disabled period, the data is saved in the alternative storage means, and then the operating temperature of the semiconductor storage device itself or When the ambient environmental temperature of the semiconductor storage device does not exceed a predetermined temperature, the above-described disabling is canceled and data saved in the alternative storage means is written (written back) to the semiconductor storage device.
[0053]
Therefore, when the operating temperature of the semiconductor storage device itself or the ambient environment temperature of the semiconductor storage device is higher than a predetermined temperature, that is, in a high temperature environment, only the semiconductor storage device is disabled. In other words, since the “rewriting operation” as in the prior art is not performed at all, it is possible to avoid unnecessary consumption of the number of writable times. In addition, it is possible to provide a useful control device for a semiconductor storage device that can avoid data loss in a high-temperature environment and can extend the life by not performing rewriting.
[0054]
Further, according to a more preferred configuration of the present invention, heat generation accompanying power consumption of the semiconductor memory device itself can be suppressed, the chip temperature can be lowered, and data loss can be further suppressed.
Further, according to a more preferable configuration of the present invention, the signal current entering from the data input / output terminal can be cut off, and the heat generation of the chip accompanying the application of the signal current can be suppressed.
According to a more preferable configuration of the present invention, for example, when a volatile semiconductor storage device such as a RAM is used as a data save destination (alternate storage means), the replacement is performed by an inadvertent program stop signal or reset signal. The saved data stored in the storage means is not lost. Thereby, the stability of the system operation can be ensured.
[Brief description of the drawings]
FIG. 1 is a block diagram of a control device 1;
2 is a terminal arrangement partial view of an EEPROM 9 and an example circuit diagram of a temperature sensor 10. FIG.
FIG. 3 is a view showing a part of a flowchart of a control program (control program stored in advance in a ROM 5) executed by the CPU 3 of the control device 1;
FIG. 4 is a schematic diagram of processing in a high temperature environment and processing in a non-high temperature environment.
[Explanation of symbols]
1 .... Control equipment (Semiconductor memory device control device)
3 ... CPU (immobilization means, writing means)
4 ... RAM (alternative storage means)
9 ... EEPROM (semiconductor memory device)
10 .... Temperature sensor (temperature detection means)
11... Switch (immobilization means)

Claims (5)

Temperature detecting means for detecting the operating temperature of the semiconductor storage device itself or the ambient environment temperature of the semiconductor storage device;
Disabling means for disabling the semiconductor memory device when the temperature detected by the temperature detecting means exceeds a predetermined temperature;
Alternative storage means for storing data in place of the semiconductor storage device when data is to be written to the semiconductor storage device while the semiconductor storage device is disabled;
A semiconductor memory comprising: writing means for writing data into the semiconductor storage device when data is stored in the alternative storage means when the disabling of the semiconductor storage device is released or after the release. Device controller. 2. The control apparatus for a semiconductor memory device according to claim 1, wherein the disabling means disables the semiconductor storage device by cutting off power supply to the semiconductor storage device. The disabling means shuts off the power supply to the semiconductor storage device and disables the semiconductor storage device by setting at least a data input / output terminal of the semiconductor storage device to an L logic level or a high impedance state. 2. The control device for a semiconductor memory device according to claim 1, wherein: 4. The semiconductor memory device according to claim 1, wherein an external program stop signal or reset signal is not accepted while the semiconductor memory device is disabled. Control device. Detecting the operating temperature of the semiconductor storage device itself or the ambient temperature of the semiconductor storage device;
Disabling the semiconductor storage device when the detected temperature is above a predetermined temperature;
Storing data in an alternative storage means different from the semiconductor storage device when data is to be written to the semiconductor storage device while the semiconductor storage device is disabled; and ,
A step of writing the data to the semiconductor storage device when data is stored in the alternative storage means when or after the disabling of the semiconductor storage device is canceled Control method.

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