JP3918675B2

JP3918675B2 - Thin film capacitor, wiring board incorporating the same, semiconductor integrated circuit and electronic equipment system incorporating the same

Info

Publication number: JP3918675B2
Application number: JP2002224362A
Authority: JP
Inventors: 新太郎山道; 透森; 明信渋谷
Original assignee: NEC Corp
Current assignee: NEC Corp
Priority date: 2002-08-01
Filing date: 2002-08-01
Publication date: 2007-05-23
Anticipated expiration: 2022-08-01
Also published as: JP2004071589A

Description

【０００１】
【産業上の利用分野】
本発明は基材上に形成された薄膜キャパシタおよびその薄膜キャパシタを内蔵した多層配線基板さらにはその薄膜キャパシタを搭載した半導体集積回路に関するものである。
【０００２】
【従来の技術】
電子機器の小型化・薄型化に伴い、受動素子であるキャパシタも小型化・薄型化が進んでいる。積層セラミクスコンデンサでは０６０３サイズ（０．６ｍｍ×０．３ｍｍ）から０４０２サイズ（０．４ｍｍ×０．２ｍｍ）まで小型の製品が開発されているが、実装時の取り扱い上の困難さが増しており、これ以上の小型化は難しいとされている。また積層セラミクスコンデンサはその積層構造のために、共振周波数が数百ＭＨｚ程度までであり、ＧＨｚ以上の高速・高周波のシステムに対応させることは難しい。
【０００３】
一方、基材上に下部電極、容量絶縁膜、上部電極を積層した薄膜キャパシタは、共振周波数が数ＧＨｚ以上となり、高速・高周波システムに必要なキャパシタを実現することが可能である。特に（Ｂａ，Ｓｒ）ＴｉＯ_３やＰｂ（Ｚｒ，Ｔｉ）Ｏ_３に代表されるペロブスカイト型酸化物薄膜は１００以上の高い比誘電率を有し、限られた基材面積上に高容量密度の薄膜キャパシタを作製することができる。また近年、ＺｒＯ_２、ＨｆＯ_２あるいはＴｉＯ_２、あるいは、それらの固溶体の薄膜も、比誘電率は１５前後とペロブスカイト型酸化物薄膜に比べると小さいものの、物理膜厚を１０ｎｍ程度に薄く、かつ４００℃以下の低温で成膜できることから、薄膜キャパシタの容量絶縁膜として注目されている。
【０００４】
基材上に形成された薄膜キャパシタで特徴的な構造を有するものとして、特開平６−３２５９６９号公報に開示された薄膜キャパシタが挙げられる。同公報によれば、表面に凹凸部や欠陥のある基材上に薄い容量絶縁膜を有する薄膜キャパシタを形成する際、基材とキャパシタ部との間に空隙を設け、基材の凹凸や欠陥の影響が下部電極や容量絶縁膜に及ばないようにすることにより、キャパシタの短絡を防止している。同様にキャパシタと基材との間に空隙を設ける構造が特開平９−１８１３６３号公報に開示されている。さらに、特開平７−２４５２３３号公報には、基材の表面側に下部電極、容量絶縁膜、上部電極、上部電極の外部接続電極を積層してキャパシタを形成し、基材内に設けた貫通スルーホールを通して下部電極の外部接続電極を引き出した薄膜キャパシタが開示されている。
【０００５】
ここで、実際の電子機器において、マザーボード等の実装基板の面積を縮小するために、キャパシタをはじめ抵抗やインダクタなどの受動素子を多層配線基板に内蔵する方法が提案されている。例えば特開平１１−１２６９７８号公報には、多層配線基板内に空隙を設け、その空隙内にキャパシタや抵抗などの電子素子を内蔵する技術が開示されている。また特開２００１−１６８５３４号公報には、貫通スルーホールを用いて、内蔵した受動素子を配線層に接続させた多層配線基板が開示されている。これら配線基板に内蔵されるキャパシタは、従来の積層セラミクスコンデンサあるいは薄膜を単純に積層した薄膜キャパシタである。
【０００６】
またＬＳＩ(大規模集積回路)においては、その動作周波数が数百ＭＨｚからＧＨｚオーダーとなり、クロックの立ち上がり時間が非常に短くなってきたため、ＬＳＩに急激な負荷がかかると、電源とＬＳＩの配線間に存在する寄生抵抗と寄生インダクタンスにより電圧降下が生じ、それに伴う誤動作が問題となっている。この電圧降下を低減するために、デカップリングキャパシタとして、従来は積層セラミクスコンデンサをＬＳＩの近傍に実装し、それによってノイズ低減を図っていた。
【０００７】
【発明が解決しようとする課題】
図１６に、基材上に形成された従来の薄膜キャパシタの断面構造を示す。基材８０１上に下部電極８０２、容量絶縁膜８０３、上部電極８０４が積層されたキャパシタ部８２３と、下部電極８０２あるいは上部電極８０４と接触する外部接続電極８０７、８０６が存在する接続端子部８２２、８２４とから薄膜キャパシタが構成されているが、このキャパシタ部８２３と接続端子部８２２、８２４との間が、ＳｉＯ_２、ＢＰＳＧ（boro-phospho silicate glass）やＮＳＧ（non-doped silicate glass）、あるいは、ポリイミドやエポキシなどの絶縁樹脂を用いた層間絶縁膜８０５で埋め込まれ、薄膜キャパシタが一体的にリジットに固定されている。このような従来の薄膜キャパシタを、配線が存在する多層配線基板あるいはＬＳＩ上に搭載した場合、配線の段差によって薄膜キャパシタがたわみ、キャパシタ部や配線に応力が集中し、キャパシタが短絡状態または開放状態となってしまうということが、発明者の鋭意研究の結果、明らかとなった。
【０００８】
特開平１１−１２６９７８号公報に開示された多層配線基板では、内部の空隙に電気素子が内蔵されているが、配線段差上に搭載された電気素子の、搭載時の圧力による変形については考慮されていない。また、特開２００１−１６８５３４号公報に開示された多層配線基板においても、その内部のくぼみに内蔵された薄膜キャパシタへの応力集中は考慮されていない。同様に、特開平７−２４５２３３号公報に開示された薄膜キャパシタもリジッドな構造で、変形時に生じる応力を吸収する手段を有しないので、例えば容量絶縁膜が断線して下部電極と上部電極とが短絡してしまうなどの問題が発生し得る。一方、特開平６−３２５９６９号公報や特開平９−１８１３６３号公報に開示された、基材に空隙が存在する薄膜キャパシタは、キャパシタ上方からのプレス圧力を受けたときに、基材の空隙内部に下部電極や容量絶縁膜が変形して埋め込まれてしまい、結果として電極の短絡や開放による不良を引き起こしてしまう。ＬＳＩ上への搭載時にもキャパシタ変形による同様の不良が発生しやすい。
【０００９】
本発明は、上記課題に鑑みてなされたものであって、その目的は、第一に、多層配線基板やＬＳＩに薄膜キャパシタを内蔵・搭載する際に、配線の段差によって生じた薄膜キャパシタの変形が引き起こす短絡や開放による不良を回避し、キャパシタ作製直後の初期特性が、多層配線基板やＬＳＩへの搭載後も変化しないような薄膜キャパシタを提供することであり、第二に、そのような信頼性の高い薄膜キャパシタを搭載した多層配線基板や半導体集積回路を提供することである。第三に、そのような多層配線基板や半導体集積回路を含む電子機器システムを提供することである。
【００１０】
【課題を解決するための手段】
上記目的を達成するため、本発明によれば、基材上に、下部電極が形成され、前記下部電極の一部領域上に容量絶縁膜が形成され、前記容量絶縁膜の一部領域上に上部電極が形成され、前記下部電極と前記容量絶縁膜と前記上部電極を覆う層間絶縁膜が形成され、前記層間絶縁膜に設けられたビアを介して前記下部電極及び前記上部電極にそれぞれ接続された下部接続電極及び上部接続電極が設けられている薄膜キャパシタであって、前記上部接続電極が前記上部電極の上方に形成され、前記上部接続電極と前記下部接続電極の間の前記層間絶縁膜の一部に表面側から空隙が設けられていることを特徴とする薄膜キャパシタ、が提供される。
【００１１】
また、上記目的を達成するため、本発明によれば、基材上に、下部電極が形成され、前記下部電極の一部領域上に容量絶縁膜が形成され、前記容量絶縁膜の一部領域上に上部電極が形成され、前記下部電極と前記容量絶縁膜と前記上部電極を覆う層間絶縁膜が形成され、前記層間絶縁膜に設けられたビアを介して前記下部電極及び前記上部電極にそれぞれ接続された下部接続電極及び上部接続電極が設けられ、前記上部接続電極が前記容量絶縁膜の形成されていない領域まで延在している薄膜キャパシタであって、前記容量絶縁膜と前記下部接続電極の間の前記層間絶縁膜の一部に表面側から第一の空隙が設けられ、前記上部接続電極が前記延在している領域の前記層間絶縁膜の一部に表面側から第二の空隙が設けられ、前記上部接続電極が前記第二の空隙の側面と底面に沿って前記第二の空隙を完全に埋めないように設けられていることを特徴とする薄膜キャパシタ、が提供される。
そして、好ましくは、前記空隙が下部電極表面まで到達し、前記下部電極の露出した空隙が設けられたり、あるいは、前記第二の空隙が前記基材表面まで到達し、前記上部接続電極が前記層間絶縁膜の側面と前記基材の底面に沿って前記第二の空隙を完全に埋めないように設けられている。また、好ましくは、前記基材の厚さが、前記薄膜キャパシタ全体の厚さの半分以下であったり、前記基材がフレキシブル材料である。
【００１２】
また、上記目的を達成するため、本発明によれば、上記の薄膜キャパシタが樹脂基板内に埋め込まれ、前記薄膜キャパシタの下部接続電極が該下部接続電極を貫通するスルーホールまたは該下部接続電極に達するビアホールを介して引き出され、前記薄膜キャパシタの上部接続電極が該上部接続電極を貫通するスルーホールまたは該上部接続電極に達するビアホールを介して引き出されていることを特徴とする薄膜キャパシタを内蔵した配線基板、が提供される。
【００１３】
また、上記目的を達成するため、本発明によれば、上記の薄膜キャパシタを搭載した半導体集積回路であって、その表面上に形成された電極パッドに前記薄膜キャパシタの下部接続電極および上部接続電極が接続されていることを特徴とする薄膜キャパシタを搭載した半導体集積回路、が提供される。
【００１４】
【発明の実施の形態】
次に、本発明の実施の形態について図面を参照して詳細に説明する。
図１は、本発明の薄膜キャパシタの第１の実施の形態を示す断面図である。樹脂または金属からなる厚さ５０μｍ程度の基材１０１上に、下部電極１０２と容量絶縁膜１０３と上部電極１０４とが積層されたキャパシタ部１２３と、層間絶縁膜１０５を介して上部電極１０４および下部電極１０２にそれぞれ接続されている外部接続電極１０６および１０７が存在する接続端子部１２４、１２２とを有して薄膜キャパシタが構成されている。キャパシタ部１２３と接続端子部１２４、１２２との間の層間絶縁膜１０５には、空隙１０８が存在している。空隙１０８は、基材１０１の変形によって生じる応力を吸収して、下部電極１０２、容量絶縁膜１０３、上部電極１０４が損傷を受けないようにするために設けられている。外部接続電極１０６、１０７は、接続抵抗を小さくするために１０μｍ以上の十分厚い膜厚を有することが望ましく、また、その材料としては抵抗率の小さなＣｕを主成分とすることが好ましい。また容量絶縁膜１０３は、下部電極１０２と上部電極１０４との電気的短絡を防止するために下部電極１０２の端部を十分覆うことができるように、ＣＶＤ法やゾルゲル法など段差被覆性に優れた成膜手法で作製されることが望ましい。
【００１５】
次に、この第１の実施の形態の薄膜キャパシタの作製プロセルを、基材１０１としてポリイミドフィルムを用いた場合について説明する。まず、市販のポリイミドフィルムの上に、ＤＣスパッタ法により下部電極１０２として、ＴｉＮ／Ｍｏ／Ｔｉの積層膜を堆積した後、フォトリソグラフィー法とウェットエッチング法により所望のパターンを形成した。その上に容量絶縁膜１０３として、ＣＶＤ法により成膜温度３００℃でＡｌ_２Ｏ_３薄膜を成膜した後、フォトリソグラフィー法とＩＢＥ（イオンビームエッチング）法により所望の形状に加工した。さらに上部電極１０４として、ＤＣスパッタ法によりＡｕ／ＴｉＮ積層膜を堆積した後、フォトリソグラフィー法とウェットエッチング法により所望のパターンを形成した。次に、層間絶縁膜１０５として、感光性ポリイミド樹脂を塗布した後、フォトリソグラフィー法により所望のパターンを形成した。その後、ＤＣスパッタ法によりＣｕ／Ｔｉ積層膜を全面に堆積した。次に、フォトリソグラフィー法により形成すべき外部接続電極形状の開口を有するレジスト膜を形成し、その開口にＣｕ／Ｔｉ膜を給電層として電解めっき法によりＣｕを１２μｍの厚さに成膜し、外部接続電極１０６および１０７とした。最後に、レジスト膜を除去した後、外部接続電極１０６および１０７以外の領域に露出したＣｕ／Ｔｉ積層膜をウェットエッチング法で除去して、図１に示す本実施の形態に係る薄膜キャパシタの製造工程を完了した。図１では空隙部に層間絶縁膜が無い構造が示されているが、十分な応力緩和が得られる範囲内であれば、空隙内の下部電極１０２や上部電極１０４の直上に層間絶縁膜の一部が残っていても構わない。
【００１６】
図２（ａ）、（ｂ）は、本発明の薄膜キャパシタの第２の実施の形態を示す平面図と断面図である。図２において、図１に示した第１の実施の形態の部分と同等の部分には同一の参照符号を付し重複する説明を省略する。本実施の形態の薄膜キャパシタが図１に示した第１の実施の形態の薄膜キャパシタと異なる点は、上部電極１０４が容量絶縁膜１０３の上にしか形成されず、上部電極側の外部接続電極１０６が、上部電極側の接続端子部１２４からキャパシタ部１２３まで延びてきており、キャパシタ部１２３の層間絶縁膜１０５に形成した開口を通して上部電極１０４に接続されているという点である。このように、上部電極１０４を容量絶縁膜１０３の上だけに形成することによって、容量絶縁膜１０３は、下部電極１０２の端部を覆う必要がなくなるので、ＣＶＤ法やゾルゲル法以外にスパッタ法等の段差被覆性の乏しい成膜手法で作製されることが可能になる。また、外部接続電極１０６と基材１０１との間に下部電極１０２と同じ材料で形成された外部接続電極受け１０２ｂが存在しているが、この外部接続電極受け１０２ｂは、外部接続電極１０６と基材１０１とを密着させるための単なる密着層であって、外部接続電極１０６が基材１０１と直接接しても密着するものである場合には、省略されても構わない。
【００１７】
図２（ａ）の５０２、５０２ｂ、５０３は、それぞれ、接続端子部１２２、１２４、キャパシタ部１２３において、下部電極１０２、外部接続電極受け１０２ｂ、上部電極１０４に対して外部接続電極のコンタクトを得るために層間絶縁膜１０５に形成したコンタクト開口部である。キャパシタ部１２３と接続端子部１２４、１２２との間には、第１の実施の形態と同様に、層間絶縁膜１０５を介して空隙１０８が存在している。
【００１８】
次に、この第２の実施の形態の薄膜キャパシタの作製プロセスを、基材１０１としてポリイミドフィルムを用いた場合について説明する。まず、市販のポリイミドフィルムを用い、この上にＤＣスパッタ法により下部電極１０２としてＰｔ／Ｔｉ／Ｍｏ／Ｔｉの積層膜を堆積し、その上に容量絶縁膜１０３として、ｒｆスパッタ法により成膜温度３５０℃でＳｒＴｉＯ_３薄膜を成膜し、さらに上部電極１０４としてＤＣスパッタ法によりＰｔ膜を堆積し、フォトリソグラフィー法とウェットエッチング法により、順次、所望のパターンを形成した。次に、層間絶縁膜１０５として、感光性ポリイミド樹脂を塗布した後、フォトリソグラフィー法により所望のパターンを形成した。その後、ＤＣスパッタ法によりＣｕ／Ｔｉ積層膜を全面に堆積した。次に、フォトリソグラフィー法により形成すべき外部接続電極形状の開口を有するレジスト膜をキャパシタ部１２３と接続端子部１２４、１２２とに形成し、その開口にＣｕ／Ｔｉ積層膜を給電層として電解めっき法によりＣｕを１２μｍの厚さに成膜した。次いで、レジスト膜を除去した後、露出したＣｕ／Ｔｉ積層膜をウェットエッチング法で除去した。次に、キャパシタ部１２３と接続端子部１２２との間の空隙をレジスト膜で覆い、スパッタ法を用いて、キャパシタ部１２３に形成したＣｕ層と接続端子部１２４に形成したＣｕ層とを接続する金属層を形成した。最後にレジスト膜を除去して、図２に示す本実施の形態に係る薄膜キャパシタの製造工程を完了した。上述の製造工程において、最後に形成する金属層の金属を種々選択することによって、外部接続電極の最上層の金属としてＣｕ以外の金属を選択できるというメリットが生じる。キャパシタ部１２３に形成したＣｕ層と接続端子部１２４に形成したＣｕ層とを接続する金属層を形成する方法として、給電層として利用した、この部分のＣｕ／Ｔｉ積層膜を除去せずに残して利用する方法もある。この場合は、最後の金属層の成膜工程が省略できるというメリットがある。さらに、キャパシタ部１２３に形成したＣｕ層と接続端子部１２４に形成したＣｕ層とを接続する金属層を形成する方法として、キャパシタ部１２３と接続端子部１２２、１２４とにＣｕめっき層を形成する際、キャパシタ部１２３と接続端子部１２４との間にもＣｕめっき層を形成し、エッチング法によって内部に空隙を有する金属層に加工する方法も考えられるが、金属層の膜厚の制御が難しく、生産性において劣る。なお、図２では空隙部には層間絶縁膜が無い構造が示されているが、第１の実施の形態と同様に、十分な応力緩和が得られる範囲内で、空隙内の下部電極１０２や外部接続電極１０６の直上に層間絶縁膜の一部が残っていても構わない。
【００１９】
本実施の形態の薄膜コンデンサの製造方法においては、第１の実施の形態と違って、容量絶縁膜１０３の成膜方法として、段差被覆性の乏しいｒｆスパッタ法を用いることが可能である。
【００２０】
図３は、図２に示す本実施の形態の薄膜キャパシタを配線の段差の存在する配線基板上に搭載した様子を示している。配線基板のコア層２０１上に厚さ２４〜３０μｍ程度の配線層２０２が形成されており、コア層２０１と配線層２０２との間に、配線層の厚さの段差が生じている。配線層２０２の上に、エポキシ樹脂等の接着剤を用いて、本発明の薄膜キャパシタ２０５が搭載されている。この薄膜キャパシタ２０５が上方よりプレスされると、薄膜キャパシタ２０５のキャパシタ部１２３が下に凸状に変形する。しかしながら、キャパシタ部１２３と接続端子部１２２、１２４との間に存在する空隙１０８が、変形によって発生する応力を吸収するため、電極膜（下部電極や上部電極）が断線したり、容量絶縁膜にクラックが入ることはない。
【００２１】
図４は、図２に示す本実施の形態の薄膜キャパシタを上下逆転させて、その外部接続電極をはんだボールによって半導体集積回路上の電極パッドに接続した様子を示している。薄膜キャパシタ３０５の外部接続電極１０６、１０７のはんだボール３０８による電極パッド３０２への接続後、薄膜キャパシタ３０５は下に凸（薄膜キャパシタ本来の上下方向では上に凸）状に変形するが、空隙１０８が存在するため、電極膜（下部電極や上部電極）が断線したり、容量絶縁膜にクラックが入ったりすることがない。
【００２２】
図５（ａ）、（ｂ）は、本実施の形態の薄膜キャパシタの変形例を示す平面図である。図５において、図２（ａ）に示した部分と同等の部分には同一の参照符号を付し重複する説明を省略する。図５（ａ）に示す薄膜キャパシタは、空隙１０８の領域において、層間絶縁膜１０５が、キャパシタ部１２３と接続端子部１２４、１２２との間で、櫛形状に入り組んだ構造となっている。また、図５（ｂ）に示す薄膜キャパシタは、キャパシタ部１２３と接続端子部１２４、１２２との間で、層間絶縁膜１０５がのこぎり歯形状に入り組んだり、図５（ａ）の場合と９０°異なる向きに櫛形状に入り組んでいるような構造となっている。このように、空隙１０８からは必ずしも層間絶縁膜１０５を完全に除去する必要はなく、空隙１０８は、変形による応力を吸収もしくは低減できる構造を有していればよい。図５（ａ）、（ｂ）に示す薄膜コンデンサの構造は、図２に示す薄膜コンデンサの構造と比べて、ねじり方向の強度が増し、製造上の取り扱いが容易になるという利点を有する。
【００２３】
図６は、本発明の薄膜キャパシタの第３の実施の形態を示す断面図である。図６において、図２に示した第２の実施の形態の部分と同等の部分には同一の参照符号を付し重複する説明を省略する。本実施の形態の薄膜キャパシタが図２に示した第２の実施の形態の薄膜キャパシタと異なる点は、キャパシタ部１２３と接続端子部１２２、１２４との間が、空隙ではなく、弾性率の小さなゴムなどの低弾性率材料１０９で完全に、あるいは部分的に充填されているという点である。この低弾性率材料１０９に要求される特性は、層間絶縁膜１０５よりも低いヤング率（弾性率）を有するということである。低弾性率材料１０９のヤング率が層間絶縁膜１０５のヤング率よりも低ければ、薄膜キャパシタが変形して紙面左右方向に応力が働いたとき、層間絶縁膜１０５が歪まずに低弾性率材料１０９が歪んで応力を吸収することができる。外部接続電極は、第１の実施の形態と同様、接続抵抗を小さくするために１０μｍ以上の十分厚い膜厚を有することが望ましく、また、抵抗率の小さなＣｕを主成分とすることが好ましい。図６に示す本実施の形態の薄膜キャパシタは、図１、図２に示す第１、第２の実施の形態の薄膜キャパシタと同様に、変形によって生じる応力を吸収して、電極の短絡や開放による不良を防止することができる。図６に示す本実施の形態の薄膜キャパシタは、さらに、図２に示した第２の実施の形態の薄膜キャパシタに比べ、キャパシタ部１２３と接続端子部１２２、１２４との間が低弾性率材料１０９で充填されているため、薄膜キャパシタを取り扱う際の折れ曲がりが防止され、ハンドリングが容易になり、製造上の歩留まりが向上するという効果を有する。
【００２４】
図７は、本発明の薄膜キャパシタの第４の実施の形態を示す断面図である。図７において、図２に示した第２の実施の形態の部分と同等の部分には同一の参照符号を付し重複する説明を省略する。本実施の形態の薄膜キャパシタが図２に示す第２の実施の形態の薄膜キャパシタと異なる点は、上部電極１０４の接続端子部が存在しないという点である。このように、上部電極１０４の接続端子部をなくすると、上部電極１０４に接続される外部接続電極１０６が容量絶縁膜１０３の真上に引き出されるため、配線基板に内蔵したときに表面配線層との電気的接続にプロセス上安価な貫通スルーホールを使うことができないというデメリットはあるが、外部接続電極１０６が横方向に引き延ばされることがないので、図２に示した第２の実施の形態の薄膜キャパシタと比べて、薄膜キャパシタの形状が小さくなるというメリット、および、高周波特性が向上するというメリットがある。また、ビルドアップ工法によるビア接続およびはんだボールでの接続は可能であって、キャパシタの搭載面積が小さくなる効果がある。
【００２５】
図８は、本発明の薄膜キャパシタの第５の実施の形態を示す断面図である。図８において、図７に示した第４の実施の形態の部分と同等の部分には同一の参照符号を付し重複する説明を省略する。本実施の形態の薄膜キャパシタが図７に示した第４の実施の形態の薄膜キャパシタと異なる点は、キャパシタ部１２３と接続端子部１２２との間が、低弾性率材料１０９で完全に、あるいは部分的に充填されているという点である。図８に示す薄膜キャパシタは、図６に示した薄膜キャパシタと同様に、薄膜キャパシタを取り扱う際の折れ曲がりが防止され、ハンドリングが容易になり、製造上の歩留まりが向上するという効果を有する。
【００２６】
図９は、本発明の薄膜キャパシタの第６の実施の形態を示す断面図である。図９において、図２に示した第２の実施の形態の部分と同等の部分には同一の参照符号を付し重複する説明を省略する。本実施の形態の薄膜キャパシタが図２に示した第２の実施の形態の薄膜キャパシタと異なる点は、キャパシタ部１２３と接続端子部１２２との間の空隙部において下部電極１０１に電極ギャップ１１１が存在し、キャパシタ部１２３と接続端子部１２４との間の空隙部において外部接続電極１０６に電極ギャップ１１２が存在し、少なくとも電極ギャップ１１１、１１２を満たすように、圧縮応力が印加されると印加圧縮応力の方向の寸法が減少するとともにその方向の導電率が増加する材料〔以下、「圧力依存導電率材料」という〕１１０が充填されているという点である。圧力依存導電率材料１１０は、紙面左右方向に応力の働いていないときにその方向の導電率が低く、紙面左右方向に圧縮応力が働いたときにその方向の導電率が高くなる。このような圧力依存導電率材料は、例えば弾性率の低い樹脂内部に金属粒子などの導電材料を分散させて作製することができる。
【００２７】
図１０は、本発明の薄膜キャパシタの第７の実施の形態を示す断面図である。図１０において、図９に示した第６の実施の形態の部分と同等の部分には同一の参照符号を付し重複する説明を省略する。本実施の形態の薄膜キャパシタが図７に示した第６の実施の形態の薄膜キャパシタと異なる点は、少なくとも電極ギャップ１１１、１１２を満たす圧力依存導電率材料１１０の上に、空隙部を完全にあるいは部分的に充填するように低弾性率材料１０９が形成されているという点である。本実施の形態の薄膜キャパシタにおいて低弾性率材料１０９を使用した効果は、図６および図８に示した薄膜キャパシタにおいて低弾性率材料を使用した効果と同じである。なお、第７、第８の実施の形態においても、外部接続電極は、第１の実施の形態の薄膜キャパシタの場合と同様に、接続抵抗を小さくするために１０μｍ以上の十分厚い膜厚を有することが望ましく、また、抵抗率の小さなＣｕを主成分とすることが好ましい。
【００２８】
図９、図１０に示す薄膜キャパシタは、作製直後では電極ギャップ１１１、１１２内の圧力依存導電率材料１１０の抵抗が高く、特性評価を行なうことが不可能である。しかしながら、例えば図３に示すような薄膜キャパシタが下に凸の形状になるような応力が加わると、圧力依存導電率材料１１０が紙面左右方向に圧縮応力を受け、その結果、樹脂中に分散している導電材料が接触し合うことによって圧力依存導電率材料１１０の導電率が増加し、キャパシタ部１２３の下部電極１０２および上部電極１０４と、接続端子部１２２、１２４の外部接続電極１０７、１０６とがそれぞれ電気的に導通し、薄膜キャパシタとしての動作が可能になる。圧力依存導電率材料１１０は変形することによって応力を吸収する役割をも果たすので、図２に示す第２の実施の形態のように電極膜が存在する場合に比べ、容量絶縁膜への印加応力がさらに小さくなり、設計値どおりの容量値が高歩留まりで得られる。
【００２９】
図１１は、本発明の薄膜キャパシタを内蔵した多層配線基板の断面図である。図１１に示す薄膜キャパシタ内蔵多層配線基板は、以下のように作製される。本発明の薄膜キャパシタ２０５をコア層２０１に形成された配線層２０２の上に搭載した後、コア層２０１をプリプレグ層２０３で挟み、プレスにより一体化する。その後、薄膜キャパシタ２０５の外部接続電極１０６、１０７を貫通するように基板を貫通する貫通スルーホール２０４を設け、プリプレグ層２０３の表面に配線パターン２０６を形成するとともに、貫通スルーホール２０４の内壁面に、配線パターン２０６と薄膜キャパシタ２０５の外部接続電極１０６、１０７や配線層２０２とを接続するＣｕめっき層２０７を形成する。
【００３０】
一体化の際のプレスにより、薄膜キャパシタは下に凸状に変形するが、空隙１０８が変形によって発生する応力を吸収するため、電極層が断線したり、容量絶縁膜にクラックが入ったりすることがなく、多層配線基板内蔵後も良好な容量値が得られる。
なお、上述の説明においては、薄膜キャパシタの外部接続電極は、貫通スルーホールを介して配線パターンに接続されたが、外部接続電極に達するビアホールを形成して、このビアホールを介して配線パターンに接続されるようにしてもよい。また、本発明のキャパシタ内蔵配線基板において、本発明の全ての実施の形態の薄膜キャパシタを使用することができる。
【００３１】
図１２は、本発明の薄膜キャパシタを搭載した半導体集積回路の断面図である。本発明の半導体集積回路は、本発明の薄膜キャパシタを半導体集積回路の配線最上層にはんだボールを用いて上下逆転して搭載した例に関するものである。薄膜キャパシタ３０５は、半導体集積回路３０６の配線最上層の電極パッド３０２にはんだボール３０８を用いて搭載されており、その一方の電極（上部電極）は電源線に、他方の電極（下部電極）はグラウンド線に接続されている。電源線は、また、層間絶縁膜３０１に形成したビアホール３０７の内壁に堆積されたＣｕめっき層を介して、ＭＯＳトランジスタ３０４のドレイン電極に接続されている。したがって、薄膜キャパシタ３０５は、ＭＯＳトランジスタ３０４や外部電源のノイズを低減するデカップリングキャパシタとして作用している。
【００３２】
薄膜キャパシタ３０５は、半導体集積回路３０６への搭載時の押し付け圧力により、図１２において下に凸（薄膜キャパシタ本来の上下方向では上に凸）状に変形するが、空隙１０８が存在するために、容量絶縁膜にクラックが入ったりすることがなく、結果として、半導体集積回路３０６の電源線とグラウンド線が短絡するというような故障の発生することがない。
なお、上述の説明においては、薄膜キャパシタの外部接続電極は、はんだボールを介して電極パッドに接続されたが、スタッドバンプを介して電極パッドに接続されるようにしてもよい。また、本発明の薄膜キャパシタ搭載半導体集積回路において、本発明の薄膜キャパシタの第１〜第５の実施の形態のものが好適に用いられる。
【００３３】
〔比較例〕
従来の技術に基づいて薄膜キャパシタを作製した。図１３は、本比較例において作製された薄膜キャパシタの断面図である。図１３において、図２に示した第２の実施の形態の部分と同等の部分には同一の参照符号を付し重複する説明を省略する。本実施の形態の薄膜キャパシタが図２に示した第２の実施の形態の薄膜キャパシタと異なる点は、キャパシタ部１２３と接続端子部１２２、１２４との間に空隙が存在せず、キャパシタ部１２３と接続端子部１２２、１２４が層間絶縁膜１０５によってリジッドに固定されているという点である。このような構造の薄膜キャパシタにおいても、本発明の全ての実施の形態の薄膜キャパシタと同様に、作製直後においては設計どおりの容量値が得られた。しかしながら、図１１に示す薄膜キャパシタ内蔵配線基板の場合と同様にして、この薄膜キャパシタを多層配線基板に内蔵し、外部接続電極を用いて薄膜キャパシタの特性を評価したところ、多くの開放あるいは短絡による不良が発生した。
【００３４】
その原因を調べるため、薄膜キャパシタの断面部を観察したところ、図１４に示すように、層間絶縁膜、下部電極、容量絶縁膜に欠陥が発生することが明らかとなった。即ち、配線層２０２がコア層２０１に対して段差を有するために、薄膜キャパシタ実装時の押し付け圧力によって薄膜キャパシタが下に凸状に変形しており、キャパシタ部１２３と接続端子部１２２、１２４との間の層間絶縁膜１０５にクラック４０１が観察された。層間絶縁膜１０５のクラック４０１は、下部電極１０２の内部を通って基材１０１の表面まで達し、下部電極１０２に断線が見られた。このことが、本比較例の薄膜キャパシタが多層配線基板内蔵後に開放による不良となった原因であると考えられる。さらに、容量絶縁膜１０３にもクラック４０２が観察された。このことが、上部電極と下部電極との短絡による不良の原因であると考えられる。これらのクラックが発生するのは、キャパシタ部１２３と接続端子部１２２、１２４とが層間絶縁膜１０５によってリジッドに固定され、薄膜キャパシタの変形によって発生する応力を吸収する層が存在しないためである。
【００３５】
図１５に本発明の薄膜キャパシタおよび比較例の薄膜キャパシタを多層配線基板に内蔵したときの測定容量値のばらつきを示す。薄膜キャパシタの容量の設計値は１０００ｐＦである。本発明の薄膜キャパシタを用いた場合、７５％以上の歩留まりで目標容量値が得られており、短絡や開放による不良も発生していない。一方、比較例の薄膜キャパシタを用いた場合、容量値のばらつきが大きく、１５％以上もの割合で短絡や開放による不良が発生している。
【００３６】
以上、本発明をその好適な実施の形態に基づいて説明したが、本発明の薄膜キャパシタ、それを用いた半導体集積回路および配線基板は、上述した実施の形態のみに制限されるものではなく、本願発明の要旨を変更しない範囲で種々の変化を施した薄膜キャパシタ、それを用いた半導体集積回路および配線基板も、本発明の範囲に含まれる。例えば、基材としては、主に樹脂を用いて説明されたが、ある程度の弾力を有し、多層配線基板や半導体集積装置に搭載可能な厚さを有するものであればどのような材料であってもよい。例えば、ＳＵＳやＣｕに代表される金属板や、１００μｍ程度の厚さに研磨したシリコン基板、サファイア基板などであっても良い。また低弾性率材料としては、ゴムの例を述べたが、樹脂やシリコーン等、弾性率が小さく、応力緩和の効果のある材料であればよい。また、薄膜コンデンサの容量絶縁膜としては、Ｔａ_２Ｏ_５やＳｒＴｉＯ_３薄膜の場合について説明したが、その一部あるいは全部が、化学式がＡＢＯ_３で表され、それぞれ、ＡとしてＢａ、Ｓｒ、Ｐｂ、Ｃａ、Ｌａ、Ｌｉ、Ｋのうち少なくとも1種以上、ＢとしてＺｒ、Ｔｉ、Ｔａ、Ｎｂ、Ｍｇ、Ｍｎ、Ｆｅ、Ｚｎ、Ｗのうち少なくとも1種以上を含むものであってもよい。あるいは、化学式が（Ｂｉ_２Ｏ_２）（Ａ_ｍ−１Ｂ_ｍＯ_３ｍ＋１）（Ｍ＝１，２，３，４，５）で表され、それぞれＡとしてＢａ、Ｓｒ、Ｐｂ、Ｃａ、Ｋ、Ｂｉのうち少なくとも1種以上、ＢとしてＮｂ、Ｔａ、Ｔｉ、Ｗの少なくとも1種以上を含むものであってもよい。あるいは、Ｔａ_２Ｏ_５、ＺｒＯ_２、ＴｉＯ_２、ＨｆＯ_２、ＳｉＯ_２、Ａｌ_２Ｏ_３、Ｓｉ_３Ｎ_４またはそれらの固溶体であってもよい。また、薄膜キャパシタの第３、第６、第７の実施の形態は、その基となる薄膜キャパシタとして薄膜キャパシタの第２の実施の形態を例に説明されているが、基となる薄膜キャパシタとしては、薄膜キャパシタの第２の実施の形態に限られず、薄膜キャパシタの第１、第４の実施の形態も同様に用いられる。
【００３７】
【発明の効果】
以上説明したように、本発明の薄膜キャパシタは、キャパシタ部と接続端子部との間に空隙を設け、あるいはその空隙に低弾性率材料を充填するものであるから、薄膜キャパシタが変形しても、変形による応力を吸収することが可能である。したがって、本発明によれば、内蔵あるいは実装した薄膜キャパシタが変形しても電極の開放や短絡による不良の発生が防止され、また、薄膜キャパシタの容量絶縁膜が絶縁破壊に至るまでの期間が長く、長寿命である、信頼性の高い配線基板および半導体集積回路を提供することが可能である。
また、本発明の薄膜キャパシタを内蔵した多層配線基板は、その内部に薄膜キャパシタを内蔵することにより、多層配線基板上のキャパシタ実装面積を不要とするものであるから、基板面積の縮小を可能にする。
また、本発明の薄膜キャパシタを搭載した半導体集積回路は、搭載された薄膜キャパシタの２端子が電源線と接地線に接続され、デカップリングキャパシタとして作用するものであるから、自身の電源ノイズを小さくするとともに、本発明の薄膜キャパシタおよびそれを搭載した半導体集積回路を用いた電子機器やシステムの低ノイズかつ高速な動作を可能にする。
【図面の簡単な説明】
【図１】本発明の薄膜キャパシタの第１の実施の形態を示す断面図。
【図２】本発明の薄膜キャパシタの第２の実施の形態を示す平面図〔（ａ）〕と断面図〔（ｂ）〕。
【図３】図２の薄膜キャパシタを搭載した配線基板の断面図。
【図４】図２の薄膜キャパシタを搭載した半導体集積回路の断面図。
【図５】本発明の薄膜キャパシタの第２の実施の形態の変形例を示す平面図。
【図６】本発明の薄膜キャパシタの第３の実施の形態を示す断面図。
【図７】本発明の薄膜キャパシタの第４の実施の形態を示す断面図。
【図８】本発明の薄膜キャパシタの第５の実施の形態を示す断面図。
【図９】本発明の薄膜キャパシタの第６の実施の形態を示す断面図。
【図１０】本発明の薄膜キャパシタの第７の実施の形態を示す断面図。
【図１１】本発明の薄膜キャパシタ内蔵配線基板の断面図。
【図１２】本発明の薄膜キャパシタ搭載半導体集積回路の断面図。
【図１３】比較例の薄膜キャパシタの断面図。
【図１４】比較例の薄膜キャパシタを搭載した配線基板の断面図。
【図１５】本発明と比較例との薄膜キャパシタの配線基板内に内蔵したときの容量値の分布図。
【図１６】従来の技術の薄膜キャパシタの断面図。
【符号の説明】
１０１基材
１０２下部電極
１０２ｂ外部接続電極受け
１０３容量絶縁膜
１０４上部電極
１０５層間絶縁膜
１０６、１０７外部接続電極
１０８空隙
１０９低弾性率材料
１１０圧力依存導電率材料
１１１、１１２電極ギャップ
１２２、１２４接続端子部
１２３キャパシタ部
２０１コア層
２０２配線層
２０３プリプレグ層
２０４貫通スルーホール
２０５薄膜キャパシタ
２０６配線パターン
２０７Ｃｕめっき層
３０１層間絶縁膜
３０２電極パッド
３０４ＭＯＳトランジスタ
３０５薄膜キャパシタ
３０６半導体集積回路
３０７ビアホール
３０８はんだボール
４０１、４０２クラック
５０２、５０２ｂ、５０３コンタクト開口部
８０１基材
８０２下部電極
８０２ｂ外部接続電極受け
８０３容量絶縁膜
８０４上部電極
８０５層間絶縁膜
８０６、８０７外部接続電極
８２２、８２４接続端子部
８２３キャパシタ部[0001]
[Industrial application fields]
The present invention relates to a thin film capacitor formed on a base material, a multilayer wiring board in which the thin film capacitor is built, and a semiconductor integrated circuit on which the thin film capacitor is mounted.
[0002]
[Prior art]
As electronic devices are made smaller and thinner, capacitors that are passive elements are also becoming smaller and thinner. Multi-layer ceramic capacitors have been developed with small size from 0603 size (0.6mm x 0.3mm) to 0402 size (0.4mm x 0.2mm), but the handling difficulties during mounting are increasing. It is said that further downsizing is difficult. In addition, the multilayer ceramic capacitor has a multilayer structure, so that the resonance frequency is up to about several hundred MHz, and it is difficult to correspond to a high-speed / high-frequency system of GHz or higher.
[0003]
On the other hand, a thin film capacitor in which a lower electrode, a capacitive insulating film, and an upper electrode are laminated on a substrate has a resonance frequency of several GHz or more, and a capacitor necessary for a high-speed / high-frequency system can be realized. Especially (Ba, Sr) TiO₃And Pb (Zr, Ti) O₃The perovskite type oxide thin film represented by (1) has a high relative dielectric constant of 100 or more, and a high-capacity density thin film capacitor can be produced on a limited substrate area. In recent years, ZrO₂, HfO₂Or TiO₂Alternatively, thin films of these solid solutions also have a relative dielectric constant of around 15 compared to perovskite oxide thin films, but can be formed at a low physical temperature of about 10 nm and at a low temperature of 400 ° C. or less. It is attracting attention as a capacitive insulating film for capacitors.
[0004]
As a thin film capacitor formed on a substrate having a characteristic structure, there is a thin film capacitor disclosed in JP-A-6-325969. According to the publication, when forming a thin film capacitor having a thin capacitive insulating film on a substrate having irregularities or defects on the surface, a gap is provided between the substrate and the capacitor portion, and irregularities or defects on the substrate are formed. Thus, the capacitor is prevented from being short-circuited. Similarly, Japanese Patent Laid-Open No. 9-181363 discloses a structure in which a gap is provided between a capacitor and a base material. Further, JP-A-7-245233 discloses that a capacitor is formed by laminating a lower electrode, a capacitor insulating film, an upper electrode, and an external connection electrode of the upper electrode on the surface side of the substrate, and a through-hole provided in the substrate. A thin film capacitor in which an external connection electrode of a lower electrode is drawn through a through hole is disclosed.
[0005]
Here, in an actual electronic device, in order to reduce the area of a mounting substrate such as a mother board, a method of incorporating passive elements such as capacitors and resistors and inductors in a multilayer wiring substrate has been proposed. For example, Japanese Patent Application Laid-Open No. 11-126978 discloses a technique in which a gap is provided in a multilayer wiring board, and electronic elements such as capacitors and resistors are built in the gap. Japanese Laid-Open Patent Publication No. 2001-168534 discloses a multilayer wiring board in which a built-in passive element is connected to a wiring layer using a through-through hole. The capacitors built in these wiring boards are conventional multilayer ceramic capacitors or thin film capacitors obtained by simply laminating thin films.
[0006]
Also, in LSI (Large Scale Integrated Circuit), the operating frequency is in the order of several hundred MHz to GHz, and the clock rise time has become very short. A voltage drop occurs due to the parasitic resistance and the parasitic inductance present in the circuit, and the accompanying malfunction is a problem. In order to reduce this voltage drop, conventionally, a multilayer ceramic capacitor was mounted as a decoupling capacitor in the vicinity of the LSI, thereby reducing noise.
[0007]
[Problems to be solved by the invention]
  FIG. 16 shows a cross-sectional structure of a conventional thin film capacitor formed on a substrate. A capacitor portion 823 in which a lower electrode 802, a capacitor insulating film 803, and an upper electrode 804 are stacked on a base material 801, and a connection terminal portion 822 in which external connection electrodes 807 and 806 are in contact with the lower electrode 802 or the upper electrode 804, 824 includes a thin film capacitor.Connecting terminalThe space between the parts 822 and 824 is SiO.₂, Interlayer insulation film using BPSG (boro-phospho silicate glass), NSG (non-doped silicate glass), or insulating resin such as polyimide or epoxy8The thin film capacitor is integrally fixed to the rigid. When such a conventional thin film capacitor is mounted on a multilayer wiring board or LSI in which wiring exists, the thin film capacitor bends due to a step in the wiring, stress is concentrated on the capacitor portion or wiring, and the capacitor is short-circuited or opened. It became clear as a result of inventors' earnest research.
[0008]
In the multilayer wiring board disclosed in Japanese Patent Laid-Open No. 11-126978, electrical elements are built in the internal gaps, but the deformation of the electrical elements mounted on the wiring step due to the pressure at the time of mounting is considered. Not. Further, in the multilayer wiring board disclosed in Japanese Patent Laid-Open No. 2001-168534, the stress concentration on the thin film capacitor built in the recess is not taken into consideration. Similarly, the thin film capacitor disclosed in Japanese Patent Application Laid-Open No. 7-245233 has a rigid structure and does not have means for absorbing stress generated during deformation. For example, the capacitor insulating film is disconnected and the lower electrode and the upper electrode are disconnected. Problems such as short circuit may occur. On the other hand, a thin film capacitor disclosed in Japanese Patent Laid-Open Nos. 6-325969 and 9-181363 has a void in the base material. As a result, the lower electrode and the capacitor insulating film are deformed and embedded, resulting in defects due to short-circuiting or opening of the electrodes. Similar defects are likely to occur due to capacitor deformation when mounted on an LSI.
[0009]
The present invention has been made in view of the above problems, and its purpose is firstly to deform a thin film capacitor caused by a wiring step when a thin film capacitor is built in or mounted on a multilayer wiring board or LSI. Secondly, it is necessary to provide a thin film capacitor that avoids defects due to short-circuiting and opening caused by the capacitor, and whose initial characteristics immediately after fabrication of the capacitor do not change even after mounting on a multilayer wiring board or LSI. It is to provide a multilayer wiring board or a semiconductor integrated circuit on which a highly efficient thin film capacitor is mounted. Third, it is to provide an electronic device system including such a multilayer wiring board and a semiconductor integrated circuit.
[0010]
[Means for Solving the Problems]
  In order to achieve the above object, according to the present invention, a lower electrode is formed on a substrate,A capacitive insulating film is formed on a partial region of the lower electrode, an upper electrode is formed on a partial region of the capacitive insulating film, and an interlayer insulating film covering the lower electrode, the capacitive insulating film, and the upper electrode is provided. A thin film capacitor formed and provided with a lower connection electrode and an upper connection electrode respectively connected to the lower electrode and the upper electrode through vias provided in the interlayer insulating film, wherein the upper connection electrode A gap is provided from the surface side in a part of the interlayer insulating film formed above the upper electrode and between the upper connection electrode and the lower connection electrode.A thin film capacitor is provided.
[0011]
  In order to achieve the above object, according to the present invention, a lower electrode is formed on a substrate,A capacitive insulating film is formed on a partial region of the lower electrode, an upper electrode is formed on a partial region of the capacitive insulating film, and an interlayer insulating film covering the lower electrode, the capacitive insulating film, and the upper electrode is provided. A lower connection electrode and an upper connection electrode are provided and connected to the lower electrode and the upper electrode through vias provided in the interlayer insulating film, respectively, and the upper connection electrode is formed on the capacitor insulating film. A thin-film capacitor extending to a non-existing region, wherein a first gap is provided from a surface side in a part of the interlayer insulating film between the capacitive insulating film and the lower connection electrode, and the upper connection electrode A second gap is provided from the surface side in a part of the interlayer insulating film in the extending region, and the upper connection electrode extends along the side and bottom surfaces of the second gap. So that it is not filled completely And areA thin film capacitor is provided.
  And preferably,The gap reaches the surface of the lower electrode, the exposed gap of the lower electrode is provided, or the second gap reaches the surface of the substrate, and the upper connection electrode is connected to the side surface of the interlayer insulating film. It is provided so as not to completely fill the second gap along the bottom surface of the base material. Preferably, the thickness of the base material is half or less of the entire thickness of the thin film capacitor, or the base material is a flexible material.
[0012]
In order to achieve the above object, according to the present invention, the thin film capacitor is embedded in a resin substrate, and the lower connection electrode of the thin film capacitor is formed in a through hole penetrating the lower connection electrode or the lower connection electrode. Built-in thin film capacitor, wherein the thin film capacitor is drawn out through a via hole reaching the upper connection electrode of the thin film capacitor, and is pulled out through a through hole penetrating the upper connection electrode or a via hole reaching the upper connection electrode A wiring board is provided.
[0013]
In order to achieve the above object, according to the present invention, there is provided a semiconductor integrated circuit having the above thin film capacitor mounted thereon, the electrode pad formed on the surface thereof having a lower connection electrode and an upper connection electrode of the thin film capacitor. A semiconductor integrated circuit having a thin film capacitor mounted thereon is provided.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
  Next, embodiments of the present invention will be described in detail with reference to the drawings.
  FIG. 1 is a cross-sectional view showing a first embodiment of a thin film capacitor of the present invention. A capacitor portion 123 in which a lower electrode 102, a capacitor insulating film 103, and an upper electrode 104 are laminated on a base material 101 made of resin or metal and having a thickness of about 50 μm, and the upper electrode 104 and the lower portion are interposed via an interlayer insulating film 105. A thin film capacitor is configured with connection terminal portions 124 and 122 where external connection electrodes 106 and 107 are connected to the electrodes 102 respectively. Between the capacitor part 123 and the connection terminal parts 124 and 122Interlayer insulating film 105There is a void 108. The gap 108 is provided in order to absorb stress generated by deformation of the base material 101 and prevent the lower electrode 102, the capacitor insulating film 103, and the upper electrode 104 from being damaged. The external connection electrodes 106 and 107 desirably have a sufficiently thick film thickness of 10 μm or more in order to reduce the connection resistance, and the material is preferably composed mainly of Cu having a low resistivity. In addition, the capacitor insulating film 103 has excellent step coverage such as a CVD method or a sol-gel method so that the end portion of the lower electrode 102 can be sufficiently covered to prevent an electrical short circuit between the lower electrode 102 and the upper electrode 104. It is desirable that the film is produced by a film forming method.
[0015]
Next, a case where a polyimide film is used as the base material 101 in the thin film capacitor manufacturing process of the first embodiment will be described. First, a TiN / Mo / Ti laminated film was deposited as a lower electrode 102 on a commercially available polyimide film by DC sputtering, and then a desired pattern was formed by photolithography and wet etching. On top of that, as the capacitor insulating film 103, Al is formed at a film forming temperature of 300 ° C. by CVD.₂O₃After forming a thin film, it was processed into a desired shape by a photolithography method and an IBE (ion beam etching) method. Further, after depositing an Au / TiN laminated film as the upper electrode 104 by DC sputtering, a desired pattern was formed by photolithography and wet etching. Next, a photosensitive polyimide resin was applied as the interlayer insulating film 105, and then a desired pattern was formed by photolithography. Thereafter, a Cu / Ti laminated film was deposited on the entire surface by DC sputtering. Next, a resist film having an external connection electrode-shaped opening to be formed by photolithography is formed, and Cu is formed in a thickness of 12 μm by electrolytic plating using the Cu / Ti film as a power feeding layer in the opening. External connection electrodes 106 and 107 were used. Finally, after removing the resist film, the Cu / Ti laminated film exposed in the region other than the external connection electrodes 106 and 107 is removed by a wet etching method to manufacture the thin film capacitor according to the present embodiment shown in FIG. The process was completed. Although FIG. 1 shows a structure in which there is no interlayer insulating film in the gap portion, if it is within a range where sufficient stress relaxation can be obtained, one layer of the interlayer insulating film is directly above the lower electrode 102 and the upper electrode 104 in the gap. The part may remain.
[0016]
FIGS. 2A and 2B are a plan view and a cross-sectional view showing a second embodiment of the thin film capacitor of the present invention. 2, parts that are the same as the parts of the first embodiment shown in FIG. 1 are given the same reference numerals, and redundant descriptions are omitted. The thin film capacitor of the present embodiment is different from the thin film capacitor of the first embodiment shown in FIG. 1 in that the upper electrode 104 is formed only on the capacitive insulating film 103, and the external connection electrode on the upper electrode side. 106 extends from the connection terminal portion 124 on the upper electrode side to the capacitor portion 123, and is connected to the upper electrode 104 through an opening formed in the interlayer insulating film 105 of the capacitor portion 123. In this manner, by forming the upper electrode 104 only on the capacitor insulating film 103, the capacitor insulating film 103 does not need to cover the end portion of the lower electrode 102. Therefore, in addition to the CVD method and the sol-gel method, a sputtering method, etc. It is possible to produce the film by a film forming method having a poor step coverage. Further, an external connection electrode receiver 102b made of the same material as that of the lower electrode 102 exists between the external connection electrode 106 and the substrate 101. The external connection electrode receiver 102b is connected to the external connection electrode 106 and the base electrode 101. The contact layer may be omitted if the contact layer is a simple contact layer for contacting the material 101 and the external connection electrode 106 is in contact with the substrate 101 even if it is in direct contact.
[0017]
2A, 502, 502 b, and 503 obtain external connection electrode contacts to the lower electrode 102, the external connection electrode receiver 102 b, and the upper electrode 104 in the connection terminal portions 122 and 124 and the capacitor portion 123, respectively. Therefore, it is a contact opening formed in the interlayer insulating film 105. A gap 108 exists between the capacitor portion 123 and the connection terminal portions 124 and 122 via the interlayer insulating film 105, as in the first embodiment.
[0018]
  Next, a fabrication process of the thin film capacitor of the second embodimentTheThe case where a polyimide film is used as the substrate 101 will be described. First, a commercially available polyimide film is used, and a Pt / Ti / Mo / Ti laminated film is deposited thereon as the lower electrode 102 by DC sputtering, and a film forming temperature is deposited thereon by rf sputtering as the capacitive insulating film 103. SrTiO at 350 ° C₃A thin film was formed, a Pt film was deposited as the upper electrode 104 by DC sputtering, and a desired pattern was sequentially formed by photolithography and wet etching. Next, a photosensitive polyimide resin was applied as the interlayer insulating film 105, and then a desired pattern was formed by photolithography. Thereafter, a Cu / Ti laminated film was deposited on the entire surface by DC sputtering. Next, a resist film having an external connection electrode-shaped opening to be formed by photolithography is formed on the capacitor portion 123 and the connection terminal portions 124 and 122, and electrolytic plating is performed using the Cu / Ti laminated film as a power feeding layer in the opening. Cu was deposited to a thickness of 12 μm by the method. Next, after removing the resist film, the exposed Cu / Ti laminated film was removed by a wet etching method. Next, the gap between the capacitor portion 123 and the connection terminal portion 122 is covered with a resist film, and the Cu layer formed on the capacitor portion 123 and the Cu layer formed on the connection terminal portion 124 are connected using a sputtering method. A metal layer was formed. Finally, the resist film was removed, and the manufacturing process of the thin film capacitor according to the present embodiment shown in FIG. 2 was completed. In the above-described manufacturing process, by selecting various metals of the metal layer to be finally formed, there is an advantage that a metal other than Cu can be selected as the uppermost metal of the external connection electrode. As a method of forming a metal layer for connecting the Cu layer formed in the capacitor portion 123 and the Cu layer formed in the connection terminal portion 124, the Cu / Ti laminated film of this portion used as a power feeding layer is left without being removed. There is also a method to use. In this case, there is an advantage that the last metal layer deposition step can be omitted. Further, as a method of forming a metal layer for connecting the Cu layer formed on the capacitor portion 123 and the Cu layer formed on the connection terminal portion 124, a Cu plating layer is formed on the capacitor portion 123 and the connection terminal portions 122 and 124. At this time, a method of forming a Cu plating layer between the capacitor portion 123 and the connection terminal portion 124 and processing it into a metal layer having a void inside by an etching method is also conceivable, but it is difficult to control the thickness of the metal layer. Inferior in productivity. Note that FIG. 2 shows a structure without an interlayer insulating film in the gap, but as in the first embodiment, the lower electrode 102 and the gap in the gap are within the range where sufficient stress relaxation can be obtained. A part of the interlayer insulating film may remain directly on the external connection electrode 106.
[0019]
In the thin film capacitor manufacturing method of the present embodiment, unlike the first embodiment, the rf sputtering method with poor step coverage can be used as the method of forming the capacitive insulating film 103.
[0020]
FIG. 3 shows a state in which the thin film capacitor of the present embodiment shown in FIG. 2 is mounted on a wiring board having a wiring step. A wiring layer 202 having a thickness of about 24 to 30 μm is formed on the core layer 201 of the wiring board, and a step in the thickness of the wiring layer is generated between the core layer 201 and the wiring layer 202. The thin film capacitor 205 of the present invention is mounted on the wiring layer 202 using an adhesive such as an epoxy resin. When the thin film capacitor 205 is pressed from above, the capacitor portion 123 of the thin film capacitor 205 is deformed in a convex shape downward. However, since the gap 108 existing between the capacitor portion 123 and the connection terminal portions 122 and 124 absorbs the stress generated by the deformation, the electrode film (lower electrode or upper electrode) is disconnected, or the capacitor insulating film There will be no cracks.
[0021]
FIG. 4 shows a state in which the thin film capacitor of the present embodiment shown in FIG. 2 is turned upside down and its external connection electrodes are connected to electrode pads on the semiconductor integrated circuit by solder balls. After the external connection electrodes 106 and 107 of the thin film capacitor 305 are connected to the electrode pads 302 by the solder balls 308, the thin film capacitor 305 is deformed downward (convex upward in the original vertical direction of the thin film capacitor), but the gap 108 Therefore, the electrode film (lower electrode or upper electrode) is not disconnected, and the capacitive insulating film is not cracked.
[0022]
FIGS. 5A and 5B are plan views showing a modification of the thin film capacitor of the present embodiment. In FIG. 5, parts that are the same as the parts shown in FIG. 2A are given the same reference numerals, and redundant descriptions are omitted. The thin film capacitor shown in FIG. 5A has a structure in which the interlayer insulating film 105 is interdigitated between the capacitor portion 123 and the connection terminal portions 124 and 122 in the region of the gap 108. Further, in the thin film capacitor shown in FIG. 5B, the interlayer insulating film 105 is formed in a sawtooth shape between the capacitor portion 123 and the connection terminal portions 124 and 122, or 90 ° as compared with the case of FIG. It has a structure like a comb shape in different directions. Thus, it is not always necessary to completely remove the interlayer insulating film 105 from the gap 108, and the gap 108 only needs to have a structure that can absorb or reduce stress due to deformation. The structure of the thin film capacitor shown in FIGS. 5A and 5B has the advantage that the strength in the torsional direction is increased and the handling in manufacturing becomes easier as compared with the structure of the thin film capacitor shown in FIG.
[0023]
FIG. 6 is a cross-sectional view showing a third embodiment of the thin film capacitor of the present invention. 6, parts that are the same as the parts of the second embodiment shown in FIG. 2 are given the same reference numerals, and redundant descriptions are omitted. The thin film capacitor of the present embodiment is different from the thin film capacitor of the second embodiment shown in FIG. 2 in that the gap between the capacitor portion 123 and the connection terminal portions 122 and 124 is not an air gap but has a small elastic modulus. This is that the material is completely or partially filled with a low elastic modulus material 109 such as rubber. The characteristic required for the low elastic modulus material 109 is that it has a Young's modulus (elastic modulus) lower than that of the interlayer insulating film 105. If the Young's modulus of the low elastic modulus material 109 is lower than the Young's modulus of the interlayer insulating film 105, when the thin film capacitor is deformed and stress is applied in the left-right direction on the paper surface, the interlayer insulating film 105 is not distorted and the low elastic modulus material 109 is not distorted. Can be distorted to absorb the stress. As in the first embodiment, the external connection electrode desirably has a sufficiently thick film thickness of 10 μm or more in order to reduce the connection resistance, and preferably contains Cu having a low resistivity as a main component. The thin film capacitor of the present embodiment shown in FIG. 6 absorbs the stress caused by the deformation and shorts or opens the electrodes, similarly to the thin film capacitors of the first and second embodiments shown in FIGS. It is possible to prevent the failure due to. The thin film capacitor of the present embodiment shown in FIG. 6 further has a low elastic modulus material between the capacitor portion 123 and the connection terminal portions 122 and 124 as compared with the thin film capacitor of the second embodiment shown in FIG. Since it is filled with 109, bending during handling of the thin film capacitor is prevented, handling becomes easy, and the manufacturing yield is improved.
[0024]
FIG. 7 is a cross-sectional view showing a fourth embodiment of the thin film capacitor of the present invention. In FIG. 7, parts that are the same as the parts of the second embodiment shown in FIG. 2 are given the same reference numerals, and redundant descriptions are omitted. The thin film capacitor of the present embodiment is different from the thin film capacitor of the second embodiment shown in FIG. 2 in that the connection terminal portion of the upper electrode 104 does not exist. As described above, when the connection terminal portion of the upper electrode 104 is eliminated, the external connection electrode 106 connected to the upper electrode 104 is drawn right above the capacitor insulating film 103. Although there is a demerit that an inexpensive through hole cannot be used for electrical connection, the external connection electrode 106 is not extended in the lateral direction, so the second embodiment shown in FIG. Compared with this thin film capacitor, there are the merit that the shape of the thin film capacitor is small and the high frequency characteristic is improved. Further, via connection by a build-up method and connection by a solder ball are possible, and there is an effect that the mounting area of the capacitor is reduced.
[0025]
FIG. 8 is a cross-sectional view showing a fifth embodiment of the thin film capacitor of the present invention. In FIG. 8, parts that are the same as the parts of the fourth embodiment shown in FIG. 7 are given the same reference numerals, and redundant descriptions are omitted. The thin film capacitor of this embodiment is different from the thin film capacitor of the fourth embodiment shown in FIG. 7 in that the low elastic modulus material 109 is completely between the capacitor portion 123 and the connection terminal portion 122, or It is that it is partially filled. The thin film capacitor shown in FIG. 8 has the effects of preventing bending during handling of the thin film capacitor, facilitating handling, and improving the manufacturing yield, similarly to the thin film capacitor shown in FIG.
[0026]
FIG. 9 is a sectional view showing a sixth embodiment of the thin film capacitor of the present invention. In FIG. 9, parts that are the same as the parts of the second embodiment shown in FIG. 2 are given the same reference numerals, and redundant descriptions are omitted. The thin film capacitor of this embodiment is different from the thin film capacitor of the second embodiment shown in FIG. 2 in that an electrode gap 111 is formed in the lower electrode 101 in the gap between the capacitor portion 123 and the connection terminal portion 122. The electrode gap 112 exists in the external connection electrode 106 in the gap between the capacitor portion 123 and the connection terminal portion 124, and the compression is applied when compressive stress is applied so as to satisfy at least the electrode gaps 111 and 112. The material is filled with a material 110 (hereinafter referred to as “pressure-dependent conductivity material”) whose conductivity in the direction increases as the dimension in the direction of stress decreases. The pressure-dependent conductivity material 110 has low conductivity in the direction when no stress is applied in the left-right direction on the paper surface, and increases in that direction when compressive stress is applied in the left-right direction on the paper surface. Such a pressure-dependent conductivity material can be produced, for example, by dispersing a conductive material such as metal particles inside a resin having a low elastic modulus.
[0027]
FIG. 10 is a sectional view showing a seventh embodiment of the thin film capacitor of the present invention. 10, parts that are the same as the parts of the sixth embodiment shown in FIG. 9 are given the same reference numerals, and redundant descriptions will be omitted. The thin film capacitor of the present embodiment is different from the thin film capacitor of the sixth embodiment shown in FIG. 7 in that the gap is completely formed on the pressure-dependent conductive material 110 satisfying at least the electrode gaps 111 and 112. Alternatively, the low elastic modulus material 109 is formed so as to be partially filled. The effect of using the low elastic modulus material 109 in the thin film capacitor of the present embodiment is the same as the effect of using the low elastic modulus material in the thin film capacitor shown in FIGS. In the seventh and eighth embodiments as well, the external connection electrode has a sufficiently thick film thickness of 10 μm or more in order to reduce the connection resistance, as in the case of the thin film capacitor of the first embodiment. In addition, it is desirable that Cu having a low resistivity is a main component.
[0028]
The thin film capacitors shown in FIGS. 9 and 10 have a high resistance due to the pressure-dependent conductivity material 110 in the electrode gaps 111 and 112 immediately after fabrication, and cannot be evaluated for characteristics. However, for example, when stress is applied such that the thin film capacitor as shown in FIG. 3 has a downwardly convex shape, the pressure-dependent conductivity material 110 is subjected to compressive stress in the left-right direction of the paper, and as a result, is dispersed in the resin. The electrical conductivity of the pressure-dependent electrical conductivity material 110 increases as a result of the contact of the electrically conductive materials, and the lower electrode 102 and upper electrode 104 of the capacitor portion 123 and the external connection electrodes 107 and 106 of the connection terminal portions 122 and 124 Are electrically connected to each other, and can operate as a thin film capacitor. Since the pressure-dependent conductivity material 110 also plays a role of absorbing stress by being deformed, compared to the case where an electrode film is present as in the second embodiment shown in FIG. 2, the applied stress to the capacitive insulating film Becomes smaller, and a capacitance value as designed can be obtained with a high yield.
[0029]
FIG. 11 is a cross-sectional view of a multilayer wiring board incorporating the thin film capacitor of the present invention. The multilayer wiring board with a built-in thin film capacitor shown in FIG. 11 is manufactured as follows. After mounting the thin film capacitor 205 of the present invention on the wiring layer 202 formed on the core layer 201, the core layer 201 is sandwiched between the prepreg layers 203 and integrated by pressing. Thereafter, a through-through hole 204 that penetrates the substrate is provided so as to penetrate the external connection electrodes 106 and 107 of the thin film capacitor 205, and a wiring pattern 206 is formed on the surface of the prepreg layer 203, and an inner wall surface of the through-through hole 204 is formed. Then, a Cu plating layer 207 for connecting the wiring pattern 206 to the external connection electrodes 106 and 107 of the thin film capacitor 205 and the wiring layer 202 is formed.
[0030]
Although the thin film capacitor is deformed downward by pressing during integration, the gap 108 absorbs the stress generated by the deformation, so that the electrode layer is disconnected or the capacitor insulating film is cracked. A good capacitance value can be obtained even after the multilayer wiring board is built.
In the above description, the external connection electrode of the thin film capacitor is connected to the wiring pattern through the through-through hole. However, a via hole reaching the external connection electrode is formed and connected to the wiring pattern through the via hole. You may be made to do. Moreover, the thin film capacitors of all the embodiments of the present invention can be used in the capacitor built-in wiring board of the present invention.
[0031]
FIG. 12 is a cross-sectional view of a semiconductor integrated circuit on which the thin film capacitor of the present invention is mounted. The semiconductor integrated circuit of the present invention relates to an example in which the thin film capacitor of the present invention is mounted upside down using solder balls on the uppermost wiring layer of the semiconductor integrated circuit. The thin film capacitor 305 is mounted on the electrode pad 302 of the uppermost wiring layer of the semiconductor integrated circuit 306 using solder balls 308, one electrode (upper electrode) serving as a power supply line and the other electrode (lower electrode) serving as a power supply line. Connected to the ground wire. The power supply line is also connected to the drain electrode of the MOS transistor 304 through a Cu plating layer deposited on the inner wall of the via hole 307 formed in the interlayer insulating film 301. Therefore, the thin film capacitor 305 functions as a decoupling capacitor that reduces noise of the MOS transistor 304 and the external power supply.
[0032]
The thin film capacitor 305 is deformed in a convex shape in FIG. 12 (convex upward in the original vertical direction of the thin film capacitor) due to the pressing pressure at the time of mounting on the semiconductor integrated circuit 306, but since the air gap 108 exists, The capacitor insulating film is not cracked, and as a result, a failure such as a short circuit between the power supply line and the ground line of the semiconductor integrated circuit 306 does not occur.
In the above description, the external connection electrode of the thin film capacitor is connected to the electrode pad via the solder ball, but may be connected to the electrode pad via a stud bump. In the thin film capacitor-mounted semiconductor integrated circuit of the present invention, the thin film capacitors of the first to fifth embodiments of the present invention are preferably used.
[0033]
[Comparative Example]
A thin film capacitor was fabricated based on the conventional technology. FIG. 13 is a cross-sectional view of a thin film capacitor fabricated in this comparative example. In FIG. 13, parts that are the same as the parts of the second embodiment shown in FIG. The thin film capacitor of the present embodiment is different from the thin film capacitor of the second embodiment shown in FIG. 2 in that there is no gap between the capacitor portion 123 and the connection terminal portions 122 and 124, and the capacitor portion 123 The connection terminal portions 122 and 124 are rigidly fixed by the interlayer insulating film 105. Also in the thin film capacitor having such a structure, a capacitance value as designed was obtained immediately after fabrication, as in the thin film capacitors of all the embodiments of the present invention. However, as in the case of the wiring board with a built-in thin film capacitor shown in FIG. 11, when this thin film capacitor is built in the multilayer wiring board and the characteristics of the thin film capacitor are evaluated using the external connection electrodes, many open or short-circuited A defect occurred.
[0034]
In order to investigate the cause, the cross section of the thin film capacitor was observed, and as shown in FIG. 14, it was found that defects occurred in the interlayer insulating film, the lower electrode, and the capacitor insulating film. That is, since the wiring layer 202 has a step with respect to the core layer 201, the thin film capacitor is deformed downward by the pressing pressure when the thin film capacitor is mounted, and the capacitor portion 123 and the connection terminal portions 122 and 124 Cracks 401 were observed in the interlayer insulating film 105 between them. The crack 401 in the interlayer insulating film 105 reached the surface of the substrate 101 through the inside of the lower electrode 102, and disconnection was seen in the lower electrode 102. This is considered to be the reason why the thin film capacitor of this comparative example was defective due to opening after being built in the multilayer wiring board. Furthermore, cracks 402 were also observed in the capacitor insulating film 103. This is considered to be the cause of a failure due to a short circuit between the upper electrode and the lower electrode. These cracks occur because the capacitor portion 123 and the connection terminal portions 122 and 124 are rigidly fixed by the interlayer insulating film 105, and there is no layer that absorbs the stress generated by the deformation of the thin film capacitor.
[0035]
FIG. 15 shows variations in measured capacitance values when the thin film capacitor of the present invention and the thin film capacitor of the comparative example are incorporated in a multilayer wiring board. The designed value of the capacitance of the thin film capacitor is 1000 pF. When the thin film capacitor of the present invention is used, the target capacitance value is obtained with a yield of 75% or more, and no defect due to short circuit or open circuit occurs. On the other hand, when the thin film capacitor of the comparative example is used, the variation in capacitance value is large, and defects due to short circuit or open circuit occur at a rate of 15% or more.
[0036]
As described above, the present invention has been described based on the preferred embodiment. However, the thin film capacitor of the present invention, the semiconductor integrated circuit using the same, and the wiring board are not limited to the above-described embodiment. Thin film capacitors that have undergone various changes without departing from the scope of the present invention, semiconductor integrated circuits and wiring boards using the same are also included in the scope of the present invention. For example, the base material has been described mainly using resin, but any material can be used as long as it has a certain degree of elasticity and can be mounted on a multilayer wiring board or a semiconductor integrated device. May be. For example, a metal plate typified by SUS or Cu, a silicon substrate polished to a thickness of about 100 μm, or a sapphire substrate may be used. Moreover, although the example of rubber | gum was described as a low elastic modulus material, as long as it is a material with a small elastic modulus and the effect of stress relaxation, such as resin and silicone. Moreover, as a capacitive insulating film of a thin film capacitor, Ta₂O₅And SrTiO₃In the case of a thin film, a part or all of the chemical formula is ABO.₃And A as at least one of Ba, Sr, Pb, Ca, La, Li, and K, and B as Zr, Ti, Ta, Nb, Mg, Mn, Fe, Zn, and W, respectively. One or more types may be included. Alternatively, the chemical formula is (Bi₂O₂(A_m-1B_mO_{3m + 1}) (M = 1, 2, 3, 4, 5), wherein A is at least one of Ba, Sr, Pb, Ca, K, and Bi, and B is at least one of Nb, Ta, Ti, and W. One or more types may be included. Or Ta₂O₅, ZrO₂TiO₂, HfO₂, SiO₂, Al₂O₃, Si₃N₄Alternatively, a solid solution thereof may be used. Further, the third, sixth, and seventh embodiments of the thin film capacitor have been described by taking the second embodiment of the thin film capacitor as an example of the thin film capacitor that is the basis thereof. Is not limited to the second embodiment of the thin film capacitor, and the first and fourth embodiments of the thin film capacitor are also used in the same manner.
[0037]
【The invention's effect】
As described above, the thin film capacitor of the present invention has a gap between the capacitor portion and the connection terminal portion, or is filled with a low elastic modulus material, so that even if the thin film capacitor is deformed. It is possible to absorb stress due to deformation. Therefore, according to the present invention, even if the built-in or mounted thin film capacitor is deformed, a failure due to the opening or short-circuiting of the electrode is prevented, and the period until the capacitive insulating film of the thin film capacitor is broken down is increased. It is possible to provide a highly reliable wiring board and semiconductor integrated circuit having a long lifetime.
In addition, since the multilayer wiring board incorporating the thin film capacitor of the present invention eliminates the capacitor mounting area on the multilayer wiring board by incorporating the thin film capacitor therein, the substrate area can be reduced. To do.
In addition, the semiconductor integrated circuit equipped with the thin film capacitor of the present invention has its two terminals connected to the power supply line and the ground line and acts as a decoupling capacitor, so that its own power supply noise is reduced. In addition, low-noise and high-speed operation of an electronic device or system using the thin film capacitor of the present invention and a semiconductor integrated circuit on which the thin film capacitor is mounted is enabled.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a first embodiment of a thin film capacitor of the present invention.
FIG. 2 is a plan view (a) and a cross-sectional view (b) showing a second embodiment of a thin film capacitor of the present invention.
3 is a cross-sectional view of a wiring board on which the thin film capacitor of FIG. 2 is mounted.
4 is a cross-sectional view of a semiconductor integrated circuit on which the thin film capacitor of FIG. 2 is mounted.
FIG. 5 is a plan view showing a modification of the second embodiment of the thin film capacitor of the present invention.
FIG. 6 is a cross-sectional view showing a third embodiment of a thin film capacitor of the present invention.
FIG. 7 is a cross-sectional view showing a fourth embodiment of a thin film capacitor of the present invention.
FIG. 8 is a cross-sectional view showing a fifth embodiment of a thin film capacitor of the present invention.
FIG. 9 is a sectional view showing a sixth embodiment of a thin film capacitor of the present invention.
FIG. 10 is a cross-sectional view showing a seventh embodiment of a thin film capacitor of the present invention.
FIG. 11 is a cross-sectional view of a thin film capacitor built-in wiring board according to the present invention.
FIG. 12 is a cross-sectional view of a thin film capacitor-mounted semiconductor integrated circuit according to the present invention.
FIG. 13 is a cross-sectional view of a thin film capacitor of a comparative example.
FIG. 14 is a cross-sectional view of a wiring board on which a thin film capacitor of a comparative example is mounted.
FIG. 15 is a distribution diagram of capacitance values when the thin film capacitors of the present invention and a comparative example are built in a wiring board.
FIG. 16 is a cross-sectional view of a conventional thin film capacitor.
[Explanation of symbols]
101 Substrate
102 Lower electrode
102b External connection electrode holder
103 capacitive insulating film
104 Upper electrode
105 Interlayer insulation film
106,107 External connection electrode
108 gap
109 Low modulus material
110 Pressure-dependent conductivity material
111, 112 electrode gap
122,124 Connection terminal
123 Capacitor section
201 Core layer
202 Wiring layer
203 Prepreg layer
204 Through-hole
205 Thin film capacitors
206 Wiring pattern
207 Cu plating layer
301 Interlayer insulation film
302 Electrode pad
304 MOS transistor
305 Thin film capacitor
306 Semiconductor integrated circuit
307 Via hole
308 Solder ball
401, 402 crack
502, 502b, 503 Contact opening
801 base material
802 Lower electrode
802b External connection electrode holder
803 capacitive insulating film
804 Upper electrode
805 Interlayer insulating film
806, 807 External connection electrode
822, 824 connection terminal
823 Capacitor section

Claims

A lower electrode is formed on a substrate, a capacitive insulating film is formed on a partial region of the lower electrode, an upper electrode is formed on a partial region of the capacitive insulating film, and the capacitive insulation is formed between the lower electrode and the capacitive insulating film. An interlayer insulating film covering the film and the upper electrode is formed, and a lower connection electrode and an upper connection electrode connected to the lower electrode and the upper electrode through openings provided in the interlayer insulating film are provided. A thin film capacitor,
The thin film capacitor, wherein the upper connection electrode is formed above the upper electrode, and a gap is provided from a surface side in a part of the interlayer insulating film between the upper connection electrode and the lower connection electrode .

2. The thin film capacitor according to claim 1, wherein the gap reaches the surface of the lower electrode, and an exposed gap of the lower electrode is provided.

A lower electrode is formed on a substrate, a capacitive insulating film is formed on a partial region of the lower electrode, an upper electrode is formed on a partial region of the capacitive insulating film, and the capacitive insulation is formed between the lower electrode and the capacitive insulating film. An interlayer insulating film is formed to cover the film and the upper electrode, and a lower connection electrode and an upper connection electrode connected to the lower electrode and the upper electrode through openings provided in the interlayer insulating film, respectively, The upper connection electrode is a thin film capacitor extending to a region where the capacitive insulating film is not formed,
A part of the interlayer insulating film between the capacitive insulating film and the lower connection electrode is provided with a first gap from the surface side, and one of the interlayer insulating films in the region where the upper connection electrode extends. A second gap is provided on the surface side from the surface side, and the upper connection electrode is provided so as not to completely fill the second gap along the side and bottom surfaces of the second gap. Thin film capacitor.

4. The thin film capacitor according to claim 3, wherein the first gap reaches the surface of the lower electrode, and an exposed gap of the lower electrode is provided.

The second gap reaches the substrate surface, and the upper connection electrode is provided so as not to completely fill the second gap along the side surface of the interlayer insulating film and the bottom surface of the substrate. 4. The thin film capacitor according to claim 3, wherein

The first gap reaches the surface of the lower electrode, the exposed gap of the lower electrode is provided, the second gap reaches the surface of the base material, and the upper connection electrode is formed of the interlayer insulating film. 4. The thin film capacitor according to claim 3, wherein the second gap is provided so as not to completely fill the second gap along the side surface and the bottom surface of the base material.

7. The thin film capacitor according to claim 3, wherein a pseudo lower electrode made of the same material as the lower electrode is formed between the upper connection electrode and the base material.

Thin film capacitor according to any one of claims 1 to 7, characterized in that comb-like or sawtooth of the interlayer insulating film with a protrusion across the air gap is formed.

The gap is at least partially a thin film capacitor according to any one of claims 1 to 8, characterized in that it is filled with a low modulus of elasticity material having a lower Young's modulus than the interlayer insulating film.

The lower electrode under the gap, the lower electrode under the gap and the upper electrode under the gap, or the lower electrode under the gap and the upper connection electrode in the gap, There is a gap part from which they are removed, and a material whose conductivity in the direction of the applied compressive stress decreases and the conductivity in that direction increases when compressive stress is applied to at least the gap part. thin film capacitor according to any one of claims 1 to 9 as rates material "] is characterized in that it is filled.

11. The thin film capacitor according to claim 10, wherein a low elastic modulus material having a Young's modulus lower than that of the interlayer insulating film is formed on the pressure dependent conductivity material.

Thin film capacitor according to any one of claims 1 to 11, wherein the substrate is a flexible material.

Thin film capacitor according to any one of claims 1 to 12 is embedded in the resin substrate, pulled through a via hole lower connection electrode of the thin film capacitor reaches a through-hole or the lower connection electrode penetrating the lower connection electrode A wiring board having a built-in thin film capacitor, wherein the upper connection electrode of the thin film capacitor is led out through a through hole penetrating the upper connection electrode or a via hole reaching the upper connection electrode.

14. The wiring board with a built-in thin film capacitor according to claim 13 , wherein the thin film capacitor is fixed to a wiring layer of the resin substrate through an adhesive.

A semiconductor integrated circuit having a thin film capacitor according to any one of claims 1 to 12, the lower connection electrode and an upper connection electrode of the thin film capacitor electrode pads formed on its surface is connected A semiconductor integrated circuit equipped with a thin film capacitor.

16. The semiconductor integrated circuit having a thin film capacitor mounted thereon according to claim 15 , wherein the lower connection electrode and the upper connection electrode are connected to the electrode pad via solder balls or stud bumps.

Through the respective electrode pads, the one lower connection electrode and an upper connection electrode is electrically connected to the power source line, according to claim 15 or 16 other is characterized in that it is electrically connected to a ground wire A semiconductor integrated circuit equipped with the thin film capacitor described in 1.

Electronic device system with a wiring board or a semiconductor integrated circuit according to claims 13 17.