JP2004071589A

JP2004071589A - Thin film capacitor, wiring board containing it, semiconductor integrated circuit mounted with it, and electronic equipment system

Info

Publication number: JP2004071589A
Application number: JP2002224362A
Authority: JP
Inventors: Shintaro Yamamichi; 山道　新太郎; Toru Mori; 森　透; Akinobu Shibuya; 渋谷　明信
Original assignee: NEC Corp
Current assignee: NEC Corp
Priority date: 2002-08-01
Filing date: 2002-08-01
Publication date: 2004-03-04
Anticipated expiration: 2022-08-01
Also published as: JP3918675B2

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin film capacitor that is constituted so that its initial characteristics immediately after manufacturing may not change even after the capacitor is mounted on a multilayered wiring board or an LSI chip by avoiding a fault due to a short circuit or open circuit caused when the capacitor is deformed by a step in wiring at the time of containing or mounting the capacitor in or on the board or LSI chip, and to provide a multilayered wiring board or semiconductor integrated circuit mounted with the capacitor and an electronic equipment system containing the board or circuit. <P>SOLUTION: The thin film capacitor is provided with a capacitor section 123 in which a lower electrode 102 is formed on a substrate 101 and a dielectric thin film 103 and an upper electrode 104 are laminated upon a partial area of the electrode 102, a connecting terminal section 122 in which an external connecting electrode 107 is led out upward from the area of the electrode 102 in which the dielectric thin film 103 is not formed, and a connecting terminal section 124 in which an external connecting electrode 106 is led out upward from an external connecting electrode receiver 102b formed on the substrate 101. Between the capacitor section 123 and both connecting terminal sections 122 and 124, gaps 108 are provided. The electrode 106 is led out from the upper electrode 104 to the electrode receiver 102b and the stress formed by the deformation of the capacitor when the capacitor is contained/mounted is absorbed by the gaps 108. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【産業上の利用分野】
本発明は基材上に形成された薄膜キャパシタおよびその薄膜キャパシタを内蔵した多層配線基板さらにはその薄膜キャパシタを搭載した半導体集積回路に関するものである。
【０００２】
【従来の技術】
電子機器の小型化・薄型化に伴い、受動素子であるキャパシタも小型化・薄型化が進んでいる。積層セラミクスコンデンサでは０６０３サイズ（０．６ｍｍ×０．３ｍｍ）から０４０２サイズ（０．４ｍｍ×０．２ｍｍ）まで小型の製品が開発されているが、実装時の取り扱い上の困難さが増しており、これ以上の小型化は難しいとされている。また積層セラミクスコンデンサはその積層構造のために、共振周波数が数百ＭＨｚ程度までであり、ＧＨｚ以上の高速・高周波のシステムに対応させることは難しい。
【０００３】
一方、基材上に下部電極、容量絶縁膜、上部電極を積層した薄膜キャパシタは、共振周波数が数ＧＨｚ以上となり、高速・高周波システムに必要なキャパシタを実現することが可能である。特に（Ｂａ，Ｓｒ）ＴｉＯ_３やＰｂ（Ｚｒ，Ｔｉ）Ｏ_３に代表されるペロブスカイト型酸化物薄膜は１００以上の高い比誘電率を有し、限られた基材面積上に高容量密度の薄膜キャパシタを作製することができる。また近年、ＺｒＯ_２、ＨｆＯ_２あるいはＴｉＯ_２、あるいは、それらの固溶体の薄膜も、比誘電率は１５前後とペロブスカイト型酸化物薄膜に比べると小さいものの、物理膜厚を１０ｎｍ程度に薄く、かつ４００℃以下の低温で成膜できることから、薄膜キャパシタの容量絶縁膜として注目されている。
【０００４】
基材上に形成された薄膜キャパシタで特徴的な構造を有するものとして、特開平６−３２５９６９号公報に開示された薄膜キャパシタが挙げられる。同公報によれば、表面に凹凸部や欠陥のある基材上に薄い容量絶縁膜を有する薄膜キャパシタを形成する際、基材とキャパシタ部との間に空隙を設け、基材の凹凸や欠陥の影響が下部電極や容量絶縁膜に及ばないようにすることにより、キャパシタの短絡を防止している。同様にキャパシタと基材との間に空隙を設ける構造が特開平９−１８１３６３号公報に開示されている。さらに、特開平７−２４５２３３号公報には、基材の表面側に下部電極、容量絶縁膜、上部電極、上部電極の外部接続電極を積層してキャパシタを形成し、基材内に設けた貫通スルーホールを通して下部電極の外部接続電極を引き出した薄膜キャパシタが開示されている。
【０００５】
ここで、実際の電子機器において、マザーボード等の実装基板の面積を縮小するために、キャパシタをはじめ抵抗やインダクタなどの受動素子を多層配線基板に内蔵する方法が提案されている。例えば特開平１１−１２６９７８号公報には、多層配線基板内に空隙を設け、その空隙内にキャパシタや抵抗などの電子素子を内蔵する技術が開示されている。また特開２００１−１６８５３４号公報には、貫通スルーホールを用いて、内蔵した受動素子を配線層に接続させた多層配線基板が開示されている。これら配線基板に内蔵されるキャパシタは、従来の積層セラミクスコンデンサあるいは薄膜を単純に積層した薄膜キャパシタである。
【０００６】
またＬＳＩ（大規模集積回路）においては、その動作周波数が数百ＭＨｚからＧＨｚオーダーとなり、クロックの立ち上がり時間が非常に短くなってきたため、ＬＳＩに急激な負荷がかかると、電源とＬＳＩの配線間に存在する寄生抵抗と寄生インダクタンスにより電圧降下が生じ、それに伴う誤動作が問題となっている。この電圧降下を低減するために、デカップリングキャパシタとして、従来は積層セラミクスコンデンサをＬＳＩの近傍に実装し、それによってノイズ低減を図っていた。
【０００７】
【発明が解決しようとする課題】
図１６に、基材上に形成された従来の薄膜キャパシタの断面構造を示す。基材８０１上に下部電極８０２、容量絶縁膜８０３、上部電極８０４が積層されたキャパシタ部８２３と、下部電極８０２あるいは上部電極８０４と接触する外部接続電極８０７、８０６が存在する接続端子部８２２、８２４とから薄膜キャパシタが構成されているが、このキャパシタ部８２３と引き出し電極部８２２、８２４との間が、ＳｉＯ_２、ＢＰＳＧ（ｂｏｒｏ−ｐｈｏｓｐｈｏ　ｓｉｌｉｃａｔｅ　ｇｌａｓｓ）やＮＳＧ（ｎｏｎ−ｄｏｐｅｄ　ｓｉｌｉｃａｔｅ　ｇｌａｓｓ）、あるいは、ポリイミドやエポキシなどの絶縁樹脂を用いた層間絶縁膜１０５で埋め込まれ、薄膜キャパシタが一体的にリジットに固定されている。このような従来の薄膜キャパシタを、配線が存在する多層配線基板あるいはＬＳＩ上に搭載した場合、配線の段差によって薄膜キャパシタがたわみ、キャパシタ部や配線に応力が集中し、キャパシタが短絡状態または開放状態となってしまうということが、発明者の鋭意研究の結果、明らかとなった。
【０００８】
特開平１１−１２６９７８号公報に開示された多層配線基板では、内部の空隙に電気素子が内蔵されているが、配線段差上に搭載された電気素子の、搭載時の圧力による変形については考慮されていない。また、特開２００１−１６８５３４号公報に開示された多層配線基板においても、その内部のくぼみに内蔵された薄膜キャパシタへの応力集中は考慮されていない。同様に、特開平７−２４５２３３号公報に開示された薄膜キャパシタもリジッドな構造で、変形時に生じる応力を吸収する手段を有しないので、例えば容量絶縁膜が断線して下部電極と上部電極とが短絡してしまうなどの問題が発生し得る。一方、特開平６−３２５９６９号公報や特開平９−１８１３６３号公報に開示された、基材に空隙が存在する薄膜キャパシタは、キャパシタ上方からのプレス圧力を受けたときに、基材の空隙内部に下部電極や容量絶縁膜が変形して埋め込まれてしまい、結果として電極の短絡や開放による不良を引き起こしてしまう。ＬＳＩ上への搭載時にもキャパシタ変形による同様の不良が発生しやすい。
【０００９】
本発明は、上記課題に鑑みてなされたものであって、その目的は、第一に、多層配線基板やＬＳＩに薄膜キャパシタを内蔵・搭載する際に、配線の段差によって生じた薄膜キャパシタの変形が引き起こす短絡や開放による不良を回避し、キャパシタ作製直後の初期特性が、多層配線基板やＬＳＩへの搭載後も変化しないような薄膜キャパシタを提供することであり、第二に、そのような信頼性の高い薄膜キャパシタを搭載した多層配線基板や半導体集積回路を提供することである。第三に、そのような多層配線基板や半導体集積回路を含む電子機器システムを提供することである。
【００１０】
【課題を解決するための手段】
上記目的を達成するため、本発明によれば、基材上に、下部電極が形成され、該下部電極の一部領域上に誘電体薄膜および上部電極が積層されている薄膜キャパシタであって、前記下部電極の前記誘電体薄膜の形成されていない領域からその上方に向けて、前記下部電極に接続する下部接続電極が引き出され、前記誘電体薄膜の形成されている領域と前記下部接続電極が形成されている領域との間に前記下部電極の露出している領域が存在することを特徴とする薄膜キャパシタ、が提供される。
【００１１】
また、上記目的を達成するため、本発明によれば、基材上に、下部電極が形成され、該下部電極の一部領域上に誘電体薄膜および上部電極が積層されている薄膜キャパシタであって、前記下部電極の前記誘電体薄膜の形成されていない領域からその上方に向けて、前記下部電極に接続する下部接続電極が引き出され、前記誘電体薄膜の形成されている領域から前記下部接続電極が形成されている領域に渡って、前記下部電極上に絶縁層が形成され、該絶縁層の一部に空隙が形成されていることを特徴とする薄膜キャパシタ、が提供される。
そして、好ましくは、上部接続電極の少なくとも一部が上部電極の誘電体薄膜の形成されていない領域からその上方に向けて引き出され、誘電体薄膜の形成されている領域と前記少なくとも一部の上部接続電極が形成されている領域との間に前記上部電極の露出している領域あるいは空隙が存在する。
【００１２】
また、上記目的を達成するため、本発明によれば、上記の薄膜キャパシタが樹脂基板内に埋め込まれ、前記薄膜キャパシタの下部接続電極が該下部接続電極を貫通するスルーホールまたは該下部接続電極に達するビアホールを介して引き出され、前記薄膜キャパシタの上部接続電極が該上部接続電極を貫通するスルーホールまたは該上部接続電極に達するビアホールを介して引き出されていることを特徴とする薄膜キャパシタを内蔵した配線基板、が提供される。
【００１３】
また、上記目的を達成するため、本発明によれば、上記の薄膜キャパシタを搭載した半導体集積回路であって、その表面上に形成された電極パッドに前記薄膜キャパシタの下部接続電極および上部接続電極が接続されていることを特徴とする薄膜キャパシタを搭載した半導体集積回路、が提供される。
【００１４】
【発明の実施の形態】
次に、本発明の実施の形態について図面を参照して詳細に説明する。
図１は、本発明の薄膜キャパシタの第１の実施の形態を示す断面図である。樹脂または金属からなる厚さ５０μｍ程度の基材１０１上に、下部電極１０２と容量絶縁膜（誘電体薄膜）１０３と上部電極１０４とが積層されたキャパシタ部１２３と、層間絶縁膜１０５を介して上部電極１０４および下部電極１０２にそれぞれ接続されている外部接続電極１０６および１０７が存在する接続端子部１２４、１２２とを有して薄膜キャパシタが構成されている。キャパシタ部１２３と接続端子部１２４、１２２との間には、空隙１０８が存在している。空隙１０８は、基材１０１の変形によって生じる応力を吸収して、下部電極１０２、容量絶縁膜１０３、上部電極１０４が損傷を受けないようにするために設けられている。外部接続電極１０６、１０７は、接続抵抗を小さくするために１０μｍ以上の十分厚い膜厚を有することが望ましく、また、その材料としては抵抗率の小さなＣｕを主成分とすることが好ましい。また容量絶縁膜１０３は、下部電極１０２と上部電極１０４との電気的短絡を防止するために下部電極１０２の端部を十分覆うことができるように、ＣＶＤ法やゾルゲル法など段差被覆性に優れた成膜手法で作製されることが望ましい。
【００１５】
次に、この第１の実施の形態の薄膜キャパシタの作製プロセルを、基材１０１としてポリイミドフィルムを用いた場合について説明する。まず、市販のポリイミドフィルムの上に、ＤＣスパッタ法により下部電極１０２として、ＴｉＮ／Ｍｏ／Ｔｉの積層膜を堆積した後、フォトリソグラフィー法とウェットエッチング法により所望のパターンを形成した。その上に容量絶縁膜１０３として、ＣＶＤ法により成膜温度３００℃でＡｌ_２Ｏ_３薄膜を成膜した後、フォトリソグラフィー法とＩＢＥ（イオンビームエッチング）法により所望の形状に加工した。さらに上部電極１０４として、ＤＣスパッタ法によりＡｕ／ＴｉＮ積層膜を堆積した後、フォトリソグラフィー法とウェットエッチング法により所望のパターンを形成した。次に、層間絶縁膜１０５として、感光性ポリイミド樹脂を塗布した後、フォトリソグラフィー法により所望のパターンを形成した。その後、ＤＣスパッタ法によりＣｕ／Ｔｉ積層膜を全面に堆積した。次に、フォトリソグラフィー法により形成すべき外部接続電極形状の開口を有するレジスト膜を形成し、その開口にＣｕ／Ｔｉ膜を給電層として電解めっき法によりＣｕを１２μｍの厚さに成膜し、外部接続電極１０６および１０７とした。最後に、レジスト膜を除去した後、外部接続電極１０６および１０７以外の領域に露出したＣｕ／Ｔｉ積層膜をウェットエッチング法で除去して、図１に示す本実施の形態に係る薄膜キャパシタの製造工程を完了した。図１では空隙部に層間絶縁膜が無い構造が示されているが、十分な応力緩和が得られる範囲内であれば、空隙内の下部電極１０２や上部電極１０４の直上に層間絶縁膜の一部が残っていても構わない。
【００１６】
図２（ａ）、（ｂ）は、本発明の薄膜キャパシタの第２の実施の形態を示す平面図と断面図である。図２において、図１に示した第１の実施の形態の部分と同等の部分には同一の参照符号を付し重複する説明を省略する。本実施の形態の薄膜キャパシタが図１に示した第１の実施の形態の薄膜キャパシタと異なる点は、上部電極１０４が容量絶縁膜１０３の上にしか形成されず、上部電極側の外部接続電極１０６が、上部電極側の接続端子部１２４からキャパシタ部１２３まで延びてきており、キャパシタ部１２３の層間絶縁膜１０５に形成した開口を通して上部電極１０４に接続されているという点である。このように、上部電極１０４を容量絶縁膜１０３の上だけに形成することによって、容量絶縁膜１０３は、下部電極１０２の端部を覆う必要がなくなるので、ＣＶＤ法やゾルゲル法以外にスパッタ法等の段差被覆性の乏しい成膜手法で作製されることが可能になる。また、外部接続電極１０６と基材１０１との間に下部電極１０２と同じ材料で形成された外部接続電極受け１０２ｂが存在しているが、この外部接続電極受け１０２ｂは、外部接続電極１０６と基材１０１とを密着させるための単なる密着層であって、外部接続電極１０６が基材１０１と直接接しても密着するものである場合には、省略されても構わない。
【００１７】
図２（ａ）の５０２、５０２ｂ、５０３は、それぞれ、接続端子部１２２、１２４、キャパシタ部１２３において、下部電極１０２、外部接続電極受け１０２ｂ、上部電極１０４に対して外部接続電極のコンタクトを得るために層間絶縁膜１０５に形成したコンタクト開口部である。キャパシタ部１２３と接続端子部１２４、１２２との間には、第１の実施の形態と同様に、層間絶縁膜１０５を介して空隙１０８が存在している。
【００１８】
次に、この第２の実施の形態の薄膜キャパシタの作製プロセルを、基材１０１としてポリイミドフィルムを用いた場合について説明する。まず、市販のポリイミドフィルムを用い、この上にＤＣスパッタ法により下部電極１０２としてＰｔ／Ｔｉ／Ｍｏ／Ｔｉの積層膜を堆積し、その上に容量絶縁膜１０３として、ｒｆスパッタ法により成膜温度３５０℃でＳｒＴｉＯ_３薄膜を成膜し、さらに上部電極１０４としてＤＣスパッタ法によりＰｔ膜を堆積し、フォトリソグラフィー法とウェットエッチング法により、順次、所望のパターンを形成した。次に、層間絶縁膜１０５として、感光性ポリイミド樹脂を塗布した後、フォトリソグラフィー法により所望のパターンを形成した。その後、ＤＣスパッタ法によりＣｕ／Ｔｉ積層膜を全面に堆積した。次に、フォトリソグラフィー法により形成すべき外部接続電極形状の開口を有するレジスト膜をキャパシタ部１２３と接続端子部１２４、１２２とに形成し、その開口にＣｕ／Ｔｉ積層膜を給電層として電解めっき法によりＣｕを１２μｍの厚さに成膜した。次いで、レジスト膜を除去した後、露出したＣｕ／Ｔｉ積層膜をウェットエッチング法で除去した。次に、キャパシタ部１２３と接続端子部１２２との間の空隙をレジスト膜で覆い、スパッタ法を用いて、キャパシタ部１２３に形成したＣｕ層と接続端子部１２４に形成したＣｕ層とを接続する金属層を形成した。最後にレジスト膜を除去して、図２に示す本実施の形態に係る薄膜キャパシタの製造工程を完了した。上述の製造工程において、最後に形成する金属層の金属を種々選択することによって、外部接続電極の最上層の金属としてＣｕ以外の金属を選択できるというメリットが生じる。キャパシタ部１２３に形成したＣｕ層と接続端子部１２４に形成したＣｕ層とを接続する金属層を形成する方法として、給電層として利用した、この部分のＣｕ／Ｔｉ積層膜を除去せずに残して利用する方法もある。この場合は、最後の金属層の成膜工程が省略できるというメリットがある。さらに、キャパシタ部１２３に形成したＣｕ層と接続端子部１２４に形成したＣｕ層とを接続する金属層を形成する方法として、キャパシタ部１２３と接続端子部１２２、１２４とにＣｕめっき層を形成する際、キャパシタ部１２３と接続端子部１２４との間にもＣｕめっき層を形成し、エッチング法によって内部に空隙を有する金属層に加工する方法も考えられるが、金属層の膜厚の制御が難しく、生産性において劣る。なお、図２では空隙部には層間絶縁膜が無い構造が示されているが、第１の実施の形態と同様に、十分な応力緩和が得られる範囲内で、空隙内の下部電極１０２や外部接続電極１０６の直上に層間絶縁膜の一部が残っていても構わない。
【００１９】
本実施の形態の薄膜コンデンサの製造方法においては、第１の実施の形態と違って、容量絶縁膜１０３の成膜方法として、段差被覆性の乏しいｒｆスパッタ法を用いることが可能である。
【００２０】
図３は、図２に示す本実施の形態の薄膜キャパシタを配線の段差の存在する配線基板上に搭載した様子を示している。配線基板のコア層２０１上に厚さ２４〜３０μｍ程度の配線層２０２が形成されており、コア層２０１と配線層２０２との間に、配線層の厚さの段差が生じている。配線層２０２の上に、エポキシ樹脂等の接着剤を用いて、本発明の薄膜キャパシタ２０５が搭載されている。この薄膜キャパシタ２０５が上方よりプレスされると、薄膜キャパシタ２０５のキャパシタ部１２３が下に凸状に変形する。しかしながら、キャパシタ部１２３と接続端子部１２２、１２４との間に存在する空隙１０８が、変形によって発生する応力を吸収するため、電極膜（下部電極や上部電極）が断線したり、容量絶縁膜にクラックが入ることはない。
【００２１】
図４は、図２に示す本実施の形態の薄膜キャパシタを上下逆転させて、その外部接続電極をはんだボールによって半導体集積回路上の電極パッドに接続した様子を示している。薄膜キャパシタ３０５の外部接続電極１０６、１０７のはんだボール３０８による電極パッド３０２への接続後、薄膜キャパシタ３０５は下に凸（薄膜キャパシタ本来の上下方向では上に凸）状に変形するが、空隙１０８が存在するため、電極膜（下部電極や上部電極）が断線したり、容量絶縁膜にクラックが入ったりすることがない。
【００２２】
図５（ａ）、（ｂ）は、本実施の形態の薄膜キャパシタの変形例を示す平面図である。図５において、図２（ａ）に示した部分と同等の部分には同一の参照符号を付し重複する説明を省略する。図５（ａ）に示す薄膜キャパシタは、空隙１０８の領域において、層間絶縁膜１０５が、キャパシタ部１２３と接続端子部１２４、１２２との間で、櫛形状に入り組んだ構造となっている。また、図５（ｂ）に示す薄膜キャパシタは、キャパシタ部１２３と接続端子部１２４、１２２との間で、層間絶縁膜１０５がのこぎり歯形状に入り組んだり、図５（ａ）の場合と９０°異なる向きに櫛形状に入り組んでいるような構造となっている。このように、空隙１０８からは必ずしも層間絶縁膜１０５を完全に除去する必要はなく、空隙１０８は、変形による応力を吸収もしくは低減できる構造を有していればよい。図５（ａ）、（ｂ）に示す薄膜コンデンサの構造は、図２に示す薄膜コンデンサの構造と比べて、ねじり方向の強度が増し、製造上の取り扱いが容易になるという利点を有する。
【００２３】
図６は、本発明の薄膜キャパシタの第３の実施の形態を示す断面図である。図６において、図２に示した第２の実施の形態の部分と同等の部分には同一の参照符号を付し重複する説明を省略する。本実施の形態の薄膜キャパシタが図２に示した第２の実施の形態の薄膜キャパシタと異なる点は、キャパシタ部１２３と接続端子部１２２、１２４との間が、空隙ではなく、弾性率の小さなゴムなどの低弾性率材料１０９で完全に、あるいは部分的に充填されているという点である。この低弾性率材料１０９に要求される特性は、層間絶縁膜１０５よりも低いヤング率（弾性率）を有するということである。低弾性率材料１０９のヤング率が層間絶縁膜１０５のヤング率よりも低ければ、薄膜キャパシタが変形して紙面左右方向に応力が働いたとき、層間絶縁膜１０５が歪まずに低弾性率材料１０９が歪んで応力を吸収することができる。外部接続電極は、第１の実施の形態と同様、接続抵抗を小さくするために１０μｍ以上の十分厚い膜厚を有することが望ましく、また、抵抗率の小さなＣｕを主成分とすることが好ましい。図６に示す本実施の形態の薄膜キャパシタは、図１、図２に示す第１、第２の実施の形態の薄膜キャパシタと同様に、変形によって生じる応力を吸収して、電極の短絡や開放による不良を防止することができる。図６に示す本実施の形態の薄膜キャパシタは、さらに、図２に示した第２の実施の形態の薄膜キャパシタに比べ、キャパシタ部１２３と接続端子部１２２、１２４との間が低弾性率材料１０９で充填されているため、薄膜キャパシタを取り扱う際の折れ曲がりが防止され、ハンドリングが容易になり、製造上の歩留まりが向上するという効果を有する。
【００２４】
図７は、本発明の薄膜キャパシタの第４の実施の形態を示す断面図である。図７において、図２に示した第２の実施の形態の部分と同等の部分には同一の参照符号を付し重複する説明を省略する。本実施の形態の薄膜キャパシタが図２に示す第２の実施の形態の薄膜キャパシタと異なる点は、上部電極１０４の接続端子部が存在しないという点である。このように、上部電極１０４の接続端子部をなくすると、上部電極１０４に接続される外部接続電極１０６が容量絶縁膜１０３の真上に引き出されるため、配線基板に内蔵したときに表面配線層との電気的接続にプロセス上安価な貫通スルーホールを使うことができないというデメリットはあるが、外部接続電極１０６が横方向に引き延ばされることがないので、図２に示した第２の実施の形態の薄膜キャパシタと比べて、薄膜キャパシタの形状が小さくなるというメリット、および、高周波特性が向上するというメリットがある。また、ビルドアップ工法によるビア接続およびはんだボールでの接続は可能であって、キャパシタの搭載面積が小さくなる効果がある。
【００２５】
図８は、本発明の薄膜キャパシタの第５の実施の形態を示す断面図である。図８において、図７に示した第４の実施の形態の部分と同等の部分には同一の参照符号を付し重複する説明を省略する。本実施の形態の薄膜キャパシタが図７に示した第４の実施の形態の薄膜キャパシタと異なる点は、キャパシタ部１２３と接続端子部１２２との間が、低弾性率材料１０９で完全に、あるいは部分的に充填されているという点である。図８に示す薄膜キャパシタは、図６に示した薄膜キャパシタと同様に、薄膜キャパシタを取り扱う際の折れ曲がりが防止され、ハンドリングが容易になり、製造上の歩留まりが向上するという効果を有する。
【００２６】
図９は、本発明の薄膜キャパシタの第６の実施の形態を示す断面図である。図９において、図２に示した第２の実施の形態の部分と同等の部分には同一の参照符号を付し重複する説明を省略する。本実施の形態の薄膜キャパシタが図２に示した第２の実施の形態の薄膜キャパシタと異なる点は、キャパシタ部１２３と接続端子部１２２との間の空隙部において下部電極１０１に電極ギャップ１１１が存在し、キャパシタ部１２３と接続端子部１２４との間の空隙部において外部接続電極１０６に電極ギャップ１１２が存在し、少なくとも電極ギャップ１１１、１１２を満たすように、圧縮応力が印加されると印加圧縮応力の方向の寸法が減少するとともにその方向の導電率が増加する材料〔以下、「圧力依存導電率材料」という〕１１０が充填されているという点である。圧力依存導電率材料１１０は、紙面左右方向に応力の働いていないときにその方向の導電率が低く、紙面左右方向に圧縮応力が働いたときにその方向の導電率が高くなる。このような圧力依存導電率材料は、例えば弾性率の低い樹脂内部に金属粒子などの導電材料を分散させて作製することができる。
【００２７】
図１０は、本発明の薄膜キャパシタの第７の実施の形態を示す断面図である。図１０において、図９に示した第６の実施の形態の部分と同等の部分には同一の参照符号を付し重複する説明を省略する。本実施の形態の薄膜キャパシタが図７に示した第６の実施の形態の薄膜キャパシタと異なる点は、少なくとも電極ギャップ１１１、１１２を満たす圧力依存導電率材料１１０の上に、空隙部を完全にあるいは部分的に充填するように低弾性率材料１０９が形成されているという点である。本実施の形態の薄膜キャパシタにおいて低弾性率材料１０９を使用した効果は、図６および図８に示した薄膜キャパシタにおいて低弾性率材料を使用した効果と同じである。なお、第７、第８の実施の形態においても、外部接続電極は、第１の実施の形態の薄膜キャパシタの場合と同様に、接続抵抗を小さくするために１０μｍ以上の十分厚い膜厚を有することが望ましく、また、抵抗率の小さなＣｕを主成分とすることが好ましい。
【００２８】
図９、図１０に示す薄膜キャパシタは、作製直後では電極ギャップ１１１、１１２内の圧力依存導電率材料１１０の抵抗が高く、特性評価を行なうことが不可能である。しかしながら、例えば図３に示すような薄膜キャパシタが下に凸の形状になるような応力が加わると、圧力依存導電率材料１１０が紙面左右方向に圧縮応力を受け、その結果、樹脂中に分散している導電材料が接触し合うことによって圧力依存導電率材料１１０の導電率が増加し、キャパシタ部１２３の下部電極１０２および上部電極１０４と、接続端子部１２２、１２４の外部接続電極１０７、１０６とがそれぞれ電気的に導通し、薄膜キャパシタとしての動作が可能になる。圧力依存導電率材料１１０は変形することによって応力を吸収する役割をも果たすので、図２に示す第２の実施の形態のように電極膜が存在する場合に比べ、容量絶縁膜への印加応力がさらに小さくなり、設計値どおりの容量値が高歩留まりで得られる。
【００２９】
図１１は、本発明の薄膜キャパシタを内蔵した多層配線基板の断面図である。図１１に示す薄膜キャパシタ内蔵多層配線基板は、以下のように作製される。本発明の薄膜キャパシタ２０５をコア層２０１に形成された配線層２０２の上に搭載した後、コア層２０１をプリプレグ層２０３で挟み、プレスにより一体化する。その後、薄膜キャパシタ２０５の外部接続電極１０６、１０７を貫通するように基板を貫通する貫通スルーホール２０４を設け、プリプレグ層２０３の表面に配線パターン２０６を形成するとともに、貫通スルーホール２０４の内壁面に、配線パターン２０６と薄膜キャパシタ２０５の外部接続電極１０６、１０７や配線層２０２とを接続するＣｕめっき層２０７を形成する。
【００３０】
一体化の際のプレスにより、薄膜キャパシタは下に凸状に変形するが、空隙１０８が変形によって発生する応力を吸収するため、電極層が断線したり、容量絶縁膜にクラックが入ったりすることがなく、多層配線基板内蔵後も良好な容量値が得られる。
なお、上述の説明においては、薄膜キャパシタの外部接続電極は、貫通スルーホールを介して配線パターンに接続されたが、外部接続電極に達するビアホールを形成して、このビアホールを介して配線パターンに接続されるようにしてもよい。また、本発明のキャパシタ内蔵配線基板において、本発明の全ての実施の形態の薄膜キャパシタを使用することができる。
【００３１】
図１２は、本発明の薄膜キャパシタを搭載した半導体集積回路の断面図である。本発明の半導体集積回路は、本発明の薄膜キャパシタを半導体集積回路の配線最上層にはんだボールを用いて上下逆転して搭載した例に関するものである。薄膜キャパシタ３０５は、半導体集積回路３０６の配線最上層の電極パッド３０２にはんだボール３０８を用いて搭載されており、その一方の電極（上部電極）は電源線に、他方の電極（下部電極）はグラウンド線に接続されている。電源線は、また、層間絶縁膜３０１に形成したビアホール３０７の内壁に堆積されたＣｕめっき層を介して、ＭＯＳトランジスタ３０４のドレイン電極に接続されている。したがって、薄膜キャパシタ３０５は、ＭＯＳトランジスタ３０４や外部電源のノイズを低減するデカップリングキャパシタとして作用している。
【００３２】
薄膜キャパシタ３０５は、半導体集積回路３０６への搭載時の押し付け圧力により、図１２において下に凸（薄膜キャパシタ本来の上下方向では上に凸）状に変形するが、空隙１０８が存在するために、容量絶縁膜にクラックが入ったりすることがなく、結果として、半導体集積回路３０６の電源線とグラウンド線が短絡するというような故障の発生することがない。
なお、上述の説明においては、薄膜キャパシタの外部接続電極は、はんだボールを介して電極パッドに接続されたが、スタッドバンプを介して電極パッドに接続されるようにしてもよい。また、本発明の薄膜キャパシタ搭載半導体集積回路において、本発明の薄膜キャパシタの第１〜第５の実施の形態のものが好適に用いられる。
【００３３】
〔比較例〕
従来の技術に基づいて薄膜キャパシタを作製した。図１３は、本比較例において作製された薄膜キャパシタの断面図である。図１３において、図２に示した第２の実施の形態の部分と同等の部分には同一の参照符号を付し重複する説明を省略する。本実施の形態の薄膜キャパシタが図２に示した第２の実施の形態の薄膜キャパシタと異なる点は、キャパシタ部１２３と接続端子部１２２、１２４との間に空隙が存在せず、キャパシタ部１２３と接続端子部１２２、１２４が層間絶縁膜１０５によってリジッドに固定されているという点である。このような構造の薄膜キャパシタにおいても、本発明の全ての実施の形態の薄膜キャパシタと同様に、作製直後においては設計どおりの容量値が得られた。しかしながら、図１１に示す薄膜キャパシタ内蔵配線基板の場合と同様にして、この薄膜キャパシタを多層配線基板に内蔵し、外部接続電極を用いて薄膜キャパシタの特性を評価したところ、多くの開放あるいは短絡による不良が発生した。
【００３４】
その原因を調べるため、薄膜キャパシタの断面部を観察したところ、図１４に示すように、層間絶縁膜、下部電極、容量絶縁膜に欠陥が発生することが明らかとなった。即ち、配線層２０２がコア層２０１に対して段差を有するために、薄膜キャパシタ実装時の押し付け圧力によって薄膜キャパシタが下に凸状に変形しており、キャパシタ部１２３と接続端子部１２２、１２４との間の層間絶縁膜１０５にクラック４０１が観察された。層間絶縁膜１０５のクラック４０１は、下部電極１０２の内部を通って基材１０１の表面まで達し、下部電極１０２に断線が見られた。このことが、本比較例の薄膜キャパシタが多層配線基板内蔵後に開放による不良となった原因であると考えられる。さらに、容量絶縁膜１０３にもクラック４０２が観察された。このことが、上部電極と下部電極との短絡による不良の原因であると考えられる。これらのクラックが発生するのは、キャパシタ部１２３と接続端子部１２２、１２４とが層間絶縁膜１０５によってリジッドに固定され、薄膜キャパシタの変形によって発生する応力を吸収する層が存在しないためである。
【００３５】
図１５に本発明の薄膜キャパシタおよび比較例の薄膜キャパシタを多層配線基板に内蔵したときの測定容量値のばらつきを示す。薄膜キャパシタの容量の設計値は１０００ｐＦである。本発明の薄膜キャパシタを用いた場合、７５％以上の歩留まりで目標容量値が得られており、短絡や開放による不良も発生していない。一方、比較例の薄膜キャパシタを用いた場合、容量値のばらつきが大きく、１５％以上もの割合で短絡や開放による不良が発生している。
【００３６】
以上、本発明をその好適な実施の形態に基づいて説明したが、本発明の薄膜キャパシタ、それを用いた半導体集積回路および配線基板は、上述した実施の形態のみに制限されるものではなく、本願発明の要旨を変更しない範囲で種々の変化を施した薄膜キャパシタ、それを用いた半導体集積回路および配線基板も、本発明の範囲に含まれる。例えば、基材としては、主に樹脂を用いて説明されたが、ある程度の弾力を有し、多層配線基板や半導体集積装置に搭載可能な厚さを有するものであればどのような材料であってもよい。例えば、ＳＵＳやＣｕに代表される金属板や、１００μｍ程度の厚さに研磨したシリコン基板、サファイア基板などであっても良い。また低弾性率材料としては、ゴムの例を述べたが、樹脂やシリコーン等、弾性率が小さく、応力緩和の効果のある材料であればよい。また、薄膜コンデンサの容量絶縁膜としては、Ｔａ_２Ｏ_５やＳｒＴｉＯ_３薄膜の場合について説明したが、その一部あるいは全部が、化学式がＡＢＯ_３で表され、それぞれ、ＡとしてＢａ、Ｓｒ、Ｐｂ、Ｃａ、Ｌａ、Ｌｉ、Ｋのうち少なくとも１種以上、ＢとしてＺｒ、Ｔｉ、Ｔａ、Ｎｂ、Ｍｇ、Ｍｎ、Ｆｅ、Ｚｎ、Ｗのうち少なくとも１種以上を含むものであってもよい。あるいは、化学式が（Ｂｉ_２Ｏ_２）（Ａ_ｍ−１Ｂ_ｍＯ_３ｍ＋１）（Ｍ＝１，２，３，４，５）で表され、それぞれＡとしてＢａ、Ｓｒ、Ｐｂ、Ｃａ、Ｋ、Ｂｉのうち少なくとも１種以上、ＢとしてＮｂ、Ｔａ、Ｔｉ、Ｗの少なくとも１種以上を含むものであってもよい。あるいは、Ｔａ_２Ｏ_５、ＺｒＯ_２、ＴｉＯ_２、ＨｆＯ_２、ＳｉＯ_２、Ａｌ_２Ｏ_３、Ｓｉ_３Ｎ_４またはそれらの固溶体であってもよい。また、薄膜キャパシタの第３、第６、第７の実施の形態は、その基となる薄膜キャパシタとして薄膜キャパシタの第２の実施の形態を例に説明されているが、基となる薄膜キャパシタとしては、薄膜キャパシタの第２の実施の形態に限られず、薄膜キャパシタの第１、第４の実施の形態も同様に用いられる。
【００３７】
【発明の効果】
以上説明したように、本発明の薄膜キャパシタは、キャパシタ部と接続端子部との間に空隙を設け、あるいはその空隙に低弾性率材料を充填するものであるから、薄膜キャパシタが変形しても、変形による応力を吸収することが可能である。したがって、本発明によれば、内蔵あるいは実装した薄膜キャパシタが変形しても電極の開放や短絡による不良の発生が防止され、また、薄膜キャパシタの容量絶縁膜が絶縁破壊に至るまでの期間が長く、長寿命である、信頼性の高い配線基板および半導体集積回路を提供することが可能である。
また、本発明の薄膜キャパシタを内蔵した多層配線基板は、その内部に薄膜キャパシタを内蔵することにより、多層配線基板上のキャパシタ実装面積を不要とするものであるから、基板面積の縮小を可能にする。
また、本発明の薄膜キャパシタを搭載した半導体集積回路は、搭載された薄膜キャパシタの２端子が電源線と接地線に接続され、デカップリングキャパシタとして作用するものであるから、自身の電源ノイズを小さくするとともに、本発明の薄膜キャパシタおよびそれを搭載した半導体集積回路を用いた電子機器やシステムの低ノイズかつ高速な動作を可能にする。
【図面の簡単な説明】
【図１】本発明の薄膜キャパシタの第１の実施の形態を示す断面図。
【図２】本発明の薄膜キャパシタの第２の実施の形態を示す平面図〔（ａ）〕と断面図〔（ｂ）〕。
【図３】図２の薄膜キャパシタを搭載した配線基板の断面図。
【図４】図２の薄膜キャパシタを搭載した半導体集積回路の断面図。
【図５】本発明の薄膜キャパシタの第２の実施の形態の変形例を示す平面図。
【図６】本発明の薄膜キャパシタの第３の実施の形態を示す断面図。
【図７】本発明の薄膜キャパシタの第４の実施の形態を示す断面図。
【図８】本発明の薄膜キャパシタの第５の実施の形態を示す断面図。
【図９】本発明の薄膜キャパシタの第６の実施の形態を示す断面図。
【図１０】本発明の薄膜キャパシタの第７の実施の形態を示す断面図。
【図１１】本発明の薄膜キャパシタ内蔵配線基板の断面図。
【図１２】本発明の薄膜キャパシタ搭載半導体集積回路の断面図。
【図１３】比較例の薄膜キャパシタの断面図。
【図１４】比較例の薄膜キャパシタを搭載した配線基板の断面図。
【図１５】本発明と比較例との薄膜キャパシタの配線基板内に内蔵したときの容量値の分布図。
【図１６】従来の技術の薄膜キャパシタの断面図。
【符号の説明】
１０１　基材
１０２　下部電極
１０２ｂ　外部接続電極受け
１０３　容量絶縁膜
１０４　上部電極
１０５　層間絶縁膜
１０６、１０７　外部接続電極
１０８　空隙
１０９　低弾性率材料
１１０　圧力依存導電率材料
１１１、１１２　電極ギャップ
１２２、１２４　接続端子部
１２３　キャパシタ部
２０１　コア層
２０２　配線層
２０３　プリプレグ層
２０４　貫通スルーホール
２０５　薄膜キャパシタ
２０６　配線パターン
２０７　Ｃｕめっき層
３０１　層間絶縁膜
３０２　電極パッド
３０４　ＭＯＳトランジスタ
３０５　薄膜キャパシタ
３０６　半導体集積回路
３０７　ビアホール
３０８　はんだボール
４０１、４０２　クラック
５０２、５０２ｂ、５０３　コンタクト開口部
８０１　基材
８０２　下部電極
８０２ｂ　外部接続電極受け
８０３　容量絶縁膜
８０４　上部電極
８０５　層間絶縁膜
８０６、８０７　外部接続電極
８２２、８２４　接続端子部
８２３　キャパシタ部[0001]
[Industrial applications]
The present invention relates to a thin film capacitor formed on a base material, a multilayer wiring board incorporating the thin film capacitor, and a semiconductor integrated circuit mounting the thin film capacitor.
[0002]
[Prior art]
As electronic devices become smaller and thinner, capacitors, which are passive elements, are also becoming smaller and thinner. Small multilayer ceramic capacitors have been developed from 0603 size (0.6 mm x 0.3 mm) to 0402 size (0.4 mm x 0.2 mm), but handling difficulties during mounting are increasing. It is said that further miniaturization is difficult. Further, the multilayer ceramic capacitor has a resonance frequency up to about several hundred MHz due to its multilayer structure, and it is difficult to correspond to a high-speed and high-frequency system of GHz or more.
[0003]
On the other hand, a thin film capacitor in which a lower electrode, a capacitor insulating film, and an upper electrode are stacked on a base material has a resonance frequency of several GHz or more, and can realize a capacitor required for a high-speed and high-frequency system. In particular, (Ba, Sr) TiO ₃ And Pb (Zr, Ti) O ₃ The perovskite-type oxide thin film represented by has a high relative dielectric constant of 100 or more, and a thin film capacitor having a high capacity density can be manufactured on a limited substrate area. In recent years, ZrO ₂ , HfO ₂ Or TiO ₂ Alternatively, the thin films of these solid solutions also have a relative dielectric constant of about 15, which is smaller than that of the perovskite-type oxide thin film, but can be formed at a low physical thickness of about 10 nm and at a low temperature of 400 ° C. or less. It is attracting attention as a capacitor insulating film of a capacitor.
[0004]
As a thin film capacitor formed on a substrate and having a characteristic structure, there is a thin film capacitor disclosed in JP-A-6-325969. According to the gazette, when forming a thin film capacitor having a thin capacitive insulating film on a substrate having an uneven portion or a defect on the surface, a gap is provided between the substrate and the capacitor portion, and irregularities or defects on the substrate are provided. Is prevented from affecting the lower electrode and the capacitor insulating film, thereby preventing a short circuit of the capacitor. Similarly, a structure in which a gap is provided between a capacitor and a substrate is disclosed in JP-A-9-181363. Further, Japanese Patent Application Laid-Open No. 7-245233 discloses that a capacitor is formed by laminating a lower electrode, a capacitor insulating film, an upper electrode, and an external connection electrode of an upper electrode on the surface side of a base material, A thin film capacitor in which an external connection electrode of a lower electrode is drawn through a through hole is disclosed.
[0005]
Here, in actual electronic devices, in order to reduce the area of a mounting board such as a motherboard, a method of incorporating passive elements such as a resistor, an inductor, and the like in a multilayer wiring board has been proposed. For example, Japanese Patent Application Laid-Open No. H11-126978 discloses a technique in which a gap is provided in a multilayer wiring board and an electronic element such as a capacitor or a resistor is built in the gap. Japanese Patent Application Laid-Open No. 2001-168534 discloses a multilayer wiring board in which a built-in passive element is connected to a wiring layer by using a through-hole. The capacitors incorporated in these wiring boards are conventional multilayer ceramic capacitors or thin film capacitors in which thin films are simply laminated.
[0006]
Also, in an LSI (large-scale integrated circuit), the operating frequency has been increased from several hundred MHz to the order of GHz, and the rise time of the clock has become extremely short. The voltage drop occurs due to the parasitic resistance and the parasitic inductance existing in the device, and a malfunction due to the voltage drop is a problem. In order to reduce this voltage drop, a multilayer ceramic capacitor has conventionally been mounted as a decoupling capacitor near the LSI, thereby reducing noise.
[0007]
[Problems to be solved by the invention]
FIG. 16 shows a cross-sectional structure of a conventional thin-film capacitor formed on a base material. A capacitor portion 823 in which a lower electrode 802, a capacitor insulating film 803, and an upper electrode 804 are stacked on a base material 801; a connection terminal portion 822 in which external connection electrodes 807 and 806 are in contact with the lower electrode 802 or the upper electrode 804; 824 constitutes a thin-film capacitor. The space between the capacitor portion 823 and the lead electrode portions 822 and 824 is ₂ , BPSG (boro-phosphosilicate glass), NSG (non-doped silica glass), or an interlayer insulating film 105 using an insulating resin such as polyimide or epoxy, and the thin film capacitor is integrally fixed to the rigid. I have. When such a conventional thin film capacitor is mounted on a multilayer wiring board or LSI having wiring, the thin film capacitor bends due to wiring steps, stress is concentrated on the capacitor portion and the wiring, and the capacitor is shorted or opened. It became clear as a result of the inventor's earnest research that it would be.
[0008]
In the multilayer wiring board disclosed in Japanese Patent Application Laid-Open No. H11-126978, an electric element is built in an internal space, but deformation of an electric element mounted on a wiring step due to pressure at the time of mounting is taken into consideration. Not. Also, in the multilayer wiring board disclosed in Japanese Patent Application Laid-Open No. 2001-168534, no consideration is given to stress concentration on a thin film capacitor built in a recess inside the multilayer wiring board. Similarly, the thin film capacitor disclosed in Japanese Patent Application Laid-Open No. 7-245233 has a rigid structure and does not have a means for absorbing a stress generated at the time of deformation. Problems such as short-circuiting may occur. On the other hand, the thin film capacitor disclosed in JP-A-6-325969 and JP-A-9-181363, in which a gap exists in the base material, has a disadvantage that when a pressing pressure is applied from above the capacitor, the inside of the gap in the base material is reduced. In this case, the lower electrode and the capacitor insulating film are deformed and embedded, and as a result, a failure due to a short circuit or opening of the electrode is caused. Similar defects are likely to occur due to capacitor deformation when mounted on an LSI.
[0009]
The present invention has been made in view of the above problems, and has as its object the first object of the present invention is to deform a thin film capacitor caused by a wiring step when a thin film capacitor is built in or mounted on a multilayer wiring board or LSI. It is to provide a thin film capacitor in which the initial characteristics immediately after fabrication of the capacitor do not change even after being mounted on a multilayer wiring board or LSI, avoiding defects caused by short-circuiting or opening caused by the above. It is an object of the present invention to provide a multilayer wiring board and a semiconductor integrated circuit on which a thin film capacitor having high performance is mounted. A third object is to provide an electronic device system including such a multilayer wiring board or a semiconductor integrated circuit.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, according to the present invention, a thin film capacitor in which a lower electrode is formed on a base material and a dielectric thin film and an upper electrode are laminated on a partial region of the lower electrode, A lower connection electrode connected to the lower electrode is drawn upward from an area of the lower electrode where the dielectric thin film is not formed, and the area where the dielectric thin film is formed and the lower connection electrode are There is provided a thin-film capacitor, wherein an area where the lower electrode is exposed exists between the area and the area where the lower electrode is formed.
[0011]
In order to achieve the above object, according to the present invention, there is provided a thin film capacitor in which a lower electrode is formed on a base material, and a dielectric thin film and an upper electrode are laminated on a partial region of the lower electrode. A lower connection electrode connected to the lower electrode is drawn upward from a region of the lower electrode where the dielectric thin film is not formed, and the lower connection electrode is connected to the lower connection electrode from a region where the dielectric thin film is formed. A thin-film capacitor is provided, wherein an insulating layer is formed over the lower electrode over a region where the electrode is formed, and a void is formed in a part of the insulating layer.
Preferably, at least a part of the upper connection electrode is drawn upward from a region of the upper electrode where the dielectric thin film is not formed, and a region where the dielectric thin film is formed and an upper part of the at least part of the upper electrode. There is a region or a gap where the upper electrode is exposed between the region where the connection electrode is formed.
[0012]
In order to achieve the above object, according to the present invention, the thin film capacitor is embedded in a resin substrate, and a lower connection electrode of the thin film capacitor is formed in a through hole or the lower connection electrode penetrating the lower connection electrode. A thin film capacitor, wherein the thin film capacitor is drawn out through a via hole reaching the upper connection electrode, and the upper connection electrode of the thin film capacitor is drawn out through a through hole penetrating the upper connection electrode or a via hole reaching the upper connection electrode. A wiring board is provided.
[0013]
According to the present invention, there is provided a semiconductor integrated circuit having the above thin film capacitor mounted thereon, wherein a lower connection electrode and an upper connection electrode of the thin film capacitor are provided on an electrode pad formed on a surface thereof. And a semiconductor integrated circuit having a thin-film capacitor mounted thereon.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a sectional view showing a first embodiment of the thin film capacitor of the present invention. A capacitor portion 123 in which a lower electrode 102, a capacitor insulating film (dielectric thin film) 103, and an upper electrode 104 are stacked on a base material 101 having a thickness of about 50 μm made of resin or metal, and an interlayer insulating film 105 A thin-film capacitor is formed having connection terminal portions 124 and 122 having external connection electrodes 106 and 107 connected to the upper electrode 104 and the lower electrode 102, respectively. An air gap 108 exists between the capacitor 123 and the connection terminals 124 and 122. The gap 108 is provided to absorb the stress generated by the deformation of the base material 101 and prevent the lower electrode 102, the capacitor insulating film 103, and the upper electrode 104 from being damaged. It is desirable that the external connection electrodes 106 and 107 have a sufficiently thick film thickness of 10 μm or more in order to reduce the connection resistance, and it is preferable that the material of the external connection electrodes is mainly Cu having a small resistivity. Further, the capacitor insulating film 103 is excellent in step coverage such as a CVD method or a sol-gel method so as to sufficiently cover an end of the lower electrode 102 in order to prevent an electrical short circuit between the lower electrode 102 and the upper electrode 104. It is desirable to be manufactured by a suitable film forming technique.
[0015]
Next, a case where a polyimide film is used as the base material 101 in the production process of the thin film capacitor according to the first embodiment will be described. First, a laminated film of TiN / Mo / Ti was deposited as a lower electrode 102 on a commercially available polyimide film as a lower electrode 102 by DC sputtering, and then a desired pattern was formed by photolithography and wet etching. Al is formed thereon as a capacitive insulating film 103 by a CVD method at a film forming temperature of 300 ° C. ₂ O ₃ After forming the thin film, it was processed into a desired shape by photolithography and IBE (ion beam etching). Further, an Au / TiN laminated film was deposited as the upper electrode 104 by DC sputtering, and then a desired pattern was formed by photolithography and wet etching. Next, after a photosensitive polyimide resin was applied as the interlayer insulating film 105, a desired pattern was formed by photolithography. Thereafter, a Cu / Ti laminated film was deposited on the entire surface by DC sputtering. Next, a resist film having an opening in the shape of the external connection electrode to be formed is formed by photolithography, and Cu is formed to a thickness of 12 μm by electrolytic plating using the Cu / Ti film as a power supply layer in the opening. The external connection electrodes 106 and 107 were used. Lastly, after removing the resist film, the Cu / Ti laminated film exposed in regions other than the external connection electrodes 106 and 107 is removed by a wet etching method, thereby manufacturing the thin film capacitor according to the present embodiment shown in FIG. The process was completed. FIG. 1 shows a structure in which there is no interlayer insulating film in the gap, but if the stress can be sufficiently reduced, the interlayer insulating film may be directly over the lower electrode 102 or the upper electrode 104 in the gap. You may leave the department.
[0016]
FIGS. 2A and 2B are a plan view and a sectional view showing a second embodiment of the thin film capacitor of the present invention. In FIG. 2, parts that are the same as the parts of the first embodiment shown in FIG. 1 are given the same reference numerals, and duplicate descriptions are omitted. The difference between the thin film capacitor of the present embodiment and the thin film capacitor of the first embodiment shown in FIG. 1 is that the upper electrode 104 is formed only on the capacitive insulating film 103 and the external connection electrode on the upper electrode side. 106 extends from the connection terminal portion 124 on the upper electrode side to the capacitor portion 123, and is connected to the upper electrode 104 through an opening formed in the interlayer insulating film 105 of the capacitor portion 123. Since the upper electrode 104 is formed only on the capacitor insulating film 103 in this manner, the capacitor insulating film 103 does not need to cover the end of the lower electrode 102, and therefore, besides the CVD method or the sol-gel method, a sputtering method or the like can be used. It can be manufactured by a film forming method with poor step coverage. Further, an external connection electrode receiver 102b formed of the same material as the lower electrode 102 exists between the external connection electrode 106 and the base material 101. The external connection electrode receiver 102b is If the external connection electrode 106 is a mere adhesion layer for bringing the material 101 into close contact with the base material 101 even if the external connection electrode 106 is in direct contact with the base material 101, it may be omitted.
[0017]
Reference numerals 502, 502b, and 503 in FIG. 2A denote external connection electrode contacts with the lower electrode 102, the external connection electrode receiver 102b, and the upper electrode 104 in the connection terminal portions 122, 124 and the capacitor portion 123, respectively. The contact opening formed in the interlayer insulating film 105. As in the first embodiment, a gap 108 exists between the capacitor 123 and the connection terminals 124 and 122 via the interlayer insulating film 105.
[0018]
Next, a case where a polyimide film is used as the substrate 101 in the production process of the thin film capacitor according to the second embodiment will be described. First, a laminated film of Pt / Ti / Mo / Ti is deposited as a lower electrode 102 on the commercially available polyimide film by DC sputtering as a lower electrode 102, and a film forming temperature is formed thereon by rf sputtering as a capacitive insulating film 103. SrTiO at 350 ° C ₃ A thin film was formed, a Pt film was further deposited as the upper electrode 104 by a DC sputtering method, and a desired pattern was sequentially formed by a photolithography method and a wet etching method. Next, after a photosensitive polyimide resin was applied as the interlayer insulating film 105, a desired pattern was formed by photolithography. Thereafter, a Cu / Ti laminated film was deposited on the entire surface by DC sputtering. Next, a resist film having an opening in the shape of an external connection electrode to be formed by photolithography is formed in the capacitor section 123 and the connection terminal sections 124 and 122, and the Cu / Ti laminated film is used as a power supply layer in the opening and electrolytic plating is performed. Cu was deposited to a thickness of 12 μm by the method. Next, after removing the resist film, the exposed Cu / Ti laminated film was removed by a wet etching method. Next, the gap between the capacitor portion 123 and the connection terminal portion 122 is covered with a resist film, and the Cu layer formed on the capacitor portion 123 and the Cu layer formed on the connection terminal portion 124 are connected by sputtering. A metal layer was formed. Finally, the resist film was removed, and the manufacturing process of the thin film capacitor according to the present embodiment shown in FIG. 2 was completed. In the above-described manufacturing process, by selecting various metals of the metal layer formed last, there is an advantage that a metal other than Cu can be selected as the metal of the uppermost layer of the external connection electrode. As a method of forming a metal layer for connecting the Cu layer formed on the capacitor section 123 and the Cu layer formed on the connection terminal section 124, the Cu / Ti laminated film in this portion used as a power supply layer is left without being removed. There is also a method to use. In this case, there is an advantage that the last metal layer deposition step can be omitted. Further, as a method of forming a metal layer for connecting the Cu layer formed on the capacitor portion 123 and the Cu layer formed on the connection terminal portion 124, a Cu plating layer is formed on the capacitor portion 123 and the connection terminal portions 122 and 124. At this time, a method of forming a Cu plating layer between the capacitor portion 123 and the connection terminal portion 124 and processing the Cu layer into a metal layer having a void therein by an etching method can be considered, but it is difficult to control the thickness of the metal layer. , Inferior in productivity. Note that FIG. 2 shows a structure in which no interlayer insulating film is provided in the gap, but as in the first embodiment, the lower electrode 102 in the gap is provided within a range where sufficient stress relaxation can be obtained. A part of the interlayer insulating film may be left directly above the external connection electrode 106.
[0019]
In the method for manufacturing a thin film capacitor according to the present embodiment, unlike the first embodiment, an rf sputtering method with poor step coverage can be used as a method for forming the capacitance insulating film 103.
[0020]
FIG. 3 shows a state in which the thin film capacitor of the present embodiment shown in FIG. 2 is mounted on a wiring board having wiring steps. A wiring layer 202 having a thickness of about 24 to 30 μm is formed on a core layer 201 of a wiring board, and a step in the thickness of the wiring layer is generated between the core layer 201 and the wiring layer 202. The thin film capacitor 205 of the present invention is mounted on the wiring layer 202 using an adhesive such as an epoxy resin. When the thin film capacitor 205 is pressed from above, the capacitor section 123 of the thin film capacitor 205 is deformed downwardly. However, the gap 108 existing between the capacitor portion 123 and the connection terminal portions 122 and 124 absorbs the stress generated by the deformation, so that the electrode film (the lower electrode or the upper electrode) is disconnected or the capacitor insulating film is damaged. There is no crack.
[0021]
FIG. 4 shows a state in which the thin film capacitor of the present embodiment shown in FIG. 2 is turned upside down, and its external connection electrodes are connected to electrode pads on the semiconductor integrated circuit by solder balls. After the external connection electrodes 106 and 107 of the thin-film capacitor 305 are connected to the electrode pad 302 by the solder balls 308, the thin-film capacitor 305 is deformed downward (convex upward in the original vertical direction of the thin-film capacitor). , There is no breakage of the electrode film (lower electrode or upper electrode) and no crack in the capacitor insulating film.
[0022]
FIGS. 5A and 5B are plan views showing modified examples of the thin-film capacitor of the present embodiment. In FIG. 5, parts that are the same as the parts shown in FIG. 2A are given the same reference numerals, and overlapping descriptions will be omitted. The thin film capacitor shown in FIG. 5A has a structure in which the interlayer insulating film 105 is interdigitated between the capacitor portion 123 and the connection terminal portions 124 and 122 in the region of the gap 108. In the thin-film capacitor shown in FIG. 5B, the interlayer insulating film 105 has a saw-toothed shape between the capacitor portion 123 and the connection terminal portions 124 and 122, or has a 90 ° angle compared to the case of FIG. The structure is such that the comb shape is intricate in different directions. As described above, it is not always necessary to completely remove the interlayer insulating film 105 from the gap 108, and the gap 108 only needs to have a structure capable of absorbing or reducing stress due to deformation. The structure of the thin film capacitor shown in FIGS. 5A and 5B has an advantage that the strength in the torsional direction is increased and the handling in manufacturing is easy as compared with the structure of the thin film capacitor shown in FIG.
[0023]
FIG. 6 is a sectional view showing a thin-film capacitor according to a third embodiment of the present invention. In FIG. 6, parts that are the same as the parts of the second embodiment shown in FIG. 2 are given the same reference numerals, and overlapping descriptions will be omitted. The difference between the thin film capacitor of the present embodiment and the thin film capacitor of the second embodiment shown in FIG. 2 is that the space between the capacitor portion 123 and the connection terminal portions 122 and 124 is not an air gap but a small elastic modulus. The point is that it is completely or partially filled with the low elastic modulus material 109 such as rubber. A characteristic required for the low elastic modulus material 109 is that it has a lower Young's modulus (elastic modulus) than the interlayer insulating film 105. If the Young's modulus of the low elastic modulus material 109 is lower than the Young's modulus of the interlayer insulating film 105, when the thin film capacitor is deformed and a stress acts in the left-right direction on the paper, the interlayer insulating film 105 is not distorted and the low elastic modulus material 109 is not deformed. Can be distorted to absorb stress. As in the first embodiment, the external connection electrode desirably has a sufficiently thick film thickness of 10 μm or more in order to reduce the connection resistance, and preferably includes Cu having a small resistivity as a main component. The thin-film capacitor of the present embodiment shown in FIG. 6 absorbs the stress caused by deformation and short-circuits or opens the electrodes similarly to the thin-film capacitors of the first and second embodiments shown in FIGS. Can be prevented. The thin film capacitor of the present embodiment shown in FIG. 6 further has a lower elastic material between the capacitor portion 123 and the connection terminal portions 122 and 124 than the thin film capacitor of the second embodiment shown in FIG. Since it is filled with 109, it is possible to prevent bending when handling the thin film capacitor, to facilitate handling, and to improve the production yield.
[0024]
FIG. 7 is a sectional view showing a thin-film capacitor according to a fourth embodiment of the present invention. 7, parts that are the same as the parts of the second embodiment shown in FIG. 2 are given the same reference numerals, and overlapping descriptions are omitted. The thin film capacitor of the present embodiment is different from the thin film capacitor of the second embodiment shown in FIG. 2 in that the connection terminal of the upper electrode 104 does not exist. As described above, when the connection terminal portion of the upper electrode 104 is eliminated, the external connection electrode 106 connected to the upper electrode 104 is drawn out right above the capacitor insulating film 103. Although there is a disadvantage that an inexpensive through-hole cannot be used in the electrical connection of the process, the external connection electrode 106 is not elongated in the lateral direction, so the second embodiment shown in FIG. Compared with the thin film capacitor described above, there is an advantage that the shape of the thin film capacitor is reduced and an advantage that the high frequency characteristics are improved. In addition, via connection by a build-up method and connection by solder balls are possible, which has the effect of reducing the mounting area of the capacitor.
[0025]
FIG. 8 is a sectional view showing a thin-film capacitor according to a fifth embodiment of the present invention. 8, parts that are the same as the parts of the fourth embodiment shown in FIG. 7 are given the same reference numerals, and redundant description will be omitted. The difference between the thin film capacitor of the present embodiment and the thin film capacitor of the fourth embodiment shown in FIG. 7 is that the space between the capacitor portion 123 and the connection terminal portion 122 is completely formed of the low elastic modulus material 109, or It is partially filled. The thin film capacitor shown in FIG. 8 has the effect of preventing bending when handling the thin film capacitor, facilitating handling, and improving the manufacturing yield, similarly to the thin film capacitor shown in FIG.
[0026]
FIG. 9 is a sectional view showing a thin film capacitor according to a sixth embodiment of the present invention. In FIG. 9, parts that are the same as the parts of the second embodiment shown in FIG. 2 are given the same reference numerals, and overlapping descriptions are omitted. The difference between the thin film capacitor of the present embodiment and the thin film capacitor of the second embodiment shown in FIG. 2 is that the electrode gap 111 is formed in the lower electrode 101 in the gap between the capacitor portion 123 and the connection terminal portion 122. There is an electrode gap 112 in the external connection electrode 106 in a gap between the capacitor portion 123 and the connection terminal portion 124. When a compressive stress is applied so as to fill at least the electrode gaps 111 and 112, an applied compression is performed. The material 110 is filled with a material (hereinafter, referred to as a “pressure-dependent conductivity material”) 110 in which the dimension in the stress direction decreases and the conductivity in that direction increases. The pressure-dependent conductivity material 110 has a low conductivity in the left-right direction of the paper when no stress is applied, and has a high conductivity in the left-right direction when a compressive stress is applied in the left-right direction. Such a pressure-dependent conductivity material can be produced, for example, by dispersing a conductive material such as metal particles inside a resin having a low elastic modulus.
[0027]
FIG. 10 is a sectional view showing a thin film capacitor according to a seventh embodiment of the present invention. In FIG. 10, parts that are the same as the parts of the sixth embodiment shown in FIG. 9 are given the same reference numerals, and redundant description will be omitted. The difference between the thin film capacitor of the present embodiment and the thin film capacitor of the sixth embodiment shown in FIG. 7 is that the void portion is completely formed on at least the pressure-dependent conductivity material 110 which fills the electrode gaps 111 and 112. Alternatively, the low elastic modulus material 109 is formed so as to be partially filled. The effect of using the low elastic modulus material 109 in the thin film capacitor of the present embodiment is the same as the effect of using the low elastic modulus material in the thin film capacitors shown in FIGS. In the seventh and eighth embodiments, the external connection electrode has a sufficiently thick film thickness of 10 μm or more in order to reduce the connection resistance, similarly to the case of the thin film capacitor of the first embodiment. It is preferable that Cu having a small resistivity be a main component.
[0028]
In the thin film capacitors shown in FIGS. 9 and 10, the resistance of the pressure-dependent conductivity material 110 in the electrode gaps 111 and 112 is high immediately after fabrication, so that it is impossible to evaluate the characteristics. However, when a stress is applied so that the thin film capacitor as shown in FIG. 3 becomes convex downward, for example, the pressure-dependent conductive material 110 receives a compressive stress in the left-right direction of the drawing, and as a result, is dispersed in the resin. The conductivity of the pressure-dependent conductivity material 110 is increased by the contact of the conductive materials, and the lower electrode 102 and the upper electrode 104 of the capacitor unit 123 and the external connection electrodes 107 and 106 of the connection terminal units 122 and 124 are connected to each other. Are electrically connected to each other, and can operate as a thin film capacitor. Since the pressure-dependent conductivity material 110 also plays a role of absorbing stress by being deformed, the stress applied to the capacitance insulating film is smaller than that in the case where the electrode film exists as in the second embodiment shown in FIG. Is further reduced, and a capacitance value as designed can be obtained with a high yield.
[0029]
FIG. 11 is a sectional view of a multilayer wiring board incorporating the thin film capacitor of the present invention. The multilayer wiring board with a built-in thin film capacitor shown in FIG. 11 is manufactured as follows. After the thin film capacitor 205 of the present invention is mounted on the wiring layer 202 formed on the core layer 201, the core layer 201 is sandwiched between prepreg layers 203 and integrated by pressing. Thereafter, a through-hole 204 penetrating the substrate is provided so as to penetrate the external connection electrodes 106 and 107 of the thin-film capacitor 205, a wiring pattern 206 is formed on the surface of the prepreg layer 203, and an inner wall surface of the through-hole 204 is formed. Then, a Cu plating layer 207 for connecting the wiring pattern 206 to the external connection electrodes 106 and 107 of the thin film capacitor 205 and the wiring layer 202 is formed.
[0030]
Pressing at the time of integration causes the thin film capacitor to deform downwardly convex, but the gap 108 absorbs the stress generated by the deformation, so that the electrode layer is disconnected or the capacitance insulating film is cracked. And a good capacitance value can be obtained even after the built-in multilayer wiring board.
In the above description, the external connection electrode of the thin film capacitor is connected to the wiring pattern through the through-hole, but a via hole reaching the external connection electrode is formed, and the external connection electrode is connected to the wiring pattern through this via hole. May be performed. Further, in the wiring board with a built-in capacitor of the present invention, the thin film capacitors of all the embodiments of the present invention can be used.
[0031]
FIG. 12 is a sectional view of a semiconductor integrated circuit on which the thin film capacitor of the present invention is mounted. The semiconductor integrated circuit of the present invention relates to an example in which the thin film capacitor of the present invention is mounted upside down using a solder ball on the uppermost layer of wiring of the semiconductor integrated circuit. The thin film capacitor 305 is mounted on the uppermost electrode pad 302 of the semiconductor integrated circuit 306 by using solder balls 308. One electrode (upper electrode) is used as a power supply line, and the other electrode (lower electrode) is used as a thin film capacitor 305. Connected to ground line. The power supply line is connected to the drain electrode of the MOS transistor 304 via a Cu plating layer deposited on the inner wall of the via hole 307 formed in the interlayer insulating film 301. Therefore, the thin-film capacitor 305 functions as a decoupling capacitor for reducing noise of the MOS transistor 304 and an external power supply.
[0032]
The thin film capacitor 305 is deformed downward (convex upward in the original vertical direction of the thin film capacitor) in FIG. 12 due to the pressing pressure when the thin film capacitor 305 is mounted on the semiconductor integrated circuit 306. There is no crack in the capacitor insulating film, and as a result, a failure such as a short circuit between the power supply line and the ground line of the semiconductor integrated circuit 306 does not occur.
In the above description, the external connection electrode of the thin film capacitor is connected to the electrode pad via a solder ball, but may be connected to the electrode pad via a stud bump. In the semiconductor integrated circuit with a thin film capacitor according to the present invention, the thin film capacitors according to the first to fifth embodiments of the present invention are preferably used.
[0033]
(Comparative example)
A thin film capacitor was manufactured based on a conventional technique. FIG. 13 is a cross-sectional view of the thin-film capacitor manufactured in this comparative example. 13, parts that are the same as the parts of the second embodiment shown in FIG. 2 are given the same reference numerals, and overlapping descriptions will be omitted. The difference between the thin film capacitor of the present embodiment and the thin film capacitor of the second embodiment shown in FIG. 2 is that there is no gap between the capacitor portion 123 and the connection terminal portions 122 and 124, and the capacitor portion 123 And the connection terminal portions 122 and 124 are rigidly fixed by the interlayer insulating film 105. Also in the thin film capacitor having such a structure, as in the thin film capacitors according to all the embodiments of the present invention, a capacitance value as designed was obtained immediately after fabrication. However, as in the case of the wiring board with a built-in thin film capacitor shown in FIG. 11, this thin film capacitor was built in a multilayer wiring board and the characteristics of the thin film capacitor were evaluated using external connection electrodes. A defect has occurred.
[0034]
Observation of the cross section of the thin film capacitor to investigate the cause revealed that defects were generated in the interlayer insulating film, the lower electrode, and the capacitive insulating film as shown in FIG. That is, since the wiring layer 202 has a step with respect to the core layer 201, the thin film capacitor is deformed to be convex downward by the pressing pressure at the time of mounting the thin film capacitor, and the capacitor portion 123 and the connection terminal portions 122, 124 A crack 401 was observed in the interlayer insulating film 105 during the period. The crack 401 in the interlayer insulating film 105 reached the surface of the base material 101 through the inside of the lower electrode 102, and the lower electrode 102 was broken. This is considered to be the cause of the failure of the thin film capacitor of this comparative example due to opening after the multilayer wiring board was built. Further, cracks 402 were also observed in the capacitance insulating film 103. This is considered to be the cause of the failure due to the short circuit between the upper electrode and the lower electrode. These cracks occur because the capacitor portion 123 and the connection terminal portions 122 and 124 are rigidly fixed by the interlayer insulating film 105, and there is no layer that absorbs stress generated by deformation of the thin film capacitor.
[0035]
FIG. 15 shows variations in measured capacitance values when the thin film capacitor of the present invention and the thin film capacitor of the comparative example are incorporated in a multilayer wiring board. The design value of the capacitance of the thin film capacitor is 1000 pF. When the thin film capacitor of the present invention is used, a target capacitance value is obtained with a yield of 75% or more, and no failure due to short circuit or opening occurs. On the other hand, when the thin film capacitor of the comparative example is used, the variation in capacitance value is large, and a failure due to short circuit or opening occurs at a rate of 15% or more.
[0036]
As described above, the present invention has been described based on the preferred embodiments. However, the thin film capacitor of the present invention, a semiconductor integrated circuit and a wiring substrate using the same are not limited to the above embodiments, A thin film capacitor in which various changes are made without changing the gist of the present invention, a semiconductor integrated circuit and a wiring board using the same are also included in the scope of the present invention. For example, although the description has been made mainly using a resin as the base material, any material may be used as long as it has a certain elasticity and a thickness that can be mounted on a multilayer wiring substrate or a semiconductor integrated device. You may. For example, a metal plate represented by SUS or Cu, a silicon substrate polished to a thickness of about 100 μm, or a sapphire substrate may be used. Further, as an example of the low elastic modulus material, rubber is described, but any material having a small elastic modulus and an effect of relaxing stress, such as resin and silicone, may be used. In addition, as a capacitance insulating film of a thin film capacitor, Ta ₂ O ₅ And SrTiO ₃ Although the case of a thin film has been described, a part or all of the film has a chemical formula of ABO. ₃ And A represents at least one of Ba, Sr, Pb, Ca, La, Li, and K, and B represents at least one of Zr, Ti, Ta, Nb, Mg, Mn, Fe, Zn, and W. One or more types may be included. Alternatively, if the chemical formula is (Bi ₂ O ₂ ) (A _m-1 B _m O _{3m + 1} ) (M = 1, 2, 3, 4, 5), wherein A is at least one of Ba, Sr, Pb, Ca, K, and Bi, and B is at least one of Nb, Ta, Ti, and W. One or more types may be included. Or Ta ₂ O ₅ , ZrO ₂ , TiO ₂ , HfO ₂ , SiO ₂ , Al ₂ O ₃ , Si ₃ N ₄ Alternatively, a solid solution thereof may be used. In the third, sixth, and seventh embodiments of the thin-film capacitor, the second embodiment of the thin-film capacitor is described as an example of the thin-film capacitor on which the thin-film capacitor is based. Is not limited to the second embodiment of the thin film capacitor, and the first and fourth embodiments of the thin film capacitor can be used similarly.
[0037]
【The invention's effect】
As described above, the thin-film capacitor of the present invention provides a gap between the capacitor section and the connection terminal section, or fills the gap with the low elastic modulus material. It is possible to absorb the stress due to deformation. Therefore, according to the present invention, even if the built-in or mounted thin-film capacitor is deformed, the occurrence of defects due to the opening and short-circuiting of the electrodes is prevented, and the period until the capacitive insulating film of the thin-film capacitor reaches dielectric breakdown is long. It is possible to provide a highly reliable wiring board and a semiconductor integrated circuit which have a long service life.
Further, the multilayer wiring board incorporating the thin-film capacitor of the present invention eliminates the need for a capacitor mounting area on the multilayer wiring board by incorporating the thin-film capacitor therein, so that the board area can be reduced. I do.
Further, in the semiconductor integrated circuit on which the thin film capacitor of the present invention is mounted, two terminals of the mounted thin film capacitor are connected to the power supply line and the ground line, and function as a decoupling capacitor. In addition, the present invention enables low-noise and high-speed operation of electronic devices and systems using the thin film capacitor of the present invention and a semiconductor integrated circuit on which the thin film capacitor is mounted.
[Brief description of the drawings]
FIG. 1 is a sectional view showing a first embodiment of a thin film capacitor of the present invention.
FIG. 2 is a plan view [(a)] and a sectional view [(b)] showing a thin-film capacitor according to a second embodiment of the present invention.
FIG. 3 is a sectional view of a wiring board on which the thin film capacitor of FIG. 2 is mounted.
FIG. 4 is a sectional view of a semiconductor integrated circuit on which the thin film capacitor of FIG. 2 is mounted.
FIG. 5 is a plan view showing a modification of the second embodiment of the thin film capacitor of the present invention.
FIG. 6 is a sectional view showing a third embodiment of the thin film capacitor of the present invention.
FIG. 7 is a sectional view showing a thin-film capacitor according to a fourth embodiment of the present invention.
FIG. 8 is a sectional view showing a thin-film capacitor according to a fifth embodiment of the present invention.
FIG. 9 is a sectional view showing a thin-film capacitor according to a sixth embodiment of the present invention.
FIG. 10 is a sectional view showing a thin film capacitor according to a seventh embodiment of the present invention.
FIG. 11 is a cross-sectional view of a wiring board with a built-in thin film capacitor of the present invention.
FIG. 12 is a sectional view of a semiconductor integrated circuit mounted with a thin film capacitor according to the present invention.
FIG. 13 is a sectional view of a thin film capacitor of a comparative example.
FIG. 14 is a sectional view of a wiring board on which a thin film capacitor of a comparative example is mounted.
FIG. 15 is a distribution diagram of capacitance values when the thin film capacitors of the present invention and the comparative example are incorporated in a wiring board.
FIG. 16 is a cross-sectional view of a conventional thin film capacitor.
[Explanation of symbols]
101 substrate
102 lower electrode
102b External connection electrode receiver
103 Capacitive insulation film
104 upper electrode
105 interlayer insulating film
106, 107 External connection electrode
108 void
109 Low modulus material
110 Pressure dependent conductivity material
111, 112 electrode gap
122, 124 connection terminal
123 Capacitor section
201 core layer
202 Wiring layer
203 prepreg layer
204 Through-hole
205 Thin Film Capacitor
206 Wiring pattern
207 Cu plating layer
301 interlayer insulating film
302 electrode pad
304 MOS transistor
305 Thin film capacitor
306 Semiconductor integrated circuit
307 Via hole
308 Solder ball
401, 402 crack
502, 502b, 503 Contact opening
801 base material
802 Lower electrode
802b External connection electrode receiver
803 Capacitive insulating film
804 upper electrode
805 interlayer insulating film
806, 807 External connection electrode
822, 824 connection terminal
823 Capacitor part

Claims

A thin film capacitor in which a lower electrode is formed on a base material, and a dielectric thin film and an upper electrode are laminated on a partial region of the lower electrode, wherein the dielectric thin film of the lower electrode is not formed. A lower connection electrode connected to the lower electrode is drawn upward from the region, and the lower electrode of the lower electrode is provided between a region where the dielectric thin film is formed and a region where the lower connection electrode is formed. A thin-film capacitor having an exposed region.

2. The thin film capacitor according to claim 1, wherein an upper connection electrode connected to the upper electrode is drawn upward from the upper electrode.

The upper electrode extends on the base material to a region where the dielectric thin film is not formed, and is connected to the upper electrode from the region where the dielectric thin film is not formed of the upper electrode upward. The connection electrode is drawn out, and a region where the upper electrode is exposed exists between a region where the dielectric thin film is formed and a region where the upper connection electrode is formed. 2. The thin film capacitor according to 1.

The upper electrode is connected to an upper connection electrode, and the upper connection electrode is connected to an extraction electrode formed above the upper electrode, and an external connection electrode formed on a substrate on which the lower electrode is not formed. And a connection wiring portion electrode for connecting the lead portion electrode and the external connection portion electrode, wherein at least a part of the connection wiring portion electrode is formed on the base material. 2. The thin film capacitor according to 1.

The exposed lower electrode, or the exposed lower electrode and the exposed upper electrode, or the exposed lower electrode and the connection wiring portion electrode, the gap portion of which is removed. Is filled in the gap portion with a material (hereinafter referred to as a "pressure-dependent conductivity material") whose dimensions in the direction of the applied compressive stress are reduced and the conductivity in that direction is increased when a compressive stress is applied. The thin-film capacitor according to claim 1, wherein:

A thin film capacitor in which a lower electrode is formed on a base material, and a dielectric thin film and an upper electrode are laminated on a partial region of the lower electrode, wherein the dielectric thin film of the lower electrode is not formed. A lower connection electrode connected to the lower electrode is drawn upward from the region, and the lower connection electrode extends from the region where the dielectric thin film is formed to the region where the lower connection electrode is formed. A thin film capacitor, wherein an insulating layer is formed on the insulating layer, and a void is formed in a part of the insulating layer.

7. The thin-film capacitor according to claim 6, wherein an upper connection electrode connected to the upper electrode is drawn upward from the upper electrode.

The upper electrode extends on the base material to a region where the dielectric thin film is not formed, and is connected to the upper electrode from the region where the dielectric thin film is not formed of the upper electrode upward. An insulating layer is formed on the upper electrode from the region where the dielectric thin film is formed to the region where the upper connecting electrode is formed, and a gap is formed in a part of the insulating layer. The thin film capacitor according to claim 6, wherein?

The upper electrode is connected to an upper connection electrode, and the upper connection electrode is connected to an extraction electrode formed above the upper electrode, and an external connection electrode formed on a substrate on which the lower electrode is not formed. And a connection wiring portion electrode for connecting the lead portion electrode and the external connection portion electrode, from a region where the dielectric thin film is formed to a region where the external connection portion electrode is formed, 7. An insulating layer is formed on the base material, a gap is formed in a part of the insulating layer, and the connection wiring electrode is formed along a wall surface and a bottom surface of the gap. 3. The thin film capacitor according to item 1.

10. The thin film capacitor according to claim 4, wherein a pseudo lower electrode made of the same material as the lower electrode is formed between the external connection portion electrode and the base.

11. The method according to claim 6, wherein at least a part of the bottom surface of the gap reaches the lower electrode, or the lower electrode and the upper electrode, or the lower electrode and the base material. 3. The thin film capacitor according to item 1.

12. The thin film capacitor according to claim 11, wherein an insulating layer is formed with a comb-like or saw-tooth-like projection across the gap.

13. The thin film capacitor according to claim 6, wherein the void is at least partially filled with a low elastic modulus material having a lower Young's modulus than the insulating layer.

The lower electrode below the gap, or the lower electrode below the gap and the upper electrode below the gap, or the lower electrode below the gap and the connection wiring section electrode below the gap are removed. 13. The thin film capacitor according to claim 6, wherein a gap portion is provided, and at least the gap portion is filled with a pressure-dependent conductivity material.

The thin film capacitor according to claim 14, wherein a low elastic modulus material having a lower Young's modulus than the insulating layer is formed on the pressure-dependent conductivity material.

16. The thin film capacitor according to claim 2, wherein the thin film capacitor is embedded in a resin substrate, and a lower connection electrode of the thin film capacitor penetrates the lower connection electrode or a via hole reaching the lower connection electrode. A wiring board having a built-in thin film capacitor, wherein the upper connection electrode of the thin film capacitor is drawn out through a through hole penetrating the upper connection electrode or a via hole reaching the upper connection electrode. .

17. The wiring board according to claim 16, wherein the thin film capacitor is fixed to a wiring layer of the resin substrate via an adhesive.

14. A semiconductor integrated circuit on which the thin film capacitor according to claim 2 is mounted, wherein a lower connection electrode and an upper connection electrode of the thin film capacitor are connected to an electrode pad formed on a surface thereof. A semiconductor integrated circuit having a thin film capacitor mounted thereon.

19. The semiconductor integrated circuit according to claim 18, wherein the lower connection electrode and the upper connection electrode are connected to the electrode pad via a solder ball or a stud bump.

20. The method according to claim 18, wherein one of the lower connection electrode and the upper connection electrode is electrically connected to a power supply wiring and the other is connected to a ground wiring via the respective electrode pads. Semiconductor integrated circuit with a thin film capacitor.

An electronic device system comprising the wiring board or the semiconductor integrated circuit according to claim 16.