JP3917689B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a semiconductor device for driving an inductive load, and more particularly to a semiconductor device having a built-in flyback diode for flowing a regenerative current of the inductive load.
[0002]
[Prior art]
  Stepping motors, also called pulse motors or step motors, can be used for office automation because they can control the positioning without using a feedback system, such as changing the rotation angle with the number of pulses or changing the rotation speed with the pulse frequency. It is actively used for FA applications. Along with this, power ICs for driving stepping motors have been widely used.
[0003]
  Reference numeral 100 in FIG. 3 shows an example of a circuit block of such a stepping motor driving IC. Symbol L in FIG.₁, L₂Represents the inductance component of a two-phase stepping motor as an inductive load, and the inductive load L₁And inductive load L₂Are magnetically coupled in reverse phase.
[0004]
  Inductive load L₁, L₂One end of the power supply E₀Is connected to the other end of the transistor Q.₁, Q₂Are connected to the collector terminals respectively. The transistor Q₁, Q₂The emitter terminal of the current detection resistor R_S0Is connected to one end of the transistor Q, and when the other end is connected to the ground potential, each transistor Q₁, Q₂When a predetermined one of them becomes ON, the power source E₀To inductive load L₁And inductive load L₂Is configured to be supplied with current. The current is the current detection resistor R_S0Current detection resistor R_S0Is input to the comparator Comp, and the current detection resistor R_S0Is compared with the reference voltage Vref by the comparator Comp, and based on the comparison result, the control circuit B₀Is each transistor Q₁, Q₂When the above control is performed, the two-phase stepping motor is configured to be driven in an open loop.
[0005]
  Transistor Q₁, Q₂The flyback diode FD is connected between the collector terminal and the ground potential.₁, FD₂Each transistor Q₁, Q₂The transistor Q is now connected in the opposite direction.₁Is ON, transistor Q₂Is in the OFF state and the inductive load L₁Power supply E₀Drive current i supplied from₁Is assumed to be flowing.
[0006]
  From that state, transistor Q₁Is turned off, the inductive load L₁Inductive load L magnetically coupled with₂A voltage is generated at both ends of the flyback diode FD₂Power from ground through E₀Regenerative current i₂Will be washed away. This regenerative current i₂Inductive load L₁The energy stored in is released.
[0007]
  FIG. 5 shows a partial diffusion structure of such a stepping motor driving IC 100.
  This stepping motor driving IC 100 has p⁺A substrate 120 made of a silicon single crystal of the type, and n in advance on the substrate 120⁺After the n-type buried layer 126 of the type is formed, n^-A semiconductor crystal layer 121 made of a silicon epitaxial layer of the type is deposited.
[0008]
  P from the surface of the semiconductor crystal layer 121⁺The isolation diffusion layer 124 of the mold is diffused so as to reach the substrate 120, and a plurality of element regions 150 including those not shown are formed by the isolation diffusion layer 124 and the pn junction formed by the substrate 120 and the semiconductor crystal layer 121. 151 are formed.
[0009]
  Each element region has n⁺Type low resistance diffusion layer 128 and p⁺Type diode diffusion layer 129, n⁺A desired diffusion layer of the type emitter diffusion layer 130 is formed, and an electric element such as a transistor or a resistor is formed by the diffusion layer.
[0010]
  A diode diffusion layer 129 is formed in the element region denoted by reference numeral 150. Here, in the semiconductor crystal layer 121 described above, a portion where the respective diffusion layers are not formed is denoted by reference numeral 113. Then, a flyback diode FD is formed by a pn junction formed by the semiconductor crystal layer 113 and the diode diffusion layer 129.₂Is configured.
[0011]
  On the other hand, in the element region 151, an emitter diffusion layer 130 is formed on the surface of the diode diffusion layer 129. The NPN includes the emitter diffusion layer 130 as an emitter region, the diode diffusion layer 129 as a base region, and the semiconductor crystal layer 113 as a collector region. Transistor Q₂Is formed.
[0012]
  In these element regions 150 and 151, a low resistance diffusion layer 128 is diffused so as to reach the n buried layer 126, and the flyback diode FD₂And transistor Q₂Is configured to pass through the low resistance diffusion layer 128 in each of the element regions 150 and 151.
[0013]
  A patterned aluminum thin film 132 is formed on the surface of the silicon oxide film 131 formed on each diffusion layer, and a window provided in the silicon oxide film 131 is formed on a predetermined surface of each diffusion layer. An electrode 132 is formed through the portion.
[0014]
  Each electrode 132 is taken out of the semiconductor device 100 and a flyback diode FD₂P⁺When the type diffusion layer 129 is placed at the ground potential, the transistor Q₁When the load turns from the ON state to the OFF state, the inductive load L₁Inductive load L magnetically coupled with₂A voltage is induced to the power source E from the diode diffusion layer 129 through the semiconductor crystal layer 113.₀Regenerative current i₂Will be washed away.
[0015]
  In this semiconductor device 100, the isolation diffusion layer 124 is placed at the ground potential in order to electrically isolate the element regions from each other.₂Since the semiconductor crystal layer 113 in the element region 150 is moved to a negative potential when the current flows, the pn junction formed by the separation diffusion layer 124 and the substrate 120 and the semiconductor crystal layer 113 is forward-biased, and the pn junction Parasitic current i_ThreeWill flow.
[0016]
  The parasitic current i_ThreeThe parasitic NPN transistor Q having the semiconductor crystal layer 113 in the element region 150 as an emitter region, the isolation diffusion layer 124 as a base region, and the semiconductor crystal layer 113 in another adjacent element region as a collector region._PThe base current of the parasitic NPN transistor Q_PWhen a collector current having a magnitude according to the current amplification factor of 'is passed, the collector current is extracted from the semiconductor crystal layer 113 in the adjacent element region. Such a collector current cannot be ignored in terms of the stability of circuit operation and heat loss design, and if it is too large, it causes various problems such as malfunction of the circuit and increased heat generation.
[0017]
[Problems to be solved by the invention]
  The present invention was created to solve the above-mentioned disadvantages of the prior art, and an object thereof is to provide a semiconductor device for driving an inductive load with a small exclusive area and a small amount of heat generation.
[0018]
[Means for Solving the Problems]
  In order to solve the above problems, the invention according to claim 1 is a substrate, a semiconductor crystal layer having a different conductivity type from the substrate and formed on the surface of the substrate, and the same conductivity type as the substrate. Diffused from the surface of the semiconductor crystal layerReached the substrateA separation diffusion layer,A plurality of element regions that are regions surrounded by the isolation diffusion layer are formed,In the semiconductor device in which an electric element is formed in the element region,A collector region, a base region, and an emitter region are arranged in the element region to constitute a transistor for driving an inductive load,As the electrical elementSaidA diode diffusion layer diffused from the surface of the semiconductor crystal layer is provided in an element region having a transistor, and a flyback diode is formed by a pn junction formed by the semiconductor crystal layer and the diode diffusion layer. It is configured to allow current to flow through the flyback diode in the OFF state.In the element region where the transistor is formed, a low resistance diffusion layer having the same conductivity type as the semiconductor crystal layer and diffused from the surface of the semiconductor crystal layer is provided, and a current flowing through the transistor and the flyback diode But the same low resistance expansion A substrate bias electrode is provided on a part of the surface of the separation diffusion layer, and the separation diffusion layer is used as a substrate bias diffusion layer, and a voltage is applied to the substrate bias electrode. When the substrate is placed at a predetermined potential via the substrate bias diffusion layer, the pn junction formed by the substrate and the semiconductor crystal layer can be set in a reverse bias state, and the transistor and the fly The element region in which the back diode is formed is separated from other element regions by an isolation diffusion layer in which the substrate bias electrode is not provided on the surface, and between the isolation diffusion layer and the substrate bias diffusion layer. A dummy region having a conductivity type different from that of the substrate is disposed, and the flyback diode is disposed in front of the isolation biasing layer for the substrate bias in the element region. Transistors are located remotely, the the dummy region, near said flyback diode, said transistors are located remotely, the dummy area, characterized in that connected to the electrode for the substrate bias.
  The invention described in claim 2 is described in claim 1.A semiconductor device comprising a plurality of element regions in which the transistor and the flyback diode are formed, wherein each of the transistors is connected to an inductive load and can drive the inductive load When one or more of the transistors changes from an ON state to an OFF state, the energy stored in the inductive load connected to the transistor has other transistors. It is characterized in that it can be emitted through the flyback diode in the element region.
[0019]
  According to the configuration of the present invention described above, the separation diffusion layer having the same conductivity type as the substrate reaches the substrate from the surface of the substrate and the semiconductor crystal layer having a conductivity type different from that of the substrate and formed on the substrate surface. When a pn junction is formed by the semiconductor crystal layer and the isolation diffusion layer, a plurality of element regions electrically isolated from each other can be formed by the pn junction.
[0020]
  When an electric element is provided in such an element region to constitute a semiconductor device, the electric element has a conductivity type different from that of the semiconductor crystal layer from the surface of the semiconductor crystal layer in the element area where a transistor for driving an inductive load is provided. When a flyback diode is formed by diffusing a diode diffusion layer and a pn junction formed by the diode diffusion layer and the semiconductor crystal layer, the transistor and the flyback diode are formed in the same element region. In addition, an isolation diffusion layer between the flyback diodes is unnecessary, and the area of the semiconductor device can be saved. Such a flyback diode is suitable for a circuit having a plurality of transistors that drive an inductive load because a current can flow when the transistor that drives the inductive load is in an OFF state.
[0021]
  In that case, since current does not flow simultaneously through the transistor and the diode in the same element region, a low resistance diffusion layer having the same conductivity type as the semiconductor crystal layer is formed from the surface of the semiconductor crystal layer in the element region where the transistor is formed. If the transistor and the flyback diode are diffused and the current flows through the low resistance diffusion layer, the low resistance diffusion layer can be shared. A device can be configured.
[0022]
  In addition, when such a semiconductor device has a plurality of element regions in which a transistor and a flyback diode are formed together, any one or more of the transistors are turned on. The element region where other transistors (transistors other than the transistors that changed from the ON state to the OFF state) are formed when the ON state of the transistors stored in the inductive load changes to the OFF state. It can be emitted through an internal flyback diode.
[0023]
  For these semiconductor devices, a substrate bias electrode is provided on a part of the surface of the separation diffusion layer, the separation diffusion layer is used as a substrate bias diffusion layer, a voltage is applied to the substrate bias electrode, and the substrate bias diffusion layer is formed. If the substrate can be placed at a predetermined potential via the semiconductor device, the pn junction formed by the substrate and the semiconductor crystal layer is placed in a reverse bias state without connecting the ground potential electrode to the back surface of the semiconductor device. it can.
[0024]
  In this case, in order to separate the element region in which the transistor and the flyback diode are formed from other element regions, an isolation diffusion layer without a substrate bias electrode is provided on the surface, and a semiconductor in the element region is provided. When a pn junction is formed with the crystal layer and a dummy region having a conductivity type different from that of the substrate is disposed between the isolation diffusion layer and the substrate bias diffusion layer, a parasitic transistor in the vicinity of the substrate bias diffusion layer is used. Current amplification factor can be reduced.
[0025]
  Further, when the flyback diode is placed close to the substrate bias isolation diffusion layer and the transistor is arranged far from the substrate bias isolation diffusion layer, the base region of the parasitic transistor located far from the substrate bias isolation diffusion layer is disposed. Since the resistance component is increased, the operation of the parasitic transistor can be further suppressed.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
  Embodiments of the present invention will be described with reference to the drawings.
  Referring to FIG. 1, reference numeral 2 denotes a semiconductor device as an example of the present invention, and includes the same blocks as the block diagram shown in FIG. 3. The semiconductor device 2 has p⁺A substrate 20 made of silicon single crystal of the type, and the surface of the substrate 20 has p⁺Type p buried layer 23 and n⁺After the n-type buried layer 26 of the type is formed, the single crystal grown n^-A semiconductor crystal layer 21 made of a silicon epitaxial layer of the type is formed.
[0027]
  P from the surface of the semiconductor crystal layer 21⁺The type isolation diffusion layer 24 is diffused so as to be in contact with the p buried layer 23, and the separation diffusion layer 24 and the substrate 20 are separated from each other by the pn junction formed with the semiconductor crystal layer 21 and the n buried layer 26. A large number of element regions are formed (the element region 4 is shown in FIG. 1).
[0028]
  From the surface of the semiconductor crystal layer 21, a desired portion is p.⁺Type diode diffusion layer 29 and n⁺A type emitter diffusion layer 30 is diffused, and the semiconductor crystal layer 21, the diode diffusion layer 29, and the emitter diffusion layer 30 form desired electrical elements such as transistors and resistors in each element region. .
[0029]
  Among these element regions, in particular, the emitter diffusion layer 30 is partially diffused from the surface of the diode diffusion layer 29 in the element region 4, and the NPN transistor Q₂Is formed. In the following, no diffusion layer or buried layer is formed in the semiconductor crystal layer 21, and n^-If the portion maintaining the concentration of the epitaxial layer is denoted by reference numeral 13, the NPN transistor Q₂Then, the semiconductor crystal layer 13 is a collector region, the emitter diffusion layer 30 is an emitter region, and the diode diffusion layer 29 having the emitter diffusion layer 30 on the surface is a base region.
[0030]
  The NPN transistor Q₂A diode diffusion layer 29 in which the emitter diffusion layer 30 is not diffused is provided in the element region 4 including the flyback diode having the diode diffusion layer 29 as an anode region and the semiconductor crystal layer 13 as a cathode region. FD₂Is formed.
[0031]
  On each diffusion layer and on the semiconductor crystal layer 13, a silicon oxide film 31 having a window opened in a predetermined portion is formed, and a patterned aluminum thin film is formed on the surface thereof, and a flyback diode FD is formed.₂The anode region (diode diffusion layer 29) of the anode electrode 42, the NPN transistor Q₂An emitter electrode 44 is formed on the emitter region (emitter diffusion layer 30), and a base electrode 45 is formed on the base region (diode diffusion layer 29).
[0032]
  The patterned aluminum thin film is also formed on a part of the surface of the separation diffusion layer 24 as the substrate bias electrode 41, and when the substrate bias electrode 41 is connected to the ground potential, the substrate bias electrode is formed. The separation diffusion layer 24 located on the bottom surface 41 is used as the substrate bias diffusion layer 16 so that the substrate 20 can be set to the ground potential.
[0033]
  By the way, NPN transistor Q₂And flyback diode FD₂In the element region 4 including the isolation diffusion layer 24, the semiconductor crystal layer 13 is surrounded by a substantially square ring shape, while the low resistance diffusion layer 28 includes the diode diffusion layer 29 including the emitter diffusion layer 30. It has a shape that surrounds it. The low resistance diffusion layer 28 includes an NPN transistor Q₂Collector current and flyback diode FD₂Therefore, the aluminum thin film formed on the surface of the low resistance diffusion layer 28 is configured to be used as the common electrode 43 as both a collector electrode and a cathode electrode. The common electrode 43 is an inductive load L outside the semiconductor device 2.₂It is comprised so that it can connect to one end of.
[0034]
  The impurity concentration of the low resistance diffusion layer 28 is higher than that of the semiconductor crystal layer 13 so that the voltage drop is reduced even when a large current flows.₂Becomes ON and inductive load L₂And the flyback diode FD₂Inductive load L₁Regenerative current i₂In both cases, the current flows through the low resistance diffusion layer 28, so that the NPN transistor Q₂And flyback diode FD₂Thus, the heat loss generated in the above can be reduced by the same low resistance diffusion layer 28.
[0035]
  Now, NPN transistor Q₁Is ON, NPN transistor Q₂Is in the OFF state and the inductive load L₁Drive current i₁Is assumed to be flowing.
[0036]
  Since the semiconductor crystal layer 13 in the element region 4 functions as both a collector region and a cathode region, the NPN transistor Q₁Turns off and the inductive load L₁Inductive load L magnetically coupled with₂When an electromotive force is generated in the flyback diode FD₂Is conducted and regenerative current i₂Is flowing to the negative potential of the semiconductor crystal layer 13.
[0037]
  The anode electrode 42 and the substrate bias electrode 41 are short-circuited on the silicon oxide film 31 by the above-described patterned aluminum thin film, and thus are formed by the substrate 20, the separation diffusion layer 24, and the semiconductor crystal layer 13. The pn junction is also forward biased, and it is inevitable that a parasitic current flows.
[0038]
  The parasitic current is a base current of a parasitic NPN transistor in which the semiconductor crystal layer 13 in the element region 4 is an emitter region, a p-type layer adjacent to the emitter region is a base region, and an n-type layer adjacent to the base region is a collector region. Therefore, as the collector current, a current is drawn from the semiconductor crystal layer 13 in another element region adjacent to the element region 4.
[0039]
  In this case, the base electrode of the parasitic NPN transistor is the substrate bias electrode 41, but in this semiconductor device 2, the surface of the isolation diffusion layer 24 that separates the element region 4 from the other element regions has a substrate bias. The operation electrode 41 is not provided, and the separation diffusion layer 24 located near the element region 4 is suppressed from operating as a base region.
[0040]
  Between the element region 4 and the separation diffusion layer 24 that separates the substrate bias diffusion layer 16 provided with the substrate bias electrode 41, a semiconductor crystal layer 13 having a conductivity type different from that of the substrate 20 is formed. A dummy region 5 is disposed, so that minority carriers injected from the semiconductor crystal layer 13 which is the emitter region of the parasitic transistor do not easily reach the collector region, and the current amplification factor of the parasitic NPN transistor in that portion is reduced. Has been lowered.
[0041]
  Further, the low resistance diffusion layer 28 is diffused from the surface of the dummy region 5 so as to be in contact with the n buried layer 26, and the substrate bias electrode 41 is formed on the surface of the low resistance diffusion layer 28. The dummy region 5 is configured to be placed at the same potential as the lowest potential substrate 20. Therefore, even when the dummy region 5 becomes a collector of the parasitic NPN transistor and a parasitic current flows, the voltage drop due to the parasitic current is small and the loss is also reduced.
[0042]
  Here, as shown in FIG. 1, among the isolation diffusion layers 24 that isolate the element region 4, those adjacent to the dummy region 5 are adjacent diffusion layers 18, and those that are not adjacent are non-adjacent diffusion layers 19. Then, flyback diode FD₂Is close to the adjacent diffusion layer 18 and the NPN transistor Q₂Are located far away.
[0043]
  NPN transistor Q₁, Q₂, Flyback diode FD₁, FD₂FIG. 2 (a) shows a plan view of FIG. In FIG. 2A, the emitter diffusion layer 30 and each electrode are omitted. The diffusion structure shown in FIG. 1 corresponds to a cross-sectional view taken along line AA in FIG.
[0044]
  As can be seen from FIGS. 1 and 2A, in the semiconductor device 2 of the present invention, the dummy region 5 is provided between the substrate bias diffusion layer 16 and the semiconductor crystal layer 13 in the element region 4. , A parasitic NPN transistor Q whose base region is the substrate bias layer 16 or the adjacent diffusion layer 18_P1The current amplification factor is very low. Therefore, the parasitic NPN transistor Q_p1Base current i_ThreeCollector current i flows even if_FourIs very small and can be ignored.
[0045]
  On the other hand, the parasitic NPN transistor Q having the non-adjacent diffusion layer 19 as a base region_P2Includes a resistance R due to a resistance component of the substrate 20 between the base-emitter junction and the substrate bias electrode 41 serving as a base electrode._BIs added to the parasitic NPN transistor Q_p2Base current i of_FourIs difficult to flow, and therefore the flowing collector current i_FiveIs also getting smaller.
[0046]
  When the current amplification factor of the parasitic NPN transistor when the dummy region 5 is provided as in the semiconductor device 2 of the present invention and when the dummy region 5 is not provided as in the conventional technology is measured, 0.2 to 0. Whereas the size was about 3, in the semiconductor device 2 of the present invention, it was reduced to 1/10 or less of the value. According to the experimental results, when the low-resistance diffusion layer 28 is not provided in the dummy region 5, the current amplification factor of the parasitic NPN transistor is somewhat larger.
[0047]
  In the plan view shown in FIG. 2A, the dummy region 5 is not provided on the non-adjacent diffusion layer 19 side. However, as shown in FIG.₁, Q₂And flyback diode FD₁, FD₂Alternatively, the dummy region 5 may be provided over the entire circumference of the element region formed together.
[0048]
  Next, the semiconductor device of the present invention having other circuit blocks will be described.
  Referring to the circuit block diagram of FIG. 4, reference numeral 3 denotes the semiconductor device, and an NPN transistor Q₁₁, Q₁₂And PNP transistor Q_{twenty one}, Q_{twenty two}And flyback diode FD₁₁, FD₁₂, FD_{twenty one}, FD_{twenty two}And control circuit B_TenAnd current detection resistor R_S10And have.
[0049]
  NPN transistor Q₁₁, Q₁₂Collector electrode and PNP transistor Q_{twenty one}, Q_{twenty two}Are connected to each other by a patterned aluminum thin film, as described above, and the NPN transistor Q₁₁, Q₁₂The emitter electrode of the current detection resistor R provided outside_S10The other end is connected to the ground potential.
[0050]
  Also, the PNP transistor Q_{twenty one}, Q_{twenty two}Are connected to each other by a patterned aluminum thin film, taken out of the semiconductor device 3, and supplied with a power source E._TenConnected with.
[0051]
  In the semiconductor device 3, where the collector electrodes of the transistors are connected to each other, they are taken out to the outside, and inductive load L such as a motor between them₁₁Both ends of the inductive load L₁₁And each transistor Q₁₁, Q₁₂, Q_{twenty one}, Q_{twenty two}And the H bridge circuit is configured.
[0052]
  Control circuit B_TenEach transistor Q₁₁, Q₁₂, Q_{twenty one}, Q_{twenty two}The base electrode of the control circuit B is connected._TenOperates and the PNP transistor Q_{twenty one}And NPN transistor Q₁₁Or a PNP transistor Q_{twenty two}And NPN transistor Q₁₁Inductive load L₁₁In addition, the current flows in either the forward or reverse direction.
[0053]
  Flyback diode FD_{twenty one}, FD_{twenty two}PNP transistor Q_{twenty one}, Q_{twenty two}Each PNP transistor Q is formed by a patterned aluminum thin film formed in a separate element region._{twenty one}, Q_{twenty two}Are connected in antiparallel. On the other hand, flyback diode FD₁₁, FD₁₂Is the flyback diode FD shown in FIG. 1, FIG. 2 (a), (b).₁, FD₂Like NPN transistor Q₁₁, Q₁₂NPN transistor Q is provided in each element region having₁₁, Q₁₂The collector region and the cathode region are formed of the same semiconductor crystal layer.
[0054]
  Therefore, the flyback diode FD is expressed in the circuit block diagram as shown in FIG.₁₁, FD₁₂The cathode electrode of NPN transistor Q₁₁, Q₁₂Each collector electrode is connected to each other. On the other hand, this flyback diode FD₁₁, FD₁₂The anode electrode is taken out to the outside and connected to the ground potential.
[0055]
  Current detection resistor R_S10The voltage generated at the control circuit B_TenEach transistor Q detected by₁₁, Q₁₂, Q_{twenty one}, Q_{twenty two}This control is performed in the same manner as in the semiconductor device 2 shown in FIG.
[0056]
  Now, PNP transistor Q_{twenty one}And NPN transistor Q₁₂And ON state, PNP transistor Q_{twenty two}And NPN transistor Q₁₁Are in the OFF state and the symbol i₁₁Is the inductive load L₁₁Suppose that
[0057]
  When all the transistors are turned off from this state, the inductive load L₁₁Flyback diode FD by the electromotive force generated in₁₁, FD_{twenty two}Are forward-biased and the sign i₁₂A regenerative current shown in FIG.
[0058]
  NPN transistor Q₁₁And flyback diode FD₁₁The isolation diffusion layer that separates the element region formed with and from the other element regions is provided with no substrate bias electrode on the surface, as shown in FIG. A dummy region having a conductivity type different from that of the substrate is disposed between the substrate bias diffusion layer. Further, the flyback diode FD is applied to the substrate bias separation diffusion layer provided with the substrate bias electrode.₁₁Near the NPN transistor Q₁₁Are located far away.
[0059]
  Therefore, flyback diode FD₁₁Even when the semiconductor crystal layer in the element region having a negative potential is applied, the current drawn from the semiconductor crystal layer in another element region can be small.
[0060]
  What has been described above is the case where the NPN transistor and the flyback diode are formed in the same element region, but an n-type substrate and a p-type semiconductor crystal layer are used, and the semiconductor crystal layer is used. A PNP transistor and a flyback diode may be formed in the same element region. In this case, it is necessary to apply a power supply voltage to the substrate bias electrode.
[0061]
  Whether the transistor in the same element area as the flyback diode is a PNP transistor or an NPN transistor, drive the inductive load if it is configured to allow regenerative current to flow when the transistor is OFF. Is possible.
[0062]
  In many cases, the regenerative current has almost the same magnitude (about 1.0 to 4.0 A) as the current supplied from the power source to the inductive load. is there. When the transistor and the flyback diode are formed in separate element regions as in the prior art, the area of the isolation diffusion layer is increased, which is uneconomical. In the semiconductor device of the present invention, the transistor and the flyback diode are formed in the same element region, and an isolation diffusion layer between them is not necessary.
[0063]
【The invention's effect】
  Since the area of the element region can be reduced, the cost is reduced.
  Since the current amplification factor of the parasitic NPN transistor can be reduced, malfunctions are eliminated and heat generation is also reduced.
[Brief description of the drawings]
FIG. 1 is a diagram showing an example of a diffusion structure of a semiconductor device of the present invention.
FIG. 2 (a): an example of a plan view thereof
            (b): Another example of a plan view
FIG. 3 is a diagram showing an example of a circuit block of a semiconductor device of the present invention.
FIG. 4 is a diagram illustrating an example of another circuit block.
FIG. 5 is a diagram for explaining a diffusion structure of a conventional semiconductor device;
[Explanation of symbols]
  2, 3 ... Semiconductor device 4 ... Element area 5 ... Dummy area
16 ... Diffusion layer for substrate bias 20 ... Substrate 21 ... Semiconductor crystal layer
24 …… Separation diffusion layer 28 …… Low resistance diffusion layer 29 …… Diode diffusion layer
41 …… Substrate bias electrode
Q₁, Q₂, Q₁₁, Q₁₂...... NPN transistor
FD₁, FD₂, FD₁₁, FD₁₂…… Flyback diode

Claims (2)

A substrate,
A semiconductor crystal layer having a different conductivity type from the substrate and formed on the substrate surface;
A separation diffusion layer that has the same conductivity type as the substrate and is diffused from the surface of the semiconductor crystal layer and reaches the substrate ;
A plurality of element regions that are regions surrounded by the isolation diffusion layer are formed,
In the semiconductor device in which an electric element is formed in the element region,
A collector region, a base region, and an emitter region are arranged in the element region to constitute a transistor for driving an inductive load,
Wherein the device region having the transistor as an electrical device, the semiconductor crystal layer diode diffusion layer diffused from the surface is provided,
A flyback diode is formed by a pn junction formed by the semiconductor crystal layer and the diode diffusion layer,
When the transistor is in an OFF state, it is configured to allow a current to flow through the flyback diode ,
In the element region where the transistor is formed, a low resistance diffusion layer having the same conductivity type as the semiconductor crystal layer and diffused from the surface of the semiconductor crystal layer is provided,
The current flowing through the transistor and the flyback diode is configured to pass through the same low resistance diffusion layer,
A substrate bias electrode is provided on a part of the surface of the separation diffusion layer, and the separation diffusion layer serves as a substrate bias diffusion layer,
By applying a voltage to the substrate bias electrode and placing the substrate at a predetermined potential through the substrate bias diffusion layer, the pn junction formed by the substrate and the semiconductor crystal layer can be in a reverse bias state. Composed of
The element region in which the transistor and the flyback diode are formed is separated from other element regions by an isolation diffusion layer in which the substrate bias electrode is not provided on the surface, and the isolation diffusion layer and the substrate bias diffusion are separated from each other. Between the layers, a dummy region of a conductivity type different from that of the substrate is disposed,
In the element region, the flyback diode is located close to the substrate bias isolation diffusion layer, and the transistor is arranged far away.
The flyback diode is located close to the dummy region, and the transistor is located far away.
The semiconductor device according to claim 1, wherein the dummy region is connected to the substrate bias electrode. A plurality of element regions in which the transistor and the flyback diode are formed;
Each transistor is connected to an inductive load;
A semiconductor device configured to drive the inductive load,
When any one or more of the transistors changes from the ON state to the OFF state, the energy accumulated in the inductive load connected to the transistor is within the element region including the other transistors. The semiconductor device according to claim 1, wherein the semiconductor device is configured to be able to emit through the flyback diode.

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