JP3916206B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device for controlling electric power.
[0002]
[Prior art]
As a semiconductor device used for power control, there are a MOSFET and an IGBT. These semiconductor devices are controlled by an insulated gate, have a wide safe operation region and high-speed switching characteristics, and have a feature that the control device can be miniaturized. In recent years, it has been widely used in the field of power electronics such as inverters and switching power supplies.
[0003]
However, this type of semiconductor device has the following problems. In order to increase the current capacity, a large number of channels must be formed. As a result, the gate capacity increases, and it takes time to charge and discharge the gate during switching, and not only the control device is negatively charged, but also the operation is uneven, which may lead to the destruction of the semiconductor device. Of course, the loss also increases.
[0004]
In addition, the use of this type of IGBT in a high breakdown voltage region has the following problems. A high breakdown voltage element requires a large junction termination around the current-carrying region of the element in order to generate a breakdown voltage. When energized, the carrier is filled up to the junction end. At the time of turn-off operation, a large amount of carriers filled in the junction termination portion are concentrated and discharged to the outer peripheral portion of the current-carrying region, so that current concentration easily occurs in this portion, and as a result, the device is easily destroyed. .
[0005]
[Problems to be solved by the invention]
As described above, in a conventional semiconductor device using an insulated gate, when the current capacity is increased, there is a possibility that breakdown and loss are increased.
[0006]
Further, the conventional high breakdown voltage IGBT has a drawback that current concentration tends to occur around the energized region at the time of turn-off, and as a result, the IGBT is easily broken.
[0007]
An object of the present invention is to provide a semiconductor device having high turn-off performance by preventing problems associated with an increase in current capacity, particularly current concentration at turn-off.
[0008]
[Means for Solving the Problems]
The semiconductor device according to the present invention is a semiconductor device having a plurality of elements arranged side by side, each of the elements being a first conductivity type collector layer and a first conductivity type collector layer disposed on the first conductivity type collector layer. A two-conductivity type base layer; a first conductive type source layer formed in a surface of the second conductive type base layer; and the first conductive type source layer and the first conductive type collector layer A gate electrode disposed on a second conductivity type base layer via a gate insulating film; a source electrode in contact with the first conductivity type source layer and the second conductivity type base layer; and the first conductivity type collector. And a gate electrode of the element is electrically connected to a gate wiring formed on an insulating film thicker than the gate insulating film, and is electrically connected to the gate wiring. Connected to Serial gate electrode is characterized by being electrically connected to each other only via the gate line.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings, assuming that the first conductivity type is n-type and the second conductivity type is p-type.
(First embodiment)
In the first embodiment, a MOSFET will be described as an example. FIG. 1 is a plan view showing a main part of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of the semiconductor device along the line AA ′ in FIG. FIG. 3 is a cross-sectional view of the semiconductor device along the line BB ′ in FIG. The gate electrode 1 is formed on the surface of a p-type base layer 3 sandwiched between an n-type source layer (not shown) and an n-type collector layer 4. The source electrode 11 is formed on the source contact hole 2 so as to contact the n-type source layer and the p-type base layer 3. Each gate electrode 1 is drawn out to the outside of the element region, and is connected to each other through the gate wiring 14 in this portion.
[0011]
Conventionally, polysilicon and its metallized material are often used for the gate electrode 1. Further, when the gate electrode 1 is formed, the gate electrodes between the elements are mostly formed integrally. In this case, the portion used for connection of the gate electrode of each element does not form a channel, and thus is a portion unrelated to the operation of the element. The capacitance generated in this portion has an adverse effect on the operation of the semiconductor device.
[0012]
Certainly, even in the conventional element, as shown in FIG. 2, the second insulating film 10 made of, for example, an oxide film thicker than the gate insulating film 8 is formed, and the gate wiring 14 is formed thereon. Has been done.
[0013]
However, when an extremely thick oxide film (second insulating film 10) is formed in the conventional structure, if the gate electrode 1 is formed of polysilicon, polysilicon is formed at the boundary between the thin gate insulating film 8 and the thick oxide film. However, this causes disconnection, which becomes a factor of deteriorating the yield of the semiconductor device. In order to prevent this, an intermediate thickness insulating film may be formed, and polysilicon may be disposed in the gate wiring region step by step. However, this method increases the number of processes and reduces the effective area of the semiconductor device, leading to an increase in cost.
[0014]
When polysilicon is used as the gate electrode, a conventional semiconductor device often uses a metal such as aluminum in combination with the gate wiring in order to reduce the resistance. In the present embodiment, the gate contact hole 15 is continuously formed in the first insulating film 9, and the gate electrode and the gate wiring are brought into contact with each other.
[0015]
From a different point of view, it is not always necessary to integrally form the gate electrode made of polysilicon, and it is sufficient that the gate electrode is connected by a metal gate wiring.
[0016]
As shown in FIG. 3, the advantage of the structure in this embodiment is that the gate wiring is formed on the first insulating film 9 and the second insulating film 10 in the region between the gate electrode 1 and the gate electrode 1. Since 14 is arranged, the capacity of this portion can be significantly reduced.
(Second Embodiment)
FIG. 4 is a cross-sectional view of the second embodiment taken along line BB ′ in FIG. The second embodiment is characterized in that the p-type ring layer 12 and the p-type base layer 3 formed immediately below the gate wiring region shown in FIG. 3 are not directly connected.
[0017]
When the diffusion layer is formed in this way, the potential of the p-type ring layer 12 is not necessarily fixed to the potential of the source electrode 11, but takes an intermediate potential. At this time, since the potential difference between the gate wiring 14 and the inside of the element is reduced, the gate capacitance is effectively reduced.
(Third embodiment)
FIG. 5 is a cross-sectional view of the third embodiment taken along line BB ′ in FIG. The difference from FIG. 4 is that the p-type base layer 3 and the p-type ring layer 12 are connected by a low-concentration p-type low-concentration layer 16. As shown in FIG. 4, when the p-type base layer 3 and the p-type ring layer 12 are completely separated, the potential of the p-type ring layer 12 becomes unstable, the waveform is disturbed during switching, and the semiconductor device is destroyed. May lead to a connection. On the other hand, if the connection is made by the p-type low-concentration layer 16 as shown in FIG. 5, the potential becomes stable and no breakdown occurs.
(Fourth embodiment)
FIG. 6 is a cross-sectional view of the fourth embodiment along the line AA ′ in FIG. 1. In the first to third embodiments, the description has been given taking the MOSFET as an example, but FIG. 6 illustrates an IGBT as an example. The same effect as the above embodiment can be obtained.
(Fifth embodiment)
FIG. 7 is a cross-sectional view of the fifth embodiment along the line AA ′ in FIG. In order to further reduce the gate capacitance, a terrace gate structure is formed in which a part of the gate insulating film (the terrace insulating film 18) of the element portion is formed thick. By combining such a structure with the present invention, the gate capacity of the entire semiconductor device can be more effectively reduced, and high-speed switching and strong breakdown tolerance can be obtained.
[0018]
FIG. 8 is a cross-sectional view taken along line CC ′ in FIG. This is an example of a MOSFET using the terrace gate structure shown in FIG.
[0019]
In the first to fifth embodiments, in the semiconductor device formed of a plurality of elements, a gate wiring is provided on the thick insulating film to connect the gate electrode formed in each element. The gate capacitance generated in the wiring region can be reduced, leading to further high-speed operation of the semiconductor device and prevention of breakdown.
[0020]
This is because the gate wiring region occupies a non-negligible area in a semiconductor device using an insulated gate although it is not directly related to the operation of the element. This is because the gate capacitance can be reduced.
(Sixth embodiment)
FIG. 9 is a cross-sectional view showing a main part of a semiconductor device according to the sixth embodiment of the present invention. As illustrated, the gate electrode 106 is formed on the surface of a p-type base layer 103 sandwiched between an n-type source layer 104 and an n-type base layer 102.
[0021]
The portion of the element region A in FIG. 9 constitutes a main energization region, and most of the current flows through this portion during energization.
[0022]
Further, the junction termination region in FIG. 9 is a region provided for relaxing the electric field so that a high voltage is not applied to the element region, and a structure called RESURF is illustrated in this embodiment. In addition, a guard ring structure, a bevel structure, and the like are applicable.
[0023]
The source electrodes 107 of a plurality of elements arranged in the element region B sandwiched between the element region A and the junction termination region are connected to the source electrode 107 in the element region A via the limiting resistor 114. Thereby, the current flowing through the element region B is reduced by the limiting resistor 114. Further, the limiting resistor 114 applies a negative feedback to the current flowing through the element region B, and the current reducing effect can be further enhanced in the case of current concentration.
(Seventh embodiment)
FIG. 10 is a cross-sectional view showing the main parts of the semiconductor device according to the seventh embodiment. FIG. 9 is a conceptual diagram in which the limiting resistor 114 is externally attached to the element. However, since an assembly is complicated in an actual product, it is difficult to adopt such a structure.
[0024]
FIG. 10 shows a structure in which the limiting resistor 114 is integrally formed in the entire element. If, for example, polysilicon is used for the limiting resistor 114, the gate electrode step and the limiting resistor forming step can be performed at the same time, and the cost does not increase. Further, the resistance value can be arbitrarily set by setting the dose amount of the implantation or setting the pattern of the region to be implanted.
(Eighth embodiment)
FIG. 11 is a cross-sectional view showing a main part of a semiconductor device according to the eighth embodiment. In the embodiment shown in FIG. 9 and FIG. 10, the resistance is put in the source, but the same effect can be realized by another method. In the embodiment shown in FIG. 11, the gate capacitance of the element arranged in the element region B is made smaller than that of the element arranged in the element region A. In this way, the element disposed in the element region B can close the channel earlier at the time of turn-off than the element region A. Due to the charge neutrality condition established in the bipolar element, the current flows mainly through the element region A and hardly flows into the element region B which is the peripheral portion.
[0025]
In addition, this effect can also be realized by making the gate resistance connected to the second gate electrode 115 in the element region B smaller than the gate resistance connected to the gate electrode 106 in the element region A. The gate resistance here is a resistance that is usually inserted between the gate electrode and the gate power supply in order to stably perform the switching operation of the element.
(Ninth embodiment)
FIG. 12 is a plan view of a chip made according to the present invention as seen from above. The element region A is disposed at the center, and the element region B is disposed so as to surround the periphery thereof. A junction termination region is formed in the remaining peripheral portion.
[0026]
At this time, the width L of the element region B is preferably formed to be approximately the carrier diffusion length l. More specifically, 0.5 × l ≦ L ≦ 2 × l is preferable. By so doing, the element region A and the junction termination region can be efficiently separated, and the element region B can be made less likely to affect each other.
[0027]
FIG. 13 is a plan view of another embodiment of a chip produced according to the present invention as seen from above. In the present embodiment, the element region B formed so as to surround the entire element region A in FIG. 12 is arranged only at the corner portion of the element region A. The corner portion has a curvature in the junction termination region, so that the electric field tends to concentrate. Therefore, it is easy to destroy at turn-off. If the element region B is provided only in the corner portion as in the present embodiment, not only is destruction prevented, but the area occupied by the element region A increases, so that the current loss during steady energization is kept low. I can do it.
[0028]
The size of the element region B may be set similarly to the size described with reference to FIG.
(Tenth embodiment)
FIG. 14 is a cross-sectional view of the semiconductor device according to the tenth embodiment. In the tenth embodiment, both the effect of reducing the capacitance due to the insulating film thickness of the gate wiring portion shown in FIG. 1 and the current limiting effect of the peripheral portion shown in FIG. 9 are incorporated. It is. In the element designed in this way, not only does the element switch uniformly by reducing the gate capacitance, but also has a current-limiting effect in a portion where current is likely to concentrate, so that it is extremely resistant to destruction.
(Eleventh embodiment)
FIG. 15 is an example of a top view showing the arrangement of the p-type ring layer 109 and the p-type base layer 103 according to the present invention. In FIG. 14, the source electrode 107 in the element region B and the source electrode 107 in the element region A are illustrated as being connected by the limiting resistor 114, but actually, as shown in FIG. 15, each p-type base layer 103 is at least Since they are connected to each other by the p-type ring layer 109, this portion can be used in place of the limiting resistor 114. The resistance value of the limiting resistor 114 can be determined optimally according to the diffusion dose, and it is not necessary to use a complicated process. The same effect can be obtained not only by the dose amount but also by a method in which the diffusion pattern of the connection portion between the p-type base layer 103 and the p-type ring layer 109 is designed to be narrow, for example.
[0029]
In the ninth to eleventh embodiments, regarding a certain range of elements adjacent to the junction termination portion among the plurality of elements provided in the element region, by providing a current limiting resistor to the source electrode, Current concentration due to the flow of carriers from the junction termination during turn-off can be prevented.
[0030]
In addition, the current is not provided with a current limiting resistor, but the gate capacitance of the element in this part is reduced, or the gate resistance is reduced to cut off the channel at the time of turn-off at a faster timing than other parts. The effect of can be obtained.
[0031]
Of course, various modifications can be made without departing from the scope of the present invention.
[0032]
【The invention's effect】
According to the present invention, in a semiconductor device formed of a plurality of elements, a gate wiring is formed on a thick insulating film, whereby a gate generated in a gate wiring region connecting gate electrodes formed in each element. The capacity can be reduced, and the semiconductor device can be further operated at high speed and prevented from being destroyed.
[0033]
Further, the source electrodes of the plurality of elements arranged in the element region A forming the main current-carrying region and the element region B sandwiched between the junction termination regions are connected to the source electrode of the element region A via the limiting resistor 114. Has been. As a result, the current flowing through the element region B is reduced by the limiting resistor. Further, this limiting resistor applies a negative feedback to the current flowing through the element region B, and can further increase the current reducing effect when the current is concentrated.
[0034]
Moreover, there is no possibility of causing an increase in cost due to an increase in the process.
[Brief description of the drawings]
FIG. 1 is a plan view of a semiconductor device according to a first embodiment.
FIG. 2 is a step view of the semiconductor device according to the first embodiment.
FIG. 3 is a cross-sectional view of the semiconductor device according to the first embodiment.
FIG. 4 is a cross-sectional view of a semiconductor device according to a second embodiment.
FIG. 5 is a cross-sectional view of a semiconductor device according to a third embodiment.
FIG. 6 is a cross-sectional view of a semiconductor device according to a fourth embodiment.
FIG. 7 is a cross-sectional view of a semiconductor device according to a fifth embodiment.
FIG. 8 is a cross-sectional view of a semiconductor device according to a fifth embodiment.
FIG. 9 is a cross-sectional view of a semiconductor device according to a sixth embodiment.
FIG. 10 is a cross-sectional view of a semiconductor device according to a seventh embodiment.
FIG. 11 is a cross-sectional view of a semiconductor device according to an eighth embodiment.
FIG. 12 is a plan view of a semiconductor device according to a ninth embodiment.
FIG. 13 is a plan view of a semiconductor device according to a ninth embodiment.
FIG. 14 is a cross-sectional view of a semiconductor device according to a tenth embodiment.
FIG. 15 is a plan view of a semiconductor device according to an eleventh embodiment.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1,106 ... Gate electrode 2 ... Contact hole 3, 103 ... P-type base layer 4 ... N-type collector layer 5, 104 ... N-type source layer 6, 101 ... P-type emitter layer 7 ... Collector electrodes 8, 105 ... Gate insulation Film 9 ... first insulating film 10 ... second insulating film 11, 107 ... source electrode 12, 109 ... p-type ring layer 13 ... n-type buffer layer 14 ... gate wiring 15 ... gate contact hole 16 ... low concentration p-type Layers 17, 102 ... n-type base layer 18 ... terrace insulating film 108 ... drain electrode 110 ... RESURF layer 111 ... passivation film 112 ... n-type stopper layer 113 ... field plate 114 ... limiting resistor 115 ... second gate electrode 116 ... insulation film

Claims (5)

A semiconductor device having a plurality of elements arranged in parallel,
Each of the elements is
A first conductivity type collector layer;
A second conductivity type base layer disposed on the first conductivity type collector layer;
A first conductivity type source layer formed in a surface of the second conductivity type base layer;
A gate electrode disposed on the second conductivity type base layer sandwiched between the first conductivity type source layer and the first conductivity type collector layer via a gate insulating film;
A source electrode in contact with the first conductivity type source layer and the second conductivity type base layer;
A collector electrode in contact with the first conductivity type collector layer;
Each of the gate electrodes of the element is electrically connected to a gate wiring formed on an insulating film thicker than a gate insulating film, and the gate electrodes electrically connected to the gate wiring are connected to the gate. A semiconductor device which is electrically connected to each other only through wiring . Comprising a second conductivity type ring layer formed under the thick insulating film;
The semiconductor device according to claim 1, wherein the second conductivity type ring layer and the second conductivity type base layer are connected. Comprising a second conductivity type ring layer formed under the thick insulating film;
The semiconductor device according to claim 1, wherein the second conductivity type ring layer and the second conductivity type base layer are separated. Comprising a second conductivity type ring layer formed under the thick insulating film;
2. The semiconductor device according to claim 1, wherein the second conductivity type ring layer and the second conductivity type base layer are electrically connected via a low-concentration second conductivity type layer. The collector electrode is
2. The semiconductor device according to claim 1, wherein the semiconductor device is formed on a second conductivity type emitter layer formed on a surface of the first conductivity type collector layer.

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