JP3907940B2 - Exposure method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method EXPOSURE, in particular, U E ha - an exposure method according to the arrangement of the click - alignment mark.
[0002]
[Prior art]
FIG. 12 is a diagram showing an example of the arrangement of alignment marks in the prior art.
Conventionally, this type of alignment mark 10a to 10d is arranged on a scribe line between a chip 1 and a chip 1 of a wafer as shown in FIG. Then, alignment is performed by detecting several alignment marks in the horizontal direction (X direction) and vertical direction (Y direction) of the chip 1 at the time of exposure in the next process. In this case the alignment mark - click 10a, 10b, 10c, 10d are irregularities made by the foundation 6 group to be patterns in the short palisade are formed. Although this unevenness is detected optically and pattern recognition is performed, alignment marks in other processes cannot be arranged in an overlapping manner to prevent erroneous detection.
[0003]
Also, in recent years, planarization technology has become the mainstream in the manufacturing process of semiconductor devices, and unless the alignment mark is formed for each process, uneven steps are reduced and recognition becomes difficult. Is needed. As a result, the types of alignment marks are increasing. The alignment mark increases, and there are cases where one chip cannot fit in.
[0004]
FIG. 13 is a diagram showing another example of the alignment mark arrangement in the prior art. A method for avoiding this problem is disclosed in Japanese Patent Laid-Open No. 61-248526. In this method, as shown in FIG. 13, a plurality of chips (in this case, four chips in one exposure region) are imposed on a reticle, and alignment marks 31 to 38 are divided into the respective chips 21 to 24. Arranged. That is, the alignment marks 31, 32, 33, 34 are arranged on the scribe line between the chips 21, 22 and the chips 23, 24, and the alignment marks 35, 36, 37, 34 are arranged on the adjacent (lower) scribe line. 38 are arranged side by side. When detecting these alignment marks, the coordinates on the wafer are designated and predetermined alignment is performed.
[0005]
However, as the pattern becomes finer, the difference in the finished dimensions between the center and the outer periphery of the reticle is becoming a problem, and it is necessary to use only the vicinity of the center of the reticle as much as possible.
[0006]
The required alignment mark varies depending on the process. For example, when a chip size of about 12 mm □ is required, the chip size is limited to about 16 mm □ in consideration of variations during exposure. ing.
[0007]
Chip size 12 mm □ to 16 mm □: Accessories can be arranged by single-sided attachment (one chip in one exposure area).
[0008]
8mm □ or less: Accessories can be placed by imposing multiple impositions and making the total chip size more than 12mm □.
[0009]
8 mm □ to 12 mm □: A plurality of impositions are impossible. Accessories cannot be placed.
Thus, depending on the chip size, accessories (alignment marks, check transistors, etc.) may not be arranged.
[0010]
[Problems to be solved by the invention]
As described above, the problem with the prior art is that depending on the chip size, the alignment mark may not be arranged. If What becomes, alignment mark - although coming increase in the number of click, patterns formable area on the reticle is narrowed and can be arranged by increasing the number of imposition (if 4 chips described above in FIG. 13) This is because it has disappeared.
[0011]
Accordingly, an object of the present invention, the exposure step is alignment mark without compromising the accuracy of the time of exposure also increased - to provide a click exposure method - the wafer can be placed click - alignment mark.
[0012]
[Means for solving the problem]
A feature of the present invention is that the IC pattern and the alignment mark are moved on the wafer by an amount of movement determined by the chip size of the IC pattern using the reticle on which the IC pattern and the alignment mark are formed. in line intends eXPOSURE mETHOD exposure of the wafer by using the alignment marks arranged in the same position on different reticles - when exposing above the alignment mark by selecting the row or column exposed on the wafer by exposing the a that eXPOSURE mETHOD to place the alignment marks at different positions on the wafer corresponding to different reticles.
[0013]
Further, the present invention uses the reticle on which the IC pattern and the alignment mark are formed, and moves the IC pattern and the alignment mark on the wafer by an amount of movement determined by the chip size of the IC pattern. in line intends eXPOSURE mETHOD exposure of the wafer by using the alignment marks arranged at a position overlapping on different reticles - when exposing above the alignment mark by selecting the row or column exposed on the wafer By performing exposure, alignment marks corresponding to the different reticles may be arranged at different positions on the wafer.
[0014]
The alignment mark is preferably formed on a scribe line.
[0015]
Another feature of the present invention is that, using a reticle on which an IC pattern and an alignment mark are formed, the IC pattern and the alignment mark are moved on a wafer by an amount of movement determined by the chip size of the IC pattern. - in the row intends eXPOSURE mETHOD exposure of click, one alignment mark is divided placed on a reticle, a wafer using the a-line instrument marks which are the divided and arranged in the same position on different reticles - exposed above when, to the divided arranged alignment mark is re-synthesized to the one alignment mark on the wafer by selectively exposing according to said divided arranged alignment marks in rows or columns, the eXPOSURE place the one of the alignment marks corresponding to different reticle at different positions on the wafer Is the method.
[0016]
Another feature of the present invention is that, using a reticle on which an IC pattern and an alignment mark are formed, the IC pattern and the IC pattern are moved on a wafer by an amount of movement determined by the chip size of the IC pattern. alignment mark - in the row intends eXPOSURE mETHOD exposure of click, one alignment mark is divided placed on a reticle, a wafer using the a-line instrument marks which are the divided disposed at a position overlapping on different reticles - up when exposing, so that the divided arranged alignment mark is re-synthesized to the one alignment mark on the wafer by selectively exposing according to said divided arranged alignment marks in a row or column The one alignment mark corresponding to the different reticle is arranged at a different position on the wafer. It is also the be that exposure light method.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Next, the present invention will be described with reference to the drawings.
[0018]
Figure 1 (a) and (b) and (c) the alignment mark for explaining the exposure light method of an embodiment of the present invention - is a diagram showing the data - click layout de of. The wafer alignment mark - clause de by using a CAD (C-omputer Aided Design) - When creating a data, the different layers alignment mark - arranging repeatedly click. For example, the alignment mark 2 shown in FIG. 1A includes a single-layer alignment mark 2-1 shown in FIG. 1B and a five-layer alignment mark 2-2 shown in FIG. Are placed in layers.
[0019]
Similarly, the alignment mark 3 in FIG. 1A is a two-layer alignment mark and a six-layer alignment mark, and the alignment mark 4 is a three-layer alignment mark and a seven-layer alignment mark. The alignment mark 5 and the alignment mark 5 are arranged by superposing a 4-layer alignment mark and an 8-layer alignment mark.
[0020]
When data is created using CAD or the like in this way, alignment marks of different layers are arranged on the reticle for one layer, the reticle for two layers,..., The reticle for eight layers. Since the stacked alignment mark uses different layers, as shown in FIGS. 1B and 1C, one alignment mark 2-1 and five alignment marks 2-2 are arranged. Is created on each reticle. Other layers are created similarly.
[0021]
Figure 2 is the alignment mark 1 - click Layout data of - first alignment layout on the wafer for explaining the exposure light method with reference to data, Figure 3 is the alignment mark 1 - click Layout data of - second alignment layout on the wafer for explaining the exposure light method using the data, and Figure 4 is a alignment mark 1 - click layout data of - a wafer for explaining the exposure light method using a data It is the 1st and 2nd alignment arrangement drawing of the top. Next, an exposure method will be described with reference to FIGS. 2, 3 and 4 using the reticle having the alignment mark shown in FIG.
[0022]
First, the case of performing exposure from one to four layers will be described with reference to FIG. When exposure is performed using the single-layer reticle, the right-side light shielding plate is opened with respect to the chips 1 in the odd-numbered rows, and the alignment mark 2-1 is exposed. When the even-numbered rows are exposed, the exposure apparatus is controlled to expose so that the right-side light shielding plate is closed and the alignment mark 2-1 portion of the reticle is hidden. When exposing odd-numbered rows, the lower light-shielding plate on the chip 1 is opened to expose the alignment mark 2-1, and when exposing even-numbered rows, the lower light-shielding plate on the chip 1 is exposed. And the exposure apparatus is controlled so as to close the alignment mark 2-1. In the same manner, two to four layers are exposed in the same manner.
[0023]
Next, a case where exposure is performed from 5 layers to 8 layers will be described with reference to FIG. First, when exposure is performed using a five-layer reticle, when the odd-numbered rows are exposed, the light shielding plate on the right side of the chip 1 is closed and the alignment mark 2-2 is hidden and exposed, and the even-numbered rows are exposed. When the exposure is performed, the exposure apparatus is controlled so that the light shielding plate on the right side of the chip 1 is opened and the alignment mark 2-2 is exposed. Further, when exposing odd-numbered columns, the lower light-shielding plate of the chip 1 is closed to hide the alignment mark 2-2 portion, and when exposing even-numbered columns, the lower light-shielding of the chip 1 is shielded. The exposure apparatus is controlled so that the plate is opened and the alignment mark 2-2 is exposed. Similarly, 6 to 8 layers are exposed.
[0024]
As a result, as shown in FIG. 4, as the wafer is completed, one layer alignment mark 2-1 and five layers alignment mark 2-2 are alternately formed. Thus, the alignment mark of each layer can be arbitrarily arranged at a different position by combining the opening / closing of the light shielding plate and the chip of the column or row to be exposed.
[0025]
A technique of using a light shielding plate at the time of exposure is not particularly shown in the drawing, but is disclosed in, for example, Japanese Patent Application Laid-Open No. 5-291106 as a technique for exposing a TEG chip only at a specific position in a wafer. . However, this exposure method requires a simple mechanism for opening and closing the light shielding plate. For example, the opening / closing mechanism includes a leaf spring that always pushes the light shielding plate so as to advance the light shielding plate and cover the alignment mark, and a piezoelectric element that moves the light shielding plate backward against the repulsive force of the leaf spring. The mechanism is simple. Then, a light shielding plate is opened by applying a predetermined voltage to the piezoelectric element. This voltage application signal may be transferred from the sequence controller of the exposure apparatus.
[0026]
Figure 5 (a) and (b) the wafer for explaining that EXPOSURE METHOD put to another embodiment of the present invention - the partial plan view (a) and layout de - data view, FIG. 6 (a) and (B) is a figure which shows the reticle for 1 layers, and the reticle for 5 layers. In the embodiment described above, the right to the plane of the side and lower side in the short Suzaku shaped alignment mark chip 1 - has been described by way of arranging the click, EXPOSURE how put in this embodiment As shown in FIG. 5A, the alignment mark in FIG. 5 is composed of a pattern group in which the foundation 6 to be a pattern is repeatedly arranged. In the alignment mark 2b , the foundations 6 are arranged in a row below the center line of the scribe line region, that is, on the chip 1 on the lower side of the paper surface. On the other hand, in the alignment mark 2a , the foundations 6 are arranged in two rows above the center line of the scribe line region, that is, below the chip 1 above the chip 1. Also in this case, exposure can be performed so as not to overlap other layers by opening and closing the light shielding plates provided on the four sides of the chip.
[0027]
To explain this structure with reference to FIG. 5 (b), CAD tool - de using such Le - When creating a data is alignment mark - consisting of patterns set of a row of one layer as a click 2a 6 alignment mark of (a) - alignment of Figure 6 the click 2-1a and five layers (b) Ma - arranged to overlap with the click 2-2a, alignment mark - consisting of patterns set of two rows as click 2b 1 alignment mark of FIG layer 6 (a) - consisting of two rows patterns group of 6 of the click 2-1b and five layers (b) alignment mark - to place overlapping with the click 2-2b.
[0028]
Similarly, alignment mark - click. 3a alignment mark formed of patterns set of one row of two layers - arranged repeatedly click, alignment mark - - alignment mark made by the click and patterns set of one row of six layers click 3b is alignment mark with two rows patterns group of two layers - click and 6 layers of two rows of patterns over consisting in emission group alignment mark - to click and overlapping arrangement [0029]
Furthermore, alignment mark - click 4a is alignment mark formed of patterns set of a row of three layers - arranged click and stacked, alignment mark - - alignment mark consisting of a row patterns group of click and 7-layer click. 4b three layers of two rows of patterns alignment made of group Ma - click and 7 layers of two rows of patterns over consisting in emission group alignment mark - to click and overlapping arrangement.
[0030]
The alignment mark - click 5a is alignment mark formed of patterns set of one row of four layers - arranged click and stacked, alignment mark - - alignment mark consisting of a row patterns group of click and eight layers click 5b is four layers of two rows of patterns alignment made of group Ma - click and eight layers of two rows of patterns over consisting in emission group alignment mark - to click and overlapping arrangement.
[0031]
Thus, alignment mark consisting of patterns set of one row - click and alignment mark made by the patterns set two rows - be arranged on the four sides of the reticle corresponding to click on each layer, each layer of the alignment mark - clause Can be arranged so that they do not overlap.
[0032]
7, 8 and 9 are layout diagrams of a wafer alignment mark for explaining an exposure method according to another embodiment of the present invention. Next, an exposure method using the reticle prepared as described above will be described. When exposure is performed using a single-layer reticle, as shown in FIG. 7, when exposing odd-numbered rows, the light shielding plates on both the left and right sides of the chip 1 are opened, and both alignment marks 2-1a and 2-1b are opened. When the exposure is performed and the even-numbered rows are exposed, the exposure apparatus is controlled so that the light shielding plates on both the left and right sides of the chip 1 are closed and the alignment marks 2-1a and 2-1b are both hidden. Further, when exposing odd-numbered columns, the light shielding plates on both the upper and lower sides of the chip 1 are opened, the alignment marks 2-1a and 2-1b are exposed, and when exposing even-numbered columns, the chip 1 The exposure apparatus is controlled to close the upper and lower light shielding plates and hide the alignment mark.
[0033]
Similarly, exposure of 2 to 4 layers is performed. Next, the case of performing exposure from 5 to 8 layers will be described with reference to FIG. First, in the case of exposing with a five-layer reticle, when exposing odd-numbered rows, the light shielding plates on both the left and right sides of the chip 1 are closed to hide both the alignment marks 2-2a and 2-2b, and even-numbered rows. When exposing this row, the exposure apparatus is controlled so that the light shielding plates on both the left and right sides of the chip are opened and the alignment marks 2-2a and 2-2b are exposed. When exposing odd-numbered columns, the light shielding plates on both the upper and lower sides of the chip 1 are closed to hide both the alignment marks 2-2a and 2-2b. When exposing even-numbered columns, the upper and lower sides of the chip 1 are exposed. The exposure apparatus is controlled so that the light shielding plates on both sides are opened and the alignment marks 2-2a and 2-2b are exposed.
[0034]
Thus, if exposure is performed by controlling the opening and closing of the upper and lower (X direction) and left and right (Y direction) light shielding plates of the chip 1, as a result, as shown in FIG. Marks 2-1a and 2-1b and five layers of alignment marks 2-2a and 2-2b are alternately formed. Further, as described above, an alignment mark made up of one row of pattern groups and an alignment mark made up of two rows of pattern groups are arranged adjacent to each other, resulting in three rows of pattern groups necessary for the exposure apparatus. An alignment mark can be formed.
[0035]
FIGS. 10A and 10B are views for explaining a modification of the alignment mark according to the exposure method of the present invention. There are cases where the portion serving as the foundation 6 of the pattern of the alignment mark is transmitted (FIG. 10a) and light shielding (FIG. 10b). Then, as shown in FIG. 10A, layout data is created in which layers that are transparent to the portion serving as the basis 6 of the alignment mark pattern are overlapped. Thereafter, when exposure is performed using the created reticle, patterning is selectively performed using a light shielding plate.
[0036]
Figure 11 (a) and (b) is a partial plan view of the wafer for explaining that EXPOSURE METHOD put in other other embodiments of the present invention. The wafer - alignment mark - exposure method click is either shielded or partially shielded all regions of the scribe line of the periphery of the chip 1.
[0037]
For example, as shown in FIG. 11A, a light shielding plate having a light shielding region 7 that is equal to or slightly longer than the side of the chip 1 is opened and closed along one side of the chip 1 and selectively exposed. In this case, the alignment marks 12, 13, 14, and 15 may be arranged at any position.
[0038]
As another method, for example, as shown in FIG. 11B, a light shielding region 7 may be partially provided. According to this method, the alignment marks 12 and 13 can be selectively exposed on each side of the chip 1. On the other hand, by arranging the check transistor 8 which is one of the accessories on the right side of the paper surface, each side of the chip 1 can be exposed.
[0039]
【The invention's effect】
As described above, according to the present invention, on the alignment mark arrangement data, the alignment marks are arranged so as to overlap each other, and each layer is supported based on the created layout data. Each time a reticle is manufactured and exposed, the alignment mark portion is selectively shielded from light so that the overlapping alignment marks can be placed at different positions and as with imposition. Alignment marks across multiple chips Alignment marks can be placed on the periphery of the chip where the IC pattern is formed. Therefore, even if the number of exposure steps increases, alignment can be performed for each exposure step. There is no loss of accuracy.
[Brief description of the drawings]
[1] alignment mark for explaining the exposure light method of an embodiment of the present invention - click Layout data of - a diagram showing the data.
[Figure 2] of alignment mark 1 - click Layout data of - a first alignment layout on the wafer for explaining the exposure light method using the data.
[Figure 3] of alignment mark 1 - click Layout data of - a second alignment layout on the wafer for explaining the exposure light method using the data.
[Figure 4] of alignment mark 1 - click Layout data of - a first and second alignment layout on the wafer for explaining the exposure light method using the data.
[5] the wafer for explaining that EXPOSURE METHOD put to another embodiment of the present invention - partial plan view of (a) and layout de - a data view.
FIG. 6 is a view showing a 1-layer reticle and a 5-layer reticle.
FIG. 7 is a layout view of an example of a wafer alignment mark for explaining an exposure method according to another embodiment of the present invention.
FIG. 8 is a layout view of another example of a wafer alignment mark for explaining an exposure method according to another embodiment of the present invention.
FIG. 9 is a layout view of a wafer alignment mark synthesized with FIGS. 7 and 8 for describing an exposure method according to another embodiment of the present invention.
FIG. 10 is a view for explaining a modification of the alignment mark according to the exposure method of the present invention.
11 is a partial plan view of the wafer for explaining that EXPOSURE METHOD put in other other embodiments of the present invention.
FIG. 12 is a diagram showing an example of the arrangement of alignment marks in the prior art.
FIG. 13 is a diagram showing another example of the arrangement of alignment marks in the prior art.

Claims (5)

IC pattern and alignment mark - click using the reticle which is formed, the wafer - the while moving only the amount of the movement amount determined by the chip size of the IC pattern on IC pattern and alignment mark - line intends dew exposure of click In the light method,
Corresponding to the different reticles by selecting and exposing the alignment mark on the wafer when exposing on the wafer using alignment marks arranged at the same position on different reticles. eXPOSURE how to said placing the alignment marks at different positions on the wafer. IC pattern and alignment mark - click using the reticle which is formed, the wafer - the while moving only the amount of the movement amount determined by the chip size of the IC pattern on IC pattern and alignment mark - line intends dew exposure of click In the light method,
Corresponding to the different reticles by selecting and exposing the alignment marks on the wafer when exposing on the wafer using alignment marks arranged at overlapping positions on different reticles. eXPOSURE how to said placing the alignment marks at different positions on the wafer. EXPOSURE method according to claim 1 or 2, wherein the forming the alignment mark on the scribe line. IC pattern and alignment mark - click using the reticle which is formed, the wafer - the while moving only the amount of the movement amount determined by the chip size of the IC pattern on IC pattern and alignment mark - line intends dew exposure of click In the light method,
One alignment mark is divided placed on a reticle, a wafer using the A-line instrument marks which are the divided and arranged in the same position on different reticles - when exposing above, the divided arranged alignment marks wafer The one alignment mark corresponding to the different reticle is obtained by selectively exposing the divided alignment marks according to rows or columns so that the alignment marks are recombined with the one alignment mark. eXPOSURE how to characterized in that arranged in different positions on the wafer. IC pattern and alignment mark - click using the reticle which is formed, the wafer - the while moving only the amount of the movement amount determined by the chip size of the IC pattern on IC pattern and alignment mark - line intends dew exposure of click In the light method,
One alignment mark is divided placed on a reticle, a wafer using the A-line instrument marks which are the divided disposed at a position overlapping on different reticles - when exposing above, the divided arranged alignment marks wafer The one alignment mark corresponding to the different reticle is obtained by selectively exposing the divided alignment marks according to rows or columns so that the alignment marks are recombined with the one alignment mark. eXPOSURE how to characterized in that arranged in different positions on the wafer.

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