JP3901677B2 - Driving method of nonvolatile semiconductor memory device - Google Patents

Description

  The present invention relates to a method for driving a nonvolatile semiconductor memory device, and more particularly to a method for driving a flash memory cell using a P-channel type memory cell.

  In recent years, a method using a P-channel type memory cell has been proposed for a flash memory (for example, Patent Document 1). One example of the conventional driving method of the memory cell will be described below.

FIG. 13 shows a memory cell array using conventional P-channel type memory cells.
The P channel type memory cell 1 includes a floating gate type memory transistor 18 having a gate electrode connected to a floating gate and a P channel type selection transistor 2 connected in series to the floating gate type memory transistor 18. 2 is arranged adjacent to.

  The floating gate type memory transistor 18 has a P-type drain connected to the P-type source of the selection transistor 2, a P-type source connected to the common source line 17, and a control gate connected to the control gate line 14. The selection transistor 2 has a P-type drain connected to the bit line 16 having 16a to 16d and a selection gate connected to the word line 15 having 15a to 15d.

Further, the conventional memory cell array includes a source opening means 17a that can turn on and off the connection between the common source line 17 and the power supply voltage Vcc.
Here, the memory cell has a positive threshold value when it is in a written state, and has a negative threshold value when it is in an erased state.

  As a driving method, at the time of writing, hot electrons caused by band-to-band tunneling are injected from the drain of the floating gate type memory transistor 18 to the floating gate to perform writing. At the time of erasing, erasing is performed by extracting electrons of the floating gate of the floating gate type memory transistor 18 through a tunnel oxide film on the N type region by an FN (Fowler-Nordheim) tunnel current.

With regard to the memory cell driving method as described above, according to the conventional technique, at the time of writing, the N-type region is set to the power supply voltage Vcc, the first negative voltage is applied to the bit line 16, and the first positive voltage is applied to the control gate line 14. A voltage is applied, a second negative voltage is applied to the word line 15, the source line 17 is opened by the source opening means 17a, and hot electrons due to the band-to-band tunnel are injected from the P-type drain of the memory cell to the floating gate. And write.
Special table 2001-506063 gazette

The floating gate type memory transistor 18 and the selection transistor 2 are formed on the N type substrate 13 as shown in FIG.
The floating gate type memory transistor 18 includes a P + drain 7 and a source 8 formed on the N type substrate 13 and a tunnel oxide film 6 between them and the floating gate 4 and the dielectric film 5 on the N type substrate 13. A gate 3 is formed.

  The selection transistor 2 is configured by forming a selection gate 9 on the N-type substrate 13 via an oxide film 10 between the P + source 7 and drain 12 formed on the N-type substrate 13.

  As the bias at the time of writing the memory cell, Vsg = −8 V is applied to the word line 15 connected to the selection gate 9, Vsub = Vcc = 2.5 V is applied to the N-type substrate 13, and the source 8 of the memory cell 1 is applied. The source line 17 connected to Vs = opens, Vd = −6V is applied to the bit line 16 connected to the drain 12 of the select transistor 2, and the control gate line 14 connected to the control gate of the memory cell 1 is applied. Vcg = 10.5V is applied.

At the time of threshold measurement, as shown in FIG. 15, Vsg = −10V, Vsub = Vs = 0V, Vd = −1.5V, and drain current = −1 μA.
FIG. 16 shows the write characteristics of a single memory cell. As can be seen from FIG. 16, the threshold value reaches 6.9 V at 3 msec, and then abrupt writing occurs at 6 msec.

As described above, when the writing operation is further continued from the normal writing state, abrupt writing occurs. This is overwriting.
On the other hand, the erased state of the memory cell is a state in which electrons are removed from the floating gate. The threshold is about -3V.

  At the time of writing, electrons generated by the band-to-band tunnel are injected into the floating gate. As the writing progresses, the potential of the floating gate gradually decreases. When the potential of the floating gate reaches a voltage at which the channel current starts to flow, hot electrons associated with the channel current are injected into the gate. At this time, rapid writing occurs, causing excessive writing.

  In the conventional example, since the source line is in an open state, no steady channel current flows, but the source line has a junction capacitance, and hot electrons due to the temporary channel current flowing into this capacitance are gated. Will be injected.

  When writing, the bit line voltage necessary for writing is applied to multiple bit lines at the same time. If this phenomenon occurs, the channel current of the memory cell that caused excessive writing flows, and the capacitor connected to the source is charged. Is done. Since the supply current amount of the bit line voltage generation circuit is finite, the supply current to other memory cells which are simultaneously writing becomes unstable. For this reason, while writing of some bits is deep, writing of other bits is shallow, and the writing distribution is greatly expanded, reducing the reliability margin.

  Accordingly, the distribution of conventional writing and erasing is roughly as shown in FIG. 17, and the distribution A of the writing cells is the distribution B of the memory cells that are written by hot electrons due to the band-to-band tunneling, and the channel current. The distribution C of the memory cells that have been overwritten by hot electrons caused by the overlap overlaps and greatly varies.

  An object of the present invention is to provide a method for driving a nonvolatile semiconductor memory device capable of suppressing excessive writing due to hot electrons caused by channel current in a P-channel type memory cell that performs writing by hot electrons caused by band-to-band tunneling. Yes.

In order to solve the above problems, a driving method of a nonvolatile semiconductor memory device according to the present invention is a driving method of a nonvolatile semiconductor memory device having a P-channel memory cell formed on an N-type region, and the P The channel type memory cell includes a floating gate type memory transistor and a selection transistor connected in series to the floating gate type memory transistor. The floating gate type memory transistor has a control gate connected to a control gate line and a source connected to a common source line. The drain is connected to the source of the selection transistor, the selection transistor is connected to the word line, the drain is connected to the bit line, and the P-channel memory cell has a positive threshold in the written state. And has a negative threshold in the erased state, and writing to the P-channel memory cell An interband tunnel hot electron is injected from the drain of the type memory transistor to the floating gate, and erasing of the P-channel type memory cell is performed by a tunnel oxide film between the floating gate and the N type region of the floating gate type memory transistor. And extracting the electrons of the floating gate electrode to the N-type region through the N-type region. During the writing, the N-type region is used as a power supply voltage, a first negative voltage is applied to the bit line, and the control gate A first positive voltage is applied to the line, a second negative voltage is applied to the word line, and a source voltage lower than the power supply voltage is applied to the source line, which is conventionally open during writing. and than the power supply voltage to the source line applies an source voltage of the low pressure, at the time of the writing, it is applied to the source line A voltage lower than the power supply voltage causes overwriting due to injection of hot electrons into the floating gate due to a temporary channel current flowing into the junction capacitance of the source line when the source line is opened. The voltage until the overwriting occurs when the voltage lower than the power supply voltage is applied to the source line is longer than the time until the N-type of the floating gate type memory transistor. By applying a potential difference between the substrate and the P-type source, it is possible to suppress channel formation and suppress excessive writing by the substrate bias effect.

  In the driving method of the nonvolatile semiconductor memory device of the present invention, the first negative voltage is about -3V to -6V, the first positive voltage is about 6V to 11V, and the second voltage is written. It is preferable that the negative voltage is about −5V to −8V, and the source voltage is lower than the power supply voltage by 0.7V or more.

  In this way, the N-type substrate is set to the power supply voltage Vcc, a voltage of Vcc−0.7 V or less is applied to the P-type source, and a potential difference of 0.7 V or more can be set between the N-type substrate and the P-type source. Compared with the case where the conventional source is opened, an effect of suppressing excessive writing can be obtained.

In the driving method of the nonvolatile semiconductor memory device of the present invention, it is preferable that the source voltage at the time of writing is a ground potential.
By doing so, channel formation at the time of writing can be suppressed and excessive writing can be suppressed without requiring a power source for generating a source voltage.

  According to the driving method of the nonvolatile semiconductor memory device of the present invention, the gate voltage at which the channel current starts to flow is changed to the negative side by setting the potential difference between the N-type substrate and the P-type source using the substrate bias effect, By suppressing channel formation, excessive writing can be suppressed.

In addition, by setting a potential difference of 0.7 V or more between the N-type substrate and the P-type source, an effect of suppressing excessive writing can be obtained as compared with the conventional writing method.
Furthermore, by forming the P-type source as the ground potential and making the potential difference between the N-type substrate and the P-type source equal to the difference between the power supply voltage and the ground potential, channel formation at the time of writing without requiring a power source for generating the source voltage is possible. And overwriting can be suppressed.

Before describing the present invention, first, the gate current injected into the floating gate of the floating gate type memory transistor 18 will be described.
In the floating gate type memory transistor 18 in which the gate electrode is connected to the floating gate of the memory cell, for example, as shown in FIG. 9, the N type region and the P type source are set to the ground potential, and −8V is applied to the P type drain. Then, the measurement was performed by changing the floating gate potential.

In this case, the relationship between the voltage of the floating gate, the gate current, and the drain current is as shown in FIG.
As shown in FIG. 10, the type of gate current varies depending on the potential of the floating gate. In this example, when the potential of the floating gate is −1 V or more, the gate current is generated by hot electrons caused by the band-to-band tunneling. When the potential of the floating gate is −1 V or less, the gate current is a gate current in which hot electrons due to the channel current are injected into the gate. The gate current in which hot electrons due to the channel current are injected into the gate rapidly increases with a change in the potential of the floating gate and has a peak.

  When the memory cell is being written, as the writing progresses, hot electrons caused by the band-to-band tunnel are injected into the floating gate, the potential of the floating gate is lowered, and the potential of the floating gate reaches the voltage at which the channel current flows. Then, the gate current suddenly flows and excessive writing occurs.

  Next, in the floating gate transistor 18, as an example, as shown in FIG. 11, the N-type region is set to the ground potential, the P-type source is set to −1 V, and the P-type drain is applied to −8 V. The measurement was performed while fluctuating.

In this case, the relationship between the voltage of the floating gate, the gate current, and the drain current is as shown in FIG.
As shown in FIG. 12, when the potential of the floating gate 4 is −2.3 V or more, the gate current is a gate current in which hot electrons due to the band-to-band tunnel are injected into the gate, and the potential of the floating gate is − When the voltage is 2.3 V or less, the gate current is a gate current in which hot electrons due to the channel current are injected into the gate.

  Comparing FIG. 10 and FIG. 12, by setting the potential difference between the N-type region and the P-type source, the gate potential at which the channel current starts flowing varies. This is a general phenomenon called the substrate bias effect.

  Due to the substrate bias effect, the gate voltage at which the channel current starts to flow in the negative direction as the potential between the P-type sources is negatively increased with respect to the N-type substrate. Accordingly, the gate voltage generated by hot electrons accompanying the channel current also moves in the negative direction.

  Therefore, with the progress of writing, even when electrons are injected into the floating gate 4 and the floating gate 4 is negatively charged, the potential of the P-type source is increased negatively with respect to the N-type substrate 13, thereby forming a channel. Therefore, the injection of hot electrons into the floating gate due to the channel current is suppressed, and it is possible to prevent overwriting.

FIG. 1 shows a memory cell array using a P-channel type memory cell of the present invention, and FIG. 2 shows a P-channel type memory cell related to the present invention.
A P channel type floating gate type memory transistor 18 is arranged adjacent to the P channel type selection transistor 2. The P-type drain 7 of the floating gate type memory transistor 18 is connected to the P-type source 11 of the selection transistor 2, and the P-type source 8 of the floating gate type memory transistor 18 is connected to the common source line 17. The control gate 3 of the transistor 18 is connected to the control gate line 14, the P-type drain 12 of the selection transistor 2 is connected to the bit line 16, and the selection gate is connected to the word line 15. The memory cell array of the present invention includes source voltage switching means 17b, and the common source line 17 can be connected to either Vcc or the source bias generation circuit 19.

Here, the floating gate type memory transistor 18 has a positive threshold value when in a writing state, and has a negative threshold value when in an erasing state.
As a driving method, at the time of writing, hot electrons caused by band-to-band tunneling are injected from the P-type drain 7 of the floating gate type memory transistor 18 to the floating gate 4 to perform writing. At the time of erasing, erasing is performed by extracting electrons from the floating gate 4 of the floating gate type memory transistor 18 through the tunnel oxide film 6 on the N type region by the FN tunnel current.

  With respect to the above memory cell driving method, in the present invention, at the time of writing, the N-type region is set to the power supply voltage Vcc, the first negative voltage is applied to the bit line 16, and the first positive voltage is applied to the control gate line 14. , A second negative voltage is applied to the word line 15, a source voltage lower than the power supply voltage Vcc is applied to the common source line 17 from the source bias generation circuit 19, and hot electrons due to the band-to-band tunneling are generated. Writing is performed by injecting from the P-type drain 7 of the floating gate type memory transistor 18 to the floating gate 4.

  In this way, by applying a source voltage lower than the power supply voltage Vcc to the source 8, channel formation is suppressed using the substrate bias effect, and injection of hot electrons due to channel current into the floating gate is suppressed. And overwriting can be suppressed.

  Specifically, in the configuration of FIG. 1, at the time of writing, the N-type substrate 13 which is an N-type region is set to the power supply voltage Vcc, the first negative voltage is about -3V to -6V, and the second negative voltage is About −5V to −8V, the first positive voltage is about 6V to 11V, the source voltage is (Vcc−0.7) V or less, and hot electrons caused by band-to-band tunneling are transferred to the P-type drain of the memory cell. To the floating gate.

  When the relationship between the potential difference applied between the N-type substrate and the P-type source and the time required for overwriting is plotted, as the potential difference between the N-type substrate 13 and the source is increased as shown in FIG. The time is getting longer.

  In the writing by the conventional driving method, as shown in FIG. 16, overwriting occurs in about 6 msec. This is because the potential difference between the N-type substrate 13 and the P-type source is set to 0.7V. It is equivalent, and it is shown that there is an improvement effect in suppressing overwriting by setting the potential difference between the N-type substrate and the source to 0.7 V or more.

  As an example of the bias at the time of writing, as shown in FIG. 3, Vsg = −8V, Vsub = 2.5V, Vs = 1.3V so that the potential difference between the N-type region and the P-type source becomes 1.2V. , Vd = -6V, and Vcg = 10.5V, the write characteristics at this time are as shown in FIG. 4, and the threshold value reaches 7.6 V in about 30 milliseconds, and then overwriting is performed in about 60 milliseconds. Has occurred. In this example, there is an improvement effect of 10 times with respect to the excessive writing occurrence time by the conventional writing method.

FIG. 6 shows a specific configuration in which the source voltage is set to the ground potential during the writing.
At the time of writing, the N-type substrate is at the power supply voltage Vcc, the P-type source is at the ground potential, and hot electrons caused by the band-to-band tunnel are injected from the P-type drain of the memory cell to the floating gate. At this time, the first negative voltage is about -3V to -6V, the first positive voltage is about 6V to 11V, the second negative voltage is about -5V to -8V, and the source voltage is based on the power supply voltage. In FIG. 6, the common source line 17 is switched to the ground potential by the source voltage switching means 17b in order to make the voltage lower by 0.7V or more. As an example, as shown in FIG. 7, Vsg = −8V, Vsub = 2.5V, Vs = ground potential, Vd = −6V, and Vcg = 10.5V.

In this way, the potential difference between the N-type substrate and the P-type source becomes equal to Vcc, and the effect of suppressing overwriting can be obtained without requiring a new power supply for supplying the source potential.
According to the present invention, in the distribution of writing and erasing, excessive writing is suppressed as shown in FIG. 8, and the distribution of the writing state converges.

  The method for driving a nonvolatile semiconductor memory device of the present invention is effective as a method for driving a flash memory cell using a P-channel type memory cell.

The figure which shows the memory cell array of this invention Memory cell configuration diagram according to the present invention The figure which shows the example of write-in bias of this invention Write characteristics of the present invention Diagram showing time to overwriting The figure which shows another memory cell array of this invention The figure which shows another example of a write bias of this invention The figure which shows distribution of writing and erasing by this invention Diagram showing bias for measuring gate current and drain current of floating gate transistor Diagram showing the gate current and drain current of a floating gate transistor Diagram showing bias for measuring gate current and drain current of floating gate transistor Diagram showing the gate current and drain current of a floating gate transistor A diagram showing a conventional memory cell array Diagram showing conventional write bias Diagram showing threshold measurement bias Diagram showing conventional write characteristics Diagram showing the distribution of conventional programming / erasing

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Memory cell 2 Select transistor 3 Memory cell control gate 4 Floating gate 5 Dielectric film 6 Tunnel oxide film 7 Memory cell drain 8 Memory cell source 9 Select gate 10 Oxide film 11 Select transistor source 12 Select transistor drain 13 N Type substrate 14 Control gate line 15 Word line 16 Bit line 17 Common source line 17a Source release means 17b Source voltage switching means 18 Floating gate type memory transistor 19 Source bias generation circuit

Claims (3)

A method for driving a nonvolatile semiconductor memory device having a P-channel memory cell formed on an N-type region,
The P-channel type memory cell includes a floating gate type memory transistor and a selection transistor connected in series to the floating gate type memory transistor.
The floating gate type memory transistor has a control gate connected to a control gate line, a source connected to a common source line, a drain connected to a source of the selection transistor,
The selection transistor has a selection gate connected to a word line, a drain connected to a bit line,
The P-channel type memory cell has a positive threshold value in a written state and a negative threshold value in an erased state,
The P-channel memory cell is written by injecting interband tunnel hot electrons from the drain of the floating gate memory transistor to the floating gate,
The erasing of the P channel type memory cell is performed by extracting electrons of the floating gate electrode to the N type region through a tunnel oxide film between the floating gate and the N type region of the floating gate type memory transistor. At the time of writing, the N-type region is set as a power supply voltage, a first negative voltage is applied to the bit line, a first positive voltage is applied to the control gate line, and a second negative voltage is applied to the word line. And applying a source voltage lower than the power supply voltage to the source line ,
At the time of writing, the voltage lower than the power supply voltage applied to the source line is the hot electron due to a temporary channel current flowing into the junction capacitance of the source line when the source line is opened. Non-volatile voltage that is longer than the time until overwriting occurs due to injection into the floating gate when the voltage lower than the power supply voltage is applied to the source line. For driving a conductive semiconductor memory device At the time of writing, the first negative voltage is about -3V to -6V, the first positive voltage is about 6V to 11V, the second negative voltage is about -5V to -8V, and the source voltage is the power source. The method of driving a nonvolatile semiconductor memory device according to claim 1, wherein the voltage is 0.7 V or more lower than the voltage. The method for driving a nonvolatile semiconductor memory device according to claim 2, wherein the source voltage at the time of writing is set to a ground potential.

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