JP3900464B2 - DRAM write driver - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a DRAM write driver capable of high-speed writing to a memory cell in a DRAM which uses automatic precharge and inputs a flat row / column address.
[0002]
[Prior art]
A DRAM (Dynamic RAM) has a basic operation of destructive reading with one capacitor and one transistor. The order of the write operation of the DRAM will be described. (1) Cell data in the word line is read, and signal development is performed on the bit lines of all the read cell data. (2) All bit line data is amplified by the sense amplifier and rewritten through the data line to the sense amplifier selected by the column switch. (3) Write to the cell through the bit line by the sense amplifier. As described above, since the data is rewritten after being amplified once by the sense amplifier, the operation of the DRAM takes time.
[0003]
The write operation to the memory cell of the DRAM 31 shown in FIG. 3 is started after the bit line pair (BL, / BL) is amplified by the sense amplifier. First, data to be written is input to the write driver 30. The output of the write driver 30 drives a relatively heavy data line pair (DL, / DL) and sends write data to the sense amplifier. Each sense amplifier has a column switch (or bit switch). The column switch is turned on by the selected column select line, and the data line pair is connected to the sense amplifier. The The data line pair inverts the sense amplifier and writes to the cell through the bit line. FIG. 4 shows a simulation result of the write operation.
[0004]
As a method for speeding up the write operation cycle, it is conceivable to accelerate the start of the write operation. However, the write driver 30 needs to be driven largely in order to invert the relatively high-load data line pair and sense amplifier. If the write operation is started at the time of signal development or early amplification in order to accelerate the start of the write operation, a large voltage fluctuation occurs in the sense amplifier and bit line pair that are turned on by driving the data line. . This generates noise in the nearby sense amplifier and bit line that are parasitically coupled. This noise causes a nearby sense amplifier to malfunction. Therefore, the start of the write operation cannot be accelerated. FIG. 5 (a), the show simulation results for the write operation when caused malfunctions in (b). 5 (a) is a simulation result including the bit line pair which has been written, by the noise according to FIG. 5 (b) (a), simulation including the bit line pair in the vicinity of a malfunction has occurred It is a result. The parasitic coupling capacitance between the bit lines and between the sense amplifiers is assumed to be 20% of the total capacitance.
[0005]
The magnitude of the noise is affected by the magnitude of the parasitic coupling capacitance. If the parasitic coupling capacitance is sufficiently reduced, the generated noise can be within an allowable range. In order to reduce the parasitic coupling capacitance between the bit lines, it is necessary to increase the chip size by widening between the bit lines. However, increasing the chip size is not realistic.
[0006]
In addition, in the DRAM 31, data (for example, “0”) opposite to stored data (for example, “1”) may be written, so that it takes longer to restore than reading, and the cycle time is large for the writing operation. Affected. Therefore, in order to increase the cycle time, it is necessary to improve the write operation. As one of the improvement measures, a method is proposed in which writing is performed before the word line is activated.
[0007]
Performing the write operation at an early stage is a method that can be rewritten in the same manner as the read operation, and has a high speed. However, if writing is performed when the bit line is floated, there is a risk that the surrounding bit lines not to be written malfunction due to coupling noise and the data is inverted. To prevent coupling noise, configure a non-operational bit line connected to the shield power supply between the bit line pair, and send the same large amplitude write signal to the data line pair and There is a way to give bit line pairs. In this case, the memory array becomes very large and cannot be adopted as a DRAM that places importance on cost.
[0008]
[Problems to be solved by the invention]
SUMMARY OF THE INVENTION An object of the present invention is to provide a DRAM write driver that speeds up a write cycle of a DRAM and prevents a malfunction in a cell in which no write is performed and performs stable write.
[0009]
[Means for Solving the Problems]
The gist of the DRAM write driver of the present invention is that the column switch is turned on, and before the sense amplifier is activated, the data is written to the bit line pair by the potential difference via the data line pair. A DRAM write driver, wherein the data line pair is a pair of a first data line and a second data line, and the bit line line connected to the sense amplifier A power supply for supplying a pair of precharge voltages and a signal for instructing writing of " 1 " are input to the gate, the first data line is connected to the drain, and the first n is connected to the source. And a signal instructing writing of “ 0 ” obtained by inverting “ 1 ” input to the gate of the first n-type MOSFET is input to the gate, A second n-type MOSFET having a first data line connected to a drain; a first resistor connecting the power supply to a source of the second n-type MOSFET; and a source of the second n-type MOSFET. And a second resistor and a capacitor for connecting to the ground, a signal for instructing writing of " 0 " is input to the gate, the second data line is connected to the drain, and the power source is connected to the source. 3 and a signal instructing writing of “ 1 ” obtained by inverting “ 0 ” input to the gate of the third n-type MOSFET are input to the gate, and the second data line is A fourth n-type MOSFET connected to the drain; a third resistor connecting the power source to a source of the fourth n-type MOSFET; and a source of the fourth n-type MOSFET connected to the ground. A fourth resistor and a capacitor connected to each other.
[001 0 ]
DETAILED DESCRIPTION OF THE INVENTION
Next, an embodiment of a DRAM write driver according to the present invention will be described in detail with reference to the drawings.
[0011]
FIG. 1 shows a circuit configuration example of the present invention. Other than the write driver 20, the circuit is the same as the conventional circuit. Signal instructing the write-out write "1" is input to the gate (G), data lines (DL) is connected to the drain (D), power supply (not shown) is connected to the source (S) that a first n-type MOSFET 1 6e, signal instructing the writing of which is obtained by inverting "0" to "1" is input to the gate of the first n-type MOSFET 1 6e (G) a gate (G) is input to the data line (DL) and a second n-type MOSFET 1 6f connected to the drain (D), a first connecting power to the source over the scan of the second n-type MOSFET 1 6f (S) It includes a resistor R1, a second resistor R2 and the key Yapashita C which respectively connect source over scan of the second n-type MOSFET 1 6f the (S) to the ground, the. On the data line bar (/ DL) side, a signal for instructing writing " 0 " is input to the gate ( G ), the data line bar (/ DL) is connected to the drain (D), and the power supply (not shown) Is instructed to write " 1 " obtained by inverting " 0 " input to the third n-type MOSFET 16g connected to the source ( S ) and the gate (G) of the third n-type MOSFET 16g. The signal is input to the gate ( G ), the data line bar (/ DL) is connected to the drain ( D ), the fourth n-type MOSFET 16h, and the power source is connected to the source ( S ) of the fourth n-type MOSFET 16h. And a fourth resistor R4 and a capacitor C for connecting the source ( S ) of the fourth n-type MOSFET 16h to the ground. The bit line (BL) and the bit line bar (/ BL) are a bit line pair. The data line (DL) and the data line bar (/ DL) are a data line pair.
[0012]
The first resistor R1 and the second resistor R2 , and the third resistor R3 and the fourth resistor R4 have resistance values for resistance division so as to generate the following voltage difference. The power supply provides the precharge voltage for the bit line.
[00 13 ]
When "1" is written, a high signal is input to the gate so that the n-type MOSFET 16e and the n-type MOSFET 16h become conductive. Further, when “0” is written, a high signal is input to the gate so that the n-type MOSFET 16f and the n-type MOSFET 16g become conductive.
[00 14 ]
In other words, the write driver 20 sets the data line (DL) to the bit line precharge voltage and the data line bar (/ DL) from the precharge voltage when writing "1" data. Connected to a source divided by a precharge voltage of about 200 mV and resistance by ground. In writing "0", conversely, (DL) is set to a value about 200 mV lower than the precharge voltage, and (/ DL) is set to the precharge voltage of the bit line.
[00 15 ]
FIG. 2 shows the simulation result. The driving of the data line pair and the operation of the column select line are started at the same timing when the word line is operated. The column select line is returned when the operation of the sense amplifier starts, and the column switch is turned off. The above differs from the conventional method in terms of timing. From the simulation results, the cycle time was about 5 ns faster than the conventional method, and an improvement of about 15% was obtained.
[00 16 ]
The magnitude of the noise is affected by the magnitude of the transient voltage at the coupling capacitance terminal. The present invention accelerates the start of the write operation by sufficiently reducing the transient voltage and suppressing noise. Specifically, the voltage value of the data line pair is controlled by the write driver 20 by an arbitrary method, and the voltage equivalent to the voltage of the bit line pair generated by the signal development is signal development. In addition to the bit line pair selected at times, this write data is simultaneously amplified and written to the cell when amplified by the sense amplifier.
[00 17 ]
Since the transient voltage generated by this write operation is controlled to the same level as that during signal development, the resulting noise is also the same as that during signal development, and the problem of malfunction due to noise has been eliminated. .
[00 18 ]
Although the DRAM write driver of the present invention has been described above, the present invention is not limited thereto. The present invention can be carried out in a mode in which various improvements, modifications, and variations are added based on the knowledge of those skilled in the art without departing from the spirit of the present invention.
[00 19 ]
【The invention's effect】
According to the present invention, at the time of writing in a DRAM, a signal similar to reading can be generated without causing noise in other surrounding bit lines, and there is no malfunction due to noise. Therefore, the DRAM can read data with a stable operation. Writing can be performed with the same short cycle time as reading.
[00 20 ]
Also, write data can be input to the sense amplifier during signal development, and writing can be performed simultaneously with amplification and rewriting of other cell data. Thereby, the write cycle can be speeded up.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing another configuration example of a write driver of a DRAM according to the present invention.
FIG. 2 is a timing chart showing the operation of the write drive shown in FIG. 1;
FIG. 3 is a circuit diagram showing a configuration example of a conventional DRAM write driver.
4 is a timing chart showing an operation of the write drive shown in FIG. 3. FIG.
FIG. 5 is a waveform diagram showing the operation of the write drive shown in FIG. 3. (a) is a waveform diagram of a bit line in which a write operation was performed during signal development, and (b) is a waveform diagram of (a). FIG. 6 is a waveform diagram of a neighboring bit line in which a malfunction occurs due to the noise of the bit line shown.
[Explanation of symbols]
20 , 30: Light driver
21 , 31: DRAM
12: Cell capacitor 14a, 14b, 14c, 14d: p-type MOSFET
16a, 16b, 16c, 16d, 16e, 16f, 16g, 16h: n-type MOSFET

Claims (2)

A DRAM write driver for writing data by a potential difference to a bit line pair through a data line pair before the column switch is turned on and the sense amplifier is activated .
The data line pair is a pair of a first data line and a second data line;
A power source for supplying a precharge voltage of said bit line pair connected to a sense amplifier,
Signal instructing the write-out write "1" is input to the gate, the first data line is connected to the drain, a first n-type MOSFET which power source is connected to the source,
The signal for instructing the writing of the input to the gate of the first n-type MOSFET "1" to the inverted "0" is input to the gate, the first data line is connected to the drain Two n-type MOSFETs;
A first resistor connecting the power supply to a source of the second n-type MOSFET;
A second resistor and a capacitor respectively connecting the source of the second n-type MOSFET to the ground;
A third n-type MOSFET in which a signal instructing writing of “ 0 ” is input to the gate, the second data line is connected to the drain, and the power source is connected to the source;
A signal instructing writing of “ 1 ” obtained by inverting “ 0 ” input to the gate of the third n-type MOSFET is input to the gate, and the second data line is connected to the drain. N-type MOSFET of
A third resistor connecting the power supply to the source of the fourth n-type MOSFET;
A fourth resistor and a capacitor respectively connecting the source of the fourth n-type MOSFET to the ground;
DRAM write driver including It said first resistor and said second resistor and the third resistor and the first 4 D RAM write driver of claim 1 resistance and have the same value of.

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