JP3897963B2 - Semiconductor wafer and manufacturing method thereof - Google Patents
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Description
【０００１】
【発明の属する技術分野】
本発明は、半導体ウェーハの製造方法に関し、特に基板表面の平坦度に優れた半導体ウェーハの製造方法に関するものである。
【０００２】
【従来の技術】
半導体ウェーハ、例えばシリコンウェーハの製造分野においては、基板の表面にシリコンエピタキシャル層を形成した、いわゆるエピタキシャルウェーハ（以下、エピウェーハと略す）が従来から知られている。この技術によれば、基板上に任意の膜厚や抵抗率を持つ単結晶シリコン層を形成できるので、高性能の半導体デバイスを製造することができる。例えばバイポーラトランジスタの分野では高速化の目的で、ＣＭＯＳメモリの分野ではソフトエラー、ラッチアップ等の不良対策として、エピウェーハの使用が極めて有効であることが認識されており、需要が高まっている。
【０００３】
この種のエピウェーハにおいて、通常、シリコンエピタキシャル層の膜厚は規定されており、規格管理されたものが出荷されている。例えば、厚いエピタキシャル層が要求される用途では数μｍ〜２０μｍ程度、薄いエピタキシャル層が要求される用途では１μｍ弱〜数μｍ程度に設定されている。
【０００４】
【発明が解決しようとする課題】
ところで、半導体デバイスの分野においては高集積化が年々進んでおり、より微細な加工が必要になってきている。この際、例えばフォトリソグラフィー工程における露光装置の焦点深度等の関係から、デバイス材料となるシリコンウェーハの平坦度が高いことが要求される。ウェーハの平坦度は、フォトリソグラフィー工程のみならず、他の工程においても加工精度を向上させる上で重要なファクターとなっている。
【０００５】
しかしながら、従来のシリコンウェーハの製造工程において、ウェーハの平坦度はスライシングからポリッシングまでの加工工程によって制御されており、ポリッシングの後、仮にウェーハの平坦度が良くないことがわかったとしても、平坦度を改善する有効な手段がなかった。
【０００６】
また、エピウェーハの場合、上述したように、一定の膜厚のエピタキシャル層を形成しているため、元々の基板表面の平坦度が悪ければ、その平坦度の悪さがエピタキシャル層の表面にも反映されてしまう。したがって、現状の平坦度レベルではスライシングからポリッシングまでの加工工程の制御で対応できていても、その制御には限界があり、将来的により高平坦度のウェーハが要求された際にその要求に対応できる手段の提供が望まれている。
【０００７】
本発明は、上記の課題を解決するためになされたものであって、ポリッシングの後であってもウェーハの平坦度を改善することができ、高平坦度ウェーハへの要求を満足し得る半導体ウェーハの製造方法を提供することを目的とする。
【０００８】
【課題を解決するための手段】
本発明の半導体ウェーハの製造方法は、半導体ウェーハを構成するポリッシング後の基板表面の平坦度を測定し、中央部が高く周辺部がだれた形状を呈する前記基板表面の凹凸に応じて、該基板の表面に気相エピタキシャル法により場所によって膜厚の異なる半導体層を形成させる際に、
前記半導体基板の側方に備えられた複数の原料ガス供給ノズルから供給する原料ガスの流量を各ノズルによって異ならせることで、前記基板の表面に沿って流す原料ガスの流量を基板上の場所によって異ならせ、前記基板表面のうち凹となった周辺部箇所には原料ガス流量を大きく、前記基板表面のうち凸となった中央部箇所には原料ガス流量を小さくなるようにし、これに加えて、
前記基板の周辺部の温度と中心部の温度を異ならせ、前記基板表面のうち凹となった周辺部箇所の温度を凸となった中央部箇所の温度に比べて高くして前記半導体層の成長速度を大きくすることにより、
前記基板表面のうち凹となった箇所には厚く、凸となった箇所には薄くなるように前記半導体層を成長させ、該半導体層の膜厚で前記基板表面の平坦度分布を補償して表面が平坦化された半導体ウェーハを製造するとともに、
前記基板の回転速度を大きくする手段により、前記基板の周辺部でさらに厚くなるように前記半導体層を成長させることにより上記課題を解決した。
上記の目的を達成するために、本発明の半導体ウェーハの製造方法は、半導体ウェーハを構成する基板の表面の平坦度を測定し、基板表面の凹凸に応じて、基板の表面にエピタキシャル法により場所によって膜厚の異なる半導体層を成長させ、該半導体層の膜厚で前記基板表面の平坦度分布を補償して表面が平坦化された半導体ウェーハを製造することを特徴とする。
【０００９】
［従来の技術］の項で述べたように、基板上にエピタキシャル層を成長させたエピウェーハの場合、従来は要求されるデバイス特性等の観点から一定の膜厚を有するエピタキシャル層を形成するのが通常であった。これに対して、本発明者らは発想を変えて、元々の基板表面の平坦度分布をエピタキシャル層（半導体層）の膜厚で補償することに想到した。すなわち、基板の作製が終わったところで平坦度の測定を行い、その平坦度に応じて、基板表面のうち凹となった箇所には厚く、凸となった箇所には薄くなるように半導体層を成長させることによって、表面が平坦化された半導体ウェーハを製造することができる。
【００１０】
なお、ここで言う「基板」とは、半導体層の下地となる基板本体のことであって、例えばポリッシング工程終了後の基板のことを言う。
【００１１】
この方法によれば、ポリッシング後であっても平坦度を改善することができ、従来のスライシング〜ポリッシング工程の制御では得られなかったより高い平坦度を有する半導体ウェーハを得ることができる。
【００１２】
半導体ウェーハ上で場所によって膜厚の異なる半導体層を形成する方法としては、例えば前記エピタキシャル法として気相エピタキシャル法を用い、半導体層を成長させる際に、基板の表面に沿って流す原料ガスの流量をウェーハ上の場所によって異ならせ、原料ガス流量の大きい箇所では膜厚が厚く、原料ガス流量の小さい箇所では膜厚が薄くなるように、半導体層を成長させればよい。この方法によれば、原料ガス流量の大きい箇所では膜厚が厚く、原料ガス流量の小さい箇所では膜厚が薄くなるように、半導体層を成長させ、該半導体層の膜厚で前記基板表面の平坦度分布を補償して表面が平坦化された半導体ウェーハを製造することができる。
【００１３】
例えば、ポリッシング工程での研磨特性によって、ポリッシング後の基板は中央部が高く、周辺部がだれた形状を呈した場合、このような形状に応じてウェーハ表面の平坦化を図るには、上記のように、基板の中央部で原料ガス流量が小さく、周辺部で原料ガス流量が大きくなるように条件を制御すればよい。それに加えて、前記基板の周辺部の温度と中心部の温度を異ならせ、前記基板表面のうち凹となった箇所の温度を凸となった箇所の温度に比べて高く、つまり基板の周辺部の温度を中心部の温度に比べて高くして前記基板表面のうち凹となった箇所の成長速度を凸となった箇所の成長速度に比べて大きくすることが有効である。逆に、ポリッシング後、基板の中央部が低く、周辺部が高い場合には、中央部で原料ガス流量が大きく、周辺部で原料ガス流量が小さくなるように条件を制御すればよい。その際には、前記基板の周辺部の温度と中心部の温度を異ならせ、前記基板表面のうち凹となった箇所の温度を凸となった箇所の温度に比べて高く、つまり基板の中心部の温度を基板の周辺部の温度に比べて高くして前記基板表面のうち凹となった箇所の成長速度を凸となった箇所の成長速度に比べて大きくすることが有効である。
【００１４】
本発明の半導体ウェーハは、上記本発明の半導体ウェーハの製造方法を用いて製造されたことを特徴とするものである。本発明によれば、従来に比べてより平坦度の高い半導体ウェーハが得られる。
【００１５】
【発明の実施の形態】
以下、本発明の一実施の形態を図１を参照して説明する。
本実施の形態のシリコンウェーハ（半導体ウェーハ）の製造方法は、まずシリコンウェーハの本体となるシリコン基板の表面の平坦度を測定する。このシリコン基板は、単結晶インゴットの作製、オリエンテーションフラット加工、スライシング、面取り（ベベリング）、ラッピング、裏面ゲッタリング処理、ポリッシング等のウェーハ製造の諸工程を経た後のものである。平坦度の測定には、例えば斜め入射干渉計方式、静電容量方式、光電方式、超音波方式等の周知のウェーハ形状測定装置を用いることができる。
【００１６】
次に、前工程で測定した平坦度に基づき、シリコン基板表面の凹凸に応じて、基板表面に気相エピタキシャル法により場所によって膜厚の異なるシリコンエピタキシャル層（半導体層）を成長させる。シリコンエピタキシャル層の成長には、縦型、シリンダ（バレル）型、枚葉型等、種々のエピタキシャル成長装置が用いられる。この種の装置を用いて場所によって膜厚の異なるシリコンエピタキシャル層を成長させるには、図１（ａ）に示すように、例えばチャンバー内のシリコン基板１の側方に複数の原料ガス供給ノズル２が備えられている場合、各ノズル２から供給するＳｉＣｌ4，ＳｉＨＣｌ3，ＳｉＨ2Ｃｌ2，ＳｉＨ4等の原料ガスの流量をノズルによって異ならせる。
【００１７】
図１（ｂ）に示すように、ポリッシング工程での研磨特性によって、ポリッシング後のシリコン基板１は中央部が高く、周辺部がだれた形状を呈することが多い。そこで、このような形状のシリコン基板１に応じてシリコンウェーハ４全体として表面の平坦化を図るには、基板の中央部でシリコンエピタキシャル層３を薄く、周辺部で厚く形成すればよい。そのためには、基板の中央部で原料ガス流量が小さく、周辺部で原料ガス流量が大きくなるように制御すればよい。
【００１８】
それに加えて、シリコン基板１の周辺部の温度を中心部の温度に比べて高くすると、中心部に比べて周辺部の方が成長速度が大きくなり、基板周辺部のシリコンエピタキシャル層３を厚く形成することができる。さらに、シリコン基板１の回転速度を大きくすると、基板周辺部のシリコンエピタキシャル層３を厚く形成することができる。
【００１９】
実際の原料ガス流量とシリコンエピタキシャル層３の膜厚との相関関係は、個々のエピタキシャル成長装置や製造条件に依存する。したがって、個々の装置、製造条件毎に原料ガス流量とシリコンエピタキシャル層厚との相関データを予め取得しておき、このデータに基づいて所望のシリコンエピタキシャル層厚が得られるように原料ガス流量を設定、制御する。
【００２０】
本実施の形態のシリコンウェーハの製造方法によれば、ポリッシング後のシリコン基板に対しても充分に平坦度を改善することができ、従来のスライシング〜ポリッシング工程の制御では得られなかった高平坦度のシリコンウェーハを得ることができる。
【００２１】
なお、本発明の技術範囲は上記実施の形態に限定されるものではなく、本発明の趣旨を逸脱しない範囲において種々の変更を加えることが可能である。例えばウェーハの平坦度の測定方法、シリコンエピタキシャル層の成長方法および膜厚の制御方法、等に関しては適宜選択することができる。また、上記実施の形態ではシリコンウェーハの例を説明したが、本発明はその他の半導体ウェーハにも適用可能である。
【００２２】
【実施例】
以下、本発明の効果を実証する実験の結果について報告する。
まず、直径２００ｍｍのシリコンウェーハを用意し、平坦度を測定した。その結果を図２（ａ）に示す。ここでは、平坦度を表すパラメータとして、ＳＴＩＲ（Site Total Indicator Reading）を採用した。各サイト毎のＳＴＩＲの数値を［μｍ］単位で示す。このシリコンウェーハの場合、ＳＴＩＲの数値は０．０５〜０．２０μｍ程度の範囲に分布している。そして、Ｘ方向、Ｙ方向のいずれの方向に対しても中心部に比べて周辺部の数値が大きくなっており、周辺部の平坦度が悪いことがわかる（実際には周辺部がだれている）。
【００２３】
そこで、上記実施の形態で述べたように、シリコンウェーハの中央部で原料ガス流量が小さく、周辺部で原料ガス流量が大きくなるように原料ガスの流量を制御し、基板の中央部で薄く、周辺部で厚くなるように気相エピタキシャル法を用いて膜厚６μｍ程度のシリコンエピタキシャル層を形成した。そして、形成したシリコンエピタキシャル層の膜厚を実際に測定した。測定結果を図４に示す。図４において、横軸はウェーハ中心からの距離（ｍｍ）、縦軸はシリコンエピタキシャル層の膜厚（μｍ）を示す。図４から、ウェーハ中心部に対して周辺部の膜厚が０．４〜０．６μｍ程度厚くなっていることがわかる。
【００２４】
そして、再度、シリコンエピタキシャル層表面での平坦度を測定した。その結果を図２（ｂ）に示す。図２（ａ）と同様、平坦度を表すパラメータとしてＳＴＩＲを採用し、各サイト毎のＳＴＩＲの数値を［μｍ］単位で示す。ＳＴＩＲの数値は０．０３〜０．０７μｍ程度の範囲に分布しており、図２（ａ）に比べて改善されている。また、Ｘ方向、Ｙ方向のいずれの方向に対しても周辺部の数値が図２（ａ）に比べて小さくなっており、周辺部の平坦度が改善されたことがわかった。
【００２５】
図３は以上の結果をまとめたものであり、エピ前後における同一サイトの平坦度の変化を表すグラフである。横軸はエピ前の平坦度（μｍ）、縦軸はエピ後の平坦度（μｍ）を示す。グラフの各軸に対して４５°をなす線を描いたが、各点がこの線上にあればエピ後も平坦度が変化しないことを示し、各点がこの線より下側にあればエピ後に平坦度が改善していることを示す。また逆に、各点がこの線より上側にあればエピ後に平坦度が悪化していることを示す。図３から明らかなように、プロット点の大部分が４５°の線よりも下側に位置しており、本発明のエピ成長を行ったことによってウェーハの平坦度が大幅に改善されることが実証された。
【００２６】
【発明の効果】
以上、詳細に説明したように、本発明によれば、基板の表面に基板表面の凹凸に応じて膜厚の異なる半導体層をエピタキシャル成長させたことによって、ポリッシング後の基板に対しても充分に平坦度を改善することができ、従来のスライシング〜ポリッシング工程の制御では得られなかった高平坦度の半導体ウェーハを得ることができる。
【図面の簡単な説明】
【図１】 本発明の一実施の形態のシリコンウェーハの製造方法において、エピタキシャル工程の様子を説明するための図である。
【図２】 本発明の実施例におけるウェーハの平坦度の測定結果を示す図であって、（ａ）エピ前の平坦度、（ｂ）エピ後の平坦度をそれぞれ示す。
【図３】 同実施例において、エピ前後における同一サイトの平坦度の変化をプロットしたグラフである。
【図４】 同実施例において、形成したエピタキシャル層の膜厚分布を示す図である。
【符号の説明】
１ シリコン基板（基板）
２ 原料ガス供給ノズル
３ シリコンエピタキシャル層（半導体層）
４ シリコンウェーハ（半導体ウェーハ）[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor wafer, and more particularly to a method for manufacturing a semiconductor wafer having excellent substrate surface flatness.
[0002]
[Prior art]
In the field of manufacturing semiconductor wafers such as silicon wafers, so-called epitaxial wafers (hereinafter abbreviated as epi-wafers) in which a silicon epitaxial layer is formed on the surface of a substrate are conventionally known. According to this technique, since a single crystal silicon layer having an arbitrary film thickness and resistivity can be formed on a substrate, a high-performance semiconductor device can be manufactured. For example, in the field of bipolar transistors, the use of epiwafers has been recognized to be extremely effective as a countermeasure for defects such as soft errors and latch-ups for the purpose of speeding up, and in the field of CMOS memories, and the demand is increasing.
[0003]
In this type of epi-wafer, the thickness of the silicon epitaxial layer is usually specified, and the standard-controlled one is shipped. For example, in applications where a thick epitaxial layer is required, the thickness is set to about several μm to 20 μm, and in applications where a thin epitaxial layer is required, it is set to about 1 μm to about several μm.
[0004]
[Problems to be solved by the invention]
By the way, in the field of semiconductor devices, higher integration is progressing year by year, and finer processing is required. At this time, the flatness of the silicon wafer as the device material is required to be high, for example, from the relationship of the depth of focus of the exposure apparatus in the photolithography process. The flatness of the wafer is an important factor for improving the processing accuracy not only in the photolithography process but also in other processes.
[0005]
However, in the conventional silicon wafer manufacturing process, the flatness of the wafer is controlled by the processing process from slicing to polishing, and even if it is found that the flatness of the wafer is not good after polishing, the flatness There was no effective means to improve.
[0006]
In the case of an epi-wafer, as described above, an epitaxial layer having a constant film thickness is formed. Therefore, if the flatness of the original substrate surface is poor, the poor flatness is reflected on the surface of the epitaxial layer. End up. Therefore, even if the current flatness level can be dealt with by controlling the processing process from slicing to polishing, there is a limit to that control, and if a wafer with higher flatness is demanded in the future, it will meet that demand It is desirable to provide a means that can do this.
[0007]
The present invention has been made to solve the above-described problems, and can improve the flatness of a wafer even after polishing, and can satisfy the demand for a high flatness wafer. It aims at providing the manufacturing method of.
[0008]
[Means for Solving the Problems]
The method for manufacturing a semiconductor wafer of the present invention measures the flatness of the substrate surface after polishing that constitutes the semiconductor wafer, and according to the unevenness of the substrate surface exhibiting a shape with a high central part and a peripheral part. When forming semiconductor layers with different film thickness depending on the location by vapor phase epitaxy on the surface of
By changing the flow rate of the source gas supplied from a plurality of source gas supply nozzles provided on the side of the semiconductor substrate for each nozzle, the flow rate of the source gas flowing along the surface of the substrate depends on the location on the substrate. different causes, increasing the flow rate of the raw gas in the peripheral edge part became concave of the substrate surface, the smaller the raw material gas flow rate in central position with a convex of the substrate surface, in addition to this And
The temperature of the peripheral part of the substrate is different from the temperature of the central part, and the temperature of the concave peripheral part of the substrate surface is set higher than the temperature of the convex central part of the semiconductor layer. by increasing the growth rate,
The semiconductor layer is grown to be thick in the concave portion of the substrate surface and thin in the convex portion, and the flatness distribution of the substrate surface is compensated by the film thickness of the semiconductor layer. While manufacturing a semiconductor wafer with a flat surface ,
The above problem has been solved by growing the semiconductor layer so as to be thicker at the periphery of the substrate by means of increasing the rotation speed of the substrate .
In order to achieve the above-mentioned object, the semiconductor wafer manufacturing method of the present invention measures the flatness of the surface of the substrate constituting the semiconductor wafer, and places the surface of the substrate by an epitaxial method according to the irregularities of the substrate surface. A semiconductor wafer having a flattened surface is manufactured by growing semiconductor layers having different film thicknesses, compensating for the flatness distribution of the substrate surface with the film thickness of the semiconductor layer.
[0009]
As described in [Prior Art], in the case of an epitaxial wafer in which an epitaxial layer is grown on a substrate, an epitaxial layer having a certain thickness is conventionally formed from the viewpoint of required device characteristics and the like. It was normal. On the other hand, the present inventors changed the way of thinking and came up with the idea of compensating the original flatness distribution on the substrate surface with the film thickness of the epitaxial layer (semiconductor layer). That is, the flatness is measured at the end of the production of the substrate, and the semiconductor layer is thickened at the concave portion of the substrate surface and thinned at the convex portion according to the flatness. By growing it, a semiconductor wafer having a planarized surface can be manufactured.
[0010]
Note that the “substrate” here refers to a substrate body that is a base of a semiconductor layer, for example, a substrate after a polishing process is completed.
[0011]
According to this method, even after polishing, the flatness can be improved, and a semiconductor wafer having a higher flatness that cannot be obtained by the control of the conventional slicing to polishing process can be obtained.
[0012]
As a method of forming semiconductor layers having different thicknesses depending on locations on a semiconductor wafer, for example, a vapor phase epitaxial method is used as the epitaxial method, and the flow rate of the source gas that flows along the surface of the substrate when the semiconductor layer is grown. the varied depending on the location on the wafer, the raw material gas thick thickness in a large part of the flow, so the film thickness becomes thin in the small portion of the raw material gas flow rate may be Re grown semiconductor layer. According to this method, the semiconductor layer is grown so that the film thickness is thick at the portion where the source gas flow rate is large and the film thickness is thin at the portion where the source gas flow rate is small . surface can it to manufacture a semiconductor wafer which is planarized by compensating for flatness distribution.
[0013]
For example, due to the polishing characteristics in the polishing process, when the polished substrate has a high central portion and a peripheral portion that is slender, the wafer surface can be flattened according to such a shape as described above. Thus, the conditions may be controlled so that the raw material gas flow rate is small at the central portion of the substrate and the raw material gas flow rate is large at the peripheral portion. In addition, the temperature of the peripheral portion of the substrate is different from the temperature of the central portion, the temperature of the concave portion of the substrate surface is higher than the temperature of the convex portion , that is , the peripheral portion of the substrate It is effective to increase the temperature of the substrate in comparison with the temperature of the central portion so that the growth rate of the concave portion of the substrate surface is larger than the growth rate of the convex portion . On the contrary, after polishing, when the central portion of the substrate is low and the peripheral portion is high, the conditions may be controlled so that the raw material gas flow rate is large in the central portion and the raw material gas flow rate is small in the peripheral portion. In that case, the temperature of the peripheral portion of the substrate is different from the temperature of the central portion, the temperature of the concave portion of the substrate surface is higher than the temperature of the convex portion, that is , the center of the substrate It is effective to raise the temperature of the portion compared to the temperature of the peripheral portion of the substrate and increase the growth rate of the concave portion of the substrate surface as compared to the growth rate of the convex portion .
[0014]
The semiconductor wafer of the present invention is manufactured using the above-described method for manufacturing a semiconductor wafer of the present invention. According to the present invention, it is possible to obtain a semiconductor wafer with higher flatness than in the prior art.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to FIG.
In the method for manufacturing a silicon wafer (semiconductor wafer) according to the present embodiment, first, the flatness of the surface of a silicon substrate which is a main body of the silicon wafer is measured. This silicon substrate is obtained after going through various steps of wafer production such as single crystal ingot fabrication, orientation flat processing, slicing, chamfering (beveling), lapping, back surface gettering, and polishing. For measuring the flatness, a well-known wafer shape measuring apparatus such as an oblique incidence interferometer method, a capacitance method, a photoelectric method, an ultrasonic method, or the like can be used.
[0016]
Next, based on the flatness measured in the previous step, silicon epitaxial layers (semiconductor layers) having different thicknesses are grown on the surface of the substrate by vapor phase epitaxy according to the unevenness of the surface of the silicon substrate. Various epitaxial growth apparatuses such as a vertical type, a cylinder (barrel) type, and a single wafer type are used for the growth of the silicon epitaxial layer. In order to grow a silicon epitaxial layer having a different thickness depending on the location using this type of apparatus, as shown in FIG. 1A, for example, a plurality of source
[0017]
As shown in FIG. 1B, the polished silicon substrate 1 often has a shape in which the central portion is high and the peripheral portion is slack due to the polishing characteristics in the polishing step. Therefore, in order to flatten the surface of the silicon wafer 4 as a whole in accordance with the silicon substrate 1 having such a shape, the silicon epitaxial layer 3 may be formed thin at the central portion of the substrate and thick at the peripheral portion. For that purpose, it is only necessary to control so that the raw material gas flow rate is small in the central portion of the substrate and the raw material gas flow rate is large in the peripheral portion.
[0018]
In addition, when the temperature of the peripheral portion of the silicon substrate 1 is made higher than the temperature of the central portion, the growth rate is higher in the peripheral portion than in the central portion, and the silicon epitaxial layer 3 in the peripheral portion of the substrate is formed thicker. can do. Further, when the rotational speed of the silicon substrate 1 is increased, the silicon epitaxial layer 3 in the peripheral portion of the substrate can be formed thick.
[0019]
The correlation between the actual raw material gas flow rate and the film thickness of the silicon epitaxial layer 3 depends on individual epitaxial growth apparatuses and manufacturing conditions. Therefore, the correlation data between the source gas flow rate and the silicon epitaxial layer thickness is acquired in advance for each device and manufacturing condition, and the source gas flow rate is set so that the desired silicon epitaxial layer thickness can be obtained based on this data. ,Control.
[0020]
According to the silicon wafer manufacturing method of the present embodiment, the flatness can be sufficiently improved even with respect to the polished silicon substrate, and the high flatness that cannot be obtained by the control of the conventional slicing to polishing process. The silicon wafer can be obtained.
[0021]
The technical scope of the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, a method for measuring wafer flatness, a method for growing a silicon epitaxial layer, a method for controlling a film thickness, and the like can be selected as appropriate. Moreover, although the example of the silicon wafer has been described in the above embodiment, the present invention can be applied to other semiconductor wafers.
[0022]
【Example】
The results of experiments that demonstrate the effects of the present invention are reported below.
First, a silicon wafer having a diameter of 200 mm was prepared, and the flatness was measured. The result is shown in FIG. Here, STIR (Site Total Indicator Reading) was adopted as a parameter representing flatness. The STIR value for each site is shown in [μm] units. In the case of this silicon wafer, STIR values are distributed in a range of about 0.05 to 0.20 μm. The numerical value of the peripheral portion is larger than that of the central portion in both the X direction and the Y direction, indicating that the flatness of the peripheral portion is poor (in fact, the peripheral portion is sluggish). ).
[0023]
Therefore, as described in the above embodiment, the flow rate of the source gas is controlled so that the source gas flow rate is small in the central portion of the silicon wafer and the source gas flow rate is increased in the peripheral portion, and thin in the central portion of the substrate, A silicon epitaxial layer having a film thickness of about 6 μm was formed by vapor phase epitaxy so as to be thick at the periphery. And the film thickness of the formed silicon epitaxial layer was actually measured. The measurement results are shown in FIG. In FIG. 4, the horizontal axis represents the distance (mm) from the wafer center, and the vertical axis represents the film thickness (μm) of the silicon epitaxial layer. From FIG. 4, it can be seen that the film thickness of the peripheral portion is about 0.4 to 0.6 μm thicker than the wafer central portion.
[0024]
Then, the flatness on the surface of the silicon epitaxial layer was measured again. The result is shown in FIG. As in FIG. 2A, STIR is adopted as a parameter representing flatness, and STIR values for each site are shown in [μm] units. STIR values are distributed in the range of about 0.03 to 0.07 μm, which is an improvement over FIG. Moreover, the numerical value of the peripheral part was smaller than that in FIG. 2A in both the X direction and the Y direction, and it was found that the flatness of the peripheral part was improved.
[0025]
FIG. 3 summarizes the above results and is a graph showing the change in flatness of the same site before and after epi. The horizontal axis indicates the flatness (μm) before epi, and the vertical axis indicates the flatness (μm) after epi. Draw a line that makes 45 ° with respect to each axis of the graph. If each point is on this line, it indicates that the flatness does not change after epi, and if each point is below this line, after epi Indicates that the flatness is improved. Conversely, if each point is above this line, it indicates that the flatness has deteriorated after epitaxy. As is clear from FIG. 3, the majority of the plot points are located below the 45 ° line, and the flatness of the wafer can be greatly improved by performing the epitaxial growth of the present invention. Proven.
[0026]
【The invention's effect】
As described above in detail, according to the present invention, a semiconductor layer having a different film thickness is epitaxially grown on the surface of the substrate in accordance with the unevenness of the substrate surface, so that the substrate is sufficiently flat even after polishing. It is possible to improve the degree of the semiconductor wafer, and it is possible to obtain a semiconductor wafer having a high flatness which cannot be obtained by the conventional control of the slicing to polishing process.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining an epitaxial process in a method for producing a silicon wafer according to an embodiment of the present invention.
FIGS. 2A and 2B are diagrams showing measurement results of the flatness of a wafer in an example of the present invention, showing (a) flatness before epi, and (b) flatness after epi, respectively.
FIG. 3 is a graph plotting changes in flatness of the same site before and after epi in the same example.
FIG. 4 is a view showing a film thickness distribution of the formed epitaxial layer in the same example.
[Explanation of symbols]
1 Silicon substrate (substrate)
2 Source gas supply nozzle 3 Silicon epitaxial layer (semiconductor layer)
4 Silicon wafer (semiconductor wafer)
Claims (2)
前記半導体基板の側方に備えられた複数の原料ガス供給ノズルから供給する原料ガスの流量を各ノズルによって異ならせることで、前記基板の表面に沿って流す原料ガスの流量を基板上の場所によって異ならせ、前記基板表面のうち凹となった周辺部箇所には原料ガス流量を大きく、前記基板表面のうち凸となった中央部箇所には原料ガス流量を小さくなるようにし、これに加えて、
前記基板の周辺部の温度と中心部の温度を異ならせ、前記基板表面のうち凹となった周辺部箇所の温度を凸となった中央部箇所の温度に比べて高くして前記半導体層の成長速度を大きくすることにより、
前記基板表面のうち凹となった箇所には厚く、凸となった箇所には薄くなるように前記半導体層を成長させ、該半導体層の膜厚で前記基板表面の平坦度分布を補償して表面が平坦化された半導体ウェーハを製造するとともに、
前記基板の回転速度を大きくする手段により、前記基板の周辺部でさらに厚くなるように前記半導体層を成長させることを特徴とする半導体ウェーハの製造方法。Measure the flatness of the substrate surface after polishing that constitutes the semiconductor wafer, and according to the unevenness of the substrate surface exhibiting a shape with a high central part and a peripheral part , depending on the location on the surface of the substrate by vapor phase epitaxial method When forming semiconductor layers with different thicknesses,
By changing the flow rate of the source gas supplied from a plurality of source gas supply nozzles provided on the side of the semiconductor substrate for each nozzle, the flow rate of the source gas flowing along the surface of the substrate depends on the location on the substrate. different causes, increasing the flow rate of the raw gas in the peripheral edge part became concave of the substrate surface, the smaller the raw material gas flow rate in central position with a convex of the substrate surface, in addition to this And
The temperature of the peripheral part of the substrate is different from the temperature of the central part, and the temperature of the concave peripheral part of the substrate surface is set higher than the temperature of the convex central part of the semiconductor layer. by increasing the growth rate,
The semiconductor layer is grown to be thick in the concave portion of the substrate surface and thin in the convex portion, and the flatness distribution of the substrate surface is compensated by the film thickness of the semiconductor layer. While manufacturing a semiconductor wafer with a flat surface ,
A method of manufacturing a semiconductor wafer , comprising: growing the semiconductor layer so as to be thicker at a peripheral portion of the substrate by means for increasing a rotation speed of the substrate .
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| DE102005045339B4 (en) * | 2005-09-22 | 2009-04-02 | Siltronic Ag | Epitaxial silicon wafer and process for producing epitaxially coated silicon wafers |
| US20090214843A1 (en) * | 2008-02-26 | 2009-08-27 | Siltronic Corporation | Controlled edge resistivity in a silicon wafer |
| JP2009267159A (en) * | 2008-04-25 | 2009-11-12 | Ｓｕｍｃｏ Ｔｅｃｈｘｉｖ株式会社 | Device and method for manufacturing semiconductor wafer |
| DE102009004557B4 (en) * | 2009-01-14 | 2018-03-08 | Siltronic Ag | Epitaxial silicon wafer and process for producing epitaxially coated silicon wafers |
| JP5326888B2 (en) * | 2009-07-13 | 2013-10-30 | 株式会社Ｓｕｍｃｏ | Epitaxial wafer manufacturing method |
| JP6009237B2 (en) * | 2012-06-18 | 2016-10-19 | Ｓｕｍｃｏ Ｔｅｃｈｘｉｖ株式会社 | Epitaxial silicon wafer manufacturing method and epitaxial silicon wafer |
| JP6127748B2 (en) * | 2013-06-10 | 2017-05-17 | 株式会社Sumco | Epitaxial wafer manufacturing method |
| JP6151745B2 (en) * | 2015-08-04 | 2017-06-21 | 株式会社日立国際電気 | Substrate processing apparatus, substrate processing system, semiconductor device manufacturing method, program, and recording medium |
| KR101810643B1 (en) * | 2016-02-02 | 2017-12-19 | 에스케이실트론 주식회사 | Method of controling a flatness of a epitaxial wafer |
| EP3957776A1 (en) | 2020-08-17 | 2022-02-23 | Siltronic AG | Method for depositing an epitaxial layer on a substrate wafer |
| EP3978647A1 (en) | 2020-09-30 | 2022-04-06 | Siltronic AG | Method and device for depositing an epitaxial layer on a substrate wafer of semiconductor material |
| EP3996130B1 (en) | 2020-11-09 | 2023-03-08 | Siltronic AG | Method for depositing an epitaxial layer on a substrate wafer |
| CN115821234A (en) * | 2022-12-13 | 2023-03-21 | 杭州富芯半导体有限公司 | Method for improving surface flatness of thin film |
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