JP3892521B2 - Printed circuit board - Google Patents

Description

【００２８】
この数１の各式を用いて、Ｚ₀＝１２０Ωの場合について、クロックの周波数に対する入力インピーダンスＺ₁／Ｚ₀の関係を計算した結果を図１９に示す。同図において、Ｚａ，Ｚｂ，Ｚｃ，Ｚｄは、図１７の（ａ）〜（ｄ）の各入力インピーダンスＺａ〜Ｚｄに対応している。
【００２９】
ここで、Ｚ₁／Ｚ₀＝０のときの周波数が共振周波数であり、共振周波数は、図１７の（ａ）〜（ｄ）に示したように、接続するＩＣが１ヶ増える毎にｆ１ａ＝４５１．５ＭＨｚ、ｆ１ｂ＝３４０．３ＭＨｚ、ｆ１ｃ２４０＝ＭＨｚ、ｆ１ｄ＝１９９．１ＭＨｚと低下し、最終的には１９９．１ＭＨｚとなってしまう。
【００３０】
通常、電子機器からの放射ノイズは、前述の図１４に示したように１００〜３００ＭＨｚの周波数帯であり、この帯域では殆どの電子機器に使用されるスイッチング電源からの高域ノイズのベースが盛り上がり、またピーク状の成分も最も強く現れる。しかも、２３０ＭＨｚ以下の帯域では規格限度値も、２３０ＭＨｚ以上の帯域より７ｄＢも厳しくなっているため、非常に抑制が困難な帯域である。
【００３１】
これに対し、例えば３００ＭＨｚ以上の周波数帯の成分は、２３０ＭＨｚ以上では規制値がゆるくなる他に、スイッチング電源からのベースノイズも減少し、ノイズのピーク部も、発生したとしても周波数が高いため、少しでも回路内に分布容量や浮遊インダクタンス等があればすぐに減衰し易く、その対策は容易である。
【００３２】
このため、回路内で作られる共振周波数が３００ＭＨｚ帯以下、特に２３０ＭＨｚ以下になることは放射ノイズ対策を非常に困難にするものである。
この共振周波数の低下を防ぐには、各ＩＣまでの配線パターンの距離を極力短くすることが必要であるが、ＩＣの物理的な大きさもあり、自ずからその短く出来る長さには限界がある。
【００３３】
そこで、以下この発明の実施形態について説明する。
図１はこの発明の基礎となるプリント回路基板の第１の例を示す構成図であり、マイクロコンピュータ等のデジタル回路の基本クロックを発生するクロック発振器１と、その基本クロックが供給される複数（この例では５個）のＩＣ（半導体集積回路）２とを搭載したプリント回路基板１０において、クロック発振器１の出力に複数のＩＣ２をそれぞれ接続する５本の配線パターン１３を放射状に配置し、各配線パターン１３の先端にそれぞれ１個のＩＣ２を接続している（鵜飼方式）。
【００３４】
実際例としては、例えば図１７に示した例と同様に、それぞれ１０ＰＦ，５ＰＦ，１０ＰＦ，１０ＰＦ，および５ＰＦの入力容量を持つ５個のＩＣ２を、図２に示すように、同一のクロック発振器１の出力端子ａ，ｂに、それぞれパターン長が３０ｍｍ，２０ｍｍ，２０ｍｍ，３０ｍｍ，３０ｍｍの５対の放射状に配置された各配線パターン１３を介して接続する。
【００３５】
この例において、クロック発振器の出力端子ａ，ｂからみた入力インピーダースＺ₁／Ｚ₀を計算した結果を図３に示す。
この図３から判るように、その共振周波数は４５１ＭＨｚと５５８ＭＨｚであり、低い方の４５１ＭＨｚでも、従来の図１９の（ｄ）の場合について求めた１９９．１ＭＨｚに比べて非常に高い。５個のＩＣ２の総容量が４０ｐＦで、各ＩＣ２までのそれぞれの配線パターン長が、図１７の（ｄ）と共通パターン部分を除くと同じであるにも拘らず、その共振周波数の低下量は非常に少ないプリント回路基板とすることが出来る。
【００３６】
このように、クロック発振器１と複数の各ＩＣ２とをそれぞれ個別に放射状に配置した配線ライン１３によって接続することにより、その配線パターン１３のインダクタンスとＩＣ２の入力容量で作られる共振周波数を、ＩＣ２の数が増えた場合でもあまり低下させることなく高い周波数に保つことができる。また、ＩＣ２を接続する配線パターンを放射状に配置する（鵜飼方式にする）ことにより、従来の芋づる方式のような共通パターン部分がなくなるため、各ＩＣまでのパターン長が短くなり、この面でも共振周波数を高くすることができる。
【００３７】
その結果、大きな放射ノイズ低減効果が得られ、フェライトコアやノイズフィルタなどの高価で余分なノイズ対策用の部品が不要になり、また共振周波数が高いため、ノイズが発生しても簡単に減衰させることができるので、低コストのノイズ対策が可能になる。
【００３８】
図４は、この発明の基礎となるプリント回路基板の第２の例を示す構成図であり、図１と対応する部分には同一の符号を付している。この実施形態では、複数の各配線パターン１３にそれぞれ分岐パターン１３ｃを設け、その分岐パターン１３ｃを含む各配線パターン１３の先端に、それぞれ１個のＩＣ２を接続している。
このようにしても、前述の第１の実施形態の場合と同様な作用・効果を得ることができる。なお、分岐パターン１３ｃは、各配線パターン１３の全てに設けずに一部にのみ設けてもよい。
【００３９】
図５は、この発明の基礎となるプリント回路基板の第３の例を示す構成図であり、クロック発振器１に接続すべきＩＣ２の数が、クロック発振器１のファンアウト数より多くなった場合の構成例である。
【００４０】
クロック発振器１の出力に放射状に配置された複数の各配線パターン１３を介して複数のＩＣ２と少なくとも１個のバッファＩＣ４をそれぞれ接続し、ファンアウト数以上のＩＣ２を、そのバッファＩＣ４の出力にそれぞれ放射状に配置した複数の各配線パターン２３を介して１個ずつ接続する。
ファンアウト数の制限により、第１実施形態や第２実施形態の構成をとることが不可能な場合でも、このように構成することによって、共振周波数を高く保つことができる。
【００４１】
図６は、この発明の基礎となるプリント回路基板の第４の例を示す構成図であり、クロック発振器１の出力と複数の各ＩＣ２とを接続する放射状に配置された各配線パターン１３の周囲を、接続するＩＣ２のグランドパターン（斜線を施して示すベタパターン）５によって囲むようにしたものである。あるいはグランドパターン５に代えて電源供給用パターン（以下「Ｖccパターン」という）、あるいはその双方で各配線パターン１３を囲むようにしてもよい。
【００４２】
このようにすることによって、共振周波数をさらに高く保てるので、一層低ノイズ化を図ることができる。
基板１０が両面基板の場合には、その一方の面に図６と同様に放射状の配線パターン１３と、その周囲を囲むグランドパターン５あるいはＶccパターンを形成し、図７に示すように他方の面にも、配線パターン１３を囲むグランドパターン５′あるいはＶccパターンを形成して、それらをスルーホール７で導通させるようにするとよい。このようにすることにより、サージインピーダンスをさらに低下させ、共振周波数をより高くすることができる。
【００４３】
図８は、この発明の基礎となるプリント回路基板の第５の例を示す要部断面図であり、多層基板１０′の中間層に図６と同様な各配線パターン１３が形成され、その各配線パターン１３の上下で、その各配線パターン１３をグランドパターン５とＶccパターン６で囲んだものである。あるいは、上下共にグランドパターン５あるいはＶccパターン６のいずれかによって囲むようにしてもよい。
【００４４】
この例のようなストリップラインタイプの配線パターンは、四方を絶縁物で囲まれているため、キャパシティが多いのでサージインピーダンスＺ０ が、第１から第４の実施形態のようなマイクロストリップラインタイプ（基板上に配線パターンが形成されている）より低くなることが分っている。
【００４５】
図９に、ストリップラインタイプの配線パターンのサージインピーダンスを曲線Ａで、マイクロストリップラインタイプの配線パターンのサージインピーダンスを曲線Ｂでそれぞれ示す。
ここで、ｂ，ｈはそれぞれストリップラインタイプ，マイクロストリップラインタイプの基板の厚さ、ｗは配線パターンの幅、ｔは配線パターンの厚さであり、基板の誘電率ε＝４．８で、ストリップラインタイプではｔ／ｂ＝０．０２の場合、マイクロストリップラインタイプではｔ／ｈ＝０．０３５の場合の、Ｗ／ｈ又はｗ／ｂに対する配線パターンのサージインピーダンスＺ₀（Ω）を示している。
【００４６】
そのため、単位長当りのインダクタンスＬは、数２の式からＣが一定ならばＺ₀ が小さい程小さくなるため、共振周波数を高くすることができる。
したがって、図７に示すような多層基板１０′の場合、その配線パターン１３の構造をストリップラインの構造と同様にすることによって、共振周波数をより高くすることができる。
【００４７】
【数２】

【００４８】
次に、この発明の実施形態について説明する。それは、前述したこの発明の基礎となるプリント回路基板の各例において、クロックパルス発振器の出力端子から長さの異なる複数の配線パターンが放射状に配置されている場合、複数のＩＣのうち最も入力容量の大きいＩＣを、長さが最も短い配線パターンの先端に接続するようにし、複数の各配線パターンのインダクタンスと複数の各ＩＣの入力容量とによる共振周波数を２３０ＭＨｚ以上にしたものである。
【００４９】
例えば、図１０に示すように、クロック発振器の出力端子１ａからの長さが、それぞれ３ｍｍ，５ｍｍ，５ｍｍ，１５ｍｍ，２５ｍｍの各配線パターン１３の先端に、それぞれ入力容量が１５ｐＦ，５ｐＦ，５ｐＦ，１０ｐＦ，５ｐＦのＩＣを接続した場合、出力端子１ａから見た入力インピーダンスＺ16の計算結果は図１１の線図に示すようになる。その共振周波数はサージインピーダンスに拘らず高い値となり、配線パターン１３のサージインピーダンスが１２０Ωの場合は図の外側になってしまっているが、約６００ＭＨｚの非常に高い共振周波数ｆ0aとなる。
【００５０】
これに対して、図１２に示すように、クロック発振器の出力端子１ａからの長さが、それぞれ３ｍｍ，５ｍｍ，５ｍｍ，１５ｍｍ，２５ｍｍの各配線パターン１３の先端に、それぞれ入力容量が５ｐＦ，５ｐＦ，５ｐＦ，１０ｐＦ，１５ｐＦのＩＣを接続した比較例の場合、出力端子１ａから見た入力インピーダンスＺ17の計算結果は図１３の線図に示すようになる。この図から配線パターン１３のサージインピーダンスが１２０Ωの場合についてみると、その共振周波数ｆ0bは約４００ＭＨｚとなる。
【００５１】
この比較結果から明らかなように、クロック発振器の出力配線パターンの長さが短いものに、入力容量の大きいＩＣを配置することによって、配線パターンのインダクタンスとＩＣの入力容量とによる共振周波数を高くすることができる。したがって、複数のＩＣを入力容量の大きいものから順次、複数の配線パターンの短い順に配置することによって、共振周波数を一層高くすることができる。
【００５２】
また、クロック出力の配線パターンの幅を広げるといよい。配線パターンのパターン幅が広い程サージインピーダンスは低くなり、共振周波数を高くすることができる。ここでは、そのパターン幅を広げ、サージインピーダンスを図１３からも判るように、実験結果から３６０Ω程度以下にすることによって、共振周波数をＥＭＩ規制値のゆるい２３０ＭＨｚ以上にもって行くことができ、不要輻射対策のやりやすいプリント回路基板にすることができる。
【００５３】
あるいは、クロック出力の配線パターンとして同軸ケーブルを用いるとよい。同軸ケーブルは、サージインピーダンスが５０Ωあるいは７５Ωのものが一般的である。したがって、クロック出力の配線パターンを同軸ケーブルによって形成することによっても、サージインピーダンスを低くして、共振周波数を高くすることができる。
【００５４】
なお、この発明はマイコンだけでなく、他のデジタル回路、例えばデジタルタイマ回路，Ａ／Ｄ又はＤ／Ａコンバータ，分周器，マルチプレクサ，メモリアクセス回路等、種々のデジタル回路の基本クロックを発生するクロック発振器と、その基本クロックが供給されるＩＣを搭載したプリント回路基板に同様に適用でき、その放射ノイズを低減することができる。
【００５５】
また、最も強い放射ノイズ発生源となる基本クロックについて説明したが、基本クロック以外の放射ノイズの発生が大きい周波数の信号を送出する配線パターンにおいても同様の効果が得られることは明らかである。
【００５６】
【発明の効果】
以上説明してきたように、この発明によれば、プリント回路基板上の基本クロック発振器の出力配線パターンのインダクタンスとそれに接続されるＩＣの入力容量とによる共振周波数を高くして、簡単な対策で放射ノイズを大幅に低減することができる。したがって、フェライトコアやノイズフィルタなどの高価で余分なノイズ対策用の部品が不要になる。
【００５７】
特に、上記共振周波数をＥＭＩ規制値のゆるい２３０ＭＨｚ以上に持っていくことができ、それによって不要輻射対策の容易なプリント回路基板とすることができる。それは、上記共振周波数が２３０ＭＨｚ以上では規制値がゆるくなる他に、スイッチング電源からのベースノイズも減少し、ノイズのピーク部も、発生したとしても周波数が高いため、少しでも回路内に分布容量や浮遊インダクタンス等があればすぐに減衰し易く、その対策は容易だからである。また、クロック発振器のファンアウト数が多い場合でも低ノイズ化を図れる。
その他、各請求項の発明によっても、それぞれ一層低ノイズ化対策が容易なプリント回路基板を得ることができる。
【図面の簡単な説明】
【図１】 この発明の基礎となるプリント回路基板の第１の例を示す構成図である。
【図２】 同じくその具体例を示す等価回路図である。
【図３】 同じくそのクロック発振回路の出力端から見た入力インピーダンスの周波数特性を示す線図である。
【図４】 この発明の基礎となるプリント回路基板の第２の例を示す構成図である。
【図５】 この発明の基礎となるプリント回路基板の第３の例を示す構成図である。
【図６】 この発明の基礎となるプリント回路基板の第４の例を示の構成図である。
【図７】 同じく両面基板の場合の構成例を示す部分的断面図である。
【図８】 この発明の基礎となるプリント回路基板の第５の例を示す要部断面図である。
【図９】 配線パターンのサージインピーダンスの比較例を示す線図である。
【図１０】 この発明の実施形態による複数の各配線パターンの長さとその先端に接続されるＩＣの入力容量との関係を示す図である。
【図１１】 同じくそのクロック発振回路の出力端から見たインピーダンスの周波数特性を示す線図である。
【図１２】 この発明の実施形態との比較例による複数の各配線パターンの長さとその先端に接続されるＩＣの入力容量との関係を示す図である。
【図１３】 同じくそのクロック発振回路の出力端から見たインピーダンスの周波数特性を示す線図である。
【図１４】 従来のマイコンを使用した電子機器からの放射ノイズ周波数成分の例を示す線図である。
【図１５】 同じくその配線パターンのサージインピーダンスが１２０Ωの場合のその配線パターンの長さとその先端のキャパシティ（ＩＣの入力容量）と共振周波数との関係を示す線図である。
【図１６】 従来の一般的なプリント回路基板におけるクロック発振器と複数のＩＣとの配線パターンによる接続例を示す構成図である。
【図１７】 同様な従来例において接続するＩＣを順次増加する場合の等価回路図である。
【図１８】 クロック発振器とＩＣとの１対の配線パターンによる基本的な接続例を示す図である。
【図１９】 Ｚ０＝１２０Ωの場合について図１５の（ａ）〜（ｄ）の各入力インピーダンスＺａ〜Ｚｄの周波数特性を示す線図である。
【符号の説明】
１：クロック発振器 ２：ＩＣ（半導体集積回路）
３：配線パターン ４：バッファＩＣ
５：グランドパターン
６：電源供給用パターン（Ｖccパターン）
１０：プリント回路基板 １０′：多層基板
１３，２３：放射状の配線パターン
１３ｃ：分岐パターン[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a printed circuit board (PCB) used for a digital circuit such as a microcomputer (hereinafter simply referred to as “microcomputer”) incorporated in various electronic devices, in particular, a clock oscillator for generating a basic clock of the digital circuit, The present invention relates to a technique for reducing EMI (electromagnetic interference) from a printed circuit board on which a plurality of ICs (semiconductor integrated circuits) to which the basic clock is supplied are mounted.
[0002]
[Prior art]
In recent years, microcomputers have been adopted in OA devices, personal computers, home appliances, and other electronic devices, and their clock frequencies have been increasing year by year. For this reason, the radiation noise from the electronic device using this becomes high frequency, and radiation noises of different frequencies from various devices are mixed and become very complicated.
[0003]
The limit value of such radiated noise is determined by VCCI, CISPR standard, FCC, etc., which are standards for regulating the amount of radiation, but depending on the equipment, such complicated and high frequency noise may be It has become very difficult to keep within limits.
[0004]
On the other hand, the number of wireless communication devices such as pagers, mobile phones, PHS, wireless LAN, etc. is increasing, and an electromagnetic environment in which such wireless devices and electronic devices using microcomputers do not adversely affect each other. Therefore, the realization of an effective EMI countermeasure method is an important social issue.
[0005]
As shown in FIG. 14, radiation noise from an electronic device using a microcomputer is generally a base part made up of low frequency harmonics from a switching power supply and harmonics of a clock frequency of a digital circuit such as a microcomputer. It consists of a coniferous forest belt-like peak.
In order to keep such radiated noise within the specification limit, it is of course necessary to reduce the base part, but the peak part does not affect the performance of the electronic device and is simple and low-cost. It is necessary to take measures by the method.
[0006]
Normally, functional design and evaluation of electronic devices have been completed at the time of countermeasures against radiated noise, and if radiated noise exceeds the limit value and countermeasures are required at the time of evaluation, the circuit will be changed. Again, the functional design and the review of the evaluation are required, resulting in a great deal of confusion in the design process and a great loss.
[0007]
Thus, in many cases, conventional countermeasures against radiated noise have been made after product design and evaluation thereof, so that a harness cable between wirings is wrapped around an expensive ferrite core so that the circuit is not changed as much as possible. I covered the parts that seemed to be the source of radiation noise with metal plates. For this reason, this countermeasure against radiation noise has caused a significant increase in cost.
[0008]
In addition, even if measures are taken at the time of circuit design instead of such ex-post measures, the source of radiated noise cannot be identified at the time of design. Is to be treated.
As countermeasures, for example, a method using an expensive ferrite containing board connector, or inserting a large number of CR filters or ferrite beads into each address line or bus line including a clock line is available. It has been taken.
[0009]
As a result, the number of countermeasure parts increases, and the product cost increases not only because of these countermeasure parts, but also because the parts do not fit into a limited space in the board mounting design. The problem was great, such as having to use the substrate.
[0010]
[Problems to be solved by the invention]
As described above, EMI countermeasures on printed circuit boards of electronic devices in recent years are difficult and the cost of the countermeasures is high. In the conventional countermeasures, the location of the radiation noise source is speculated by speculation. It depends on having been treated.
[0011]
In order to improve the drawbacks of the conventional EMI countermeasures as described above, the present invention makes it possible to clarify the cause of radiation noise, and to reduce the radiation noise at the design time to the location where the noise occurs, thereby reducing the cost. An object of the present invention is to realize a printed circuit board that can reduce the countermeasures against radiation noise after design evaluation.
[0012]
[Means for Solving the Problems]
  In order to achieve the above object, the present invention provides a printed circuit board including a clock oscillator for generating a basic clock of a digital circuit such as a microcomputer and a plurality of ICs to which the basic clock is supplied. A plurality of wiring patterns respectively connecting the plurality of ICs to the output are arranged radially,The plurality of ICs are sequentially connected in descending order of the input capacitance, and the plurality of wiring patterns are connected in the short order, and the resonance frequency due to the inductance of each of the plurality of wiring patterns and the input capacitance of each of the plurality of ICs is 230 MHz or more. It is what.
  In this way, multiple wiring patterns that connect the clock oscillator and multiple ICs are arranged radially.Then, if a plurality of ICs are connected in order from the largest input capacitance in the short order of the plurality of wiring patterns, the surge impedance can be increased, and the resonance frequency is increased to 230 MHz or more.It can be kept high and measures against radiation noise can be facilitated.
  the aboveWhen the resonance frequency is 230 MHz or higher, the regulation value becomes loose, the base noise from the switching power supply also decreases, and the peak part of the noise is high even if it occurs. If there is, it is easy to attenuate immediately, and the countermeasure is easy.
[0013]
One IC may be connected to the tip of each wiring pattern arranged radially. Alternatively, a branch pattern may be provided in the radially arranged wiring pattern, and one IC may be connected to the tip of each wiring pattern including the branch pattern.
[0014]
Further, at least one of the ICs connected to the tips of the respective wiring patterns arranged in a radial manner is used as a buffer IC, and wiring patterns for connecting a plurality of ICs to the output of the buffer IC are arranged in a radial manner. For example, even when the number of ICs to be connected is larger than the number of fan-outs of the clock oscillator, the noise can be reduced.
[0015]
In these printed circuit boards, by enclosing each wiring pattern with a ground pattern of an IC to be connected and / or a pattern for supplying power, the resonance frequency can be kept higher and noise can be further reduced. . When the wiring patterns are arranged on the intermediate layer of the multilayer substrate, the wiring patterns may be surrounded by the ground pattern and / or the power supply pattern above and below the wiring patterns.
[0017]
Further, by widening the pattern width of each wiring pattern so that the characteristic impedance of the wiring pattern is about 360 ohms or less, or by forming each wiring pattern with a cable having a low characteristic impedance such as a coaxial cable. However, the resonance frequency can be further increased to facilitate the countermeasure against radiation noise.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Prior to the description, the cause of radiation noise from an electronic device will be studied and the contents that have become clear will be described.
[0019]
Even if the cause of the radiated noise peak is ultimately radiated from the wire harness or casing of the electronic device, the source is due to some resonant circuit in the printed circuit board. I have been searching for the cause.
As a result, the resonant circuit in such a printed circuit board has a standing wave due to the inductance of the output wiring pattern of the clock oscillator mounted on the board and the input capacitance of the IC to which the basic clock is supplied by the wiring pattern. It is concluded that it will be made by standing. The clock oscillator generates a basic clock for a digital circuit such as a microcomputer.
[0020]
In general, when considering the 100 to 300 MHz band where radiation noise is most generated, the length of the quarter wavelength is about 38 cm at the center frequency of 200 MHz, and the radiation noise is reduced in a printed circuit board using a normal microcomputer. Since the wiring pattern is designed to be as short as possible, there are practically few such wirings, and this alone does not satisfy a resonance condition that can be a source of radiation noise.
[0021]
However, when considering an IC connected to such a wiring pattern, there is generally an input capacitance of about 5 to 15 pF. Therefore, when it is considered that such a capacitance and the wiring pattern resonate, the surge impedance Z which is the impedance of the wiring pattern itself₀ Is 120Ω, the length of the wiring pattern l₀The relationship between (mm), the capacity of the tip (IC input capacitance) and the resonance frequency is as shown by a diagram in FIG.
[0022]
Therefore, for example, when the input capacitance is 10 pF, the wiring pattern l at the point A in FIG.₀ When the length of is obtained, the length is 140 mm. In addition, considering that there is not only one IC connected, it will resonate with a shorter wiring pattern shorter than this, and this length of wiring pattern is sufficiently present in the printed circuit board. There is something to do.
[0023]
Further, it has been clarified that the most peaked radiation noise in the resonance circuit is caused by the clock signal output wiring pattern of the clock oscillator. In addition, regarding the radiated noise of electronic equipment using a microcomputer, the radiated noise level produced by the basic clock and its frequency-divided clock was measured, and as a result, it was found that the majority was derived from the basic clock.
[0024]
Therefore, in the case where a plurality of (in this example, five) ICs 2 are connected to each other through a common wiring pattern 3 to the output of the clock oscillator 1 as shown in FIG. think about.
[0025]
As an example, as shown in FIG. 17 (d), there are 5 input capacitors, one at each of the output wiring patterns 0, 20, 50, 70, and 100 mm from the output terminals a and b of the clock oscillator. , 10, 10, 5, 10 pF When five ICs are connected, a decrease in the resonance frequency generated by the inductance of these wiring patterns and the input capacitance of the IC will be considered. (A), (b), and (c) in FIG. 17 sequentially show the connection process leading to (d).
[0026]
First, as shown in FIG.₀The output of the clock oscillator 1 is connected to the input terminals {circle around (1)} and {circle around (2)} of the pair of wiring patterns 3a and 3b of (mm), and the clock terminal of the IC2 is connected to the output terminals {circle over (3)} and {circle around (4)}. In the basic equivalent circuit, the impedance of the wiring patterns 3a and 3b (surge impedance of the board) is set to Z₀, Input voltage to V₁, Input current I₁, Output voltage to V₂, Output current I₂, The input impedance viewed from the input terminal (1), (2) is Z₁, The impedance between output terminals (3) and (4) is Z₂Then, the relational expressions shown in Equations (1), (2), and (3) hold between them.
[0027]
[Expression 1]

[0028]
Using each equation of Equation 1, Z₀= Input impedance Z with respect to clock frequency for the case of 120Ω₁/ Z₀The result of calculating the relationship is shown in FIG. In the figure, Za, Zb, Zc, and Zd correspond to the input impedances Za to Zd of (a) to (d) of FIG.
[0029]
Where Z₁/ Z₀The frequency when = 0 is the resonance frequency. As shown in FIGS. 17A to 17D, the resonance frequency is f1a = 451.5 MHz and f1b = 340 every time one IC is connected. .3 MHz, f1c240 = MHz, f1d = 199.1 MHz, and finally 199.9 MHz.
[0030]
Usually, the radiated noise from the electronic device is in the frequency band of 100 to 300 MHz as shown in FIG. 14, and the base of the high frequency noise from the switching power supply used in most electronic devices rises in this band. Moreover, the peak-like component appears most strongly. In addition, the standard limit value in the band of 230 MHz or less is 7 dB that is stricter than the band of 230 MHz or more, and is therefore a band that is very difficult to suppress.
[0031]
  On the other hand, for example, a component in a frequency band of 300 MHz or higher is 230 MHz or higher.Regulatory valueIn addition to loosening, the base noise from the switching power supply is reduced, and even if the noise peak occurs, the frequency is high, so if there is any distributed capacitance or stray inductance in the circuit, it is easy to attenuate immediately The countermeasures are easy.
[0032]
For this reason, if the resonance frequency generated in the circuit is 300 MHz or less, particularly 230 MHz or less, it is very difficult to take measures against radiation noise.
In order to prevent this decrease in the resonance frequency, it is necessary to shorten the distance of the wiring pattern to each IC as much as possible. However, there is a limit to the length that can be shortened by the physical size of the IC.
[0033]
  An embodiment of the present invention will be described below.
  FIG. 1 illustrates the invention.Shows first example of underlying printed circuit board1 is a block diagram showing a configuration in which a clock oscillator 1 for generating a basic clock of a digital circuit such as a microcomputer and a plurality of (in this example, five) ICs (semiconductor integrated circuits) 2 to which the basic clock is supplied are mounted. In the circuit board 10, five wiring patterns 13 for connecting a plurality of ICs 2 to the output of the clock oscillator 1 are arranged in a radial pattern, and one IC 2 is connected to the tip of each wiring pattern 13. ).
[0034]
As an actual example, for example, similarly to the example shown in FIG. 17, five ICs 2 each having an input capacity of 10 PF, 5 PF, 10 PF, 10 PF, and 5 PF are replaced by the same clock oscillator 1 as shown in FIG. Are connected to the output terminals a and b via five wiring patterns 13 arranged in a radial pattern of 30 mm, 20 mm, 20 mm, 30 mm, and 30 mm, respectively.
[0035]
In this example, the input impedance Z viewed from the output terminals a and b of the clock oscillator.₁/ Z₀The result of calculating is shown in FIG.
As can be seen from FIG. 3, the resonance frequencies are 451 MHz and 558 MHz, and the lower 451 MHz is much higher than the 199.1 MHz obtained for the conventional case of FIG. Although the total capacitance of the five ICs 2 is 40 pF and the wiring pattern length to each IC 2 is the same as that shown in FIG. 17D except for the common pattern part, the amount of decrease in the resonance frequency is Very few printed circuit boards can be obtained.
[0036]
In this way, the clock oscillator 1 and each of the plurality of ICs 2 are connected by the wiring lines 13 that are individually arranged radially, so that the resonance frequency generated by the inductance of the wiring pattern 13 and the input capacitance of the IC 2 can be changed. Even if the number increases, it can be kept at a high frequency without much decrease. In addition, by arranging the wiring patterns for connecting the ICs 2 in a radial manner (the shark-feeding method), there is no common pattern part as in the conventional method, so the pattern length to each IC is shortened, and resonance also occurs in this aspect. The frequency can be increased.
[0037]
As a result, a large radiation noise reduction effect can be obtained, and expensive and extra noise countermeasure parts such as a ferrite core and a noise filter are not required, and since the resonance frequency is high, it can be easily attenuated even if noise occurs. As a result, low-cost noise countermeasures are possible.
[0038]
  FIG. 4 shows the present invention.Second example of a basic printed circuit boardThe same reference numerals are given to the parts corresponding to those in FIG. In this embodiment, a branch pattern 13c is provided for each of the plurality of wiring patterns 13, and one IC 2 is connected to the tip of each wiring pattern 13 including the branch pattern 13c.
  Even if it does in this way, the effect | action and effect similar to the case of the above-mentioned 1st Embodiment can be acquired. Note that the branch pattern 13c may be provided only in a part rather than in all of the wiring patterns 13.
[0039]
  FIG. 5 shows the present invention.Third example of the basic printed circuit boardFIG. 2 is a configuration diagram illustrating a case where the number of ICs 2 to be connected to the clock oscillator 1 is larger than the number of fanouts of the clock oscillator 1.
[0040]
A plurality of ICs 2 and at least one buffer IC 4 are connected to each other through a plurality of wiring patterns 13 arranged radially at the output of the clock oscillator 1, and ICs equal to or greater than the fanout number are connected to the outputs of the buffer ICs 4, respectively. One by one is connected via a plurality of wiring patterns 23 arranged radially.
Even if it is impossible to take the configuration of the first embodiment or the second embodiment due to the limitation of the number of fan-outs, this configuration can keep the resonance frequency high.
[0041]
  FIG. 6 shows the present invention.4th example of basic printed circuit boardThe ground pattern (solid pattern shown by hatching) 5 of the IC 2 to be connected around the wiring patterns 13 arranged radially connecting the output of the clock oscillator 1 and the plurality of ICs 2. It is made to enclose by. Alternatively, each wiring pattern 13 may be surrounded by a power supply pattern (hereinafter referred to as “Vcc pattern”) or both instead of the ground pattern 5.
[0042]
By doing so, the resonance frequency can be kept higher, so that noise can be further reduced.
When the substrate 10 is a double-sided substrate, a radial wiring pattern 13 and a ground pattern 5 or Vcc pattern surrounding the periphery are formed on one surface as in FIG. 6, and the other surface is formed as shown in FIG. In addition, it is preferable to form a ground pattern 5 ′ or a Vcc pattern surrounding the wiring pattern 13 and to make them conductive through the through hole 7. By doing so, the surge impedance can be further reduced and the resonance frequency can be further increased.
[0043]
  FIG. 8 shows the present invention.The fifth example of the basic printed circuit board6 is formed in the intermediate layer of the multilayer substrate 10 ′, and the wiring patterns 13 similar to those in FIG. 6 are formed above and below the wiring patterns 13, and the wiring patterns 13 are connected to the ground pattern 5 and Vcc. It is surrounded by pattern 6. Alternatively, the upper and lower sides may be surrounded by either the ground pattern 5 or the Vcc pattern 6.
[0044]
  Of this exampleSince such a stripline type wiring pattern is surrounded by an insulator on all sides, it has a large capacity. Therefore, the surge impedance Z0 is reduced to the microstripline type (on the substrate) as in the first to fourth embodiments. It is known that the wiring pattern is lower).
[0045]
FIG. 9 shows the surge impedance of the stripline type wiring pattern as a curve A, and the surge impedance of the microstripline type wiring pattern as a curve B, respectively.
Here, b and h are the thickness of the substrate of the stripline type and the microstripline type, respectively, w is the width of the wiring pattern, t is the thickness of the wiring pattern, and the dielectric constant ε = 4.8 of the substrate, Surge impedance Z of the wiring pattern with respect to W / h or w / b when t / b = 0.02 for the stripline type and t / h = 0.035 for the microstripline type₀(Ω) is shown.
[0046]
Therefore, if the inductance L per unit length is constant from the equation (2), Z₀ Since the smaller the value, the smaller the resonance frequency, the resonant frequency can be increased.
Therefore, in the case of the multilayer substrate 10 ′ as shown in FIG. 7, the resonance frequency can be further increased by making the structure of the wiring pattern 13 the same as that of the stripline.
[0047]
[Expression 2]

[0048]
  next,An embodiment of the present invention will be described. In each example of the printed circuit board that forms the basis of the present invention described above,When a plurality of wiring patterns having different lengths are arranged radially from the output terminal of the clock pulse oscillator, the IC having the largest input capacitance among the plurality of ICs is connected to the tip of the wiring pattern having the shortest length. West,The resonance frequency due to the inductance of each wiring pattern and the input capacitance of each IC is set to 230 MHz or more.It is a thing.
[0049]
For example, as shown in FIG. 10, the length from the output terminal 1a of the clock oscillator is 3 mm, 5 mm, 5 mm, 15 mm, and 25 mm, respectively, and the input capacitance is 15 pF, 5 pF, 5 pF, When 10 pF and 5 pF ICs are connected, the calculation result of the input impedance Z16 viewed from the output terminal 1a is as shown in the diagram of FIG. The resonance frequency becomes a high value regardless of the surge impedance. When the surge impedance of the wiring pattern 13 is 120Ω, the resonance frequency is outside the figure, but becomes a very high resonance frequency f0a of about 600 MHz.
[0050]
On the other hand, as shown in FIG. 12, the length from the output terminal 1a of the clock oscillator is 3 mm, 5 mm, 5 mm, 15 mm, and 25 mm at the tip of each wiring pattern 13, respectively, and the input capacitance is 5 pF and 5 pF, respectively. , 5pF, 10pF, and 15pF, the calculation result of the input impedance Z17 viewed from the output terminal 1a is as shown in the diagram of FIG. From this figure, when the surge impedance of the wiring pattern 13 is 120Ω, the resonance frequency f0b is about 400 MHz.
[0051]
As is clear from this comparison result, by placing an IC having a large input capacitance on the output wiring pattern of the clock oscillator having a short length, the resonance frequency due to the inductance of the wiring pattern and the input capacitance of the IC is increased. be able to. Therefore, the resonance frequency can be further increased by arranging a plurality of ICs in order of increasing input capacitance in order of a plurality of wiring patterns.
[0052]
  Also,The width of the clock output wiring patternWhen you spread. The wider the pattern width of the wiring pattern, the lower the surge impedance and the higher the resonance frequency. Here, as shown in FIG. 13, by increasing the pattern width and reducing the surge impedance to about 360Ω or less from the experimental results, the resonance frequency can be raised to 230 MHz or more, which is a loose EMI regulation value, and unnecessary radiation. It can be a printed circuit board that is easy to take measures against.
[0053]
  OrUse coaxial cable as clock output wiring patternAnd good. The coaxial cable generally has a surge impedance of 50Ω or 75Ω. Therefore, by forming the clock output wiring pattern with a coaxial cable, the surge impedance can be lowered and the resonance frequency can be raised.
[0054]
The present invention generates basic clocks for various digital circuits such as a digital timer circuit, an A / D or D / A converter, a frequency divider, a multiplexer, a memory access circuit, etc., as well as a microcomputer. The present invention can be similarly applied to a printed circuit board on which a clock oscillator and an IC to which the basic clock is supplied are mounted, and the radiation noise can be reduced.
[0055]
Further, although the basic clock that is the strongest radiation noise generation source has been described, it is obvious that the same effect can be obtained even in a wiring pattern that transmits a signal of a frequency other than the basic clock that generates large radiation noise.
[0056]
【The invention's effect】
As described above, according to the present invention, the resonance frequency due to the inductance of the output wiring pattern of the basic clock oscillator on the printed circuit board and the input capacitance of the IC connected thereto is increased, and radiation can be performed with a simple measure. Noise can be greatly reduced. Therefore, expensive and extra noise countermeasure parts such as a ferrite core and a noise filter are not required.
[0057]
  In particular, the resonant frequency can be brought to 230 MHz or more, which is a loose EMI regulation value, whereby a printed circuit board with easy countermeasures against unnecessary radiation can be obtained.This is because, when the resonance frequency is 230 MHz or more, the regulation value becomes loose, the base noise from the switching power supply also decreases, and the peak portion of the noise is high even if it occurs. This is because if there is a stray inductance or the like, it is easy to attenuate immediately and the countermeasures are easy.In addition, noise can be reduced even when the number of fan-outs of the clock generator is large.
  In addition, according to the invention of each claim, it is possible to obtain a printed circuit board in which measures for reducing noise can be further facilitated.
[Brief description of the drawings]
FIG. 1 of the present inventionShows first example of underlying printed circuit boardIt is a block diagram.
FIG. 2 is an equivalent circuit diagram showing a specific example of the same.
FIG. 3 is a diagram showing the frequency characteristics of the input impedance as seen from the output terminal of the clock oscillation circuit.
FIG. 4 of the present inventionShows second example of underlying printed circuit boardIt is a block diagram.
FIG. 5 of the present inventionShows third example of underlying printed circuit boardIt is a block diagram.
FIG. 6 of the present inventionShows fourth example of underlying printed circuit boardFIG.
FIG. 7 is a partial cross-sectional view showing a configuration example in the case of a double-sided substrate.
FIG. 8 of the present inventionShows fifth example of underlying printed circuit boardIt is principal part sectional drawing.
FIG. 9 is a diagram showing a comparative example of surge impedance of a wiring pattern.
FIG. 10 shows the present invention.EmbodimentIt is a figure which shows the relationship between the length of each of several wiring patterns by IC, and the input capacitance of IC connected to the front-end | tip.
FIG. 11 is a diagram showing the frequency characteristics of impedance as seen from the output terminal of the clock oscillation circuit.
FIG.Embodiment of the present inventionIt is a figure which shows the relationship between the length of each wiring pattern by the comparative example, and the input capacitance of IC connected to the front-end | tip.
FIG. 13 is a diagram showing the frequency characteristics of impedance as seen from the output end of the clock oscillation circuit.
FIG. 14 is a diagram showing an example of a noise frequency component radiated from an electronic device using a conventional microcomputer.
FIG. 15 is a diagram showing the relationship between the length of the wiring pattern, the capacity of the tip (IC input capacitance) and the resonance frequency when the surge impedance of the wiring pattern is 120Ω.
FIG. 16 is a configuration diagram showing a connection example of a clock oscillator and a plurality of ICs in a conventional general printed circuit board by a wiring pattern.
FIG. 17 is an equivalent circuit diagram in the case where ICs to be connected are sequentially increased in a similar conventional example.
FIG. 18 is a diagram illustrating a basic connection example using a pair of wiring patterns between a clock oscillator and an IC.
19 is a diagram showing frequency characteristics of input impedances Za to Zd in FIGS. 15A to 15D in the case of Z0 = 120Ω. FIG.
[Explanation of symbols]
1: Clock oscillator 2: IC (semiconductor integrated circuit)
3: Wiring pattern 4: Buffer IC
5: Ground pattern
6: Power supply pattern (Vcc pattern)
10: Printed circuit board 10 ': Multilayer board
13, 23: Radial wiring pattern
13c: Branch pattern

Claims (7)

In a printed circuit board equipped with a clock oscillator for generating a basic clock of a digital circuit such as a microcomputer and a plurality of ICs to which the basic clock is supplied,
A plurality of wiring patterns respectively connecting the plurality of ICs to the output of the clock oscillator are arranged radially, the plurality of ICs are sequentially connected in descending order of the input capacitance, and the plurality of wiring patterns are connected in the short order, A printed circuit board having a resonance frequency of 230 MHz or more due to an inductance of each wiring pattern and an input capacitance of each of the plurality of ICs . The printed circuit board according to claim 1,
A printed circuit board, wherein a branch pattern is provided in the radially arranged wiring pattern, and one IC is connected to the tip of each wiring pattern including the branch pattern. The printed circuit board according to claim 1 ,
At least one of the ICs connected to the tips of the respective wiring patterns arranged radially is used as a buffer IC, and wiring patterns that connect a plurality of ICs to the output of the buffer IC are arranged radially. Characteristic printed circuit board. In the printed circuit board according to any one of claims 1 to 3, wherein each wiring pattern, a ground pattern or the power supply pattern for connecting an IC or printed circuit, characterized in that enclosed in the patterns of the both substrate. In the printed circuit board according to claim 4,
A printed circuit, wherein each wiring pattern is formed in an intermediate layer of a multilayer substrate, and each wiring pattern is surrounded by the ground pattern and / or a power supply pattern above and below each wiring pattern. substrate. The printed circuit board according to any one of claims 1 to 5 ,
A printed circuit board characterized in that the pattern width of each wiring pattern is widened so that the characteristic impedance of the wiring pattern is about 360 ohms or less. The printed circuit board according to any one of claims 1 to 5 ,
A printed circuit board, wherein each of the wiring patterns is formed of a cable having a low characteristic impedance such as a coaxial cable.

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