JP3890014B2 - Semiconductor memory device and test method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device including a nonvolatile memory cell and a test method thereof.
[0002]
Electronic devices such as portable information terminals are equipped with a storage device for storing various kinds of information. As the storage device, a nonvolatile memory capable of electrically writing and erasing data is used. Yes. In a nonvolatile memory test performed at the time of product shipment, it is determined whether or not data writing / erasing characteristics are normal, and those having abnormal characteristics need to be removed as defective products. For this reason, a test circuit for detecting a write state is provided in the nonvolatile memory, but a technique for simplifying the circuit configuration and preventing an increase in die size is required.
[0003]
[Prior art]
In general, a flash memory cell, which is a non-volatile memory, includes two layers of polysilicon gates, a control gate and a floating gate (see, for example, Patent Document 1). The floating gate is a gate for holding electrons injected by writing, the periphery of which is completely covered with an insulator (SiO2).
[0004]
In the test of the nonvolatile memory, it is necessary to measure the threshold voltage of the cell transistor in the memory cell in order to evaluate whether the write / erase characteristics are normal.
[0005]
In a memory cell having a two-layer polysilicon structure, it is difficult to draw out the floating gate as an electrode, and the potential of the floating gate cannot be directly observed. Therefore, in a memory cell having a two-layer polysilicon structure, a desired potential change is given to the floating gate by changing the potential of the word line (control gate). Then, a method has been used in which the threshold voltage of the transistor is indirectly measured by comparing the current flowing through the memory cell and the reference current flowing through the measurement reference cell due to the potential change.
[0006]
[Patent Document 1]
JP-A-6-29494
[0007]
[Problems to be solved by the invention]
By the way, since the floating gate and the word line (control gate) are coupled by the capacitance of the oxide film between them, a desired potential change in the floating gate is generated unless a large potential change is applied to the word line. Can't get. Therefore, a circuit for applying a high voltage to the word line is required. Further, considering the reliability of the circuit for applying the high voltage and the peripheral portion thereof, the circuit configuration becomes complicated, which causes a problem that the die size of the semiconductor memory device is increased.
[0008]
The present invention has been made to solve the above-described problems, and an object of the present invention is to realize a simple and reliable test circuit and to suppress an increase in die size and a test thereof. It is to provide a method.
[0009]
[Means for Solving the Problems]
FIG. 1 is an explanatory diagram of the principle of the present invention. That is, the memory cell 1 of the semiconductor memory device is a nonvolatile memory cell and is connected to the word line SWL. Has a single-layer polysilicon structure Select transistor T1 and connected in series to select transistor T1 Has a single-layer polysilicon structure The cell transistor T2 includes a capacitor C1 connected to the gate (floating gate) of the cell transistor T2. The memory cell 1 is connected to the current comparison circuit 2 via the wiring BL. A test reference memory cell 3 is connected to the current comparison circuit 2 via a test wiring TRBL. The test reference memory cell 3 is Has a single-layer polysilicon structure A reference selection transistor T1r and a series connection to the reference selection transistor T1r Has a single-layer polysilicon structure A reference cell transistor T2r.
[0010]
Since each of the memory cells 1 and 3 has a single-layer polysilicon structure, its floating gate is formed by the same process as that of a normal MOS transistor. Therefore, unlike a memory cell having a two-layer polysilicon structure, it is possible to draw out the floating gate as an electrode. Therefore, the setting means 4 for setting the gate voltage can be connected to the gate of the reference cell transistor T2r in the test reference memory cell 3. A desired gate voltage is applied by the input signal from the setting means 4, and the reference current flowing through the test reference memory cell 3 is adjusted. Then, the current comparison circuit 2 compares the reference current with the read current flowing through the memory cell 1 to evaluate the data write / erase characteristics in the memory cell 1.
[0011]
Specifically, the current comparison circuit 2 is a sense amplifier that compares the read current of the memory cell 1 with a reference current and amplifies and outputs the current difference.
The semiconductor memory device includes a reference current generation circuit, a test reference current generation circuit, and a test circuit. A reference current used for normal read operation is generated by the reference current generation circuit. A test reference current is generated by the test reference current generation circuit. A test signal is input from the test circuit to the reference current generation circuit and the test reference current generation circuit, the reference current generation circuit is deactivated, and the test reference current generation circuit is activated. Further, the test signal of the test circuit is input to the current comparison circuit (sense amplifier). In this case, during the test, the reference current of the test reference current generating circuit and the read current flow through the sense amplifier, and these currents are compared.
[0012]
In the test reference current generation circuit, an equivalent characteristic pseudo circuit having the same circuit configuration as the path of the read current flowing through the memory cell is provided in the current path through which the test reference current flows.
[0013]
The equivalent characteristic pseudo circuit includes an equivalent circuit of a column selection circuit and an equivalent circuit of a sense amplifier. By providing this circuit, the reference current of the test reference memory cell is adjusted.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, an embodiment of the invention will be described with reference to the drawings.
FIG. 2 is a block circuit diagram showing the macro memory 11 of the present embodiment. The macro memory 11 is mounted on a one-chip semiconductor device (LSI) together with a logic unit (not shown).
[0015]
The macro memory 11 includes a read / write operation control unit 12, an X decoder 13, a Y decoder 14, a Y selection gate circuit 15, a ground supply circuit 16, a test circuit 17, a memory cell 1, a read amplifier (sense amplifier) 2, a reference A cell 20, a reference current generation circuit 21, and a test reference current generation circuit 22 are provided.
[0016]
The read / write operation control unit 12 receives an input signal such as an address / data / command from the logic unit. The read / write operation control unit 12 controls data read and write operations in the macro memory 11 based on the input signal.
[0017]
Here, for example, when a read command and an address are input as an input signal, the read / write operation control unit 12 inputs an upper bit address signal included in the input signal to the X decoder 13 and inputs a lower bit address. The signal is input to the Y decoder 14. Then, the memory cell 1 to be read is selected from the plurality of memory cells by the X decoder 13 and the Y decoder 14.
[0018]
Specifically, the X decoder 13 selects a predetermined word line by decoding an upper bit address signal. The Y decoder 14 decodes the lower bit address signal and inputs the decoded signal to the Y selection gate circuit 15. The Y selection gate circuit 15 selects the bit line BL of the memory cell 1 to be read based on the decode signal of the Y decoder 14, and connects the bit line BL to the data bus RDB. As a result, the memory cell 1 to be read is connected to the read amplifier 2 via the bit line BL and the data bus RDB, and a signal corresponding to the data stored in the memory cell 1 is output from the read amplifier 2.
[0019]
The ground supply circuit 16 is a circuit for supplying a source potential to the cell transistor of the memory cell 1 and supplies a ground potential (0 V) at the time of reading. The ground supply circuit 16 supplies a ground potential (0 V) or a high potential (6 V) to the memory cell 1 in accordance with the data value at the time of writing.
[0020]
A test entry signal RTE is input to the test circuit 17 from a test device (not shown). The test circuit 17 selects a predetermined test mode when detecting the input of the entry signal RTE. Here, when a test mode for testing data write / erase characteristics is selected, the test circuit 17 outputs an H level test signal TMRW. The test signal TMRW is input to the read / write operation control unit 12, the read amplifier 2, the reference current generation circuit 21, and the test reference current generation circuit 22.
[0021]
When the test signal TMRW is at L level (during a normal read operation), the reference current generation circuit 21 is activated and the test reference current generation circuit 22 is deactivated. A reference cell 20 is connected to the reference current generation circuit 21, and a signal corresponding to the current flowing through the reference cell 20 is output from the reference current generation circuit 21. In the read amplifier 2, a reference current corresponding to the output signal of the reference current generation circuit 21 flows, and the reference current is compared with the read current of the memory cell 1. Then, an output signal obtained by amplifying the current difference is output from the read amplifier 2 as read data.
[0022]
On the other hand, when the test signal TMRW is at the H level (during testing), the reference current generation circuit 21 is deactivated and the test reference current generation circuit 22 is activated. In this case, in the read amplifier 2, a test reference current flows based on the output signal of the test reference current generation circuit 22, and the test reference current is compared with the read current of the memory cell 1. An output signal RANAOUT obtained by amplifying the current difference is output from the read amplifier 2 as read data.
[0023]
The output signal RANAOUT is multiplexed with a signal of a logic unit provided outside the macro memory 11, and is finally output from a package pin (external terminal) of a product (LSI).
[0024]
Hereinafter, each circuit configuration of the macro memory 11 will be described in detail.
FIG. 3 shows the memory cell 1. The memory cell 1 is a nonvolatile memory cell having a single-layer polysilicon structure, and includes a selection transistor T1, a cell transistor T2, and a capacitor C1. The selection transistor T1 and the cell transistor T2 are NMOS transistors.
[0025]
The selection transistor T1 and the cell transistor T2 are connected in series. The selection transistor T1 has a drain connected to the bit line BL and a gate connected to the word line SWL. The source of the selection transistor T1 is connected to the drain of the cell transistor T2, and the signal ARVSS from the ground supply circuit 16 (0V for reading and 6V or 0V for writing) is supplied to the source of the cell transistor T2. .
[0026]
The gate of the cell transistor T2 is a floating gate made of polysilicon. A capacitor C1 is formed using a part of the floating gate as an electrode. Capacitor C1 has a triple well structure including an N well layer, a P well layer, and an N type diffusion layer formed on a P type substrate.
[0027]
The N-type diffusion layer of the capacitor C1 functions as a control gate and is connected to the control word line CWL. When a predetermined high voltage is applied between the control word line CWL and the source of the cell transistor T2 (the output signal ARVSS of the ground supply circuit 16), a tunnel current flows between the source of the cell transistor T2 and the floating gate. As a result, charges are injected into the floating gate, and the floating gate is held at a predetermined potential level.
[0028]
In the macro memory 11, a plurality of memory cells 1 are provided for one bit line BL, and a predetermined memory cell to be read out of the plurality of memory cells 1 by turning on the selection transistor T1. 1 is connected to the bit line BL. As a result, a read current corresponding to the gate voltage of the cell transistor T2 (the voltage of the floating gate) flows through the memory cell 1.
[0029]
At the time of reading, a voltage of 0 V is supplied to the control gate (N-type diffusion layer of the capacitor C1) through the control word line CWL. At this time, the signal VNW of the power supply voltage (= 3V) is supplied to the N well layer of the capacitor C1, and the signal VPW of 0V is supplied to the P well layer.
[0030]
FIG. 4 shows the ground supply circuit 16.
In the ground supply circuit 16, two PMOS transistors Tp1, Tp2 and an NMOS transistor Tn1 are connected in series. The potential at the connection between the PMOS transistor Tp2 and the NMOS transistor Tn1 is supplied as the output signal ARVSS to the source of the cell transistor T2 in the memory cell 1.
[0031]
The gates of the transistors Tp1 and Tn1 are connected to each other, and the output signal of the latch unit 16a is input to each gate. A control signal ARVREF is input to the gate of the transistor Tp2. The latch unit 16a latches the write data WDBj via the NMOS transistor Tn2 controlled by the decode signal YTi.
[0032]
At the time of data writing, one of the transistors Tp1 and Tn1 is turned on according to the data latched by the latch unit 16a. The transistor Tp2 is turned on by the control signal ARVREF. Thereby, at the time of data writing, the high potential side power supply VS (= 6V) or the low potential side power supply ARGND (= 0V) is supplied to the memory cell 1 as the output signal ARVSS of the ground supply circuit 16 according to the write data.
[0033]
Further, when reading data, the PMOS transistors Tp1 and Tp2 are turned off and the NMOS transistor Tn1 is turned on, whereby the low potential side power supply ARGND (= 0V) is supplied to the memory cell 1 as the output signal ARVSS of the ground supply circuit 16. .
[0034]
FIG. 5 shows the Y selection gate circuit 15.
The Y selection gate circuit 15 selects the bit line BL of the memory cell 1 to be read based on the decode signals YD0 and YD1, and connects the bit line BL to the data bus RDB. For the sake of convenience, in FIG. 5, the signal lines of the bit lines BL (BL0 to BL7) and the decode signal YD0 (YD00 to YD07) are shown as one common line. The Y selection gate circuit 15 is a circuit for 1 byte, and the macro memory 11 is provided with a plurality of Y selection gate circuits 15 (for example, 8 pieces of 8 bytes).
[0035]
The Y selection gate circuit 15 is provided with eight NMOS transistors T00 to T07 in order to select any of the eight bit lines BL (BL0 to BL7). Corresponding bit lines BL0 to BL7 are connected to the sources of the transistors T00 to T07, respectively. The drains of the transistors T00 to T07 are connected to each other, and further connected to the data bus RDB via the NMOS transistor T10.
[0036]
Corresponding decode signals YD00 to YD07 are input to the gates of the transistors T00 to T07, respectively. The decode signal YD1 is input to the gate of the NMOS transistor T10. One of the eight NMOS transistors T00 to T07 is turned on based on the decode signal YD00 to YD07, and the transistor T10 is turned on based on the decode signal YD1, so that the bit line BL of the memory cell 1 to be read is read. Are connected to the data bus RDB.
[0037]
Thus, in the Y selection gate circuit 15, when the bit line BL of the memory cell 1 to be read is connected to the data bus RDB, the read current of the memory cell 1 is read through the bit line BL and the data bus RDB. 2 will flow.
[0038]
Note that “◯” is marked on the gate portion of the NMOS transistor T10, which indicates that the transistor has a low threshold voltage.
FIG. 6 shows the read amplifier 2.
[0039]
In the read amplifier 2, the read current Im of the memory cell 1 flows through the NMOS transistor Tn20. The NMOS transistor Tn20 has a source connected to the data bus RDB and a drain connected to the sense node N1.
[0040]
The gate of the NMOS transistor Tn20 is connected to the power supply Vcc via the PMOS transistor Tp20, and is connected to the ground via three NMOS transistors Tn21 connected in series. Further, the gate of the NMOS transistor Tn20 is connected to the ground via the NMOS transistor Tn22.
[0041]
The gate of each NMOS transistor T21 is connected to the data bus RDB (the source of the NMOS transistor Tn20). A signal enb is input to the gates of the PMOS transistor Tp20 and the NMOS transistor Tn22. The sense node N1 is connected to the power supply Vcc via the PMOS transistor Tp21, and the signal en is input to the gate of the transistor Tp21. The signals en and enb are generated based on the signal RDmem and the signal TAC. At the time of reading data, the signal en is at H level and the signal enb is at L level.
[0042]
When the read current Im of the memory cell 1 increases and the source potential of the NMOS transistor Tn20 (the potential of the bit line BL connected via the data bus RDB) increases, hot carriers are generated and the floating gate of the memory cell 1 The voltage may change. In order to avoid this, when the source potential of the NMOS transistor Tn20 rises, the NMOS transistor Tn21 is turned on to lower the gate potential of the NMOS transistor Tn20. This prevents the source potential of the NMOS transistor Tn20 from becoming higher than necessary (for example, 1 V or higher).
[0043]
The reference current generator 2a is connected to the sense node N1, and the reference current Ir from the reference current generator 2a flows into the sense node N1 during a normal read operation.
[0044]
In the reference current generation unit 2a, a plurality of series circuits including two PMOS transistors are provided in parallel between the power supply Vcc and the sense node N1. The output signal SAREF of the reference current generation circuit 21 is input to the gate of the transistor on the sense node N1 side among the transistors constituting the series circuit, and the setting signal REF (REF0) is input to the gate of the transistor on the power supply Vcc side. To REF3) are input through an inverter circuit.
[0045]
In the read amplifier 2, the number of transistors to be turned on can be changed by the setting signal REF, and the reference current Ir flowing into the sense node N1 is adjusted by the change.
[0046]
Here, when the voltage of the floating gate in the memory cell 1 is high (when the data in the memory cell 1 is 1), the read current Im of the memory cell 1, that is, the current flowing from the sense node N1 to the data bus RDB is growing. On the other hand, when the voltage of the floating gate in the memory cell 1 is low (when the data in the memory cell 1 is 0), the read current Im of the memory cell 1 is small.
[0047]
The reference current Ir flowing from the reference current generating unit 2a into the sense node N1 is set to be an intermediate value of the read current Im when the data of the memory cell 1 is 1 and when the data is 0.
[0048]
When the data of the memory cell 1 is 1, the read current Im of the memory cell 1 is larger than the reference current Ir, so that the potential of the sense node N1 decreases, while the data of the memory cell 1 is 0. Since the read current Im of the memory cell 1 is smaller than the reference current Ir, the potential of the sense node N1 rises.
[0049]
The sense node N1 is connected to the gate of the PMOS transistor Tp23, and the PMOS transistor Tp23 is turned on / off according to the potential level of the sense node N1. The PMOS transistor Tp23 has a source connected to the power supply Vcc and a drain connected to the drain of the NMOS transistor Tn23. The source of the NMOS transistor Tn23 is connected to the ground, and the signal SAB0 is input to the gate of the NMOS transistor Tn23. At the time of reading, the signal SAB0 is at the H level, and a relatively small constant current flows through the NMOS transistor Tn23.
[0050]
When the potential of the sense node N1 decreases and the PMOS transistor Tp23 is turned on, the drain potential of the transistor Tp23 increases. Conversely, when the node potential of the sense node N1 increases and the PMOS transistor Tp23 is turned off, the drain potential of the transistor Tp23. Becomes lower. Then, the drain potential of the transistor Tp23 is output from the read amplifier 2 as the output signal RDATAB through the inverter circuit 24. The output signal RDATAB is an inverted signal of data in the memory cell 1.
[0051]
In the read amplifier 2 of the present embodiment, the test reference current generator 2b is connected to the sense node N1. The reference current Ir flows from the reference current generator 2a to the sense node N1 during the normal reading described above, whereas the test reference current It flows from the test reference current generator 2b to the sense node N1 during the test.
[0052]
The test reference current generation unit 2b includes two PMOS transistors Tp24 and Tp25 connected in series between the power supply Vcc and the sense node N1. The output signal SAREFT of the test reference current generating circuit 22 is input to the gate of the transistor Tp25 on the sense node N1 side, and the test signal TMRWB is input to the gate of the transistor Tp24 on the power supply Vcc side.
[0053]
The test signal TMRWB is a signal obtained by inverting the logic level of the test signal TMRW of the test circuit 17. During the test, the test signal TMRW is at the H level and the test signal TMRWB is at the L level. The transistor Tp24 is turned on by the L level test signal TMRWB. Then, the test reference current It according to the output signal SAREFT is driven by the transistor Tp25.
[0054]
A test output unit 2c is connected to the output terminal of the inverter circuit 24 that outputs the output signal RDATAB. During the test, the test output signal RANAOUT is output from the test output unit 2c based on the output signal RDATAB.
[0055]
The test output unit 2c includes a NAND circuit 25, an inverter circuit 26, PMOS transistors Tp27 and Tp28, and NMOS transistors Tn27 and Tn28. A signal RDmem that is at the H level during reading is input to one input terminal of the NAND circuit 25, and a test signal TMRW is input to the other input terminal. Transistors Tp27, Tp28, Tn27, and Tn28 are connected in series between the power supply Vcc and the ground, and the output signal of the NAND circuit 25 is input to the gate of the PMOS transistor Tp28 and the NMOS transistor via the inverter circuit 26. Input to the gate of Tn27.
[0056]
The output signal RDATAB of the inverter circuit 24 is input to the gate of the PMOS transistor Tp27 and also input to the gate of the NMOS transistor Tn28.
[0057]
During the test, the output signal of the NAND circuit 25 becomes L level by the H level signals RDmem and TMRW, and the PMOS transistor Tp28 and the NMOS transistor Tn27 are turned on. At this time, if the output signal RDATAB is at L level, the PMOS transistor Tp27 is turned on and the NMOS transistor Tn28 is turned off, so that the test output signal RANAOUT at H level is output from the test output unit 2c. If the output signal RDATAB is at the H level, the PMOS transistor Tp27 is turned off and the NMOS transistor Tn28 is turned on, so that the L level test output signal RANAOUT is output from the test output unit 2c.
[0058]
Further, during normal reading, the output signal of the NAND circuit 25 becomes H level by the L level test signal TMRW, so that the PMOS transistor Tp28 and the NMOS transistor Tn27 are turned off. As a result, the output of the test output signal RANAOUT by the test output unit 2c is prohibited.
[0059]
FIG. 7 shows a test reference current generation circuit 22.
The test reference current generation circuit 22 includes an equivalent characteristic pseudo circuit having the same circuit configuration as the path (the path of the read current Im) from the sense node N1 of the read amplifier 2 to the memory cell 1.
[0060]
Specifically, a first circuit unit 31 having a circuit configuration equivalent to the read amplifier 2 in FIG. 6, a second circuit unit 32 having a circuit configuration equivalent to the Y selection gate circuit 15 in FIG. A third circuit unit 33 having a circuit configuration equivalent to the memory cell 1 and a fourth circuit unit 34 having a circuit configuration equivalent to the ground supply circuit 16 of FIG. 4 are provided.
[0061]
The difference is that, in the third circuit section 33, the input signal RANAIN is input via the transfer gate 35 to the gate electrode corresponding to the floating gate of the cell transistor T2r. This input signal RANAIN is a signal input from a test apparatus (not shown) via an external terminal of the semiconductor device.
[0062]
In the present embodiment, the third circuit section 33 of the test reference current generation circuit 22 corresponds to the test reference memory cell 3 in FIG. In the third circuit unit 33, a capacitor connected to the gate of the cell transistor T2r is omitted.
[0063]
As shown in FIG. 7, the test signal TMRW is input to the gate of the NMOS transistor constituting the transfer gate 35, and the test signal TMRWB is input to the gate of the PMOS transistor. Also, an NMOS transistor Tn30 is provided between the wiring L1 for transmitting the input signal RANAIN to the third circuit unit 33 and the ground, and the test signal TMRWB is input to the gate of the transistor Tn30.
[0064]
During the test, since the test signal TMBW is at the H level and the test signal TMRWB is at the L level, the transfer gate 35 is turned on and the transistor Tn30 is turned off. At this time, the input signal RANAIN is supplied to the gate of the cell transistor T2r via the transfer gate 35 and the wiring L1, and a current corresponding to the voltage of the input signal RANAIN flows through the current path of the test reference current generation circuit 22. On the other hand, during normal operation, the test signal TMBW is at L level and the test signal TMRWB is at H level, so that the transfer gate 35 is turned off and the transistor Tn30 is turned on. At this time, the gate of the cell transistor T2r becomes 0V, and the cell transistor T2r is turned off, thereby cutting off the current path of the test reference current generating circuit 22.
[0065]
Further, the drain of the NMOS transistor Tn20 forming the current path of the first circuit unit 31 is connected to the power supply Vcc via two PMOS transistors Tp31 and Tp32 connected in series. The gate of the PMOS transistor Tp31 is connected to the ground, and the gate of the PMOS transistor Tp32 is connected to the drain of the transistor Tp32. Further, the connection portion (node) N2 between the transistor Tp32 and the first circuit portion 31 is connected to the power supply Vcc via the PMOS transistor Tp33, and the test signal TMRW is input to the gate of the transistor Tp33.
[0066]
When the test signal TMRW is at H level (during test), the transistor Tp33 is turned off, and the potential of the node N2 changes according to the amount of current flowing through the current path. Then, the potential of the node N2 is output as the output signal SAREFT of the test reference current generating circuit 22. Further, when the test signal TMRW is at the L level (normal operation), the transistor Tp33 is turned on, and the cell transistor T2r in the third circuit unit 33 is turned off to interrupt the current path, so that the output signal SAREFT. Becomes H level (power supply Vcc level).
[0067]
If the test reference current generating circuit 22 is configured in this way, the voltage of the gate of the cell transistor T2r (the gate corresponding to the floating gate of the memory cell 1) in the third circuit unit 33 is set by the input signal RANAIN, and the input A reference current corresponding to the voltage value of the signal RANAIN can be generated.
[0068]
Specifically, a current mirror circuit is configured by the test reference current generation circuit 22 and the read amplifier 2 described above, and a reference current It equal to the current value flowing through the test reference current generation circuit 22 is read out by the read amplifier 2. Generated by the test reference current generator 2b.
[0069]
Since the test reference current generation circuit 22 has a circuit configuration equivalent to the current path of the read current Im of the memory cell 1, when the voltage of the floating gate and the voltage of the input signal RANAIN in the memory cell 1 are equal, the reference current It becomes equal to the read current Im of the memory cell 1. Therefore, the voltage of the floating gate in the memory cell 1 can be observed from the voltage value of the input signal RANAIN of the test reference current generating circuit 22.
[0070]
If an appropriate gate oxide film in the memory cell 1 cannot be formed in the semiconductor manufacturing process, the data write / erase characteristics become abnormal. Specifically, the potential of the floating gate by data writing is higher than the normal value in the memory cell 1 with a thin gate oxide film, and lower than the normal value in the memory cell 1 with a thick gate oxide film.
[0071]
In the macro memory 11 of the present embodiment, the write / erase characteristics of the memory cell 1 are evaluated by changing the voltage value of the input signal RANAIN of the test reference current generating circuit 22.
[0072]
Here, when the write characteristics of the memory cell 1 are evaluated, first, a data write operation is performed for all the memory cells 1 in order to set the floating gates to a predetermined potential (for example, 3 V). Then, with respect to the predetermined potential (3 V), the input signal RANAIN is set to a slightly lower voltage (for example, 2.9 V), or the input signal RANAIN is set to a slightly higher voltage (for example, 3.1 V) to Perform a readout test.
[0073]
In this data read test, memory cells 1 to be read are sequentially selected by changing the address, and a read operation is performed on all memory cells 1. At this time, if the correct output signal RANAOUT is not output from the read amplifier 2, a characteristic abnormality of the memory cell 1 is determined.
[0074]
As described above, according to the above embodiment, the following effects can be obtained.
(1) In the test reference current generating circuit 22, the test reference current It can be adjusted by directly inputting the gate voltage of the reference cell transistor T2r. In the read amplifier 2, the write / erase characteristics of the memory cell 1 can be tested by comparing the test reference current It with the read current Im of the memory cell 1. In this way, by adopting a configuration in which the gate voltage of the reference cell transistor T2r is directly input, a circuit for applying a high voltage as in the prior art becomes unnecessary. As a result, the circuit in the macro memory 11 can be simplified and the reliability can be improved. In addition, since the circuit for the characteristic test can be simplified, an increase in the die size of the macro memory 11 can be suppressed.
[0075]
(2) Since the read amplifier 2 is used to compare the test reference current It and the read current Im of the memory cell 1, a current comparison circuit that compares the test reference current It and the read current Im is provided. The circuit area can be reduced as compared with the case where it is provided separately.
[0076]
(3) Since the test reference current generating circuit 22 is provided with an equivalent characteristic pseudo circuit having the same circuit configuration as the path of the read current Im of the memory cell 1, the test reference current It is adjusted accurately. Can do.
[0077]
(4) During a normal read operation, the test reference current generation circuit 22 turns off the transfer gate 35 and turns on the transistor Tn30, whereby the gate potential of the reference cell transistor becomes 0V. Accordingly, the reference cell transistor T2r is turned off to cut off the current path, and the output signal SAREFT of the test reference current generation circuit 22 is set to the H level. In this way, during the normal read operation, the test reference current It does not flow through the test reference current generator 2b in the read amplifier 2 by mistake.
[0078]
The above embodiment can be modified as follows.
In the above embodiment, the input signal RANAIN for setting the gate voltage of the reference cell transistor T2r is input from a test apparatus (not shown), but is not limited thereto. For example, a signal generated by a voltage generation unit in the semiconductor device may be used as the input signal RANAIN for setting the gate voltage of the reference cell transistor T2r.
[0079]
In the above embodiment, the macro memory 11 and the logic unit are embodied in a semiconductor device (LSI) mounted on one chip, but the logic unit is omitted and the semiconductor memory device having only the function of the macro memory 11 is embodied. Also good.
[0080]
The various embodiments described above can be summarized as follows.
(Supplementary note 1) In a semiconductor memory device including a nonvolatile memory cell having a selection transistor connected to a word line, a cell transistor connected in series to the selection transistor, and a capacitor connected to the gate of the cell transistor ,
A test reference memory cell having a reference select transistor and a reference cell transistor connected in series to the reference select transistor;
Means connected to a gate of a reference cell transistor of the test reference memory cell, and setting a gate voltage of the reference cell transistor during a test;
A current comparison circuit for comparing a read current flowing through the memory cell with a reference current flowing through a test reference memory cell;
A semiconductor memory device comprising:
(Supplementary note 2) The semiconductor memory device according to supplementary note 1, wherein the current comparison circuit is a sense amplifier that compares a read current of the memory cell with a reference current and amplifies and outputs the current difference. .
(Supplementary note 3) a reference current generating circuit for generating a reference current used for a normal read operation;
A test reference current generating circuit for generating a test reference current;
A test circuit for inputting a test signal to the reference current generating circuit and the test reference current generating circuit, inactivating the reference current generating circuit, and activating the test reference current generating circuit;
The semiconductor memory device according to appendix 1, characterized by comprising:
(Supplementary note 4) The semiconductor memory device according to supplementary note 3, wherein a test signal of the test circuit is input to the current comparison circuit.
(Supplementary Note 5) In the test reference current generating circuit, an equivalent characteristic pseudo circuit having the same circuit configuration as the read current path of the memory cell is provided in a current path through which the test reference current flows. The semiconductor memory device according to appendix 3.
(Supplementary note 6) The semiconductor memory device according to supplementary note 5, wherein the equivalent characteristic pseudo circuit includes an equivalent circuit of a column selection circuit.
(Supplementary note 7) The semiconductor memory device according to supplementary note 5, wherein the equivalent characteristic pseudo circuit includes an equivalent circuit of a sense amplifier.
(Supplementary note 8) The sense amplifier as the current comparison circuit includes a sense node from which the reference current flows and a read current from the memory cell flows, and a transistor having a gate connected to the sense node,
The semiconductor memory according to appendix 1, wherein the output of the sense amplifier is determined by operating the transistor based on a potential of a sense node that changes in accordance with a difference between the reference current and a read current. apparatus.
(Supplementary note 9) A semiconductor memory device including a non-volatile memory cell having a selection transistor connected to a word line, a cell transistor connected in series to the selection transistor, and a capacitor connected to the gate of the cell transistor A test method,
The semiconductor memory device is provided with a test reference memory cell having a reference selection transistor and a reference cell transistor connected in series to the reference selection transistor,
A reference current flowing through the test reference memory cell is adjusted by setting a gate voltage according to an input signal from a setting means connected to a gate of the reference cell transistor, and the reference current and a read current flowing through the memory cell are adjusted. A method for testing a semiconductor memory device, characterized in that:
(Supplementary Note 10) A test signal is input from a test circuit to a reference current generation circuit for generating a reference current in a normal read operation and a test reference current generation circuit for generating a test reference current. The semiconductor memory device testing method according to appendix 9, wherein the generation circuit is deactivated and the test reference current generation circuit is activated.
(Supplementary Note 11) By providing an equivalent characteristic pseudo circuit having the same circuit configuration as the path of the read current flowing through the memory cell in the current path through which the reference current of the test reference memory cell flows, the test reference memory cell The test method for a semiconductor memory device according to appendix 10, wherein the reference current is adjusted.
(Supplementary Note 12) A signal generated according to a reference current flowing through the test reference memory cell in the test reference current generation circuit is input to a gate of a transistor provided in the sense sense amplifier, and the reference current is generated by the transistor. A current equal to
11. The test method for a semiconductor memory device according to appendix 10, wherein a reference current by the transistor and a read current of the memory cell are compared in the sense amplifier.
(Supplementary Note 13) The sense amplifier includes a sense node from which a reference current from the transistor flows and a read current from the memory cell flows, and a transistor having a gate connected to the sense node,
13. The semiconductor memory according to appendix 12, wherein the output of the sense amplifier is determined by operating the transistor based on a potential of a sense node that changes depending on a difference between the reference current and a read current. Equipment test method.
[0081]
【The invention's effect】
As described above in detail, according to the present invention, a simple and highly reliable test circuit can be realized, and an increase in die size can be suppressed.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating the principle of the present invention.
FIG. 2 is a block circuit diagram illustrating a macro memory according to an embodiment.
FIG. 3 is a circuit diagram showing a memory cell.
FIG. 4 is a circuit diagram showing a ground supply circuit.
FIG. 5 is a circuit diagram showing a Y selection gate circuit;
FIG. 6 is a circuit diagram showing a read amplifier.
FIG. 7 is a circuit diagram showing a test reference current generating circuit.
[Explanation of symbols]
1 Memory cell
2 Readout amplifier as current comparator
3 Test reference memory cell
4 Setting means
11 Macro memory as a semiconductor memory device
15 Y selection gate circuit as column selection circuit
17 Test circuit
21 Reference current generator
22 Reference current generator for testing
31 First circuit portion as an equivalent circuit
32 Second circuit part as equivalent circuit
C1 capacitor
Im read current
Ir reference current
It test reference current
RANAIN input signal
SWL word line
T1 selection transistor
T1r reference selection transistor
T2 cell transistor
T2r reference cell transistor
TMRW test signal

Claims (10)

A selection transistor having a single-layer polysilicon structure connected to a word line, a cell transistor having a single-layer polysilicon structure connected in series to the selection transistor, and a capacitor connected to a floating gate of the cell transistor In a semiconductor memory device including a nonvolatile memory cell,
A test reference memory cell having a reference selection transistor having a single-layer polysilicon structure and a reference cell transistor having a single-layer polysilicon structure connected in series to the reference selection transistor;
Means connected to a floating gate of a reference cell transistor of the test reference memory cell, and setting a gate voltage of the reference cell transistor during a test;
A semiconductor memory device comprising: a current comparison circuit that compares a read current flowing through the memory cell with a reference current flowing through a test reference memory cell.   2. The semiconductor memory device according to claim 1, wherein the current comparison circuit is a sense amplifier that compares a read current of the memory cell with a reference current and amplifies and outputs the current difference. A reference current generating circuit for generating a reference current used for a normal read operation, a test reference current generating circuit for generating a test reference current, and a test on the reference current generating circuit and the test reference current generating circuit 2. The semiconductor memory device according to claim 1, further comprising: a test circuit that inputs a signal, deactivates the reference current generation circuit, and activates the test reference current generation circuit.   4. The semiconductor memory device according to claim 3, wherein a test signal of the test circuit is input to the current comparison circuit.   4. The test reference current generation circuit, wherein a current path through which the test reference current flows is provided with an equivalent characteristic pseudo circuit having the same circuit configuration as a read current path of the memory cell. The semiconductor memory device described in 1.   The semiconductor memory device according to claim 5, wherein the equivalent characteristic pseudo circuit includes an equivalent circuit of a column selection circuit.   6. The semiconductor memory device according to claim 5, wherein the equivalent characteristic pseudo circuit includes an equivalent circuit of a sense amplifier. A selection transistor having a single-layer polysilicon structure connected to a word line, a cell transistor having a single-layer polysilicon structure connected in series to the selection transistor, and a capacitor connected to a floating gate of the cell transistor A test method for a semiconductor memory device including a nonvolatile memory cell,
The semiconductor memory device includes a reference memory cell for testing having a reference selection transistor having a single-layer polysilicon structure and a reference cell transistor having a single-layer polysilicon structure connected in series to the reference selection transistor,
The reference current flowing in the test reference memory cell is adjusted by setting the gate voltage by an input signal from the setting means connected to the floating gate of the reference cell transistor, and the reference current and the read current flowing in the memory cell And a method for testing a semiconductor memory device.   A test signal is input from the test circuit to a reference current generation circuit for generating a reference current in a normal read operation and a test reference current generation circuit for generating a test reference current, and the reference current generation circuit is turned off. 9. The method of testing a semiconductor memory device according to claim 8, wherein the test reference current generating circuit is activated and activated.   The reference current of the test reference memory cell is adjusted by providing an equivalent characteristic pseudo circuit having the same circuit configuration as the path of the read current flowing through the memory cell in the current path through which the reference current of the test reference memory cell flows. The method of testing a semiconductor memory device according to claim 9, wherein:

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