JP3888604B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a high-power semiconductor device constituting an amplifier mounted on, for example, a mobile communication device.
[0002]
[Prior art]
A typical high-power semiconductor device has a configuration having a semiconductor element array in which a plurality of semiconductor elements are connected in parallel, and can handle a large current.
[0003]
Conventionally, in this field, it has been known that a semiconductor device for high output causes deterioration of characteristics and catastrophic failure when operated under a high power condition. This is because a local heating portion called a hot spot is formed in one of the semiconductor elements, and the current flowing through the semiconductor element increases as the temperature in the vicinity of the hot spot increases. As the current flowing through the semiconductor element increases, the temperature of the semiconductor element further rises, and a larger current flows. Finally, the total current flowing through each semiconductor element is reduced to a single heated semiconductor element. A catastrophic failure such as a thermal runaway occurs. A hot spot is likely to occur in a semiconductor element in the vicinity of the center of a semiconductor element array having a large thermal resistance among semiconductor elements constituting a high-power semiconductor device. In order to prevent the occurrence of hot spots, it is necessary to make the temperature of each semiconductor element uniform.
[0004]
As a prior art, a method for equalizing the temperature of each semiconductor element is disclosed in Japanese Patent Laid-Open No. 6-342803. 15, FIG. 16 and FIG. 17 are a plan view and a cross-sectional view showing semiconductor devices 1A, 1B, and 1C in which heterojunction bipolar transistors (abbreviation: HBT) for achieving uniform temperature are connected in parallel. is there. The semiconductor devices 1A, 1B, and 1C are formed by forming the emitter electrode 2, the base electrode 3, and the collector electrode 4 on the semi-insulating substrate 5, thereby connecting the hetero-coupled bipolar transistors that are a plurality of semiconductor elements in parallel. An element row is formed.
[0005]
In the semiconductor device 1A shown in FIG. 15, the emitter fingers 2a are arranged so that the distance between the emitter fingers 2a decreases from the center to the end of the semiconductor element array of the semiconductor device 1A. In the semiconductor device 1B shown in FIG. 16, the emitter fingers 2b, 2c, 2d, 2e, and 2f are formed with the smallest width of the finger 2d at the center of the semiconductor element array of the semiconductor device 1B. The fingers 2c and 2e at both ends of the finger 2d are formed wider than the fingers 2d, and the fingers 2b and 2f at both ends of the fingers 2c and 2e are formed wider than the fingers 2c and 2e. In the semiconductor device 1C shown in FIG. 17, the emitter fingers 2g, 2h, 2i, 2j, and 2k are formed with the shortest length of the finger 2i at the center of the semiconductor element array of the semiconductor device 1C. The fingers 2h and 2j on both ends of the finger 2i are formed longer than the finger 2i, and the fingers 2g and 2k on both ends of the fingers 2h and 2j are formed longer than the fingers 2h and 2j.
[0006]
As described above, by adjusting the spacing, width and length of the emitter fingers, the influence of heat received from adjacent semiconductor elements by each semiconductor element is adjusted, and heat is uniformized over the entire semiconductor element array. ing.
[0007]
[Problems to be solved by the invention]
In such a conventional method of arranging and arranging the intervals between the emitter fingers, the intervals between the semiconductor elements are limited, and there is a problem in miniaturization of the semiconductor device. Further, in the method of adjusting and arranging the width and length of the emitter fingers, it is necessary to design the dimensions of the emitter fingers for each semiconductor element, so that the design of the semiconductor device becomes complicated and the dimensions of the emitter fingers are limited. Therefore, there is a problem in miniaturization of the semiconductor device.
[0008]
Accordingly, an object of the present invention is to provide a semiconductor device that can average the heat of each semiconductor element without adjusting the shape, spacing, and dimensions of the semiconductor elements.
[0009]
[Means for Solving the Problems]
The present invention provides a semiconductor device having a semiconductor element array in which a plurality of semiconductor elements are connected in parallel on a semi-insulating substrate.
Partially removing the opposite sides of the semi-insulating substrate in the arrangement direction of the semiconductor element rows, that kick set the void region thermal resistance of the semiconductor elements is formed through the semi-insulating substrate to form a uniform This is a featured semiconductor device.
[0010]
According to the invention, when the semiconductor elements of the semiconductor element array generates heat, but the heat is going to spread in transmitted a semi-insulating substrate, in the present invention, a semi-insulating of both sides in the arrangement direction of the semiconductor element rows a substrate, the void region so that the heat resistance becomes uniform in each semiconductor element is formed, without a high temperature only the central portion of the semiconductor element array, since the temperature can be equalized throughout the semiconductor element rows, the semiconductor A catastrophic failure of the device can be prevented and the semiconductor device can be operated stably. In addition, since it is not necessary to adjust the shape, interval, and size of each semiconductor device, the design of the semiconductor device is facilitated.
In addition, since the void region penetrates the semi-insulating substrate, it is possible to prevent the heat generated in the semiconductor element from spreading, and to create a pattern on the back surface of the semi-insulating substrate on which the semiconductor element array is formed. When performed, the void region can be used as an alignment mark, and the manufacture of the semiconductor device can be facilitated.
[0011]
Further, the present invention provides a semiconductor device having a semiconductor element row in which a plurality of semiconductor elements are connected in parallel on a semi-insulating substrate.
The semi-insulating substrate between the semiconductor element is partially removed, wherein a set kick the void region thermal resistance of the semiconductor elements is formed through the semi-insulating substrate to form a uniform It is.
[0012]
According to the invention, between each semiconductor element, by providing the void space so that the heat resistance becomes uniform in each semiconductor device, since the temperature of the individual semiconductor elements of the semi conductor elements in a column can be made uniform, A catastrophic failure of the semiconductor device can be prevented and the semiconductor device can be operated stably. Further, since it is not necessary to adjust the shape, interval, and size of each semiconductor device, the design of the semiconductor device is facilitated.
In addition, since the void region penetrates the semi-insulating substrate, it is possible to prevent the heat generated in the semiconductor element from spreading, and to create a pattern on the back surface of the semi-insulating substrate on which the semiconductor element array is formed. When performed, the void region can be used as an alignment mark, and the manufacture of the semiconductor device can be facilitated.
[0013]
Further, the present invention provides a semiconductor device having a semiconductor element row in which a plurality of semiconductor elements are connected in parallel on a semi-insulating substrate.
In the semiconductor device of the semi-insulating substrate is removed the ambient, characterized in that kick set the void region that is formed through the semi-insulating substrate so that the heat resistance becomes uniform in each semiconductor element of the semiconductor element is there.
[0014]
According to the invention, the periphery of each semiconductor element, by providing the void space so that the heat resistance becomes uniform in each semiconductor device, since the temperature of the individual semiconductor elements of the semi conductor elements in a column can be made uniform A catastrophic failure of the semiconductor device can be prevented and the semiconductor device can be operated stably. Further, since it is not necessary to adjust the shape, interval, and size of each semiconductor device, the design of the semiconductor device is facilitated.
[0016]
In addition, since the void region penetrates the semi-insulating substrate, it is possible to prevent the heat generated in the semiconductor element from spreading, and to create a pattern on the back surface of the semi-insulating substrate on which the semiconductor element array is formed. When performed, the void region can be used as an alignment mark, and the manufacture of the semiconductor device can be facilitated.
[0017]
Further, the present invention is characterized in that the void region is embedded with a material having a lower thermal conductivity than the semi-insulating substrate.
[0018]
According to the present invention, the material embedded in the void region is an inorganic insulating film or an organic insulating film.
[0019]
According to the present invention, by embedding a material having a lower thermal conductivity than the semi-insulating substrate in the gap region, it is possible to prevent the heat generated in the semiconductor element from spreading and to smooth the surface of the semi-insulating substrate. Therefore, the subsequent semiconductor process can be easily performed.
[0020]
The present invention is also characterized in that it is used in an amplifier of a transmission / reception apparatus for communication.
According to the present invention, since there is no restriction on the shape, interval, and size of the semiconductor element, the semiconductor device can be reduced in size, and the communication transceiver device on which the semiconductor device is mounted can also be reduced in size.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a plan view showing a semiconductor device 11 according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view taken along section line S2-S2 in FIG. FIG. 3 is an enlarged view of section III of FIG. FIG. 4 is an enlarged view of section IV of FIG. The semiconductor device 11 includes a semiconductor element array in which heterojunction bipolar transistors (abbreviation: HBT) which are semiconductor elements are connected in parallel. By connecting the HBTs in parallel, a large current can be handled and it serves as an amplifier.
[0022]
As shown in FIG. 1, a comb-like base electrode 18 and a comb-like collector electrode 19 face each other to engage a base finger 18a and a collector finger 19a, and an emitter electrode 17 is interposed between a pair of base fingers 18a. A plurality of HBTs (eight HBTs 71 to 78 in FIG. 1) are arranged in a line. Each row of HBTs is connected in parallel.
[0023]
3 and 4, the semiconductor device 11 includes a collector contact layer 13 formed on a semi-insulating substrate 12, a collector layer 14 formed on the collector contact layer 13, and The base layer 15 is formed on the base layer 15, and the emitter layer 16 is formed on the base layer 15. A rectangular emitter electrode 17 is formed on the emitter layer 16, a comb-shaped base electrode 18 is formed on the base layer 15, and a comb-shaped collector electrode 19 is formed on the collector layer 14. . The HBT 71 includes an emitter electrode 17, a pair of base fingers 18a, and a pair of collector fingers 19a. Adjacent HBTs share the collector finger 19a and are arranged in parallel with the distance between the centers of the emitter electrodes 17 being F.
[0024]
On both sides of the HBT row, the semi-insulating substrate 12 is partially removed by dry etching to form the void regions 21 and 22. The gap regions 21 and 22 can prevent the heat generated from the HBT from spreading beyond the gap regions 21 and 22, thereby uniformly distributing the heat on the semi-insulating substrate 12 below the HBT row. An effect is acquired and generation | occurrence | production of a hot spot can be prevented.
[0025]
The shape and position of the air gap regions 21 and 22 so that the heat in the semiconductor device 11 is equalized will be described. The distance between the gap region 21 at one end of the HBT row and the HBT 71 at one end of the HBT row and the gap between the gap region 22 at the other end of the HBT row and the HBT 78 at the other end of the HBT row are both A. The effect of the interval A is obtained in the range of 1/10 to 3 times the interval F of each HBT. The depth D of the void regions 21 and 22 is effective when D> A / 3. As shown in FIG. 4, it is assumed that the heat generated in the central portion 25 of the HBT 71 is transmitted radially from the center of the central portion 25 in the direction of the arrow 26 at an angle θ = 45 degrees and spreads uniformly. It can be approximated to the state of Therefore, it is desirable that the interval A is ½ or less of the interval F of each HBT, and the depth D of the void region 21 is D ≧ A. Further, as shown in FIG. 3, the effect is obtained when the width C of the gap region 21 is 1/5 or more of the width E of the emitter layer 16 of the HBT 71. Since the void region 21 aims to block heat spreading in the direction of the arrow 26, the effect is increased as the width C of the void region 21 is increased, but the effect is hardly changed even when C ≧ E. Therefore, the space | gap area | region 21 should just be width | variety C> E. The effect is obtained if the length B of the void region 21 is B ≧ 0. The effect is obtained as the length B is larger. However, since the semiconductor device 11 becomes larger as the gap region 21 becomes larger, B ≦ 50 μm is desirable. The same applies to the gap region 22.
[0026]
In the present embodiment, the semi-insulating substrate 12 in the semiconductor device 11 is a semi-insulating GaAs substrate and has a thickness of 100 μm. The HBTs 71 to 78 are formed with the emitter layer 16 having a length of 6 μm and a width E of 80 μm. The eight HBTs 71 to 78 are arranged in a line at intervals of F = 70 μm. The gap area 21 is created by setting the gap A between the gap area 21 and the HBT 71 to 25 μm, the length B of the gap area 21 to 20 μm, the width C of the gap area 21 to 80 μm, and the depth D of the gap area 21 to 50 μm.
[0027]
FIG. 5 is a graph showing a simulation result of thermal resistance of each HBT 71 to 78. Compared to the simulation result (Δ mark) when there is no void area 21, 22, the thermal resistance value is uniform in the simulation result (● mark) when there is the void area 21, 22. In this manner, the temperature distribution of the semiconductor device 11 can be made uniform by creating the void regions 21 and 22.
[0028]
FIG. 6 is a plan view showing a semiconductor device 11A according to the second embodiment of the present invention. FIG. 7 is a cross-sectional view taken along section line S7-S7 in FIG. The semiconductor device 11A has substantially the same configuration as the semiconductor device 11 and has the same dimensions. The void regions 21A and 22A of the semiconductor device 11A penetrate the semi-insulating substrate 12.
[0029]
Also in the semiconductor device 11A, similarly to the semiconductor device 11, the temperature distribution of the semiconductor device 11 can be made uniform by creating the void regions 21A and 22A. Furthermore, when pattern formation is performed on the back surface of the semi-insulating substrate 12 on which the HBT is formed, the gap regions 21A and 22A can be used as alignment marks, and the semiconductor device can be easily manufactured. .
[0030]
FIG. 8 is a plan view showing a semiconductor device 11B according to the third embodiment of the present invention. FIG. 9 is a cross-sectional view taken along section line S9-S9 in FIG. The semiconductor device 11B has substantially the same configuration as the semiconductor device 11 and has the same dimensions. In the gap regions 21 and 22 of the semiconductor device 11B, a material having a lower thermal conductivity than that of the semi-insulating substrate 12 is embedded. In the present embodiment, the semi-insulating substrate 12 in the semiconductor device 11B is a semi-insulating GaAs substrate. SiN insulating film 23 is embedded in void regions 21 and 22 using SiN as a material having a lower thermal conductivity than GaAs.
[0031]
Also in the semiconductor device 11B, similarly to the semiconductor device 11, the temperature distribution of the semiconductor device 11B can be made uniform by embedding a material having a lower thermal conductivity than the semi-insulating substrate 12 in the gap regions 21 and 22. . Furthermore, since the surface of the semi-insulating substrate 12 can be smoothed, the subsequent semiconductor device can be easily manufactured.
[0032]
In this embodiment, SiN is used as a material having a thermal conductivity lower than that of the semi-insulating GaAs substrate. However, Si02 and SiON insulating films, which are inorganic insulating films having a thermal conductivity lower than that of the semi-insulating GaAs substrate, and organic The same effect can be obtained by using a dielectric film such as polyimide which is an insulating film.
[0033]
FIG. 10 is a plan view showing a semiconductor device 11C according to the fourth embodiment of the present invention. FIG. 11 is a cross-sectional view taken along section line S11-S11 in FIG. The semiconductor device 11 </ b> C has substantially the same configuration as the semiconductor device 11. In the semiconductor device 11, adjacent HBTs share the collector finger 19a. However, in the semiconductor device 11C, each of the HBTs 71C to 78C has a pair of collector fingers 19c. In the semiconductor device 11C, the air gap region 24 is between HBT71C and HBT72C, between HBT72C and HBT73C, between HBT73C and HBT74C, between HBT74C and HBT75C, between HBT75C and HBT76C, and between HBT76C and HBT77C. And between HBT77C and HBT78C. The positional relationship between each of the HBTs 71 </ b> C to 78 </ b> C and the gap region 24 is the same as that described in the semiconductor device 11. As with the void region 21, the void region 24 has a length B of 20 μm, a width C of 80 μm, and a depth D of 50 μm.
[0034]
Thus, the semiconductor device 11C has a smaller difference in thermal resistance between the HBTs 71C to 78C than the semiconductor device 11, and the HBTs 71C to 78C have a more uniform temperature distribution.
[0035]
FIG. 12 is a cross-sectional view showing a semiconductor device 11D in which two gap regions 25 having a width B smaller than the gap region 24 are arranged in parallel instead of the gap regions 24 between the HBTs in the semiconductor device 11C. The gap region 25 has a length B1 of 5 μm, a width C of 80 μm, and a depth D of 50 μm. The semiconductor device 11D also has a uniform temperature distribution, similar to the semiconductor device 11C.
[0036]
The void regions 21, 22, 24, and 25 in the semiconductor devices 11C and 11D may be formed so as to penetrate the semi-insulating substrate 12 like the semiconductor device 11A. In this case, the same effect can be obtained. Further, the insulating film 23 may be embedded in the void regions 21, 22, 24, and 25 in the semiconductor devices 11C and 11D like the semiconductor device 11B. In this case as well, a uniform temperature distribution is obtained.
[0037]
FIG. 13 is a plan view showing a semiconductor device 11E according to the fifth embodiment of the present invention. 14 is a cross-sectional view taken along section line S14-S14 in FIG. The semiconductor device 11E has substantially the same configuration as the semiconductor device 11C. A void region 26 is formed in the semi-insulating substrate 12 of the semiconductor device 11E so as to surround each of the HBTs 71C to 78C. More specifically, the air gap region 26 includes air gap regions 26a and 26b extending along the HBT row on both sides in the width direction of the HBT row, and air gap regions 26c to 26c connecting the air gap regions 26a and 26b between the HBTs 71C to 78C. 26k. The gap W1 between the gap regions 26a and 26b and the center line L1 of the HBT row is 60 μm. A distance W2 between the HBTs 71C and 78C at both ends of the HBT row and the gap regions 26c and 26k at both ends of the gap region 26 is 25 μm. The intervals between the HBTs 71C to 78C and the gap regions 26c to 26k adjacent to the HBTs 71C to 78C are all 25 μm. The depth of the void region 26 is 50 μm.
[0038]
As a result, the semiconductor device 11E has a smaller difference in thermal resistance between the HBTs 71C to 78C than the semiconductor device 11C, and the HBTs 71C to 78C have a more uniform temperature distribution.
[0039]
The void region 26 in the semiconductor device 11E may be formed so as to penetrate the semi-insulating substrate 12 like the semiconductor device 11A. In this case, the same effect can be obtained. Further, the insulating film 23 may be embedded in the void region 26 in the semiconductor device 11E as in the semiconductor device 11B. In this case, the same effect can be obtained.
[0040]
The semiconductor devices 1 and 1A to 1E are configured by arranging a plurality of heterojunction bipolar transistors provided with a common collector electrode 19 in parallel, and each HBT is configured by performing isolation between semiconductor elements by implantation or mesa etching. Even in this case, the temperature distribution in the semiconductor device becomes uniform. Further, the semiconductor device is not limited to the one in which the HBTs are arranged in one row, and the same effect can be obtained even if the semiconductor devices are arranged in a plurality of rows.
[0041]
The specific configurations of the semiconductor devices 1 and 1A to 1E of the present invention are not limited to the above-described embodiments, and the present invention includes even a design range without departing from the gist of the present invention. Shall. In this embodiment, the semiconductor device uses a heterojunction bipolar transistor (abbreviation: HBT) as a semiconductor element, but may be another bipolar transistor such as a silicon bipolar transistor or a SiGe heterojunction bipolar transistor. It may be a field effect semiconductor element such as HEMT. The semi-insulating substrate 12 is not limited to GaAs, and may be an InP substrate, Si substrate, SiC substrate, sapphire substrate, and quartz substrate. In the present embodiment, the thickness of the semi-insulating substrate 12 is 100 μm, but is not limited to this thickness. The number of semiconductor elements constituting the semiconductor device is not limited to eight.
[0042]
By using the semiconductor devices 1, 1 </ b> A to 1 </ b> E of the present invention, it is possible to reduce the size of a high-power semiconductor device for power control, a power semiconductor device for high frequency, and the like, and it is also possible to reduce the size of an amplifier using the same become. By using this amplifying device, it is possible to reduce the size of an amplifier mounted on a communication transmitting / receiving device such as a small mobile communication terminal.
[0043]
【The invention's effect】
As described above, according to the present invention, only the central portion in the semiconductor device does not become hot, and the temperature can be equalized over the entire semiconductor element array, so that a catastrophic failure of the semiconductor device can be prevented. Can be operated stably. In addition, since it is not necessary to adjust the shape, interval, and size of each semiconductor device, the design of the semiconductor device is facilitated, and the semiconductor device can be reduced in size.
[0044]
According to the invention, between each semiconductor element, by providing the void space so that the heat resistance becomes uniform in each semiconductor device, since the temperature of the individual semiconductor elements of the semi conductor elements in a column can be made uniform A catastrophic failure of the semiconductor device can be prevented and the semiconductor device can be operated stably. In addition, since it is not necessary to adjust the shape, interval, and size of each semiconductor device, the design of the semiconductor device is facilitated, and the semiconductor device can be reduced in size.
[0045]
According to the present invention, the periphery of each semiconductor element, by providing the void space so that the heat resistance becomes uniform in each semiconductor device can be a temperature of each of the semiconductor elements of the semi-conductor elements in the column uniform Therefore, a catastrophic failure of the semiconductor device can be prevented and the semiconductor device can be operated stably. In addition, since it is not necessary to adjust the shape, interval, and size of each semiconductor device, the design of the semiconductor device is facilitated.
[0046]
Further, according to the present invention, the gap region penetrates the semi-insulating substrate, so that the heat generated in the semiconductor element can be prevented from spreading and the surface on which the semiconductor element array of the semi-insulating substrate is formed. When pattern formation is performed on the back surface of the semiconductor device, the void region can be used as an alignment mark, and the manufacture of the semiconductor device can be facilitated.
[0047]
Further, according to the present invention, by embedding a material having a lower thermal conductivity than the semi-insulating substrate in the gap region, it is possible to prevent the heat generated in the semiconductor element from spreading and to reduce the surface of the semi-insulating substrate. Since smoothing can be performed, the subsequent semiconductor process can be easily performed.
[0048]
In addition, according to the present invention, since there is no limitation on the shape, interval, and size of the semiconductor element, the semiconductor device can be reduced in size, and the communication transmitting / receiving device on which the semiconductor device is mounted can also be reduced in size.
[Brief description of the drawings]
FIG. 1 is a plan view showing a semiconductor device 11 according to a first embodiment of the present invention.
2 is a cross-sectional view taken along section line S2-S2 in FIG.
FIG. 3 is an enlarged view of section III of FIG.
4 is an enlarged view of section IV of FIG.
FIG. 5 is a graph showing the result of simulation of thermal resistance of each HBT 71-78.
FIG. 6 is a plan view showing a semiconductor device 11A according to a second embodiment of the present invention.
7 is a cross-sectional view taken along section line S7-S7 in FIG. 6;
FIG. 8 is a plan view showing a semiconductor device 11B according to a third embodiment of the present invention.
9 is a cross-sectional view taken along section line S9-S9 in FIG.
FIG. 10 is a plan view showing a semiconductor device 11C according to a fourth embodiment of the present invention.
11 is a cross-sectional view taken along section line S11-S11 in FIG.
FIG. 12 is a cross-sectional view showing a semiconductor device 11D.
FIG. 13 is a plan view showing a semiconductor device 11E according to a fifth embodiment of the present invention.
14 is a cross-sectional view taken along section line S14-S14 in FIG.
15A and 15B are a plan view and a cross-sectional view showing a conventional semiconductor device 1A.
FIGS. 16A and 16B are a plan view and a cross-sectional view showing a semiconductor device 1B which is a conventional technique. FIGS.
17A and 17B are a plan view and a cross-sectional view showing a conventional semiconductor device 1C.
[Explanation of symbols]
11, 11A-11E Semiconductor device 12 Semi-insulating substrate 21, 22, 24, 25, 26 Void region 23 Insulating films 71-78, 71C-78C Hetero-coupled bipolar transistor

Claims (6)

In a semiconductor device having a semiconductor element array in which a plurality of semiconductor elements are connected in parallel on a semi-insulating substrate,
Partially removing the opposite sides of the semi-insulating substrate in the arrangement direction of the semiconductor element rows, that kick set the void region thermal resistance of the semiconductor elements is formed through the semi-insulating substrate to form a uniform A featured semiconductor device. In a semiconductor device having a semiconductor element array in which a plurality of semiconductor elements are connected in parallel on a semi-insulating substrate,
The semi-insulating substrate between the semiconductor element is partially removed, wherein a set kick the void region thermal resistance of the semiconductor elements is formed through the semi-insulating substrate to form a uniform . In a semiconductor device having a semiconductor element array in which a plurality of semiconductor elements are connected in parallel on a semi-insulating substrate,
Removing the semi-insulating substrate around the semiconductor element, wherein a set kick the void region thermal resistance of the semiconductor elements is formed through the semi-insulating substrate to be uniform. The space region, the semiconductor device according the any one of claims 1 to 3, characterized that you have embedded from a semi-insulating substrate material having a smaller thermal conductivity. The material to be embedded in the gap region, the semiconductor device according to claim 4, wherein the inorganic insulating film or an organic insulating film der Rukoto. The semiconductor device according to any one of claims 1-5, characterized in that used for the amplifier of the transceiver for communication.

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