JP3887093B2 - Display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a display device such as a liquid crystal display device, and more particularly to control of a display voltage of a drive circuit that generates a display voltage.
[0002]
[Prior art]
In recent years, electronic devices having a display device such as a telephone and a personal computer are increasing. In particular, along with the increase in functions in portable devices such as notebook personal computers, mobile phones, and small televisions, and the spread of such portable devices, some of these portable devices have a liquid crystal display (hereinafter referred to as LCD). is increasing.
[0003]
The LCD has an LCD driving circuit for driving a display portion as display means. This LCD drive circuit generates a plurality of display voltages required by the display means. The plurality of display voltages are generated by operating the booster circuit. The booster circuit generates a plurality of display voltages based on a power supply voltage supplied from a power supply voltage source, for example, VDD.
[0004]
As a booster circuit, a charge pump type is known. In this case, a capacitor storing electric charges used as a power source for the display means is required between a signal line for transmitting a plurality of display voltages generated from the booster circuit and a reference voltage source, for example, a ground voltage source. .
[0005]
[Problems to be solved by the invention]
In such an LCD drive circuit, when the power supply voltage VDD of the power supply voltage source is suddenly lowered for some reason, the charge charged in the capacitor may not be discharged. For this reason, electric charge remains in the signal line for transmitting the display voltage for a long time. As a result, since the display remains on the display portion that is the display means, there are problems such as display information being inadvertently viewed by a third party, a reduction in the life of the display means, and a malfunction during restart.
[0006]
In particular, in portable devices, since batteries are used as power sources and rechargeable batteries are used as power sources, during operation of the devices, the batteries can be removed or the charged charges can be removed without switching off the power with a switch. It may be lost. Therefore, the mobile device is particularly required to solve the above problems.
[0007]
Further, as means for solving the above problems, it is required to operate reliably even when the power supply voltage is suddenly lowered.
[0008]
Furthermore, as means for solving the above-described problems, it is desirable that the solution is realized with the simplest possible configuration and does not hinder downsizing and cost reduction of the display device itself.
[0009]
In order to solve the above-described problems, an object of the present invention is to realize a display device in which no display remains on a display portion which is a display unit even when a power supply voltage is rapidly reduced.
[0010]
Another object of the present invention is to realize a display device that reliably achieves the above object even when the power supply voltage is suddenly lowered.
[0011]
Another object of the present invention is to realize the above object without hindering the downsizing and cost reduction of the display device itself.
[0012]
[Means for Solving the Problems]
In order to achieve the above object, a display device of the present invention generates a plurality of display voltages based on a predetermined voltage, and receives the predetermined voltage in a display device that performs a desired display on the display means using the plurality of display voltages. Display voltage generation means for generating a plurality of display voltages and prohibiting the generation of the plurality of display voltages by the first control signal, and a plurality of wirings respectively transmitting any of the plurality of display voltages A plurality of charge storage means connected to each of the plurality of wirings; a setting means for setting the voltages of the plurality of wirings to a constant value by a second control signal; And monitoring means for generating a third control signal when a decrease in the predetermined voltage is detected and outputting one control signal or the third control signal as the second control signal.
[0013]
In the display device of the present invention, the monitoring unit may be driven by charges accumulated in one of a plurality of charge accumulation units respectively connected to a plurality of wirings.
[0014]
In the display device of the present invention, the generation process is controlled by the fourth control signal instructing the generation of the display voltage by the display voltage generation unit, and the plurality of charge storage units used to enable the monitoring unit to be driven. Temporary supply means for temporarily supplying a predetermined voltage in response to the fourth control signal may be provided for one of the plurality of wirings connected to one of the plurality of wirings.
[0015]
In the display device of the present invention, a resistance unit is provided between one of a plurality of wirings connected to one of a plurality of charge storage units used to drive the monitoring unit and a setting unit. There may be.
[0016]
In the display device of the present invention, one storage capacity of a plurality of charge storage means used for enabling the monitoring means to be driven may be larger than the storage capacity of other charge storage means.
[0017]
In the display device of the present invention, the setting means has one electrode connected to a corresponding one of the plurality of wirings, a voltage of a constant value is supplied to the other electrode, and a second control is supplied to the control electrode. One on-resistance of a plurality of transistors connected to one of a plurality of charge storage means used to enable driving of the monitoring means is composed of a plurality of transistors to which a signal is applied. It may be larger than the on-resistance of the transistor.
[0018]
In the display device of the present invention, the predetermined voltage may be supplied from a removable voltage supply unit.
[0019]
In the display device of the present invention, the display device and the voltage supply means may be attached to a portable device.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
The display device of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a circuit diagram of a driving circuit 100 of the display device according to the first embodiment of the present invention. In the embodiment, an LCD is used as a display device.
[0021]
As the first power supply voltage in the drive circuit 100, for example, the power supply voltage VDD is supplied as a power supply voltage source, for example, from the outside of the electronic device or supplied from a battery built in the electronic device. There are various sources. In particular, the battery may be rechargeable or removable from the electronic device.
[0022]
In FIG. 1, a driving circuit 100 includes a booster circuit 10 that is a display voltage generation unit, N-channel MOS transistors 22, 24, and 26 that are setting units, capacitors 32, 34, and 36 that are charge storage units, and a monitoring unit 50. It is composed of
[0023]
The booster circuit 10 is supplied with the power supply voltage VDD from the terminal 2 and supplied with the reference voltage VREF lower than the power supply voltage VDD from the terminal 4. The booster circuit 10 generates a plurality of display voltages V1, V2, and V3 by boosting the power supply voltage VDD or the reference voltage VREF. In the embodiment, there are three display voltages V1 to V3. However, this is merely three display voltages in order to simplify the description of the present invention, and four or more displays are provided. A working voltage may be prepared. Although a specific circuit diagram of the booster circuit 10 is not shown, it is configured to generate a plurality of display voltages by a charge pump method.
[0024]
The display voltages V1, V2, and V3 generated by the booster circuit 10 are transmitted through wirings 42, 44, and 46 that transmit the display voltage, respectively. Therefore, the terminal 12 connected to the wiring 42 can be set to the display voltage V1, the terminal 14 connected to the wiring 44 can be set to the display voltage V2, and the terminal 16 connected to the wiring 46 is used for display. The voltage V3 can be set.
[0025]
The booster circuit 10 can stop the boosting operation by a reset signal that is a boost stop signal as a first control signal input from the terminal 6. This reset signal is generated from a central processing unit (not shown) (hereinafter also referred to as CPU) when the boosting is stopped.
[0026]
The first electrode of the transistor 22 is connected to the wiring 42, and the ground voltage VSS is supplied to the second electrode. The first electrode of the transistor 24 is connected to the wiring 44, and the ground voltage VSS is supplied to the second electrode. The first electrode of the transistor 26 is connected to the wiring 46 and the second electrode is supplied with the ground voltage VSS. The gate electrodes of the transistors 22, 24, and 26 are configured to receive a reset signal as a second control signal that is an output of the monitoring unit 50. For this reason, the transistors 22, 24, and 26 electrically connect the wirings 42, 44, and 46 with the ground voltage VSS by a reset signal that is an output of the monitoring unit 50.
[0027]
The capacitors 32, 34, and 36 are connected between the wirings 42, 44, and 46, respectively, as a second power source, for example, the ground voltage VSS. Each of these capacitors charges a charge required between the corresponding wiring and the ground voltage VSS. Based on this charged electric charge, a display means (not shown) connected to the terminals 12, 14, 16 is driven. These capacitors may be MOS capacitors having a MOS transistor configuration. In this way, the manufacturing process of another configuration can be formed simultaneously, and the element layout can be considered together with the layout of other transistors.
[0028]
The monitoring unit 50 includes a comparator 60 as a comparison unit, a capacitor 62, a resistor 64 as an impedance element, a diode 66 as a rectifying element, and a NOR 70 as a logic circuit that generates a reset signal.
[0029]
The negative side terminal, which is one input terminal of the comparator 60, is connected to the terminal 2 so that the power supply voltage VDD is supplied. The positive side terminal which is the other input terminal of the comparator 60 is connected to one terminal of the capacitor 62. A ground voltage VSS is supplied to the other terminal of the capacitor 62. The resistor 64 is connected in parallel with the capacitor 62. That is, the resistor 64 has one end connected to the positive terminal of the comparator 60 and the other end supplied with the ground voltage VSS. The diode 66 has an anode that is a P-side terminal connected to the negative terminal of the comparator 60, and a cathode that is an N-side terminal connected to the positive terminal of the comparator 60.
[0030]
A detection signal, which is a third control signal, output from the output terminal of the comparator 60 is input to one input terminal of the NOR 70. The reset signal input from the terminal 6 is input to the other input terminal of the NOR 70. The output of the NOR 70 is supplied as the output of the monitoring means 50 to the gate electrodes of the transistors 22, 24 and 26, respectively.
[0031]
Further, the voltage of the wiring 42 and the ground voltage VSS are supplied to the comparator 60. That is, the comparator 60 is configured to be able to perform a comparison operation on the input from the negative terminal and the positive terminal by the voltage of the wiring 42 and the ground voltage VSS.
[0032]
The capacitor 62 may be a MOS capacitor having a MOS transistor structure, the resistor 64 may be a MOS resistor, and the diode 66 may be a MOS diode in which a MOS transistor is diode-connected. In this way, it can be formed at the same time in the manufacturing process of another structure, and can be considered together with the layout of other transistors on the element layout.
[0033]
The operation of the drive circuit 100 configured as described above will be described below with reference to the drawings. FIG. 2 is a timing chart for explaining the operation of the drive circuit 100.
[0034]
In FIG. 2, a is the voltage level of the power supply voltage VDD input from the terminal 2 (also the voltage level supplied to the negative terminal of the comparator 60), and b is the voltage of the display voltage V <b> 1 transmitted through the wiring 42. Level, c is the voltage level supplied to the positive terminal of the comparator 60, d is the voltage level of the output of the comparator 60, e is the voltage level of the reset signal input from the terminal 6, and f is the output of the monitoring means 50. This is the voltage level of the output of the NOR 70. In FIG. 2, H represents a high level (here, the voltage level of the power supply voltage VDD), and L represents a low level (here, the voltage level of the ground voltage VSS).
[0035]
In FIG. 2, it is assumed that the power supply voltage VDD is set to the high level at the timing t0 which is the initial state. The wiring 42 is also set to a voltage level VDD + α (α is a voltage boosted from the power supply voltage VDD) boosted by the booster circuit 10. Since the current flows from the power supply voltage VDD through the diode 66 and the resistor 64 to the negative side terminal of the comparator 60, the voltage level VDD-VBE (VBE is the P side terminal and the N side terminal when a forward current flows through the diode 66) Voltage difference between the two).
[0036]
Further, the comparator 60 is in an operating state when the voltage level of the wiring 42 is boosted. Here, the voltage VDD supplied to the negative terminal and the voltage VDD−VBE supplied to the positive terminal satisfy VDD> VDD−VBE. For this reason, the output of the comparator 60 is at a low level.
[0037]
Further, the reset signal input from the terminal 6 is also at a low level (here, when the reset signal is at a low level, the boosting operation of the booster circuit 10 is not instructed to stop, and when the reset signal is at a high level, the booster circuit is 10 boost operation is to be instructed to stop). Therefore, since the voltages supplied to the two inputs of the NOR 70 are both low level, the output voltage of the NOR 70 is low level. Therefore, the transistors 22, 24, and 26 are in an inactive state (in an off state, and the source and the drain in each transistor are electrically non-conductive).
[0038]
Although not shown, it is assumed that the display voltages V2 and V3 are also transmitted to the wirings 44 and 46, respectively. For this reason, it is assumed that the capacitors 32, 34, and 36 are charged. It is assumed that the capacitor 62 is also charged.
[0039]
At the timing t1, for example, when the power supply voltage VDD decreases due to some reason such as removal of the battery, the current flowing through the diode 66 and the resistor 64 also decreases. Therefore, the voltage at the positive terminal of the comparator 60 is lowered to the ground voltage VSS level by the time constant of the capacitor 62 and the resistor 64. Here, due to the discharge of the capacitor 62 based on the time constants of the capacitor 62 and the resistor 64, the voltage decrease rate of the positive side terminal of the comparator 60 is sufficiently slower than the decrease rate of the power supply voltage VDD.
[0040]
Further, the display voltage V1 transmitted through the wiring 42 is not boosted because the boosting operation of the booster circuit 10 is stopped as the power supply voltage VDD decreases. However, due to the discharge of the capacitor 32, the voltage drop rate of the wiring 42 is slow. The same applies to the wirings 44 and 46. For this reason, even if the power supply voltage VDD decreases, the display voltage is supplied to the display portion which is the display means. The first embodiment solves this.
[0041]
Note that the comparator 60 is in an operable state by the voltage of the wiring 42 whose voltage decrease rate is slow. However, at the initial point when the voltage of the power supply voltage VDD supplied to the negative terminal decreases, the output voltage of the comparator 60 remains at a low level because it is higher than the voltage VDD-VBE supplied to the positive terminal.
[0042]
Further, since the reset signal is not generated from the CPU (not shown) due to the decrease of the power supply voltage VDD, the voltage of the reset signal remains at a low level. For this reason, since the voltages supplied to the two inputs of the NOR 70 are both at the low level, the output voltage of the NOR 70 remains at the low level. Therefore, the transistors 22, 24, and 26 are inactive. Both the power supply voltage VDD supplied to the negative terminal and the voltage VDD−VBE supplied to the positive terminal are lowered, but in this state, the voltage supplied to the negative terminal is higher than the voltage supplied to the positive terminal. Maintained until low.
[0043]
It is assumed that the voltage level of the voltage VDD supplied to the negative terminal of the comparator 60 becomes lower than the voltage VDD−VBE supplied to the positive terminal at the timing t2. Therefore, the comparator 60 detects that the voltage at the negative terminal is lower than the voltage at the positive terminal, and as a result, sets the output voltage of the comparator 60 to a high level.
[0044]
With the change in the level of the output voltage of the comparator 60, the output voltage of the NOR 70, which is the output of the monitoring means 50, also becomes high level. As the level of the output voltage of the NOR 70 changes, the transistors 22, 24, and 26 are each activated (in an on state and electrically connected between the source and drain in each transistor).
[0045]
Activation of the transistors 22, 24, and 26 discharges the charges of the capacitors 32, 34, and 36, and lowers the voltages of the wirings 42, 44, and 46 to the ground voltage VSS. Therefore, it is possible to prevent the display voltage from being supplied to the display portion which is the display means. During these operations, the voltage applied to both terminals of the diode 66 is a reverse voltage, so that the charge of the capacitor 62 is not discharged. Therefore, for example, when the drive circuit 100 is re-operated (again, the power supply voltage VDD is set to the high level again), it can be expected that the comparator 60 can be returned to the original state earlier.
[0046]
At timing t3, as the voltage of the wiring 42 becomes low level, the operation of the comparator 60 becomes impossible, so the output voltage of the comparator 60 becomes indefinite (high resistance state). In FIG. 2, the level is low for the sake of simplicity. Along with this, the output voltage of the NOR 70 also becomes low level. The state in which the output of the comparator 60 is indefinite continues until the voltage of the wiring 42 that supplies the operating voltage to the comparator 60 becomes equal to or higher than VDD, but is at a low level in FIG.
[0047]
Note that at the timings t2 and t3, the reset signal remains at a low level.
[0048]
After this, for example, at the timing t4, the drive circuit 100 is restarted, the power supply voltage VDD, the voltages of the wirings 42, 44, 46, the voltage of the positive terminal, the output voltage of the comparator 60, the voltage of the reset terminal 6, The output voltage of NOR is set to the same state as the initial state (timing t0).
[0049]
At timing t5, for example, when the voltage of the reset signal is set to a high level according to an instruction from a CPU (not shown), the output voltage of the NOR 70 changes to a high level. For this reason, since the transistors 22, 24, and 26 are in a conductive state, the voltage of the wirings 42, 44, and 46 can be lowered to the ground voltage VSS.
[0050]
As described above in detail, according to the first embodiment, when the power supply voltage VDD falls for some reason during the operation of the display device, the display voltage is set to the ground voltage VSS level. Can do. Therefore, it is possible to provide a display device in which no display remains on the display portion which is a display means.
[0051]
Further, since the comparator 60 of the drive circuit 100 in the first embodiment operates with a voltage other than the power supply voltage VDD, the display voltage can be reliably set to the ground voltage VSS. In the above embodiment, the comparator 60 is operable by the voltage of the wiring 42. However, a voltage supply means that is not affected by the voltage drop of the other power supply voltage VDD is provided, and the comparator 60 is controlled by the voltage from the voltage supply means. You may make it operate. However, the above embodiment is more preferable because it is not necessary to prepare special voltage supply means. The comparator 60 is supplied with a voltage for operation from the wiring 42, but may be supplied from another wiring 44 or wiring 46.
[0052]
Furthermore, in the activation circuit 100 according to the first embodiment, the monitoring unit 50 has a simple configuration with a small number of elements, and does not hinder downsizing and cost reduction of the display device itself.
[0053]
Next, a display device according to a second embodiment of the present invention will be described in detail with reference to the drawings. FIG. 3 is a circuit diagram of the display device, particularly the drive circuit 200, according to the second embodiment of the present invention. In FIG. 3, the same reference numerals are given to the same configurations as those of the drive circuit 100 in the first embodiment.
[0054]
In FIG. 3, a characteristic is that it has a start-up circuit 150 as a temporary supply means. In response to the set signal transmitted from the terminal 102, the start-up circuit 150 temporarily connects the terminal 2 to which the power supply voltage VDD is supplied and the wiring 42 that supplies the voltage for the operation of the comparator 60 (for example, for a predetermined time). It has the function to short-circuit. Here, the set signal is a signal for instructing the start of the boosting operation of the booster circuit 10 and is supplied from a CPU (not shown). In FIG. 3, when the set signal is at a low level, it is assumed that the boosting operation of the booster circuit 10 is not instructed. When the set signal temporarily becomes a high level, the level change causes the booster circuit 10 to It is assumed that a boost operation is started. For this reason, the set signal is also transmitted to the booster circuit 10. When the set signal is not temporary but at a high level, the boosting operation of the booster circuit 10 may be instructed according to the level.
[0055]
Although the set signal is not shown in the first embodiment, it goes without saying that the boosting operation may be started by the set signal in the drive circuit 100 as well. Since the drive circuit 100 does not prepare the start-up circuit 150, for example, the boosting operation may be started when the reset signal is at a low level.
[0056]
Other configurations in FIG. 3 are the same as those of the drive circuit 100 according to the first embodiment.
[0057]
The operation of the drive circuit 200 of the second embodiment will be described in detail below with reference to the drawings. FIG. 4 is a timing chart for explaining the operation of the drive circuit 200 according to the second embodiment.
[0058]
In FIG. 4, it is assumed that the voltage of the set signal has already been temporarily at the high level at the timing t0 which is the initial state. Therefore, the power supply voltage VDD, the voltages of the wirings 42, 44, and 46, the voltage of the positive terminal, the output voltage of the comparator 60, the voltage of the reset terminal 6, and the output voltage of NOR at the timing t0 are the same as in FIG. It is. Since the voltage of the set signal is at a low level, each configuration of the drive circuit 200 is in the same operation state as that of the drive circuit 100, and therefore, the timing is the same as in the case of FIG.
[0059]
Since the voltage of the wiring 42 becomes the ground voltage after the timing t3, the voltage for the operation with respect to the comparator 60 becomes the ground voltage VSS. For this reason, the comparator 60 is disabled and the output voltage of the comparator 60 is indefinite. As a result, the output voltage of the NOR 70 also becomes unstable. Therefore, in this case, it is considered that the transistors 22, 24, and 26 are activated and prevent the voltage of the wirings 42, 44, and 46 from being increased during the operation of the booster circuit 10. The second embodiment solves this problem.
[0060]
At timing t4, the drive circuit 200 is restarted to set the voltage at the terminal 2 to the power supply voltage VDD level. Along with this, the voltage at the positive terminal of the comparator 60 also becomes the VDD-VBE level. Since the booster circuit 10 is not operating, the comparator 60 is not supplied with an operable voltage from the wiring 42.
[0061]
At timing t4 ′, the power supply voltage is stabilized at the VDD level, and the voltage of the set signal is changed from the low level to the high level according to an instruction from the CPU (not shown). For this reason, the booster circuit 10 starts the boosting operation, and the startup circuit 150 temporarily short-circuits the terminal 2 and the terminal 12. By the operation of the start-up circuit 150, the capacitor 32 can be charged with charges based on the power supply voltage VDD at high speed. At this time, even if the transistor 22 is activated, the capacitor 32 can be charged by the on-resistance of the transistor 22. In order to make charging of the capacitor 32 more reliable, the on-resistance of the transistor 22 may be set higher than the on-resistances of the transistors 24 and 26. Although all of the on-resistances of the transistors 22, 24, and 26 may be increased, it is preferable to increase only the transistor 22 in view of more reliably implementing the object of the present invention.
[0062]
As a result, when the voltage of the wiring 42 becomes the VDD level, the comparator 60 becomes operable. At this time, since the power supply voltage of VDD level is supplied to the negative terminal of the comparator 60 and the voltage of VDD-VBE level is supplied to the positive terminal, the output voltage of the comparator 60 is determined to be low level. Can do. Therefore, thereafter, the transistors 22, 24, and 26 are deactivated except when the reset signal becomes high level (at timing t5) or when the power supply voltage VDD decreases.
[0063]
As described above in detail, according to the second embodiment, the purpose of the first embodiment can be achieved, and the comparator 60 has an output voltage that is unstable. It is possible to prevent the supply of voltage for the operation of 60 from being hindered and to achieve the object of the present invention more reliably.
[0064]
In the second embodiment, only the startup circuit 150 is added. For example, as a simple configuration of the startup circuit 150, a switch that short-circuits between the terminal 2 and the terminal 12 by a set signal may be used. The configuration of the drive circuit 200 is not significantly increased. If a transistor is used as the switch, it can be simultaneously prepared in the manufacturing process of another configuration of the drive circuit.
[0065]
Next, a display device according to a third embodiment will be described below with reference to the drawings. FIG. 5 is a circuit diagram of the driving circuit 300 of the display device according to the third embodiment of the present invention. In FIG. 5, the same reference numerals are given to the same configurations as those of the drive circuit 200 in the second embodiment.
[0066]
A characteristic configuration in FIG. 5 is that a resistor 202 which is an impedance element is provided in a wiring connecting the terminal 12 and the transistor 22. The other configuration in FIG. 5 is the same as that of the drive circuit 200 in FIG.
[0067]
The operation of the drive circuit 300 in FIG. 5 will be described below. Note that the operation of the drive circuit 300 is almost the same as the operation of the drive circuit 200 except for the portion related to the resistor 202, and therefore the timing chart of FIG.
[0068]
The drive circuit 300 is the same as the drive circuit 200 until timings t0 to t2 in FIG.
[0069]
At timing t2, the output voltage of the comparator 60 changes from the low level to the high level, and accordingly, the output voltage of the NOR 70 also changes from the low level to the high level. Therefore, the transistors 22, 24, and 26 are activated. Therefore, the charges of the capacitors 32, 34, and 36 are discharged based on the time constant due to the on-resistance of each capacitor and each transistor. At this time, since the resistor 202 is provided, the time constant of the voltage in the wiring 42 is C1 × (Rt1 + RX). Here, C1 is a capacitance value of the capacitor 32, Rt1 is an on-resistance value of the transistor 22, and RX is a resistance value of the resistor 202.
[0070]
As described above, the time constant for the wiring 42 is longer than the time constant for the wirings 44 and 46. Therefore, the time required for discharging the wiring 42 is longer than the time required for discharging the wirings 44 and 46. That is, the wiring 42 can supply a voltage for the operation of the comparator 60 for a longer time. Therefore, the operation of the comparator 60 is prevented from stopping before the wirings 44 and 46 are completely discharged. Therefore, the object of the present invention can be realized more reliably. In addition, the effect (charging the capacitor 32) in the second embodiment can be performed more reliably.
[0071]
The same effect as that of the third embodiment can also be achieved by making the capacitance of the capacitor 32 larger than that of the other capacitors 34 and 36 instead of providing the resistor 202.
[0072]
In addition, it is more preferable that the resistor 202 be a MOS resistor because the resistor 202 can be simultaneously prepared in the manufacturing process of another configuration of the drive circuit 300.
[0073]
Although the display device of the present invention, particularly the drive circuit, has been described in detail above, the display device of the present invention is not limited to the above-described configuration, and various modifications can be made.
[0074]
For example, the N channel type MOS transistor and the P channel type MOS transistor may be reversed. In this case, it is also considered that the configuration of NOR or the like needs to be changed so as to satisfy the operation of the above embodiment.
[0075]
Although the above embodiment has been described as an LCD, the present invention can be applied to any other display device that can use a driving circuit similar to the present invention.
[0076]
【The invention's effect】
By applying the display device of the present invention, it is possible to realize a display device in which no display remains on the display portion which is a display unit even when the power supply voltage is suddenly lowered.
[0077]
In addition, by applying the display device of the present invention, it is possible to realize a display device that reliably achieves the above object even when the power supply voltage is suddenly reduced.
[0078]
In addition, by applying the display device of the present invention, the above object can be realized without hindering the reduction in size and cost of the display device itself.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a drive circuit 100 for driving a display means, in particular, a display device according to a first embodiment of the present invention.
FIG. 2 is a timing chart for explaining the operation of the drive circuit 100 of FIG.
FIG. 3 is a circuit diagram of a drive circuit 200 for driving a display means, in particular, a display device according to a second embodiment of the present invention.
4 is a timing chart for explaining the operation of the drive circuit 200 of FIG. 3;
FIG. 5 is a circuit diagram of a drive circuit 300 for driving a display unit, in particular, a display device according to a third embodiment of the present invention.
[Explanation of symbols]
100, 200, 300 drive circuit
10 Booster circuit
22, 24, 26 transistor
32, 34, 36, 62 capacitors
42, 44, 46 Wiring
50 Monitoring means
60 Comparator
64, 202 resistance
66 Diode
70 NOR
150 Start-up circuit

Claims (7)

In a display device that generates a plurality of display voltages based on a predetermined voltage, and performs a desired display in a display unit using the plurality of display voltages.
One of the display voltage generating means for generating the plurality of display voltages in response to the predetermined voltage and prohibiting the generation of the plurality of display voltages by a first control signal; A plurality of wirings that respectively transmit
A plurality of charge storage means connected to each of the plurality of wirings;
Setting means for setting a voltage of the plurality of wirings to a constant value by a second control signal;
Upon receiving the predetermined voltage, the decrease in the predetermined voltage is monitored, and when the decrease in the predetermined voltage is detected, a third control signal is generated, and the first control signal or the third control signal is transmitted to the second control signal. and a monitoring means for outputting a control signal,
The display device is characterized in that the monitoring means can be driven by charges accumulated in one of the plurality of charge accumulation means respectively connected to the plurality of wirings. In the display device according to claim 1 ,
In the display device, generation processing is controlled by a fourth control signal instructing generation of a display voltage by the display voltage generation unit,
In response to the fourth control signal, the predetermined voltage is applied to one of the plurality of wirings connected to one of the plurality of charge storage units used to drive the monitoring unit. A display device comprising temporary supply means for temporarily supplying. 3. The display device according to claim 2 , wherein a resistance means is provided between one of the plurality of wirings connected to one of the plurality of charge storage means used for enabling the monitoring means to be driven and the setting means. A display device provided. 3. A display device according to claim 2 , wherein one storage capacity of said plurality of charge storage means used to enable driving of said monitoring means is made larger than storage capacity of other charge storage means. apparatus. 3. The display device according to claim 2 , wherein the setting means includes one electrode connected to a corresponding one of the plurality of wirings, the other electrode supplied with the constant voltage, and a control electrode supplied with the voltage. A plurality of transistors to which a second control signal is applied;
One on-resistance of the plurality of transistors connected to one of the plurality of charge storage units used to enable the monitoring unit to be driven is larger than the on-resistance of other transistors constituting the setting unit. A display device characterized by that. The display device according to claim 1,
The display device according to claim 1, wherein the predetermined voltage is supplied from a removable voltage supply means. The display device according to claim 6 , wherein
The display device and the voltage supply means are attached to a portable device.

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