JP3886577B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
[Technical field to which the invention belongs]
The invention disclosed in this specification relates to a semiconductor device using a crystalline semiconductor film and a manufacturing method thereof. In particular, the present invention relates to a semiconductor device having a CMOS structure using a silicon film as a semiconductor film.
[0002]
[Prior art]
In recent years, CMOS technology using an insulated gate transistor has been actively developed. However, as described in JP-A-4-206971 and JP-A-4-286339, the electrical characteristics of an N-type transistor having a crystalline silicon film as an active layer are shifted in the depletion direction (negative side). , P-type transistors tend to shift in the enhancement direction (negative side). This cause is considered to be due to the work function difference between the gate electrode and the active layer due to the difference in conductivity type.
[0003]
A schematic diagram of the electrical characteristics (Id-Vg characteristics) of the above-described transistor is shown in FIG. The horizontal axis Vg is the gate voltage, and the vertical axis Id is the drain current. 201 indicates the characteristics of the N-type transistor, and 202 indicates the characteristics of the P-type transistor. Note that the contact point at which the Id-Vg characteristic indicated by 201 and 202 is in contact with the Vg axis indicates the threshold voltage.
[0004]
Reference numeral 203 denotes a window width (Vwin), and a difference (= Vth, n) between the threshold voltage (Vth, n) of the N-type transistor and the threshold voltage (Vth, p) of the P-type transistor. -Vth, p). Reference numeral 204 denotes a window center (Vcen), which is defined by a median window width (= 1/2 Vwin).
[0005]
At this time, in the conventional CMOS circuit, the window width (Vwin) is shifted to the negative side as a whole, and as a result, the window center (Vcen) becomes 0 V or less. According to Japanese Patent Laid-Open No. 4-206971, the deviation of the output voltage due to the difference in threshold voltage causes the characteristics of the CMOS circuit to deteriorate.
[0006]
As a solution to this problem, there is a method of controlling the threshold value by adding an impurity (phosphorus or boron) imparting one conductivity to the channel formation region (hereinafter referred to as channel doping method). However, this method has a problem that impurity ions cause carrier scattering and cause a reduction in operating speed.
[0007]
In particular, in the deep sub-micron region where the channel length is 0.01 to 0.1 μm, the number of impurity ions present in the channel region is one to several. Therefore, it has been reported that the electrical characteristics change as a result of the presence of impurity ions. Yes.
[0008]
Background to the Invention
Here, it is necessary to mention the short channel effect suppression technique (pinning technique) proposed by the present inventors. The outline will be described below with reference to FIG.
[0009]
The short channel effect is a generic term for a threshold voltage drop, a breakdown voltage deterioration due to a punch-through phenomenon, a subthreshold characteristic deterioration, and the like. In addition, these phenomena occur because the depletion layer on the drain side extends to the source region, making it difficult to control carriers by only the gate voltage.
[0010]
That is, a technique for suppressing the spread of the depletion layer on the drain side is a pinning technique, which can be achieved by artificially and locally providing an impurity region in the channel formation region. Note that the present inventors use the word “pinning” in the sense of “suppression”.
[0011]
Specifically, the active layer of the transistor has a structure as shown in FIG. In FIG. 3A, 301 is a source region, 302 is a drain region, 303 is a channel formation region, and an impurity region 304 is artificially formed in the channel formation region 303. In the channel formation region 303, a region 305 other than the impurity region 304 is a substantially intrinsic region and serves as a region where carriers move.
[0012]
Note that the impurity region 304 is obtained by forming a fine pattern by an electronic drawing method or the like. FIG. 3A shows an example in which the impurity region has a linear pattern shape, but it may be a dot-like dot pattern shape.
[0013]
A cross-sectional view taken along line AA ′ of FIG. 3A is shown in FIG. Reference numeral 306 denotes a substrate having an insulating surface. 3C is a cross-sectional view taken along the line BB ′ of FIG.
[0014]
At this time, the impurity region 304 disposed in the channel formation region 303 locally forms a region having a high diffusion potential (energy barrier) in the channel formation region. The energy barrier can effectively suppress (pinning) the spread of the drain side depletion layer to the source side.
[0015]
Note that a sufficient energy barrier can be formed in the impurity region 304 by adding any of oxygen, nitrogen, and carbon. Further, B (boron) may be added for an N-type transistor, and P (phosphorus) may be added for a P-type transistor.
[0016]
With the configuration as described above, it is expected to effectively suppress a decrease in threshold voltage, which is one of the short channel effects. Of course, it is also possible to suppress the breakdown voltage and the sub-threshold characteristics associated with the punch-through phenomenon.
[0017]
Further, the configuration shown in FIG. 3 is expected to produce a narrow channel effect in addition to the above-described effect. That is, by narrowing the interval between the impurity regions 304 sufficiently, a narrow channel effect can be artificially generated in the region 305 where carriers move.
[0018]
As described above, the pinning technique proposed by the present inventors has a finer sub-micron region (channel length of 0.01 to 0.1 μm) from the extent that the short channel effect occurs (channel length of 2 μm or less). This technology is effective even for device elements.
[0019]
However, as described in the prior art, the shift of the window center (Vcen) due to the difference in work function between the gate electrode and the active layer is a phenomenon that occurs similarly in the pinning technique. Therefore, in the submicron region, it is necessary to control the threshold voltage while suppressing the short channel effect.
[0020]
[Problems to be solved by the invention]
An object of the present invention is to provide a technique for correcting a difference in threshold voltage by a method other than the channel doping method in a CMOS circuit miniaturized to such an extent that a short channel effect can occur (0.01 to 2 μm). .
[0021]
In other words, a technique for bringing the above-described window center (Vcen) close to 0 V as much as possible is provided. This means that the N channel type and P channel type semiconductor devices are controlled so that the absolute values of the threshold voltages are substantially the same.
[0022]
[Means for Solving the Problems]
The gist of the present invention is to balance the threshold voltage (Vth) by utilizing the short channel effect (SCE) and the narrow channel effect (NCE) that are generated with the miniaturization of device elements. In other words, it is to correct the difference in Vth of the CMOS circuit.
[0023]
Therefore, the configuration of the invention disclosed in this specification is as follows.
In a semiconductor device having a CMOS structure in which an N-channel semiconductor device and a P-channel semiconductor device formed on a substrate having an insulating surface are complementarily combined,
The N channel type semiconductor device is provided with means for enhancing the narrow channel effect so that the absolute values of the threshold voltages of the N channel type semiconductor device and the P channel type semiconductor device are substantially the same. The type semiconductor device is provided with means for enhancing the short channel effect.
[0024]
Specifically, an impurity region is artificially and locally arranged in the channel formation region of the N-channel type semiconductor device and the P-channel type semiconductor device substantially in parallel with the channel direction.
The means for enhancing the narrow channel effect is means for intentionally narrowing the arrangement interval of the impurity regions arranged in the N channel type semiconductor device,
The means for enhancing the short channel effect is means for making the arrangement interval of the impurity regions arranged in the P-channel type semiconductor device relatively wider than the arrangement interval in the N-channel type semiconductor device. .
[0025]
Alternatively, the active layer of the N-channel type semiconductor device and the P-channel type semiconductor device has a crystal structure in which crystal grain boundaries are directional and acicular or columnar crystals that are substantially parallel to the substrate are aggregated. And
The means for enhancing the narrow channel effect is means for intentionally narrowing the crystal width of the needle-like or columnar crystal in the N-channel semiconductor device,
The means for enhancing the short channel effect is means for making the crystal width of the needle-like or columnar crystal in the P-channel semiconductor device relatively wider than the crystal width in the N-channel semiconductor device. To do.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
The difference in absolute value of the threshold voltage between the N-channel type semiconductor device and the P-channel type semiconductor device, which is a problem when manufacturing a semiconductor device having a CMOS structure, is corrected by new means not using the channel doping method.
[0027]
For this purpose, the threshold voltages of the N-channel type semiconductor device and the P-channel type semiconductor device are shifted separately by using the decrease of the threshold voltage due to the short channel effect and the increase of the threshold voltage due to the narrow channel effect. .
[0028]
A configuration in which the narrow channel effect appears strongly can be achieved by using a pinning technique to narrow the interval between impurity regions arranged in the channel formation region, that is, by strengthening the pinning effect. On the other hand, if the distance between the impurity regions is designed to be wide, the pinning effect is weakened and the short channel effect appears stronger.
[0029]
Further, when the active layer is formed using a crystal structure formed by acicular (or columnar) crystals, the same effect can be achieved by controlling the crystal width. Specifically, the narrow channel effect can be strengthened by narrowing the crystal width, and the short channel effect can be strengthened by widening the crystal width. The crystal width can be controlled by controlling the thickness of the amorphous silicon film before crystallization.
[0030]
【Example】
[ reference Example 1)
Book reference In the example, when a CMOS circuit is designed by using a thin film transistor (TFT) using a pinning technique, an active layer structure is different between an N-type transistor and a P-type transistor.
[0031]
As described in the conventional example, when the crystalline silicon film is used as the active layer, the electrical characteristics (Id-Vg characteristics) of the N-type transistor and the P-type transistor tend to shift to the negative side (negative side). The window center (Vcen) is 0 V or less.
[0032]
Therefore, in order to set the window center (Vcen) to 0 V, the threshold voltage (Vth, n) of the N-type transistor is moved in the increasing direction, and the threshold voltage (Vth, p) of the P-type transistor is decreased. Need to move in the direction.
[0033]
That is, if an impurity region is arranged with respect to the channel formation region so that a narrow channel effect is generated strongly in the active layer of the N-type transistor and a short channel effect is generated strongly in the active layer of the P-type transistor. Good (actually, increasing the short channel effect means relatively reducing the narrow channel effect).
[0034]
Where the book reference The structure of the active layer of the N-type transistor and the P-type transistor when the example is implemented is shown in FIGS. Note that the channel length of the active layer is in the range of 0.01 to 2 μm, and the channel width may be determined in an arbitrary range in consideration of the desired on-current and reliability.
[0035]
In FIG. 1A, reference numeral 101 denotes a source region, 102 denotes a drain region, and 103 denotes a channel formation region. The interval between the impurity regions 104 is adjusted so as to obtain a desired threshold voltage. Since FIG. 1A is an active layer of an N-type transistor, it is important to adjust the interval between the impurity regions 104 so that the narrow channel effect appears stronger.
[0036]
Book Shown in reference example When the invention is used, the required threshold voltage shift amount varies depending on the practitioner. In other words, the original (book Shown in reference example In consideration of the threshold voltage of the semiconductor device (not based on the invention), it is necessary to design the interval between the impurity regions so that a desired threshold voltage can be obtained experimentally.
[0037]
Typically, the interval between the impurity regions 104 may be set to 30 to 100 mm (preferably 50 to 500 mm) in order to enhance the narrow channel effect. In other words, the impurity region 104 may be arranged so that the width of the channel formation region is divided into about 100 to 1000 pieces.
[0038]
Book Shown in reference example According to the invention, it is presumed that the threshold voltage (Vth, n) of an N-type transistor having an active layer having a structure as shown in FIG. 1A changes as shown in FIG. Note that the dotted line in FIG. Shown in reference example If the invention is not implemented, the solid line is the book Shown in reference example It is an example at the time of implementing invention.
[0039]
That is, Vth, n is shifted in an increasing direction by adopting a configuration in which the narrow channel effect appears stronger. Further, since the effect of pinning the depletion layer is enhanced, the subthreshold characteristic is also improved (the slope of the Id-Vg characteristic indicated by the solid line in FIG. 1B increases).
[0040]
In addition, since FIG. 1C is an active layer of a P-type transistor, it is important to widely adjust the interval between the impurity regions 105 so that the short channel effect appears strongly. Typically, if the impurity region 105 is arranged so that the width of the channel formation region is divided into about 5 to 100, the short channel effect appears strongly. As a result, the threshold voltage (Vth, p) of the P-type transistor changes as shown in FIG.
[0041]
However, the fact that the short channel effect appears stronger means that the electrical characteristics are worsening. Therefore, as shown in FIG. 1D, the slope of the Id-Vg characteristic indicated by the solid line becomes small, so care must be taken between the deterioration of the characteristic and the control of Vth, p.
[0042]
As described above, the threshold voltage of the N-type transistor and the P-type transistor is controlled by intentionally strengthening the short channel effect or strengthening the narrow channel effect by using pinning technology. The difference in the absolute value of the threshold voltage in the CMOS circuit can be corrected. That is, it differs from the conventional pinning technique in that the interval between the impurity regions differs depending on the conductivity type.
[0043]
Further, the idea of using the short channel effect and the narrow channel effect, which have been conventionally recognized only as factors that hinder element miniaturization, for controlling the threshold voltage is completely new. Book Shown in reference example The invention makes it possible to control the threshold voltage without using the channel doping method.
[0044]
Therefore, the book Shown in reference example When the invention is used, a region where carriers move in the channel formation region is an intrinsic or substantially intrinsic region. Intrinsic or substantially intrinsic means that the activation energy is almost 1/2 (the Fermi level is located in the middle of the forbidden band), the region where the impurity concentration is lower than the spin density, and intentional This means an undoped region where no impurities are added.
[0045]
〔Example 1 ]
In this example, reference A technique for controlling Vth, n and Vth, p by controlling the short channel effect and the narrow channel effect by a method different from that in Example 1 will be described. Specifically, the crystal width of the polycrystalline silicon film is used.
[0046]
The crystalline silicon film (polycrystalline silicon film) crystallized by the technique described in Japanese Patent Laid-Open No. 6-244103 or Japanese Patent Laid-Open No. 7-321339 by the present inventors is a collection of acicular (or columnar) crystals. A crystal structure consisting of the structure is obtained. When this crystal structure is subjected to a heat treatment in an atmosphere containing a halogen element, a crystalline silicon film having extremely excellent crystallinity can be obtained.
[0047]
Further, it has been confirmed by an experiment of the present inventors that a semiconductor device using this crystalline silicon film as an active layer exhibits electrical characteristics comparable to a MOSFET fabricated on single crystal silicon. Specifically, the subthreshold characteristic (S value) is 60 to 100 mV / dec (preferably 60 to 70 mV / dec), Vth, n is -0.5 to 2.0 V, and Vth, p is -2.0 to 0.5 V. High electrical characteristics can be obtained.
[0048]
However, there is a bias in the threshold voltage due to the difference in the conductivity type of the active layer as described above. Typically, Vth, n is -0.5 to 0.5 V, Vth, p is -1.5 to -0.5 V, and the window The center (Vcen) is often near -1.0 to -0.5V. This embodiment is a technique for shifting the window center of such a semiconductor device to the positive side by 0.5 to 1.0 V.
[0049]
Here, FIG. 4 shows a photograph of the crystal structure as observed by TEM. As shown in FIG. 4, this crystal structure has regularity in which the needle-like crystals 401 are directed substantially in the same direction, and the crystal grain boundaries 402 also extend substantially parallel to each other.
[0050]
The present inventors consider that the conditions for obtaining the highest electrical characteristics are obtained when the direction connecting the source region and the drain region of the active layer (channel direction) and the growth direction of the needle crystal 401 coincide. I guessed. Then, the above-described pinning technique is schematically modeled by regarding the crystal grain boundary as a region having a high energy barrier.
[0051]
In other words, reducing the crystal width of the acicular crystal reference This corresponds to obtaining the configuration of FIG. 1A in Example 1, and a configuration in which the narrow channel effect appears strongly. Also, widening the crystal width reference This corresponds to obtaining the configuration shown in FIG. 1C of Example 1, and the short channel effect appears strongly.
[0052]
According to the experimental knowledge of the present inventors, it has been found that the crystal width of the needle-like crystal is substantially equal to the thickness of the amorphous silicon film before crystallization. Therefore, when the crystal structure has a narrow crystal width (when the narrow channel effect is enhanced), the amorphous silicon film is thinned and the crystal structure has a wide crystal width (when the short channel effect is enhanced). ) Is sufficient to increase the thickness of the amorphous silicon film.
[0053]
Here, a method for manufacturing a crystalline silicon film for carrying out this embodiment will be described with reference to FIGS. FIG. 5A shows only a specific narrow area on the substrate. In FIG. 5A, reference numeral 501 denotes a quartz substrate. Although a glass substrate can be used, if there is a heat treatment process exceeding 700 ° C. later, it is necessary to use a quartz substrate in consideration of heat resistance.
[0054]
An amorphous silicon film 502 is formed on the quartz substrate 501. What is important in this embodiment is that the amorphous silicon film 502 is partially thinned (meaning that it is thinner than the film thickness at the time of film formation). This thinning may be performed by a half etching technique or the like. Of course, it goes without saying that the region to be thinned is a region that later becomes an active layer of an N-type transistor.
[0055]
When the selective thinning is completed, crystallization is performed using the technique described in Japanese Patent Laid-Open No. Hei 6-244103 or Japanese Patent Laid-Open No. 7-321339. It is effective to use the technique described in Japanese Patent Application Laid-Open No. Hei 7-321339 in order to define the crystal growth direction of the acicular crystal and to match the growth direction with the channel direction.
[0056]
Thus, as shown in FIG. 5B, a crystalline silicon film 503 having regions with different film thicknesses is obtained. FIG. 5C is a view of the crystalline silicon film 503 in FIG. 5B as viewed from above. The first region 504 having a small thickness and the second region 505 having a large thickness depending on the thickness. And divided.
[0057]
Further, FIGS. 5D and 5E schematically show a state when the first region 504 and the second region 505 are enlarged. In FIG. 5D, since the amorphous silicon film 502 is thin during crystallization, the crystal width of the needle crystal 506 is narrow. As shown in FIG. 5E, since the second region 505 is thick, the crystal width of the needle crystal 507 is wider than that of the crystal 506.
[0058]
Therefore, when the crystal structure in the state shown in FIG. 5D is used as the active layer, the pinning effect (the effect of suppressing the spread of the drain side depletion layer) is enhanced, and the width of the needle-like crystal 506 is narrow. It is presumed that the narrow channel effect appears prominently. In addition, when the crystal structure in the state shown in FIG. 5E is used as the active layer, it is presumed that the pinning effect is weakened and the short channel effect appears.
[0059]
As described above, the influence of the narrow channel effect and the short channel effect is controlled by controlling the crystal width of the needle-like crystal, and a desired threshold voltage can be obtained for both the N-type transistor and the P-type transistor. Can be designed.
[0060]
[ reference Example 2 ]
Book reference In the example reference The structure of the CMOS circuit to which Example 1 is applied will be described with reference to FIG. Since the basic structure of the CMOS circuit is known, only necessary portions will be described with reference numerals.
[0061]
Figure 6 (A) shows a book Shown in reference example It is a top view of a CMOS circuit when the invention is applied. The left side is an N-type transistor and the right side is a P-type transistor, which basically has the same structure. Reference numerals 601 and 602 denote active layers, over which a gate electrode 603 and a data wiring 604 are arranged.
[0062]
Further, an impurity region 605 by a pinning technique is disposed in the channel formation region of the active layer 601 of the N-type transistor, and an impurity region 606 is similarly disposed in the channel formation region of the active layer 602 of the P-type transistor.
[0063]
In that case, book Shown in reference example According to the invention, the interval at which the impurity regions 605 are arranged is set narrower than the interval at which the impurity regions 606 are arranged. It is necessary for the practitioner to obtain specific numerical values experimentally.
[0064]
The cross section which cut | disconnected FIG. 6 (A) by AA 'and BB' is shown to FIG. 6 (B) and (C). Reference numeral 607 denotes a substrate having an insulating surface. At this time, a cross section in the channel width direction of the active layer 601 appears in FIG. 6B, and a cross section in the channel width direction of the active layer 602 appears in FIG. 6C.
[0065]
FIG. 6D shows a cross section that appears when FIG. 6A is cut along CC ′. Reference numeral 607 denotes a substrate having an insulating surface, and reference numeral 608 denotes a channel formation region located immediately below the gate electrode. In FIG. 6D, the hatching is changed when describing the impurity regions 605 and 606 in order to show that the arrangement density is different between the N-type transistor and the P-type transistor.
[0066]
As above, reference When the configuration of the invention shown in Example 1 is applied to a CMOS circuit, as is apparent from FIGS. 6B and 6C, the interval between the impurity regions 605 arranged in the N-type transistor is arranged in the P-type transistor. This is narrower than the distance between the impurity regions 606.
[0067]
〔Example 2 ]
In this embodiment, the embodiment 1 A description will be given of the structure of a CMOS circuit to which is applied with reference to FIG. reference Example 2 6 is different from FIG. 6 in that the narrow channel effect is controlled not by the impurity region but by the width of the needle crystal.
[0068]
FIG. 7A is a top view of a CMOS circuit when the present invention is applied. The reference numerals written in each part correspond to the same part as in FIG. Reference numeral 701 denotes an acicular crystal constituting the active layer 601, and reference numeral 702 denotes an acicular crystal constituting the active layer 602.
[0069]
The feature of this embodiment is that the crystal width of the needle crystal 701 is formed to be narrower than the crystal width of the needle crystal 702 according to the present invention. Control of the crystal width may be performed by the means shown in the second embodiment. In addition, the specific width needs to be experimentally determined by the practitioner. Typically, the width of the acicular crystal 701 may be 50 to 500 mm (preferably 50 to 200 mm).
[0070]
FIGS. 7B and 7C show cross sections of FIG. 7A cut along AA ′ and BB ′. At this time, a cross section in the channel width direction of the active layer 601 appears in FIG. 7B, and a cross section in the channel width direction of the active layer 602 appears in FIG. 7C. FIG. 7D shows a cross section that appears when FIG. 7A is cut along CC ′.
[0071]
As described above, the embodiment 1 When the structure of the present invention shown in FIG. 6 is applied to a CMOS circuit, the crystal width of the needle-like crystal 701 constituting the active layer 601 of the N-type transistor is P-type, as is apparent from FIGS. 7B and 7C. This is narrower than the crystal width of the needle crystal 702 constituting the active layer 602 of the transistor.
[0072]
〔Example 3 ]
In this embodiment, an embodiment of a CMOS circuit to which the present invention is applied will be described with reference to FIG. In addition, here is an example 1 The case where this invention is implemented by the means of is taken as an example. In FIGS. 8A, 8B, and 8C, the left side is an N-type transistor, and the right side is a P-type transistor. Further, since the structure of the CMOS circuit is known, only a special structure will be described with reference numerals.
[0073]
The CMOS circuit shown in FIG. 8A has a structure in which a low concentration impurity region for electric field relaxation is provided between a drain region and a channel formation region using the technique described in Japanese Patent Laid-Open No. 7-13518. Basically, the N-type transistor and the P-type transistor are different only in conductivity type and there is no structural difference. Therefore, the N-type transistor will be mainly described.
[0074]
In FIG. 8A, the active layer includes a source region 801, a drain region 802, a channel formation region 803, and low-concentration impurity regions 804 and 805. Reference numeral 806 denotes a gate insulating film, 807 denotes a gate electrode mainly composed of aluminum, and the gate electrode 807 is protected by an anodic oxide film 808. Reference numeral 809 denotes an interlayer insulating film, and reference numeral 810 denotes a data wiring.
[0075]
Since the gate insulating film 806 is etched using a porous anodic oxide film (removed in the process of forming the CMOS circuit) disposed on the side surface of the gate electrode 807 as a mask, it remains in a part of the active layer. It becomes. Low-concentration impurity regions 804 and 805 are formed using the end portions of the gate insulating film 806.
[0076]
Next, the structure shown in FIG. 8B shows an example in which a side wall made of an insulator is used instead of a porous anodic oxide film in the technique described in the above-mentioned Japanese Patent Application Laid-Open No. 7-13318. . Therefore, the configuration of the active layer is basically the same as the configuration of the active layer described with reference to FIG.
[0077]
The sidewall 811 is formed by leaving a silicon nitride film or a silicon oxide film only on the side surface of the gate electrode 807 by an etch back method. This sidewall 811 is also required when the silicide 812 is formed on the main surfaces of the source region 801 and the drain region 802.
[0078]
The silicide 812 may be formed using a known salicide technique. For example, a metal can be used for titanium, tantalum, molybdenum, tungsten, or the like. At this time, it is also possible to select conditions such that the entire source / drain region is silicided.
[0079]
Since the semiconductor device having a salicide structure as shown in FIG. 8B has good ohmic contact with the data wiring 810, operation speed can be improved.
[0080]
Next, the structure illustrated in FIG. 8C is an example in which the gate electrode material is crystalline silicon (polycrystalline silicon) in the structure illustrated in FIG. 8B. A side wall 811 is disposed on the side surface of the gate electrode 813 as in FIG. 8B. In this case, silicide 814 is also formed on the main surface of the gate electrode 813.
[0081]
Although not shown in FIG. 8C, since the gate electrode 813 is connected to a lead wiring for transmitting a gate signal, this configuration can improve ohmic contact with such a lead wiring.
[0082]
The structure of the CMOS circuit described above shows one embodiment, and it is up to the practitioner to apply the present invention to other structures. Therefore, for example, a multigate type structure (double gate type or triple gate type) can be adopted, and the present invention can be applied to a case where a CMOS circuit is constituted by an inverted stagger type TFT.
[0083]
〔Example 4 ]
A semiconductor device using the present invention can also be applied to an active matrix electro-optical device in which a pixel matrix circuit and a logic circuit are integrated on the same substrate. Examples of the electro-optical device include a liquid crystal display device, an EL display device, and an EC display device.
[0084]
Note that the logic circuit refers to an integrated circuit for driving the electro-optical device, such as a peripheral drive circuit or a control circuit. The control circuit includes all electric circuits necessary for driving an electro-optical device such as a processor circuit, a memory circuit, a clock generation circuit, and an A / D (D / A) converter circuit.
[0085]
Since the TFT to which the present invention is applied controls the threshold voltage without reducing the operation speed, a high-performance integrated circuit can be configured. In addition, by reducing the window center (Vcen) to 0 V or narrowing the window width (Vwin), it is possible to reduce the required driving voltage and to manufacture an electro-optical device with low power consumption.
[0086]
〔Example 5 ]
In this specification, a “semiconductor device” refers to all devices that function by using a semiconductor. Accordingly, single TFTs, semiconductor integrated circuits (logic circuits such as CMOS circuits, DRAM circuits, SRAM circuits, etc.), active matrix electro-optical devices and their application products are included in the category of semiconductor devices.
[0087]
In this embodiment, the applied product will be described with reference to examples. Examples of the semiconductor device using the present invention include a TV camera, a head mounted display, a car navigation, a projection (there are a front type and a rear type), a video camera, a personal computer, and the like. A brief description will be given with reference to FIG.
[0088]
FIG. 9A illustrates a mobile computer which includes a main body 2001, a camera portion 2002, an image receiving portion 2003, operation switches 2004, and a display device 2005. The present invention is applied to the display device 2005 and an integrated circuit 2006 incorporated in the device.
[0089]
FIG. 9B illustrates a head mounted display, which includes a main body 2101, a display device 2102, and a band portion 2103. Two display devices 2102 having a relatively small size are used.
[0090]
FIG. 9C illustrates car navigation, which includes a main body 2101, a display device 2102, operation switches 2103, and an antenna 2104. The present invention can be applied to the display device 2102 and the integrated circuit 2105 inside the device. Since it is in-vehicle, a highly reliable semiconductor device that is resistant to voltage fluctuations is required. Although the display device 2202 is used as a monitor, it can be said that the allowable range of resolution is relatively wide because the main purpose is to display a map.
[0091]
FIG. 9D illustrates a mobile phone, which includes a main body 2301, an audio output portion 2302, an audio input portion 2303, a display device 2304, operation switches 2305, and an antenna 2306. The present invention can be applied to the display device 2304 and the integrated circuit 2105 inside the device. Since it is important to reduce power consumption in the standby state, the present invention can be said to be very effective.
[0092]
FIG. 9E illustrates a video camera which includes a main body 2401, a display device 2402, an audio input portion 2403, operation switches 2404, a battery 2405, and an image receiving portion 2406. The present invention can be applied to the display device 2402 and the integrated circuit 2407 inside the device. Since long-term use by battery drive is required, it is very meaningful to reduce power consumption according to the present invention.
[0093]
FIG. 9F illustrates a front projection, which includes a main body 2501, a light source 2502, a reflective display device 2503, an optical system (including a beam splitter, a polarizer, and the like) 2504 and a screen 2505. Since the screen 2505 is a large screen screen used for presentations such as conferences and conference presentations, the display device 2503 is required to have a high resolution.
[0094]
In addition to the electro-optical device shown in this embodiment, the present invention can be applied to portable information terminal devices such as rear projection and handy terminals. As described above, the application range of the present invention is extremely wide and can be applied to display media in various fields.
[0095]
The TFT of the present invention is not limited to an electro-optical device, but can be incorporated in an integrated circuit in the form of SRAM or DRAM, for example, and used as a drive circuit for an application product as shown in this embodiment.
[0096]
【The invention's effect】
By utilizing the short channel effect and the narrow channel effect that occur with the miniaturization of device elements, it becomes possible to correct the difference in Vth of the CMOS circuit without using the channel doping method.
[0097]
Therefore, it is possible to realize a semiconductor device capable of high-speed operation that not only prevents the deterioration of the operation speed and malfunction of the CMOS circuit caused by the bias of the threshold voltage but also reduces the influence of impurity scattering in the channel formation region. Yes. Further, since the absolute value of the threshold voltage of the semiconductor device can be reduced, the power consumption of the semiconductor device can be reduced.
[0098]
In addition, the energy barrier (impurity region and grain boundary) formed almost in parallel with the channel direction in the channel formation region ensures high reliability that does not cause degradation of characteristics due to the short channel effect even in a minute region of 0.01 to 2 μm. Can be realized.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining a structure of an active layer.
FIG. 2 is a diagram for explaining a conventional example.
FIG. 3 is a diagram for explaining a pinning technique.
FIG. 4 is a photograph showing acicular crystals.
FIGS. 5A and 5B are diagrams illustrating a manufacturing process of a crystalline silicon film. FIGS.
FIG. 6 shows a structure of a CMOS circuit.
FIG. 7 shows a structure of a CMOS circuit.
FIG. 8 is a diagram showing a configuration of a CMOS circuit.
FIG. 9 illustrates an example of a semiconductor device (application product).
[Explanation of symbols]
101 Source area
102 Drain region
103 channel formation region
104 Impurity region of N-channel semiconductor device
105 Impurity region of N-channel semiconductor device

Claims (6)

In a semiconductor device having a CMOS circuit in which an N-channel thin film transistor and a P-channel thin film transistor formed on a substrate having an insulating surface are complementarily combined,
The N-channel thin film transistor includes a first active layer formed on the substrate and made of a crystalline silicon film, a first source region, a first drain region, and a first active layer formed in the first active layer. Channel forming region,
The P-channel thin film transistor includes a second active layer formed on the substrate and made of a crystalline silicon film, a second source region, a second drain region, and a second active layer formed in the second active layer. Two channel forming regions,
The first active layer of the N-channel type thin film transistor and the second active layer of the P-channel type thin film transistor are oriented at crystal grain boundaries, and acicular or columnar crystals that are substantially parallel to the substrate are assembled. Consisting of a crystal structure
A semiconductor device characterized in that a crystal structure used in the N-channel thin film transistor has a needle-like or columnar crystal having a narrower crystal width than a crystal structure used in the P-channel thin film transistor. In a semiconductor device having a CMOS circuit in which an N-channel thin film transistor and a P-channel thin film transistor formed on a substrate having an insulating surface are complementarily combined,
The N-channel thin film transistor includes a first active layer formed on the substrate and made of a crystalline silicon film, a first source region, a first drain region, and a first active layer formed in the first active layer. Channel forming region,
The P-channel type thin film transistor is a crystalline silicon film formed on the substrate. And a second source region, a second drain region, and a second channel formation region formed in the second active layer,
Each of the first source region, the first drain region, the second source region, and the second drain region is made of silicide.
The first active layer of the N-channel type thin film transistor and the second active layer of the P-channel type thin film transistor are oriented at crystal grain boundaries, and acicular or columnar crystals that are substantially parallel to the substrate are assembled. Consisting of a crystal structure
A semiconductor device characterized in that a crystal structure used for the N-channel thin film transistor has a narrower crystal width of a needle-like or columnar crystal than a crystal structure used for the P-channel thin film transistor. In claim 1 or claim 2 ,
The semiconductor device according to claim 1, wherein the first active layer is thinner than the second active layer. In a method for manufacturing a semiconductor device having a CMOS circuit in which an N-channel thin film transistor and a P-channel thin film transistor are complementarily combined on a substrate having an insulating surface,
Forming a crystalline silicon film on the substrate;
Forming a first active layer of the N-channel thin film transistor and a second active layer of the P-channel thin film transistor using the crystalline silicon film;
Forming a first source region, a first drain region, and a first channel formation region in the first active layer;
Forming a second source region, a second drain region, and a second channel formation region in the second active layer;
The first active layer and the second active layer are composed of a crystal structure in which crystal grain boundaries are oriented and acicular or columnar crystals that are substantially parallel to the substrate are aggregated,
A method for manufacturing a semiconductor device, wherein a crystal width of the needle-like or columnar crystal in the first active layer is narrower than a crystal width of the second active layer. In 請 Motomeko 4,
The method for manufacturing a semiconductor device, wherein the crystalline silicon film is formed by introducing a metal element that promotes crystallization into an amorphous silicon film and crystallizing the film by heating. In claim 4 or claim 5,
A method for manufacturing a semiconductor device, wherein the thickness of the first active layer is smaller than the thickness of the second active layer.

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