JP3885083B2 - Active matrix display device - Google Patents

Description

  The present invention relates to a liquid crystal display device having a plurality of pixels each having a switching element, a light emitting device such as an electroluminescence type display device, and a light emitting diode. The present invention relates to a so-called Active Matrix-type Display Device represented by a display device having a plurality of pixels, and in particular, a display image of a hold-type display device (Hold-type Display Device). Related to Blanking Process.

  An image based on video data (video signal in the case of television broadcasting) input from the outside every frame period is set to a predetermined period (for example, one frame period) A liquid crystal display device has been widely used as a display device that holds and displays a desired value.

  In the liquid crystal display device of the active matrix scheme (Active Matrix Scheme), as shown in FIG. 9, a pixel electrode PX and a video signal are applied to each of a plurality of pixels PIX arranged two-dimensionally or in a matrix form. A switching element SW (for example, a thin film transistor) to be supplied is provided. An element in which a plurality of pixels PIX are arranged in this way is also called a pixel array 101, and the pixel array in the liquid crystal display device is also called a liquid crystal display panel. In this pixel array, the plurality of pixels PIX form a so-called screen for displaying an image.

  In the pixel array 101 shown in FIG. 9, a plurality of gate lines 10 (also referred to as scanning signal lines) extending in the horizontal direction and a plurality of data lines extending in the vertical direction (direction intersecting with the gate lines 10) are included. 12 (Data Lines, also called video signal lines) are juxtaposed. As shown in FIG. 9, a so-called pixel row in which a plurality of pixels PIX are arranged in the horizontal direction along each gate line 10 identified by addresses G1, G2,... Gj, Gj + 1,. However, a so-called pixel column in which a plurality of pixels PIX are arranged in the vertical direction is formed along each data line 12 identified by the addresses D1R, D1G, D1B,... DmB. The gate line 10 is a switching element provided in each pixel PIX that forms a pixel row corresponding to each of the scan driver 103 (also referred to as a scanning driver circuit) (in the case of FIG. 9, below each gate line). A voltage signal is applied to the SW to open and close the electrical connection between the pixel electrode PX provided in each pixel PIX and one of the data lines 12. The operation of controlling a group of switching elements SW provided in a specific pixel row by applying a voltage signal from the corresponding gate line 10 is “selecting line (s)” or “scanning ( Scanning). The voltage signal applied to the gate line 10 from the scan driver 103 is also referred to as a scan signal. For example, the conduction state of the switching element SW is controlled by a pulse generated in the signal waveform. Further, this scanning signal is supplied as a current signal to the scanning signal line (corresponding to the gate line 10) according to the type of the switching element SW.

  On the other hand, each of the data lines 12 has a display signal (in the case of a liquid crystal display device) called a gradation voltage (Gray Scale Voltage or Tone Voltage) from the data driver 102 (also called a data driver, also called a video signal driving circuit). Voltage signal) is applied, and the gradation voltage is applied to each pixel electrode PX selected by the scanning signal of the pixel PIX forming the pixel column corresponding to each of them (in the case of FIG. 9, the right side of each data line). To do.

  When such a liquid crystal display device is incorporated in a television device, one field period of video data (video signal) received in the interlace mode (Interlace Mode) or video data received in the progressive mode (Progressive Mode). The scanning signal is sequentially applied to G1 to Gn of the gate line 10 for one frame period, and the gradation voltage generated from the video data received in one field period or one frame period constitutes each pixel row. Sequentially applied to a group of pixels. In each pixel, a so-called capacitive element is formed, in which the liquid crystal layer LC is sandwiched between the pixel electrode PX and the counter electrode CT to which a reference voltage (Common Voltage) is applied through the signal line 11, The light transmittance of the liquid crystal layer LC is controlled by an electric field generated between the pixel electrode PX and the counter electrode CT. As described above, when the operation of sequentially selecting the gate lines G1 to Gn is performed once for each field period or frame period of the video data, for example, the gradation applied to the pixel electrode PX of a certain pixel during a certain field period. The voltage is theoretically held in the pixel electrode PX until another gray scale voltage is received in the next field period following the certain field period. Therefore, the light transmittance of the liquid crystal layer LC sandwiched between the pixel electrode PX and the counter electrode CT (in other words, the brightness of the pixel having the pixel electrode PX) is maintained in a predetermined state every field period. Be drunk. A liquid crystal display device that displays an image while maintaining the brightness of a pixel for each field period or frame period is also called a hold-type display device, and at the moment when a video signal is received. It is distinguished from a so-called impulse-type display device such as a cathode-ray tube that emits a phosphor provided for each pixel by electron beam irradiation.

  Video data transmitted from a television receiver, a computer, or the like has a format corresponding to an impulse display device. Comparing the above-mentioned driving method of the liquid crystal display device and television broadcasting, a scanning signal is applied to each gate line 10 in a time corresponding to the reciprocal of the horizontal scanning frequency of television broadcasting, which corresponds to the reciprocal of the vertical frequency. The scanning signal application to all the gate lines G1 to Gn is completed in time. The impulse display device sequentially emits pixels arranged in the horizontal direction of the screen every horizontal scanning period in response to the horizontal synchronizing pulse, but the hold type display device sets a pixel row for each horizontal scanning period as described above. When selected, a voltage signal is supplied to a plurality of pixels included in this pixel row all at once, and the voltage signal is held in these pixels after the end of the horizontal scanning period.

  The operation of the hold-type display device has been described with reference to FIG. 9 as an example of the liquid crystal display device. An electroluminescence type (EL type) display element in which the liquid crystal layer LC is replaced with an electroluminescent material, or a liquid crystal layer The light-emitting diode array type display device in which the capacitive element sandwiching LC between the pixel electrode PX and the counter electrode CT is replaced with a light-emitting diode also displays its operation principle (controlling the amount of carriers injected into the light-emitting material) ) Is different, but operates as a hold type display device. In a display device that generates an image by carrier injection into a light emitting material (light emitting region), the display signal is supplied as a current signal to each pixel in the pixel array.

  By the way, since the hold type display device displays an image by holding the brightness of each pixel for each frame period, for example, the display image is replaced with a different one between a pair of consecutive frame periods. The brightness of the pixel may not respond sufficiently. In this phenomenon, a pixel set to a predetermined brightness in a certain frame period (for example, the first frame period) is scanned in the next frame period (for example, the second frame period) following this frame period. Until the brightness of the first frame period is maintained. In addition, this phenomenon is that a part of the voltage signal (or the carrier injected into the pixel) sent to the pixel in the first frame period is to be sent to the pixel in the second frame period (or This is also explained from the history (Hysteresis) of the video signal in each pixel, which interferes with the carrier to be injected into this. For example, Japanese Patent Publication No. 06-016223, Japanese Patent Publication No. 07-044670, Japanese Patent Application Laid-Open No. 05-073005, Japanese Patent Publication No. They are disclosed in Japanese Laid-Open Patent Publication No. 11-109921 and Japanese Laid-Open Patent Publication No. 2001-166280, respectively.

  Among them, in Japanese Patent Application Laid-Open No. 11-109921, when reproducing a moving image on a liquid crystal display device (an example of a display device using hold type light emission), an object is compared with a cathode ray tube that emits pixels in an impulse manner. The so-called blurring phenomenon (Blurring Phenomenon) in which the outline of the image becomes unclear is discussed. In order to solve this blurring phenomenon, Japanese Patent Application Laid-Open No. 11-109921 discloses that a pixel array (Pixels Array, a plurality of two-dimensionally arranged pixel groups) of one liquid crystal display panel is placed above and below a screen (image display area). Disclosed is a liquid crystal display device that is divided into two, and a data line driving circuit is provided for each of the divided pixel arrays. This liquid crystal display device is a so-called dual scan operation in which a video signal is supplied from a data line driving circuit provided in each pixel array while selecting one gate line for each of the upper and lower pixel arrays and two in total. Perform (Dual Scanning Operation). While performing this dual scan operation within one frame period, a signal corresponding to a display image (a so-called video signal) is shifted on one side and a blanking image (a black image, for example) signal on the other side. From the data line driving circuit to the pixel array. Therefore, a period for performing image display and a period for performing blanking display are given to both the upper and lower pixel arrays in one frame period, and the period during which an image is held in the entire screen is shortened. Thereby, even in a liquid crystal display device, a moving image display performance similar to that of a cathode ray tube can be obtained.

  As a conventional technique, Japanese Patent Application Laid-Open No. 11-109921 discloses that one liquid crystal display panel is divided into two upper and lower pixel arrays, and a data line driving circuit is provided in each of the divided pixel arrays. A total of two gate lines are selected, one for each of the above, and a blanking image is selected by shifting the upper and lower phases within one frame period while dual scanning the display area divided into two vertically by each drive circuit. It is disclosed that (black image) is inserted (interpolate). That is, one frame period takes the state of the video display period and the blanking period, and the video hold period can be shortened. Therefore, a moving image display performance of impulse type light emission can be obtained with a liquid crystal display like a cathode ray tube.

  On the other hand, another technique for suppressing the blurring phenomenon of a moving image displayed on a liquid crystal display device is disclosed in Japanese Patent Laid-Open No. 2001-166280. In this publication, the selection period of the gate line for supplying the video signal to the pixel group corresponding to each gate line is divided, and the video signal is supplied to the pixel group corresponding to the gate line selected in the first half. A driving method of a liquid crystal display device is described in which a voltage signal for black display is supplied to another pixel group corresponding to another gate line selected in the latter half. The outline will be described with an example in which the pixel array of FIG. 9 is driven according to the timing chart of FIG. For each frame period, the gate lines G1, G2,... Gj, Gj + 1,... In the pixel array 101 are each supplied with a gate pulse (Gate Pulse) generated in the scanning signal sent from the scanning driver 103 to each of them. Selected). In other words, the switching element SW provided in each of the pixels PIX corresponding to the gate line that has received the gate pulse enters a state in which the pixel PIX receives a display signal transmitted from the data line 12 by the gate pulse. For example, in response to the output from the data driver 102 of the display signal L1 generated from one line of video data to be supplied to the pixel group corresponding to the gate line G1 (also referred to as a pixel row because it is arranged in the row direction). The gate line G1 is selected by the gate pulse. In FIG. 10, a gate pulse is shown as a waveform in which a scanning signal in a low state becomes a high state, and a gate line that receives this scanning signal is selected over a period in which the scanning signal is in a high state.

In the method for driving a liquid crystal display device disclosed in Japanese Patent Laid-Open No. 2001-166280, display signals for one line of video data (L1, L2, Lj, Lj + 1,. Any one)), and the time tg during which the corresponding gate line (G1, G2, Gj, Gj + 1 in FIG. 10) was selected is selected as another gate line. A display signal (B in FIG. 10) is supplied to select the pixel line corresponding to the other gate line (B in FIG. 10). A gate line that is selected within the time (tg−tb) and to which video data for one line is written, and black data that is selected within the subsequent time tb (corresponding to a display signal for displaying pixels black) Are selected so as to be separated from each other in the pixel array. As a result, by completing video generation by writing video data to the pixel array for each frame period and erasing the video, this video is generated on the screen like an impulse-type display device, and moving image blur is also reduced. .
Japanese Patent Publication No. 06-016223 Japanese Patent Publication No. 07-044670 JP 05-073005 A JP-A-11-109921 JP 2001-166280 A

  Comparing the liquid crystal display device described in Japanese Patent Laid-Open No. 11-109921 with that described in Japanese Patent Laid-Open No. 2001-166280, the former selects two gate lines at the same time and selects a pixel corresponding to one of them. A display signal corresponding to video data for one line can be supplied to a row, and a display signal for displaying this in black can be supplied to the pixel row corresponding to the other. As a result, a time for supplying a display signal to each of the pixels constituting each pixel row is secured. However, since the period during which the pixel row holds the display signal corresponding to the video data in one frame period is limited to half of that, especially the pixel luminance from the supply of the display signal to the value corresponding thereto When a delay time is required, the problem of receiving the next display signal for displaying the pixel in black before the pixel reaches a sufficient luminance arises. In order to solve this problem, the intensity of the display signal must be increased, and therefore the output of the data driver 102 must be increased. Further, as described above, the liquid crystal display device described in Japanese Patent Application Laid-Open No. 11-109921 divides the pixel array into two regions, and thus a data line driving circuit must be provided in each region. Accordingly, the liquid crystal display panel and its peripheral circuits also have a complicated structure and a large size.

  On the other hand, the liquid crystal display device described in Japanese Patent Application Laid-Open No. 2001-166280 is more practical than that described in Japanese Patent Application Laid-Open No. 11-109921 in terms of the structure and dimensions of the liquid crystal display panel and its peripheral circuits. . However, as is apparent from the timing chart of FIG. 10, a part of the selection period of the gate line for writing video data for one line to a pixel row is different for writing black data to another pixel row. Therefore, there is a problem that the time for supplying the display signal to each pixel row is shortened. SID 01 Digest (The 2001 International Symposium of the Society for Information Display), pages 994-997 describes a technique for solving the above-described problems in a liquid crystal display device disclosed in Japanese Patent Laid-Open No. 2001-166280. If this technique is described with reference to FIG. 10, the ratio of the time tb to the time tg is suppressed to less than tg / 2, and the video data writing time to the pixel row is secured. On the other hand, the black data writing to the pixel row is repeated according to the video data writing to the pixel row a plurality of times to compensate for the shortage of the one writing time tb. For this reason, the black data writing to the gate lines Gj, Gj + 2, Gj + 4,... (The latter two are not shown in FIG. 10) is performed on the gate line G2. Black data is written to the gate lines Gj + 1, Gj + 3, Gj + 5,... (The latter two are not shown in FIG. 10).

  Thus, although the black data writing time to the gate line is ensured in total, the lack of time for each time is insufficient to compensate for the delay in the luminance response of the pixel. Compared with a pixel that has received a sufficient display signal by writing black data to the gate line once, a pixel that has received this display signal divided into a plurality of times has a weak luminance response. For this reason, there is a possibility that the display signal of the video data to be erased remains in the pixel even after the start of writing the black data, and the erasure from the screen of the image by the video data to be completed in one frame period is halfway. .

  The present invention suppresses the motion blur of the moving image displayed on the pixel array of the hold type display device represented by the liquid crystal display device to the minimum, and sufficiently maintains the display brightness. A display device and a driving method thereof are provided.

  An example of a display device according to the present invention is as follows. (1) A plurality of pixels each provided with a switching element (for example, a field effect element such as a thin film transistor) are disposed along a first direction (for example, the horizontal direction of the display screen). A pixel array in which a plurality of pixel columns are arranged along a second direction (for example, a vertical direction of the display screen) that intersects the first direction with the pixel row, and (2) the first of the pixel arrays A first signal (e.g., a gate pulse) is supplied to the group of switching elements provided in the pixel row corresponding to the pixel row and extending in the direction of 1 and juxtaposed along the second direction. A plurality of first signal lines (for example, scanning signal lines) to be transmitted; and (3) the first signal lines extending from one end to the other end of the pixel array along the second direction. First signal line by sequentially outputting signals A first driving circuit (for example, a scanning driving circuit) for selecting the corresponding pixel row; (4) extending along the second direction of the pixel array and juxtaposed along the first direction; Each of the plurality of second signal lines (for example, for supplying a second signal to at least one of the pixel rows selected by the first signal of the pixels provided in the pixel column corresponding thereto) Video signal line or data signal line), (5) a second drive circuit (for example, a data drive circuit) for outputting the second signal to each of the second signal lines, and (6) the first drive circuit with the second signal. A display control circuit (for example, a timing controller) that sends a first control signal for controlling the first signal output and sends a second control signal for controlling the output interval of the second signal and video data to the second drive circuit. Is provided.

  The first driving circuit described above outputs the first signal N times for each Y line of the plurality of first signal lines, and the first signal is output in the first scanning process of the plurality of first signal lines. The second scanning step of outputting M times for each Z line other than the (Y × N) line that has received the first signal (in other words, a group of first signal lines not selected in the first scanning step) is alternately repeated. (Y, N, Z, and M are natural numbers that satisfy the relationship of M <N and Y <N / M ≦ Z, respectively).

  The second driving circuit described above receives video data from the display control circuit line by line for each horizontal scanning period, and N times of the second signal generated for each line of video data in the first scanning step. The output and the M outputs of the second signal for masking the pixel array in the second scanning step are repeated alternately.

  The above-described video data is input and supplied to the display device from a video signal source outside the display device such as a television receiver, a personal computer, a DVD player (Digital Versatile Disc Player) or the like. In addition, image data is supplied to the display device by inputting one line of data (also referred to as line data or horizontal data) to the display device a plurality of times for each horizontal scanning frequency. Video data is input to the display device for each piece of image information for one screen, and the period required for this is called a frame period.

  On the other hand, the time for selecting the pixel row and inputting the display signal to one output of the display signal from the second drive circuit is called a horizontal period or a horizontal period. In other words, this horizontal period also corresponds to the output interval of the second signal from the second drive circuit. By making the blanking period included in the horizontal period shorter than the horizontal blanking period included in the period (horizontal scanning period) in which one line of video data is input to the display device, the video data for each line is displayed. The output interval of the display signal corresponding to this to the pixel array becomes shorter than the input interval. Therefore, at least N line memories are provided in the display control circuit, and the video data sequentially input to the display device for each line is sequentially stored for each of the N line memories, and from each of them. By sequentially reading out, the difference between the time required to input video data for N lines to the display device and the time required to transfer the video data to the second driving circuit sequentially (for N times) is determined in the second scanning step. This can be used for the second signal output to the pixel array. The second signal for masking the pixel array in the second scanning step is also called a blanking signal because it reduces the luminance of the input pixel to that before the input.

  Another example of the display device according to the present invention is (1) two-dimensionally arranged along a first direction (for example, the horizontal direction of the display screen) and a second direction (for example, the vertical direction of the display screen) intersecting therewith. A pixel array having a plurality of pixels, and (2) a plurality of pixel rows that are arranged in parallel along the second direction in the pixel array and are arranged along the first direction of the plurality of pixels. A plurality of first signal lines (e.g., scanning signal lines) that transmit scanning signals for selecting the respective pixels; and (3) the pixels that are arranged in parallel in the first direction in the pixel array and selected by the scanning signals. A plurality of second signal lines (for example, video signal lines) for supplying a display signal for determining the luminance of each pixel included in the row; and (4) a scanning signal is output to each of the plurality of first signal lines. 1 driving circuit (for example, a scanning signal driving circuit); (5) A second driving circuit (for example, a data driving circuit) that outputs a display signal to each of the plurality of second signal lines; and (6) the video data is synchronized with the horizontal synchronizing signal (for example, the horizontal scanning period described above) for each frame period. In response to the first clock signal for controlling the output of the scanning signal by the first driving circuit and the start of scanning for instructing the start of the pixel row selection step by the first clock signal. A display control circuit (for example, a timing controller) for transmitting a signal to the first drive circuit and transmitting a second clock signal to the second drive circuit together with the video data to the second drive circuit.

  In this display device, the second driving circuit is configured to generate N times of video display signals generated from one line of the video data in response to the second clock signal for each frame period (N is a natural number of 2 or more). ) And M times (M is a natural number satisfying M <N) of the blanking signal for masking the image displayed on the pixel array.

  In the display device, the first driving circuit may connect the first signal line to one end of the pixel array (for example, for each output of the N video display signals, based on the scanning signal output for each frame period). A step of sequentially selecting Y lines (Y <N / M) from the upper end of the screen toward the other end (for example, the lower end of the screen); The process of alternately selecting the first signal lines other than Y × N selected for the video display signal output from the one end to the other end of the pixel array by Z lines (Z ≧ N / M) is alternately repeated. The Y × N first signal line group and the Z × M first signal line group selected in each process sandwich another first signal line that does not belong to any of them in the pixel array. May be separated by When these signal line groups are adjacent to each other, Y × N first signal line groups and Z × M first signal line groups are arranged in this order from one end side of the pixel array. The holding time of the video display signal in the pixels corresponding to the × N first signal line groups becomes long. That is, this pixel is selected by any one of the Z × M first signal line groups from the time when the pixel is selected by any one of the Y × N first signal line groups (receives the video display signal). This is because the period until the time of receiving the ranking signal becomes longer.

  The above-described scanning start signal is a step of sequentially selecting the first signal line for each Y line at each frame period and starting the process of sequentially selecting the first signal line for each Y line from one end of the pixel array. Is determined from a second time at which the pixel array starts from one end of the pixel array. The interval between the first time in a certain frame period and the second time that follows it is defined as the second time and the next first time that follows (the selection of the first signal line for each Y line in the next frame period is By making it longer than the interval from the start time), the ratio of the time during which the pixel array holds the video display signal in one frame period (in other words, the video display period on the screen) increases, and the display luminance also increases.

  Further, at least a pair of consecutive frame periods, the interval (the timing for supplying a blanking signal to the pixel array) between the first time of the scanning start signal and the subsequent second time in each frame period is different from each other. May be. When the waveform of the scanning start signal includes a first pulse corresponding to the first time and a second pulse corresponding to the second time, at least a pair of consecutive frame periods and the first pulse and the first pulse in each frame period. The interval between the two pulses may be different from each other.

Further, according to the present invention, (a) a pixel array in which a plurality of pixel rows each including a plurality of pixels arranged along the first direction are arranged along a second direction intersecting the first direction, and (b) the plurality of pixels. A scan driving circuit for selecting each of the rows by a scanning signal; (c) a data driving circuit for supplying a display signal to each of the pixels included in at least one row selected by the scanning signals of the plurality of pixel rows; And (d) The outline of the driving method of the display device provided with the display control circuit for controlling the display operation of the pixel array is as follows.
(1) Video data is input to this display device line by line for each horizontal scanning period.
(2) By this data driving circuit, (2A) a display signal corresponding to this is sequentially generated for each line of the video data, and this display signal is output N times (N is a natural number of 2 or more) to the pixel array. (1B) and (2B) generating a display signal that makes the luminance of the pixel lower than that of the pixel in the first step (in other words, lower than the luminance before receiving the display signal in the 2B step) and this display The second step of outputting a signal to the pixel array M times (M is a natural number smaller than N) is repeated alternately.
(3) With this scan driving circuit, (3A) in the first step, the plurality of pixel rows are moved from one end to the other end of the pixel array every Y rows (Y is a natural number smaller than N / M). A first selection step for sequentially selecting along the second direction; and (3B) Z rows other than the (Y × N) rows selected in the first selection step of the plurality of pixel rows in the second step (Z Is a natural number greater than or equal to N / M), and alternately repeats the second selection step of sequentially selecting along the second direction from one end to the other end of the pixel array.

  The above-described step (2A) and step (3A), and step (2B) and step (3B) are performed substantially in parallel.

  The operation and effect of the present invention described above and details of the preferred embodiments will be apparent from the following description.

  In the method of intermittently inserting the period for inputting blanking data into the pixel array in the period for inputting video data for one frame period to the pixel array according to the present invention, one frame period (or within a period corresponding thereto) The image display by the pixel array and the blanking display are completed without impairing the luminance at the time of the image display, and the blurring of the moving image and the image quality degradation caused by this can be reduced. Further, when the present invention is applied to a liquid crystal display device, the ratio of the video display period and the blanking display period within one frame period is optimized according to the characteristics such as the liquid crystal response speed, so that the video in the pixel array It is also possible to achieve both the effect of reducing the blur of moving images that are in a trade-off relationship with the display and maintaining the display luminance.

  Hereinafter, specific embodiments of the present invention will be described with reference to the related drawings. In the drawings referred to in the following description, components having the same function are denoted by the same reference numerals, and repeated description thereof is omitted.

<< First Example >>
A first embodiment of a display device and a driving method thereof according to the present invention will be described with reference to FIGS. In this example, an active matrix type liquid crystal display panel (Active Matrix-type Liquid Crystal Display Panel) is used as a reference for a display device (liquid crystal display device) used as a pixel array (Pixels-Array). Such a structure and driving method can also be applied to a display device using an electroluminescence array or a light emitting diode array as a pixel array.

  FIG. 1 is a timing chart showing the display signal output (data driver output voltage) to the pixel array of the display device according to the present invention and the selection timing of the scanning signal line G1 in the pixel array corresponding to each. FIG. 2 is a timing chart showing video data input (input data) and video data output (driver data) timing to a display control circuit (timing controller) provided in the display device. FIG. 3 is a configuration diagram (block diagram) showing an outline of the display device according to the present embodiment in this embodiment. FIG. 9 shows an example of the details of the pixel array 101 and its periphery shown in FIG. The timing charts of FIGS. 1 and 2 described above are drawn based on the configuration of the display device (liquid crystal display device) shown in FIG. FIG. 4 is a timing chart showing another example of the display signal output (data driver output voltage) to the pixel array of the display device in this embodiment and the scanning signal line selection timing corresponding to each display signal output signal. In the output period, four scanning signal lines are selected from the scanning signal lines output from the shift register type scanning driver, and display signals are displayed on the pixel rows corresponding to these scanning signal lines. Supply. FIG. 5 shows that video data for four lines is written line by line for each of the four line memories included in the line memory circuit (Line-Memory Circuit) 105 provided in the display control circuit 104 (see FIG. 3). 6 is a timing chart showing the timing of reading out (Read-Out) from each line memory and transferring it to a data driver (video signal driving circuit). FIG. 6 relates to a display device driving method according to the present invention, and shows display timings of video data and blanking data according to the present embodiment in the pixel array, and accordingly the display device (liquid crystal display device) according to the present embodiment is shown. FIG. 7 shows the luminance response of the pixel when the) is driven (change in the light transmittance of the liquid crystal layer corresponding to the pixel).

  First, an overview of the display device 100 according to the present embodiment will be described with reference to FIG. The display device 100 includes a liquid crystal display panel (hereinafter referred to as a liquid crystal panel) having WXGA class resolution as the pixel array 101. The pixel array 101 having the resolution of the WXGA class is not limited to a liquid crystal panel, and is characterized in that 768 lines of pixel rows in which pixels of 1280 dots are arranged in the horizontal direction are arranged in parallel in the screen. The pixel array 101 of the display device in this embodiment is substantially the same as that already described with reference to FIG. 9, but because of its resolution, 768 gate lines 10 and 1280 lines are in the plane of the pixel array 101. The data lines 12 are arranged in parallel. In the pixel array 101, 983,040 pixels PIX, each of which is selected by a scanning signal transmitted by any one of the former and receives a display signal from any one of the latter, are two-dimensionally arranged. Thus, an image is generated. When the pixel array displays a color image, each pixel is divided in the horizontal direction according to the number of primary colors used for color display. For example, in a liquid crystal panel having color filters corresponding to the three primary colors of light (red, green, and blue), the number of data lines 12 is increased to 3840 lines, and the total number of pixels PIX included in the display screen is also described above. 3 times the value of.

  The liquid crystal panel used as the pixel array 101 in this embodiment will be described in more detail. Each pixel PIX included in the liquid crystal panel includes a thin film transistor (abbreviated as “Thin Film Transistor” or “TFT”) as a switching element SW. Each pixel operates in a so-called normally black-displaying mode in which the luminance increases as the display signal supplied thereto increases. In addition to the liquid crystal panel of this embodiment, the above-described electroluminescence array and light emitting diode array pixels also operate in the normally black display mode. In the liquid crystal panel operating in the normally black display mode, the pixel electrode PX sandwiched between the gradation voltage applied to the pixel electrode PX provided in the pixel PIX of FIG. 9 from the data line 12 through the switching element SW and the liquid crystal layer LC. The higher the potential difference from the counter voltage (also referred to as a reference voltage or common voltage) applied to the counter electrode CT that is opposed to, the higher the light transmittance of the liquid crystal layer LC, and the luminance of the pixel PIX. In other words, the gradation voltage, which is the display signal of the liquid crystal panel, increases the display signal as the value becomes farther from the counter voltage value.

  In the pixel array (TFT type liquid crystal panel) 101 shown in FIG. 3, the data line (signal line) 12 provided on the pixel array 101 is displayed in accordance with the display data, similarly to the pixel array 101 shown in FIG. Data driver (display signal drive circuit) 102 for providing a signal (gray scale voltage, gray scale voltage, or tone voltage) and scanning for applying a scanning signal (voltage signal) to a gate line (scanning line) 10 provided on the data driver (display signal driving circuit) 102 Drivers (scanning signal drive circuits) 103-1, 103-2, and 103-3 are provided, respectively. In this embodiment, the scan driver is divided into three along the so-called vertical direction of the pixel array 101. However, the number of the scan drivers is not limited to this, and may be replaced with one scan driver in which these functions are integrated. .

  A display control circuit (timing controller) 104 is a timing signal (data driver control) for controlling the display data (driver data) 106 and the display signal output corresponding to the display data (driver data) 106 to the data driver 102. A signal (Data Driver Control Signal) 107 is transferred to each of the scanning drivers 103-1, 103-2, and 103-3 as a scanning clock signal 112 and a scanning start signal 113, respectively. The scan control circuit 104 also provides the scan drivers 103-1, 103-2, and 103-3 with scan-condition selecting signals (Scan-Condition Selecting Signals) 114-1, 114-2, and 114-3, respectively. The function will be described later. The scanning state selection signal is also referred to as a display-operation selecting signal because of its function.

  The display control circuit 104 receives video data (video signal) 120 and a video control signal 121 input thereto from a video signal source external to the display device 100 such as a television receiver, personal computer, DVD player or the like. A memory circuit for temporarily storing the video data 120 is provided in or around the display control circuit 104. In this embodiment, the line memory circuit 105 is built in the display control circuit 104. The video control signal 121 includes a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, a dot clock signal DOTCLK, and a display timing signal that control the transmission state of the video data. (Display Timing Signal) Includes DTMG. Video data that causes the display device 100 to generate one screen image is input to the display control circuit 104 in response to (in synchronization with) the vertical synchronization signal VSYNC. In other words, the video data is sequentially input from the video signal source to the display device 100 (display control circuit 104) every cycle defined by the vertical synchronization signal VSYNC (also referred to as a vertical scanning period or a frame period). One screen image is replaced and displayed on the pixel array 101 every time. Video data in one frame period is sequentially input to a display device by dividing a plurality of line data (Line Data) included in the frame data into periods (also referred to as horizontal scanning periods) defined by the horizontal synchronization signal HSYNC. . In other words, each piece of video data input to the display device for each frame period includes a plurality of line data, and the generated one-screen video is scanned horizontally in the horizontal direction according to each line data. It is generated by sequentially arranging in the vertical direction for each period. Data corresponding to each pixel arranged in the horizontal direction of one screen is identified with a period defined by the dot clock signal for each of the line data.

  Since the video data 120 and the video control signal 121 are also input to a display device using a cathode ray tube, the electron beam is swept from the scanning end position to the scanning start position every horizontal scanning period and every frame period. It takes time to do. Since this time becomes a dead time in transmission of video information, an area called a retrace period that does not contribute to transmission of video information corresponding to this time is also provided in the video data 120. In the video data 120, an area corresponding to this blanking period is identified from other areas contributing to transmission of video information by the display timing signal DTMG.

  On the other hand, the active matrix type display device 100 described in the present embodiment generates display signals for one line of video data (the above-mentioned line data) by the data driver 102, and these are generated as scanning drivers. In response to the selection of the gate line 10 by 103, the data is simultaneously output to a plurality of data lines (signal lines) 12 arranged in parallel in the pixel array 101. Therefore, theoretically, the input of the line data to the pixel row is continued from the horizontal scanning period to the next horizontal scanning period without interposing the blanking period, and the pixel array of the video data from the frame period to the next frame period. The input to continues. For this reason, in the display device 100 of this embodiment, the display control circuit 104 reads out one line of video data (line data) from the memory circuit (line memory) 105 for the horizontal scanning period (1). This is performed in accordance with the cycle generated by shortening the blanking period included in the video data for the line). Since this cycle is also reflected in the output interval of the display signal to the pixel array 101, which will be described later, hereinafter, it will be referred to as a horizontal period or simply a horizontal period of the pixel array operation. The display control circuit 104 generates a horizontal clock CL1 that defines this horizontal period, and transfers it to the data driver 102 as one of the data driver control signals 107 described above. In this embodiment, the time for reading video data from the memory circuit 105 (the above horizontal period) is shortened with respect to the time for storing video data for one line in the memory circuit 105 (the above horizontal scanning period). A time for inputting a blanking signal to the pixel array 101 is calculated every frame period.

  FIG. 2 is a timing chart showing an example of video data input (storage) to the memory circuit 105 by the display control circuit 104 and output (readout) from this. As shown in the waveform of the input data, the video data input to the display device every frame period defined by the pulse interval of the vertical synchronization signal VSYNC includes a plurality of line data (one line video data). .. Including the retrace period for each of L1, L2, L3,..., And sequentially input to the memory circuit 105 by the display control circuit 104 in response to (synchronously with) the horizontal synchronization signal HSYNC. The display control circuit 104 sequentially reads the line data L1, L2, L3,... Stored in the memory circuit 105 in accordance with the horizontal clock CL1 or a timing signal similar thereto as shown in the waveform of the output data. At this time, the line data L1, L2, L3,... Input to the memory circuit 105 during the blanking period separating the line data L1, L2, L3,. It is shortened along the time axis than that separating each of the. Therefore, a period required to input N times (N is a natural number of 2 or more) line data to the memory circuit 105 and a period required to output these line data from the memory circuit 105 (N line data). In the output period, there is a time during which the line data can be output from the memory circuit 105 M times (M is a natural number smaller than N). In this embodiment, the video data for the M lines is output from the memory circuit 105, so that the pixel array 101 performs another display operation in a surplus time.

  Since the video data (in FIG. 2, the line data included therein) is temporarily stored in the memory circuit 105 before being transferred to the data driver 102, a delay time corresponding to the storage period is provided. Then, the data is read by the display control circuit 104. When a frame memory is used as the memory circuit 105, this delay time corresponds to one frame period. When the video data is input to the display device at a frequency of 30 Hz, the one frame period is about 33 ms (milliseconds), so the user of the display device can display the image with respect to the input time of the video data to the display device. I can't perceive the delay. However, by providing the display device 100 with a plurality of line memories in place of the frame memory as the memory circuit 105 described above, the delay time can be reduced and the display control circuit 104 or its peripheral circuit structure can be simplified or An increase in dimensions can be suppressed.

  An example of a method for driving the display device 100 using a line memory storing a plurality of line data as the memory circuit 105 will be described with reference to FIG. In the driving of the display device 100 according to this example, the video data input period for the N lines to the display control circuit 104 and the video data output period for the next N lines (display signals corresponding to the video data of the N lines are displayed as data. Display signal that masks the display signal already stored in the pixel array (video data input to the pixel array in the previous frame period) during the surplus time that occurs during the period of time that is output sequentially from the driver 102) (Hereinafter, referred to as a blanking signal) is written M times. In the driving method of the display device 100, a display signal is sequentially generated from each of N lines of video data by the data driver 102, and is sequentially output to the pixel array 101 in response to the horizontal clock CL1 (N times in total). The first step and the second step of outputting the above blanking signal to the pixel array 101 M times in response to the horizontal clock CL1 are repeated. Further explanation of the driving method of this display device will be described later with reference to FIG. 1. In FIG. 5, the value of N is 4 and the value of M is 1.

  As shown in FIG. 5, the memory circuit 105 includes four line memories 1 to 4 that can write and read data independently of each other, and are sequentially input to the display device 100 in synchronization with the horizontal synchronization signal HSYNC. The video data 120 for each line is sequentially stored in one of these line memories 1 to 4. In other words, the memory circuit 105 has a memory capacity for four lines. For example, in the acquisition period Tin of four lines of video data 120 by the memory circuit 105, four lines of video data W1, W2, W3, and W4 are sequentially input from the line memory 1 to the line memory 4. The This video data acquisition period Tin covers a time corresponding to four times the horizontal scanning period defined by the pulse interval of the horizontal synchronization signal HSYNC included in the video control signal 121. However, the video data stored in the line memory 1, the line memory 2, and the line memory 3 during this period before the video data acquisition period Tin ends by storing the video data in the line memory 4. Are sequentially read out by the display control circuit 104 as video data R1, R2, and R3. As a result, as soon as the acquisition period Tin of the video data W1, W2, W3, and W4 for four lines ends, the video data W5, W6, W7, and W8 for the next four lines to the line memories 1 to 4 are stored. Storage can begin.

  In the above description, the reference code attached to each line of the video data is changed from, for example, the former W1 to the latter R1 at the time of input to the line memory and at the time of output from the line memory. This is because the video data for each line includes the above-described blanking period, and this is in response to (in synchronization with) the horizontal clock CL1 having a frequency higher than the horizontal synchronization signal HSYNC from any of the line memories 1 to 4. When read out, this reflects that the blanking period included therein is shortened. Therefore, for example, compared to the length along the time axis of one line of video data (hereinafter referred to as line data) W1 input to the line memory 1, the line data when this is output from the line memory 1 The length along the time axis of R1 is short as shown in FIG. Processes video information contained in this line data (for example, generates one line of video along the horizontal direction of the screen) during the period from the input of line data to the line memory to the output of the line data. Even if not, the length along the time axis is compressed as described above. Therefore, the output end time of the four lines of video data R1, R2, R3, R4 from the line memories 1 to 4 and the output of the four lines of video data R5, R6, R7, R8 from the line memories 1 to 4 are output. The surplus time Tex described above occurs between the start time and the start time.

  The four lines of video data R1, R2, R3, R4 read from the line memories 1 to 4 are transferred to the data driver 102 as driver data 106, and display signals L1, L2, L3, L4 is generated (display signals L5, L6, L7, and L8 are generated in the same manner for the four lines of video data R5, R6, R7, and R8 to be read next). These display signals are respectively output to the pixel array 101 in response to the horizontal clock CL1 in the order shown in the eye diagram of the display signal output of FIG. Accordingly, by including at least the line memory (or an aggregate thereof) having the capacity of N lines in the memory circuit 105, one line of video data input to the display device in a certain frame period can be transferred to this frame period. It is possible to input to the pixel array within the display, and the response speed of the display device to the video data input is also increased.

  On the other hand, as is apparent from FIG. 5, the above-described surplus time Tex corresponds to a time for outputting one line of video data from the line memory in response to the above-described horizontal clock CL1. In this embodiment, another display signal is output to the pixel array once using this surplus time Tex. Another display signal according to the present embodiment is a so-called blanking signal B that lowers the luminance of the pixel to which it is supplied below the luminance before the supply. For example, the brightness of a pixel displayed with a relatively high gradation (white in the case of monochrome image display or light gray close to this) before one frame period is lowered by the blanking signal B. On the other hand, the luminance of pixels displayed in a relatively low gradation (black or dark gray such as Charcoal Gray close to this in the case of monochrome image display) before one frame period is almost the same after the blanking signal B is input. It does n’t change. The blanking signal B temporarily replaces the image generated in the pixel array every frame period with a dark image (blanking image). By such a display operation of the pixel array, even in the hold type display device, an image display corresponding to the video data inputted to each frame period can be performed as in the impulse type display device.

  A hold-type display device has a driving method for a display device that repeats the first step of sequentially outputting the N-line video data to the pixel array and the second step of outputting the blanking signal B to the pixel array M times. By applying, image display by this hold type display device can be performed like an impulse type display device. The display device driving method is not limited to the display device having the line memory having the capacity of at least N lines described with reference to FIG. 5 as the memory circuit 105. The present invention can also be applied to a display device replaced with a memory.

  A method of driving such a display device will be further described with reference to FIG. The operation of the display device according to the first and second steps described above defines the output of the display signal by the data driver 102 in the display device 100 of FIG. 3, but the output of the scan signal by the scan driver 103 corresponding thereto ( The selection of the pixel row is described as follows. In the following description, a “scanning signal” applied to the gate line (scanning signal line) 10 and selecting a pixel row corresponding to the gate line (a plurality of pixels PIX arranged along the gate line) is shown in FIG. A scanning signal pulse (gate pulse) in which the scanning signal applied to each of the gate lines G1, G2, G3,. In the pixel array as shown in FIG. 9, the switching element SW provided in the pixel PIX receives a gate pulse through the gate line 10 connected to the switching element SW, so that the display signal supplied from the data line 12 is received. This pixel PIX is input.

In the period corresponding to the first step described above, every time a display signal corresponding to video data of N lines is output, a scanning signal for selecting a corresponding pixel row is applied to the Y line of the gate line. Accordingly, the scanning signal is output N times from the scanning driver 103. The scanning signal is applied from one end (for example, the upper end in FIG. 3) of the pixel array 101 to the other end (for example, the lower end in FIG. 3) every Y lines of the gate lines every time the display signal is output. It is done sequentially. Therefore, in the first step, pixel rows corresponding to (Y × N) gate lines are selected, and a display signal generated from the video data is supplied to each of the pixel rows. FIG. 1 shows the display signal output timing (refer to the eye diagram of the data driver output voltage) when the value of N is 4 and the value of Y is 1, and the corresponding gate lines (scanning lines). The period of the first step corresponds to each of the data driver output voltages 1 to 4, 5 to 8, 9 to 12,..., 513 to 516,. Scan signals are sequentially applied to the G1 to G4 gate lines for the data driver output voltages 1 to 4, and scan signals are sequentially applied to the G5 to G8 gate lines for the next data driver output voltages 5 to 8. The scanning signals are sequentially applied to the gate lines from G513 to G516 with respect to the data driver output voltages 513 to 516 after a further time has elapsed. That is, the scanning signal output from the scanning driver 103 increases the address numbers (G1, G2, G3,..., G257, G258, G259,..., G513, G514, G515,...) Of the gate array 10 in the pixel array 101. It is performed sequentially.

  On the other hand, in the period corresponding to the second step, a scanning signal for selecting the corresponding pixel row is applied to the Z line of the gate line for every M outputs of the display signal described above as a blanking signal. The Accordingly, the scanning signal is output M times from the scanning driver 103. The combination of gate lines (scanning lines) to which the scanning signal is applied for one output of the scanning signal from the scanning driver 103 is not particularly limited, but the display signal supplied to the pixel row in the first process is not limited. In view of maintaining this for a long time and reducing the load applied to the data driver 102, the scanning signal may be sequentially applied every Z line of the gate line for every output of the display signal. The application of the scanning signal to the gate line in the second process is sequentially performed from one end of the pixel array 101 to the other end in the same manner as in the first process. Therefore, in the second step, pixel rows corresponding to (Z × M) line gate lines are selected, and a blanking signal is supplied to each of them. FIG. 1 shows the output timing of the blanking signal B in each of the second steps following the first step when the value of M is 1 and the value of Z is 4, and the gate line corresponding thereto. The waveform of the scanning signal applied to each (scanning line) is shown. In the second step following the first step in which scanning signals are sequentially applied to the gate lines G1 to G4, the scanning signals are applied to the four gate lines from G257 to G260 for one blanking signal B output. However, in the second step following the first step in which scanning signals are sequentially applied to the gate lines G5 to G8, four gate lines from G261 to G264 are output for one blanking signal B output. In the second step following the first step in which scanning signals are sequentially applied to the gate lines G513 to G516, four lines from G1 to G4 are output for one blanking signal B output. A scanning signal is applied to each of the gate lines.

  As described above, the scan signal is sequentially applied to each of the four gate lines in the first step, and the scan signal is simultaneously applied to the four gate lines in the second step. In response to the display signal output, it is necessary to adjust the operation of the scan driver 103 to each process. As described above, the pixel array used in this embodiment has a resolution of the WXGA class, and 768 gate lines are arranged in parallel therewith. On the other hand, the four gate line groups (for example, G1 to G4) sequentially selected in the first process and the four gate line groups (for example, G257 to G260) selected in the second process following the first process are In the pixel array 101, the gate lines 10 are separated by 252 gate lines along the direction in which the address numbers increase. Therefore, the 768 gate lines arranged in parallel in the pixel array are divided into three groups every 256 lines along the vertical direction (or the extending direction of the data lines). The scanning signal output operation is controlled independently. For this reason, in the display device shown in FIG. 3, three scanning drivers 103-1, 103-2, 103-3 are arranged along the pixel array 101, and the scanning signal output operation from each of them is performed as the scanning state selection signal 114-. Control by 1, 114-2, 114-3. For example, when the gate lines G1 to G4 are selected in the first process and the gate lines G257 to G260 are selected in the second process, the scanning state selection signal 114-1 sends the scanning clock to the scanning driver 103-1. A scanning state in which a scanning signal output for sequentially selecting gate lines for four consecutive pulses of CL3 one line at a time and an output pause of the scanning signal for one pulse of the scanning clock CL3 is designated is designated. On the other hand, the scanning state selection signal 114-2 causes the scanning driver 103-2 to stop outputting the scanning signal with respect to four consecutive pulses of the scanning clock CL3, and then to the four gate lines with respect to one pulse of the scanning clock CL3. A scanning state in which scanning signal output is repeated is designated. Further, the scanning state selection signal 114-3 invalidates the scanning clock CL3 input to the scanning driver 103-3, and thereby stops the scanning signal output. Each of the scanning drivers 103-1, 103-2, 103-3 includes two control signal transmission networks corresponding to the above-described two instructions by the scanning state selection signals 114-1, 114-2, 114-3. It is done.

  On the other hand, the waveform of the scanning start signal FLM shown in FIG. 1 includes two pulses that rise at times t1 and t2, respectively. A series of gate line selection operations in the first step is performed in response to a pulse of the scanning start signal FLM generated at time t1 (hereinafter referred to as Pulse 1; hereinafter referred to as a first pulse). The selection operation is started in response to a pulse of the scanning start signal FLM that occurs at time t2 (hereinafter referred to as Pulse 2; hereinafter referred to as a second pulse). The first pulse of the scanning start signal FLM also corresponds to the start of input of video data for one frame period to the display device (specified by the pulse of the vertical synchronization signal VSYNC). Accordingly, the first pulse and the second pulse of the scanning start signal FLM are repeatedly generated every frame period. Further, adjusting the interval between the first pulse of the scanning start signal FLM and the second pulse that follows the first pulse, and the interval between the second pulse and the following (for example, the first pulse in the next frame period). Thus, the time for holding the display signal based on the video data in the pixel array in one frame period can be adjusted. In other words, the pulse interval including the first pulse and the second pulse generated in the scanning start signal FLM can take two different values (time widths) alternately. On the other hand, the scanning start signal FLM is generated by a display control circuit (timing controller) 104. From the above, the scanning state selection signals 114-1, 114-2, 114-3 can be generated in the display control circuit 104 with reference to the scanning start signal FLM.

  The operation of writing the blanking signal once in the pixel array every time the video data shown in FIG. 1 is written into the pixel array four times for each line, as described with reference to FIG. Complete in time to enter data into the display. In response to this, the scanning signal is output to the pixel array five times. Therefore, the horizontal period required for the operation of the pixel array is 4/5 of the horizontal scanning period of the video control signal 121. In this manner, the input of the video data (display signal based on this) input to the display device in one frame period and the blanking signal to all the pixels in the pixel array is completed in this one frame period.

  The blanking signal shown in FIG. 1 generates pseudo video data (hereinafter referred to as blanking data) in the display control circuit 104 or its peripheral circuit, and transfers this to the data driver 102 to provide a data driver. Even if it is generated in 102, a circuit for generating a blanking signal in advance in the data driver 102 is provided, and the blanking signal is supplied to the pixel array 101 in accordance with a specific pulse of the horizontal clock CL1 transferred from the display control circuit 104. It may be output. In the former case, a frame memory is provided in the display control circuit 104 or the periphery thereof, and a pixel for which a blanking signal is to be strengthened from the video data for each frame period stored therein (pixel displayed with high luminance by this video data) May be specified by the display control circuit 104, and blanking data may be generated that causes the data driver 102 to generate a blanking signal having different darkness depending on the pixel. In the latter case, the data driver 102 counts the number of pulses of the horizontal clock CL1, and in accordance with the counted number, the pixel is displayed in black or a dark color close thereto (for example, a color such as Charcoal Gray). Output a signal. In some liquid crystal display devices, a display control circuit (timing converter) 104 generates a plurality of gradation voltages that determine the luminance of a pixel. In such a liquid crystal display device, a plurality of gradation voltages are transferred by the data driver 102, and the gradation voltage corresponding to the video data is selected by the data driver 102 and output to the pixel array. Thus, the blanking signal may be generated by selecting the gradation voltage according to the pulse of the horizontal clock CL1 by the data driver 102.

  The display signal output method (Outputting Manner) to the pixel array according to the present invention shown in FIG. 1 and the scanning signal output method to each gate line (scan line) corresponding to the method are as follows. This is suitable for driving a display device including a scanning driver 103 having a function of simultaneously outputting scanning signals to a plurality of gate lines in accordance with the signal 114. On the other hand, each of the scanning drivers 103-1, 103-2, and 103-3 does not simultaneously output scanning signals to a plurality of scanning lines as described above, and one gate line (scanning line) is output for each pulse of the scanning clock CL3. Even if scanning signals are sequentially output for each line, the image display operation according to this embodiment can be performed. With this operation of the scan driver 103, 4 lines of video data are sequentially input to one of the pixel rows line by line (the first step in which the video data is output four times), and the blanking data is separated. The image display operation of this embodiment, which repeats the input to the four pixel rows (the first step in which the blanking data is output once), is performed in the display signal and the scanning signal shown in FIG. The output waveform is described below.

  The display device driving method described with reference to FIG. 4 refers to the display device shown in FIG. 3 as in FIG. Each of the scanning drivers 103-1, 103-2, and 103-3 includes 256 terminals that output scanning signals. In other words, each scanning driver 103 can output a scanning signal to a maximum of 256 gate lines. On the other hand, the pixel array 101 (for example, a liquid crystal display panel) is provided with 768 gate lines 10 and corresponding pixel rows. For this reason, the three scanning drivers 103-1, 103-2, and 103-3 are sequentially arranged on one side along the vertical direction of the pixel array 101 (the extending direction of the data line 12 provided thereon). The scanning driver 103-1 outputs scanning signals to the gate line groups G1 to G256, the scanning driver 103-2 outputs to the gate line groups G257 to G512, and the scanning driver 103-3 outputs the scanning signals to the gate line groups G513 to G768, respectively. The image display on 100 full screens (the entire area of the pixel array 101) is controlled. The display device to which the driving method described with reference to FIG. 1 is applied and the display device to which the driving method described below with reference to FIG. 4 are applied share the above scan driver arrangement. To do. The waveform of the scanning start signal FLM is a first pulse for starting a series of scanning signal outputs for inputting video data to the pixel array, and a second pulse for starting a series of scanning signal outputs for inputting blanking data to the pixel array. 1 for each frame period, the driving method of the display device described with reference to FIG. 1 and that described with reference to FIG. 4 are common. Further, the scanning driver 103 takes in each of the first pulse and the second pulse of the scanning start signal FLM with the scanning clock CL3, and then outputs a terminal (or terminal group) to which the scanning signal is output in response to the scanning clock CL3. The display device driving method based on the signal waveform of FIG. 1 and the signal waveform of FIG. 4 are common even if the video data or blanking data is sequentially shifted in accordance with the acquisition to the pixel array.

  However, in the driving method of the display device of the present embodiment described with reference to FIG. 4, the roles of the scanning state selection signals 114-1, 114-2, 114-3 are those described with reference to FIG. And different. FIG. 4 shows the waveforms of the scanning state selection signals 114-1, 114-2, and 114-3 as DISP1, DISP2, and DISP3. First, the scanning state selection signal 114 is determined based on the operating condition applied to the region controlled by each of the scanning state selection signals (for example, in the case of DISP2, the pixel group corresponding to the gate line group G257 to G512). Determine the output behavior. In FIG. 4, during the period in which the data driver output voltage indicates the output of the display signals L513 to L516 corresponding to the four lines of video data (the first step in which the display signals L513 to L516 are output), these display signals are displayed. A scanning signal is applied from the scanning driver 103-3 to the gate lines G513 to G516 corresponding to the input pixel row. For this reason, the scanning state selection signal 114-3 transferred to the scanning driver 103-3 is sequentially applied to each of the gate lines G513 to G516 in response to the scanning clock CL3 (for each gate pulse output). A so-called gate line selection for each line for outputting a scanning signal is performed. As a result, the display signal L513 is displayed on the pixel row corresponding to the gate line G513, the display signal L514 is displayed on the pixel row corresponding to the gate line G514, the display signal L515 is displayed on the pixel row corresponding to the gate line G515, and finally the gate line. The display signal L516 is supplied to the pixel row corresponding to G516 for one horizontal period (defined by the pulse interval of the horizontal clock CL1).

  On the other hand, in the second step subsequent to the first step in which the display signals L513 to L516 are sequentially output every horizontal period (in response to the pulse of the horizontal clock CL1), the four horizontal periods corresponding to the first step are displayed. The blanking signal B is output in the subsequent one horizontal period. In this embodiment, the blanking signal B output between the display signal L516 output and the display signal L517 output is supplied to each of the pixel rows corresponding to the gate line groups G5 to G8. For this reason, the scanning driver 103-1 must perform so-called four-line simultaneous gate line selection in which the scanning signal is applied to all four lines of the gate lines G5 to G8 during the output period of the blanking signal B. However, in the display operation of the pixel array according to FIG. 4, as described above, the scan driver 103 applies the scan signal to only one gate line in response to the scan clock CL3 (for one pulse). The scanning signal application is not started to the plurality of gate lines. In other words, the scan driver 103 does not simultaneously raise scan signal pulses for a plurality of gate lines.

  For this reason, the scanning state selection signal 114-1 transferred to the scanning driver 103-1 is scanned before the blanking signal B is output to at least the (Z-1) line of the Z line of the gate line to which the scanning signal is applied. The scan driver 103-1 is controlled so that the signal is applied and the application time of the scan signal (pulse width of the scan signal) is extended to at least N times the horizontal period. These variables Z and N are the number of gate lines selected in the first step of writing the above-mentioned video data to the pixel array and the second step of writing blanking data to the pixel array as described in the second step: Z, and Number of display signal outputs in the first step: N. For example, from the output start time of the display signal L514 to the gate line G5, from the output start time of the display signal L515 to the gate line G6, from the output start time of the display signal L516 to the gate line G7, and to the gate line G8 The scanning signals are respectively applied over a period five times the horizontal period from the output end time of the signal L516 (subsequent blanking signal B output start time). In other words, the rise times of the gate pulses of the gate line groups G5 to G8 by the scan driver 103 are sequentially shifted every horizontal period in response to the scan clock CL3. By delaying the falling time after the N horizontal period of the rising time, all the gate pulses of the gate line groups G5 to G8 are raised (high in FIG. 4) during the blanking signal output period. Thus, in controlling the output of the gate pulse, it is desirable that the scan driver 103 includes a shift register operation function. The hatching area indicated by the gate pulse of the gate lines G1 to G12 to which the blanking signal is supplied to the corresponding pixel row will be described later.

  On the other hand, each of the gate line groups G257 to G512 that receive the scanning signal from the scanning driver 103-2 during this period (the first process in which the display signals L513 to L516 are output) and the subsequent second process. A display signal is not supplied to the pixel row corresponding to. For this reason, the scanning state selection signal 114-2 transferred to the scanning driver 103-2 disables the scanning clock CL3 with respect to the scanning driver 103-2 during the period of the first step and the second step. the Scanning Driver 103-2). Such invalidation of the scanning clock CL3 by the scanning state selection signal 114 is predetermined even when a display signal or a blanking signal is supplied to a pixel group in a region where the scanning signal is output from the scanning driver 103 to which the scanning clock CL3 is transferred. You may apply at the timing. FIG. 4 shows the waveform of the scan clock CL3 corresponding to the scan signal output from the scan driver 103-1. The pulse of the scanning clock CL3 is generated in response to the pulse of the horizontal clock CL1 that defines the output interval of the display signal and the blanking signal, but no pulse is generated at the output start time of the display signals L513, L517,. In this way, an operation of invalidating the scanning clock CL3 transferred from the display control circuit 104 to the scanning driver 103 at a specific time can be performed by the scanning state selection signal 114. Partial invalidation of the scan clock CL3 for the scan driver 103 starts by incorporating a signal processing path corresponding to the scan driver 103 into the scan driver 103, and starts the operation of this signal processing path with the scan state selection signal 114 transferred to the scan driver 103. You may let them. Although not shown in FIG. 4, the scan driver 103-3 that controls the writing of the video data to the pixel array is also insensitive to the scan clock CL3 at the output start time of the blanking signal B. Accordingly, it is possible to prevent the scanning driver 103-3 from erroneously supplying the blanking signal to the pixel row to which the display signal based on the video data is supplied in the first process following the second process by the output of the blanking signal B.

  Next, the scanning state selection signal 114 invalidates the pulse (gate pulse) of the scanning signal sequentially generated in the region controlled by each of the scanning state selection signals 114 when it is output to the gate line. This function involves the scanning state selection signal 114 transferred to the signal processing in the scanning driver 103 that supplies the blanking signal to the pixel array in the driving method of the display device according to FIG. The three waveforms DISP1, DISP2, and DISP3 shown in FIG. 4 are scanning state selection signals 114-1, 114-2, 114-2, 103-2, and 103-3 that are involved in signal processing inside the scanning drivers 103-1, 103-2, and 103-3, respectively. Shows 114-3 and enables gate pulse output when it is at low-level. Further, the waveform DISP1 of the scanning state selection signal 114-1 becomes High-level during the display signal output period to the pixel array in the first step described above, and the gate pulse generated by the scanning driver 103-1 within this period. Disable output of.

  For example, the gate pulse generated in the scanning signal corresponding to each of the gate lines G1 to G7 in the four horizontal periods when the display signals L513 to L516 are supplied to the pixel array is the scanning state selection signal DISP1 that becomes High-level in this period. Thus, each output is invalidated as if hatched. This prevents a display signal based on video data from being erroneously supplied to a pixel row to which a blanking signal should be supplied in a certain period, and blanking display by these pixel rows (displayed in these pixel rows). Erasure of the displayed video), and the loss of the intensity of the display signal itself due to the video data is prevented. Further, in one horizontal period in which the blanking signal B is output between the four horizontal periods in which the display signals L513 to L516 are output and the next four horizontal periods in which the display signals L517 to L520 are output, the scanning state selection signal DISP1 is Low-level. As a result, the gate pulses generated in the scanning signals corresponding to the gate lines G5 to G8 during this period are simultaneously output to the pixel array, and the pixel rows corresponding to the four lines of gate lines are selected at the same time. A blanking signal B is supplied to each.

  As described above, in the display operation of the display device according to FIG. 4, the operation state of the scan driver 103 to which this is transferred by the scan state selection signal 114 (the operation state according to one of the first step and the second step, or In addition, the effectiveness of the output of the gate pulse generated by the scan driver 103 is determined according to the operation state. Note that a series of control of the scan driver 103 (future scan signal output) by these scan state selection signals 114 starts scanning for both display signal writing and blanking signal writing based on video data to the pixel array. In response to the signal FLM, the scanning signal output to the gate line G1 is started. FIG. 4 mainly shows a gate line line selection operation (four-line simultaneous selection operation) by the scan driver 103 that sequentially shifts by the scanning state selection signal DISP1 in response to the second pulse of the scanning start signal FLM. Although not shown in FIG. 4, in the operation of the display device according to this, the selection operation for each gate line by the scan driver 103 is also sequentially shifted in response to the first pulse of the scan start signal FLM. For this reason, even in the operation of the display device in FIG. 4, it is necessary to start scanning of the two types of pixel arrays once for each frame period using the scan start signal FLM. The waveform of the scan start signal FLM includes the first pulse and this. And a second pulse appears.

  1 and 4 described above, the number of scanning drivers 103 arranged along one side of the pixel array 101 and the number of scanning state selection signals 114 sent thereto are the same as those shown in FIGS. The pixel array 101 can be changed without changing the structure of the pixel array 101 described with reference, and the functions assigned to the three scan drivers 103 may be combined into one scan driver 103 (for example, the inside of the scan driver 103 may be integrated). The circuit sections are divided according to the three scanning drivers 103-1, 103-2, and 103-3).

  FIG. 6 is a timing chart showing the image display timing by the display device of this embodiment over three consecutive frame periods. At the beginning of each frame period, video data writing from the first scanning line (corresponding to the gate line G1) to the pixel array is started by the first pulse of the scanning start signal FLM. After the elapse, blanking data writing from the first scanning line to the pixel array is started by the second pulse of the scanning start signal FLM. Further, after time: Δt2 has elapsed from the time of generation of the second pulse of the scanning start signal FLM, the writing of the video data input to the display device to the display device in the next frame period is the first pulse of the scanning start signal FLM. Is started. In this embodiment, the time: Δt1 ′ shown in FIG. 6 is the same as the time: Δt1, and the time: Δt2 ′ is the same as the time: Δt2. The progress of video data writing to the pixel array and that of blanking data writing are different in the number of gate lines (the former one line and the latter four lines) selected in one horizontal period, but over time. The process proceeds in a similar manner. For this reason, regardless of the position of the scanning line in the pixel array, the pixel row corresponding to each of the pixels holds a display signal based on video data (including the time for receiving this), and the time period is approximately Δt1. The period during which the pixel row holds the blanking signal (approximately the above time including the time for receiving the blanking signal: Δt2) is substantially uniform in the vertical direction of the pixel array. In other words, variation in display luminance between pixel rows (along the vertical direction) in the pixel array can be suppressed. In this embodiment, as shown in FIG. 6, 67% and 33% of one frame period are assigned to the display period of video data and the display period of blanking data in the pixel array, respectively, and scanning starts accordingly. Although the timing of the signal FLM is adjusted (the time Δt1 and Δt2 are adjusted), the display period of the video data and the display period of the blanking data can be appropriately changed by changing the timing of the scanning start signal FLM.

  An example of the luminance response of the pixel row when the display device is operated at such an image display timing according to FIG. 6 is shown in FIG. This luminance response is obtained by using a liquid crystal display panel having a WXGA class resolution and operating in a normally black display mode as the pixel array 101 in FIG. Display off data for displaying pixel rows in black is written as data. Therefore, the luminance response of FIG. 7 shows the fluctuation of the light transmittance of the liquid crystal layer corresponding to the pixel row of the liquid crystal display panel. As shown in FIG. 7, the pixel row (each pixel included therein) responds to the luminance according to the video data first in one frame period, and then responds to the black luminance. Although the light transmittance of the liquid crystal layer responds relatively loosely to the fluctuation of the electric field applied thereto, the value thereof is the electric field and blanking data corresponding to the video data for each frame period as is apparent from FIG. Fully responds to any of the electric fields corresponding to. Therefore, the image based on the video data generated on the screen (pixel row) in the frame period is displayed in the same state as the impulse-type display device after the image is sufficiently erased from the screen (pixel row) in the frame period. Is done. Due to such an impulse response of an image based on video data, it is possible to reduce motion blur caused by the response. Such an effect can be obtained even when the resolution of the pixel array is changed or the ratio of the blanking period in the horizontal period of the driver data shown in FIG. 2 is changed.

  In the present embodiment described above, the display signal generated for each line of the video data in the first step described above is sequentially output to the pixel array four times, and each of them is a pixel row corresponding to one line of the gate line. In a second step following this, a blanking signal is sequentially output once to the pixel array and supplied to pixel rows corresponding to four lines of gate lines. However, the number of display signal outputs in the first step: N (this value also corresponds to the number of line data written in the pixel array) is not limited to four, and the number of blanking signal outputs in the second step: M is not limited to 1. In addition, the number of gate lines to which a scanning signal (selection pulse) is applied for one display signal output in the first step: Y is not limited to 1, and one blanking signal in the second step. The number of gate lines Z to which the scanning signal is applied to the output: Z is not limited to four. It is required that these factors N and M are natural numbers that satisfy the condition of M <N and that N is 2 or more. The factor Y is required to be a natural number smaller than N / M, and the factor Z is required to be a natural number equal to or greater than N / M. In addition, one cycle of outputting N display signals and outputting M blanking signals is completed within a period in which video data of N lines is input to the display device. In other words, the value (N + M) times the horizontal period in the operation of the pixel array is set to be equal to or less than the value N times the horizontal scanning period when the video data is input to the display device. The former horizontal period is defined by the pulse interval of the horizontal clock CL1, and the latter horizontal scanning period is defined by the pulse interval of the horizontal synchronization signal HSYNC which is one of the video control signals.

  According to the operation conditions of such a pixel array, (N + M) times of signal output from the data driver 102 during the period Tin during which video data of N lines is input to the display device, that is, the first step described above and the subsequent steps. A one-cycle pixel array operation consisting of the second step is performed. Therefore, the time allocated to each of the display signal output and the blanking signal output in this one cycle (hereinafter, Tinvention) is one time when the display signal corresponding to the video data of N lines is sequentially output in the period Tin. (N / (N + M)) times the time required for signal output (hereinafter referred to as Tprior). However, as described above, since the factor M is a natural number smaller than N, the output period Tinvention of each signal in the one period according to the present invention can ensure a length of 1/2 or more of the Tprior. That is, from the viewpoint of writing video data to the pixel array, advantages of the technique described in the above-mentioned SID 01 Digest, pages 994-997 over the technique described in the above-mentioned JP-A-2001-166280 can be obtained. .

  Further, in the present invention, the blanking signal is supplied to the pixel in the period Tinvention, so that the luminance of the pixel is quickly reduced. Therefore, compared to the technique described in SID 01 Digest, pages 994-997, according to the present invention, the video display period and the blanking display period of each pixel row in one frame period are clearly separated, and the motion blur Is also efficiently reduced. In the present invention, the blanking signal is intermittently supplied to the pixels every (N + M) times. However, this is supplied to the pixel row corresponding to the Z-line gate line for one blanking signal output. This suppresses variation in the ratio between the video display period and the blanking display period that occurs between pixel rows. Furthermore, if a scanning signal is sequentially applied to every Z line of the gate line for every blanking signal output, this blanking signal is also supplied to the load for one output of the blanking signal from the data driver 102. This is reduced by limiting the number of pixel rows.

  Therefore, the driving of the display device according to the present invention is not limited to the above-described example in which N is 4, M is 1, Y is 1 and Z is 4 described with reference to FIGS. As long as it is satisfied, the present invention can be generally applied to driving of a hold-type display device in general. For example, when video data is input to the display device in odd-numbered lines or even-numbered lines for each frame period in an interlaced manner, the video signal of odd-numbered lines or even-numbered lines is scanned by 2 gate lines. The display signal may be supplied to the pixel rows corresponding to these lines sequentially (in this case, at least the factor Y is 2). In the driving of the display device according to the present invention, the frequency of the horizontal clock CL1 is set to ((N + M) / N) times that of the horizontal synchronization signal HSYNC (1.25 times in the examples of FIGS. 1 and 4 described above). However, the frequency of the horizontal clock CL1 may be further increased, and the operation interval of the pixel array may be ensured by reducing the pulse interval. In this case, a pulse oscillation circuit is provided around the display control circuit 104 and its periphery, and the frequency of the horizontal clock CL1 is increased with reference to a reference signal having a frequency higher than the dot clock DOTCLK included in the video control signal generated thereby. Also good.

  For each of the above factors, N should be a natural number of 4 or more, and the factor M should be 1. Also, the factor Y may be the same value as M, and the factor Z may be the same value as N.

<< Second embodiment >>
Also in this embodiment, as in the first embodiment described above, the video data input to the display device of FIG. 3 at the timing of FIG. A signal output from the driver 102 and displayed according to the display timing shown in FIG. 6, but the output timing of the blanking signal with respect to the output of the display signal based on the video data shown in FIGS. 1 and 4 is a frame period as shown in FIG. Change every time.

  In the display device using the liquid crystal display panel as the pixel array, the output timing of the blanking signal of the present embodiment shown in FIG. 8 is affected by the waveform dullness generated in the data line of the liquid crystal display panel to which the blanking signal is supplied. Is produced, thereby improving the display quality of the image. In FIG. 8, periods Th1, Th2, Th3,... Corresponding to each of the pulses of the horizontal clock CL1 are sequentially arranged in the horizontal direction, and one line of video data output from the data driver 102 in any of these periods. Each display signal m, m + 1, m + 2, m + 3,... And frame period n, n + 1, n + 2, n + 3,. In the vertical direction. The display signals m, m + 1, m + 2, and m + 3 shown here are not limited to video data of specific lines. For example, the display signals L511, L2, L3, and L4 in FIG. L512, L513, L514 can also be supported.

  When blanking data is written once every time video data is written into the pixel array in the manner described in the first embodiment, the blanking data is applied to the pixel array shown in FIG. From one group of periods arranged every four periods in the periods Th1, Th2, Th3, Th4, Th5, Th6,... (For example, the group of periods Th1, Th6, Th12,...) To another group (for example, the period Th2, (Th7, Th13,...) Are sequentially changed for each frame. For example, in the frame period n, blanking data is input to the pixel array before the mth line data is input to the pixel array (a display signal based on this is applied to the mth pixel row). Applied to a pixel row corresponding to predetermined four lines), and after the input of the mth line data to the pixel array and before the input of the (m + 1) th line data to the pixel array in the frame period n + 1, Blanking data is input to the pixel array. The input of the (m + 1) th line data to the pixel array follows the mth line data and applies a display signal based on the (m + 1) th line data to the (m + 1) th pixel row. In the subsequent input of each line data to the pixel array, a display signal based on the line data is applied to a pixel row having the same address (order).

  In the frame period n + 2, the blanking data is input to the pixel array after the (m + 1) th line data is input to the pixel array and before the (m + 2) th line data is input to the pixel array. Do. In the subsequent frame period n + 3, the blanking data is input to the pixel array after the (m + 2) th line data is input to the pixel array and before the (m + 3) th line data is input to the pixel array. I do. Hereinafter, the input of the line data and blanking data to the pixel array is repeated while shifting the timing of the blanking data every horizontal period, and the line according to the frame period n in the frame period n + 4. Return to the input pattern to the pixel array of data and blanking data. By repeating these series of operations, not only the blanking signal but also the display signal based on the line data is output to each of the data lines of the pixel array. Is uniformly distributed to improve the quality of the image displayed on the pixel array.

  On the other hand, in this embodiment, the display device can be operated at the image display timing according to FIG. 6 as in the first embodiment. However, as described above, the application timing of the blanking signal to the pixel array is the frame period. Since the shift is performed every time, the generation time of the second pulse of the scanning start signal FLM for starting scanning of the pixel array by the blanking signal is also displaced according to the frame period. According to such a change in the second pulse generation timing of the scanning start signal FLM, the time: Δt1 shown in the frame period 1 in FIG. 6 is shorter (or longer) than the time: Δt1 in the subsequent frame period 2. : Δt1 ′, and the time: Δt2 shown in the frame period 1 becomes the time: Δt2 ′ longer (or shorter) than the time: Δt2 in the subsequent frame period 2. Considering the “shift” of the scanning start time of the pixel array in the display signal based on the line data m found in a pair of frame periods n and n + 1 shown in FIG. 8 or another pair of frame periods n + 3 and n + 4, In the present embodiment, at least one of two time intervals: Δt1 and Δt2 corresponding to the pulse interval of the scanning start signal FLM varies depending on the frame period.

  As described above, when performing a display operation according to the image display timing shown in FIG. 6 according to the driving method of the display device according to the present embodiment that shifts the output period of the blanking signal along the time axis direction for each frame period. The setting of the scanning start signal requires a slight change, but the effect obtained by this change is no different from that in the first embodiment shown in FIG. Therefore, also in this embodiment, an image corresponding to the video data can be displayed on the hold type display device in substantially the same manner as that in the impulse type display device. In addition, the hold-type pixel array can display a moving image without reducing the luminance of the moving image and reducing moving image blur. Also in this embodiment, the ratio between the display period of video data and the display period of blanking data in one frame period is adjusted by adjusting the timing of the scanning start signal FLM (for example, the above-described pulse intervals: distribution of Δt1 and Δt2). It can be changed appropriately. Further, the application range of the driving method according to the present embodiment to the display device is not limited by the resolution of the pixel array (for example, a liquid crystal display panel) as in the first embodiment. Further, the display device according to the present embodiment, similarly to that according to the first embodiment, appropriately changes the ratio of the blanking period included in the horizontal period defined by the horizontal clock CL1, thereby enabling the display signal in the first step. The number of outputs: N and the number of gate lines selected in the second step: Z can be increased or decreased.

The figure which shows the output timing of the display signal demonstrated as 1st Example of the drive method of the display apparatus by this invention, and the drive waveform of the scanning line corresponding to this. The timing of the input waveform (input data) of the video data to the display control circuit (timing controller) described as the first embodiment of the driving method of the display device according to the present invention and the output waveform (driver data) in the future is shown. FIG. The block diagram which shows the outline | summary of the display apparatus (liquid crystal display device) by this invention. The figure which shows the drive waveform which selects four lines of a scanning line simultaneously in the output period of the display signal demonstrated as 1st Example of the drive method of the display apparatus by this invention. The figure which shows each timing of writing (Write) of video data to each of a plurality of (for example, four) line memories provided in the display device according to the present invention and reading (Read Out) from now on. The figure which shows the image display timing for every frame period (each of three continuous frame periods) in 1st Example of the drive method of the display apparatus by this invention. 6 shows the luminance response of a pixel to a display signal (light transmittance variation of a liquid crystal layer corresponding to the pixel) when the liquid crystal display device (an example of a display device) according to the present invention is driven according to the image display timing shown in FIG. Figure. A display signal (m, m + 1, m + 2,... By video data) supplied to each of the pixel rows corresponding to the gate lines G1, G2, G3,... Described as the second embodiment of the display device driving method according to the present invention. And FIG. 8B shows changes over a plurality of continuous frame periods m, m + 1, m + 2,. Schematic of an example of a pixel array provided in an active matrix display device. The figure which shows the waveform of the scanning signal and display signal by one of the conventional methods of suppressing the moving image blurring in a liquid crystal display device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Display apparatus (liquid crystal display device), 101 ... Pixel array (TFT type liquid crystal display panel), 102 ... Data driver, 103 ... Scan driver, 104 ... Display control circuit (timing controller), 105 ... Line memory circuit , 120 ... Video data, 121 ... Video control signal group (vertical synchronization signal, horizontal synchronization signal, dot clock, etc.), 106 ... Driver data, 107 ... Data driver control signal group, CL3 ... Scan line clock.

Claims (13)

A pixel array having a plurality of pixel columns;
A plurality of gate lines for transmitting a scanning signal for selecting each of the plurality of pixel columns;
An active matrix type display device that operates in a normally black display mode, and has a data line for supplying a signal to a pixel column selected by the scanning signal,
A first step of sequentially selecting Y (Y ≧ 2) adjacent gate lines and sequentially supplying display signals to the pixel columns selected by the Y gate lines;
Z gate lines (Z ≧ 2) spaced apart from the sequentially selected Y gate lines are selected at a time, and blanking is performed on a plurality of pixel columns selected by the Z gate lines. A second step of supplying signals collectively,
In one frame, the first step and the second step are alternately repeated while sequentially moving the Y adjacent gate lines in the pixel array. .   2. The active matrix display device according to claim 1, wherein the blanking signal is a signal for displaying black on a pixel.   3. The active device according to claim 1, wherein the number of gate lines existing between the Y gate lines and the Z gate lines separated from the Y gate lines can be changed. -Matrix type display device.   4. The active matrix display device according to claim 1, wherein a blanking signal having a darkness is supplied in accordance with each pixel of the pixel array.   5. The active matrix display device according to claim 1, wherein the Z gate lines selected in the second step are shifted by one gate line for each frame.   6. The active matrix display device according to claim 1, wherein the pixel array is an electroluminescence array. A pixel array having a plurality of pixel columns;
A plurality of gate lines for transmitting a scanning signal for selecting each of the plurality of pixel columns;
An active matrix type display device that operates in a normally black display mode, and has a data line for supplying a display signal to a pixel column selected by the scanning signal,
In one frame, Y adjacent gate lines (Y ≧ 2) are sequentially selected, and display signals are sequentially supplied to the pixel columns selected by the Y gate lines, and the first period has elapsed. Later, the Y gate lines are collectively selected, and a blanking signal is supplied to the pixel column selected by the Y gate lines.
In the one frame, X (X ≧ 2) adjacent gate lines different from the Y gate lines are sequentially selected, and display signals are sequentially applied to the pixel columns selected by the X gate lines. After the second period has elapsed, the X gate lines are collectively selected, and a blanking signal is supplied to the pixel column selected by the X gate lines. An active matrix display device.   8. The active matrix display device according to claim 7, wherein the Y gate lines and the X gate lines are adjacent gate lines.   9. The active matrix display device according to claim 7, wherein the blanking signal is a signal for displaying black on a pixel.   The active matrix display device according to claim 7, wherein the first period and the second period are the same time.   The active matrix display device according to claim 10, wherein the first period and the second period can be changed.   12. The active matrix display device according to claim 7, wherein a blanking signal having a darkness is supplied in accordance with each pixel of the pixel array. And the pixel array is an active matrix display device according to any one of claims 7 to 12, characterized in that the electroluminescent array.

Images