JP3882823B2 - Differential circuit - Google Patents

Description

  The present invention inputs a True signal (positive signal, non-inverted input signal) and a Compliment signal (negative signal, inverted input signal) transmitted in a pair of positive and negative differential formats, and a differential corresponding to the potential difference The present invention relates to a differential circuit that outputs a signal.

  As shown in FIG. 4, the differential circuit outputs a differential signal (TC) corresponding to the potential difference between the True signal (T) and the Complement signal (C). Here, as shown in FIG. 4 (2), when there is no delay difference between the True signal (T) and the Complement signal (C), the differential signal (TC) has an amplitude twice that of the True signal (T). (2V). However, as shown in FIG. 4 (3), when a delay difference occurs between the True signal (T) and the Compliment signal (C), the amplitude of the differential signal (TC) decreases from the maximum value 2V and the margin increases. Narrow.

  As one method for adjusting the delay difference between the True signal (T) and the Compliment signal (C), a function for automatically adjusting the cross-point potential between the True signal (T) and the Compliment signal (C) to the reference potential Vref. A differential circuit having the above has been proposed (Patent Document 1).

  FIG. 5 shows a configuration example of the differential circuit described in Patent Document 1. Here, in the differential output buffer and differential input buffer of Patent Document 1, only the portion corresponding to the differential circuit of the present invention is extracted and shown. In addition, the positive side signal (P), the negative side signal (N), and the differential signal (PN) in Patent Document 1 are the True signal (T), Complement signal (C), A description will be given assuming that the signal corresponds to the differential signal (TC).

  In FIG. 5, a signal (P) and a signal (N) are input to a differential input circuit 53 via delay adjustment circuits 51 and 52, respectively, and a differential signal (PN) corresponding to the potential difference is output. The The signal (P) and the signal (N) input to the differential input circuit 53 are branched and input to the comparators 54 and 55, respectively, and compared with the reference potential Vref. The comparator 54 outputs an output signal (P−Vref) that becomes “H” when the potential of the signal P is higher than the reference potential Vref and becomes “L” when it is lower. The comparator 55 outputs an output signal (N−Vref) that becomes “H” when the potential of the signal N is higher than the reference potential Vref and becomes “L” when the potential is lower. The output signal (P-Vref) of the comparator 54 is input to the flip-flop circuit 56, is latched at the rising edge of the differential signal (PN), and is output to the delay adjustment circuit 51 as a control signal. The output signal (N-Vref) of the comparator 55 is input to the flip-flop circuit 57, latched at the falling edge of the differential signal (PN), and output as a control signal for the delay adjustment circuit 52.

  In this configuration, as shown in FIG. 6 (1), the output signal (P-Vref) of the comparator 54 at the rising edge of the differential signal (PN) is latched. If the value is “H”, Since the cross-point potential between the signal (P) and the signal (N) is higher than the reference potential Vref, delay adjustment is performed so as to delay the rise of the signal (P). Further, the output signal (N-Vref) of the comparator 55 at the falling edge of the differential signal (P-N) is latched, and if the value is "H", the cross between the signal (P) and the signal (N). Since the point potential is higher than the reference potential Vref, the delay is adjusted so as to delay the rise of the signal (N).

  On the other hand, as shown in FIG. 6 (2), the output signal (P-Vref) of the comparator 54 at the rising edge of the differential signal (PN) is latched. Since the cross-point potential of P) and signal (N) is lower than the reference potential Vref, delay adjustment is performed so that the rise of signal (P) is accelerated. Further, the output signal (N-Vref) of the comparator 55 at the falling edge of the differential signal (P-N) is latched. If the value is "L", the cross between the signal (P) and the signal (N). Since the point potential is lower than the reference potential Vref, the delay is adjusted so that the rise of the signal (N) is accelerated.

Further, as shown in FIG. 6 (3), the output signal (P-Vref) of the comparator 54 at the rising edge of the differential signal (PN) is latched, and if the value is "H", the signal ( Since the cross-point potential between P) and signal (N) is higher than the reference potential Vref, delay adjustment is performed so as to delay the rise of signal (P). Further, the output signal (N-Vref) of the comparator 55 at the falling edge of the differential signal (P-N) is latched. If the value is "L", the cross between the signal (P) and the signal (N). Since the point potential is lower than the reference potential Vref, the delay is adjusted so that the rise of the signal (N) is accelerated. In general, when the signal (P) and the signal (N) are completely complementary and there is only a delay difference, delay adjustment as shown in FIG. 6 (3) is performed.
JP 2003-347860 A

  The differential circuit described in Patent Document 1 changes the rising timing of the signal (P) or the signal (N) according to the difference between the cross-point potential of the signal (P) and the signal (N) and the reference potential Vref, Finally, the configuration is such that the cross-point potential of the signal (P) and the signal (N) is matched with the reference potential Vref. However, in such a configuration, when the difference between the cross-point potential between the signal (P) and the signal (N) and the reference potential Vref becomes small, the differential signal (P-N) and the output signal (P-Vref) of the comparator 54. Alternatively, it is expected that the phase difference from the output signal (N−Vref) of the comparator 55 becomes minute and the delay adjustment for the signal (P) or the signal (N) becomes unstable.

  Incidentally, in the differential circuit shown in FIG. 4, the influence of the delay difference between the True signal (T) and the Complement signal (C) on the amplitude of the differential circuit (TC) becomes significant when the delay difference increases to some extent. become. That is, a slight delay difference between the True signal (T) and the Complement signal (C) is within an allowable range, and the delay difference does not necessarily have to be zero. Rather, rather than becoming unstable because the delay difference is zero, a configuration that can reliably adjust the delay difference exceeding the allowable range within the allowable range is desired.

  An object of the present invention is to provide a differential circuit capable of adjusting a delay difference between two signals transmitted in a differential format to a predetermined range and suppressing a decrease in the amplitude of the differential signal.

  A first differential circuit of the present invention is a differential circuit that inputs a first signal and a second signal transmitted in a differential format, and outputs a differential signal corresponding to the potential difference. A delay adjusting circuit that adjusts a delay time of at least one of the signal and the second signal, and a first reference potential Vref1 and a second reference potential Vref2 that are set in a predetermined range across the intermediate potential of the first signal. The potential of the first signal input from the outside and subjected to delay adjustment by the delay adjustment circuit is compared with the first reference potential Vref1 and the second reference potential Vref2, and the comparison result is obtained at the rise and fall of the differential signal. The comparison latch means for latching and the latch result of the comparison latch means are input, and the potential of the first signal is higher than the first reference potential Vref1 and the second reference potential Vref2 at the rising edge of the differential signal, and the difference At the falling edge of the dynamic signal When the reference potential is lower than the first reference potential Vref1 and the second reference potential Vref2, the delay adjustment circuit is controlled to delay the first signal relative to the second signal, and the potential of the first signal is different. Delay when the dynamic signal rises lower than the first reference potential Vref1 and the second reference potential Vref2 and when the differential signal falls higher than the first reference potential Vref1 and the second reference potential Vref2 And a determination circuit that performs control for causing the adjustment circuit to advance the first signal relative to the second signal.

  The second differential circuit of the present invention is a differential circuit that inputs a first signal and a second signal transmitted in a differential format, and outputs a differential signal corresponding to the potential difference. A delay adjusting circuit that adjusts a delay time of at least one of the signal and the second signal, and a first reference potential Vref1 and a second reference potential Vref2 that are set in a predetermined range across the intermediate potential of the first signal. The potential of the first signal input from the outside and subjected to delay adjustment by the delay adjustment circuit is compared with the first reference potential Vref1 and the second reference potential Vref2, and the comparison result is obtained at the rise and fall of the differential signal. The comparison latch means for latching and the latch result of the comparison latch means are input, and the potential of the first signal is higher than the first reference potential Vref1 at the rising edge of the differential signal and the first signal potential at the falling edge of the differential signal. Than the reference potential Vref2 of 2 The delay adjustment circuit controls the delay of the first signal relative to the second signal so that the potential of the first signal is lower than the second reference potential Vref2 at the rising edge of the differential signal. And a determination circuit that controls the delay adjustment circuit to advance the first signal relative to the second signal when the differential signal falls and is higher than the first reference potential Vref1. .

  The comparison latch means in the differential circuit of the present invention compares the first signal potential with the first reference potential Vref1, and latches the comparison result at the rising edge of the differential signal. A second comparison latch means for comparing the potential of the first signal with the second reference potential Vref2, and latching the comparison result at the rising edge of the differential signal; and the first signal potential and the first reference potential Vref1. The third comparison latch means for comparing and latching the comparison result at the falling edge of the differential signal, the potential of the first signal and the second reference potential Vref2 are compared, and the comparison result is compared with the rising edge of the differential signal. And fourth comparison latch means for latching at the bottom.

  The differential circuit of the present invention latches the comparison result between the potential of the first signal and the two reference potentials Vref1 and Vref2 at two timings of rising and falling of the differential signal, and at the timing of rising of the differential signal. If it is higher than Vref1, Vref2 (or Vref1) and lower than Vref1, Vref2 (or Vref2) at the falling timing of the differential signal, it is determined that the first signal is relatively advanced than the second signal, Control is performed so that the first signal is relatively delayed. In addition, when the differential signal rise timing is lower than Vref1, Vref2 (or Vref2) and the differential signal fall timing is higher than Vref1, Vref2 (or Vref1), the first signal is relative to the second signal. Therefore, control is performed so that the first signal is relatively advanced.

  As a result, the delay difference between the first signal and the second signal transmitted in the differential format can be controlled within a predetermined range, and the decrease in the amplitude of the differential signal that occurs when the delay difference increases is suppressed. be able to.

(First embodiment)
FIG. 1 shows a first embodiment of the differential circuit of the present invention.
In FIG. 1, a True signal (T) and a Complement signal (C) are respectively input to a differential input circuit 13 via delay adjustment circuits 11 and 12, and the differential input circuit 13 receives a differential signal corresponding to the potential difference. (TC) and an inverted differential signal are output. The True signal (T) input to the differential input circuit 13 is branched and input to the comparators 14, 15, 16, and 17 and compared with the reference potentials Vref1 and Vref2. Here, the True signal (T) and the Complement signal (C) are sine waves, and the reference potentials Vref1 and Vref2 are set within a predetermined range that sandwiches the intermediate potential of the True signal (T).

  The comparators 14 and 16 compare the True signal (T) with the reference potential Vref1, and when the potential of the True signal (T) is higher than the reference potential Vref1, “H (high level)” and when the potential is lower, “L ( Low level) ”is output. The comparators 15 and 17 compare the True signal (T) with the reference potential Vref2, and output a signal that becomes “H” when the potential of the True signal (T) is higher than the reference potential Vref2, and becomes “L” when it is lower. Output. The output signals of the comparators 14 and 15 are input to the flip-flop circuits 18 and 19, latched at the rising edge of the differential signal (TC), and input to the determination circuit 22 as data signals F1 and F2. The output signals of the comparators 16 and 17 are input to the flip-flop circuits 20 and 21 and latched at the rising edge of the inverted differential signal (the falling edge of the differential signal (TC)), and are determined as data signals F3 and F4. 22 is input.

  The data signals F1, F2, F3, and F4 output from each flip-flop circuit are “1” when the output signal of each comparator is “H”, and “0” when the output signal is “L”. Determines the advance / delay of the True signal (T) with respect to the Compliment signal (C) according to this logic, and sends a control signal for controlling the advance / delay of the True signal (T) to the delay adjustment circuit 11.

  In the present embodiment, a differential signal (TC) is input as a clock signal for the flip-flop circuits 18 and 19, and an inverted differential signal is input as a clock signal for the flip-flop circuits 20 and 21, respectively. It is configured to latch at the rising and falling edges of the signal (TC).

  As a result, when the True signal (T) and the Compliment signal (C) are substantially in phase, as shown in FIG. 3 (1), it corresponds to the cross point of the True signal (T) and the Compliment signal (C). At the rise and fall timings of the differential signal (TC), the potential of the True signal (T) is between the reference potentials Vref1 and Vref2, and F1 = 0, F2 = 1, F3 = 0, F4 A result of = 1 is obtained.

  When the True signal (T) is advanced with respect to the Compliment signal (C), as shown in FIG. 3 (2), the potential of the True signal (T) is the differential signal (TC). Is higher than the reference potential Vref1 at the rise timing of the signal, and smaller than the reference potential Vref2 at the fall timing of the differential signal (TC), resulting in F1 = 1, F2 = 1, F3 = 0, and F4 = 0. can get.

  On the other hand, when the True signal (T) is delayed with respect to the Compliment signal (C), as shown in FIG. 3 (3), the potential of the True signal (T) becomes the differential signal (TC). The result is such that F1 = 0, F2 = 0, F3 = 1, and F4 = 1, which are smaller than the reference potential Vref1 at the rise timing of the signal and greater than the reference potential Vref2 at the fall timing of the differential signal (TC). can get.

  Therefore, when the data signal of F1 = 1, F2 = 1, F3 = 0, F4 = 0 is input to the determination circuit 22, the True signal (T) is advanced with respect to the Complement signal (C). The delay adjustment circuit 11 is controlled to increase the delay of the True signal (T). The determination circuit 22 also delays the True signal (T) with respect to the Complement signal (C) when a data signal of F1 = 0, F2 = 0, F3 = 1, and F4 = 1 is input. The delay adjustment circuit 11 is controlled to reduce the delay of the True signal (T).

  Any delay amount control is performed until F1 = 0, F2 = 1, F3 = 0, and F4 = 1 are finally obtained as data signals. In other words, it is sufficient that the potential of the True signal (T) is between the reference potentials Vref1 and Vref2 at the rising and falling timings of the differential signal (TC), and the range is set as an allowable range for delay adjustment. Yes.

  By the way, as shown in FIG. 3 (2), when F1 = 1, it is always F2 = 1, and when F4 = 0, it is always F3 = 0, so that the determination circuit 22 is F1 = 1 and F4 = 0. At this time, it may be determined that the True signal (T) is ahead of the Compliment signal (C), and the delay adjustment circuit 11 may be controlled to increase the delay of the True signal (T). .

  Similarly, as shown in FIG. 3 (3), F1 = 0 is always obtained when F2 = 0, and F4 = 1 is always obtained when F3 = 1. Therefore, the determination circuit 22 has F2 = 0 and F3 = Even if it is determined that the True signal (T) is delayed with respect to the Compliment signal (C) when 1, the delay adjustment circuit 11 is controlled to reduce the delay of the True signal (T). Good.

(Second Embodiment)
FIG. 2 shows a second embodiment of the differential circuit of the present invention.
In the first embodiment, the flip-flop circuits 18 and 19 receive a differential signal (TC) as a clock signal and latch at the rising edge, and the flip-flop circuits 20 and 21 receive an inverted differential signal as a clock signal. The input signal is latched at the rising edge (the falling edge of the differential signal (TC)).

  In the present embodiment, the differential signal (TC) is inverted and input as the clock signal of the flip-flop circuits 20 and 21 and latched at the falling edge of the differential signal (TC). Other configurations are the same as those of the first embodiment.

  The delay adjustment circuit 12 in the first embodiment and the second embodiment gives a fixed delay amount to the Compliment signal (C), but the determination circuit 22 gives a control signal to the delay adjustment circuit 11. The delay amount control for the Compliment signal (C) may be performed with the inverse logic of The determination circuit 22 may control the delay adjustment circuit 11 and the delay adjustment circuit 12 in a complementary manner. In other words, at least one of the delay adjustment circuits may be configured so that the advance / delay of the True signal (T) and the Complement signal (C) are relatively controlled.

1 is a block diagram showing a first embodiment of a differential circuit of the present invention. It is a block diagram which shows 2nd Embodiment of the differential circuit of this invention. It is a time chart which shows the operation example of the differential circuit of this invention. It is the block diagram and time chart which show the basic composition of a differential circuit. 10 is a block diagram illustrating a configuration example of a differential circuit described in Patent Document 1. FIG. 10 is a time chart showing an operation example of the differential circuit described in Patent Document 1.

Explanation of symbols

11, 12 Delay adjustment circuit 13 Differential input circuit 14, 15, 16, 17 Comparator 18, 19, 20, 21 Flip-flop circuit 22 Determination circuit

Claims (3)

In a differential circuit for inputting a first signal and a second signal transmitted in a differential format and outputting a differential signal corresponding to the potential difference,
A delay adjustment circuit for adjusting a delay time of at least one of the first signal and the second signal;
The first reference potential Vref1 and the second reference potential Vref2 set in a predetermined range sandwiching the intermediate potential of the first signal are input from the outside, and the first signal delay-adjusted by the delay adjustment circuit A comparison latch means for comparing the first reference potential Vref1 and the second reference potential Vref2 with each other, and latching the comparison result at the rising edge and falling edge of the differential signal, respectively.
The latch result of the comparison latch means is input, and the potential of the first signal is higher than the first reference potential Vref1 and the second reference potential Vref2 at the rise of the differential signal, and the rise of the differential signal. When the first reference potential Vref1 and the second reference potential Vref2 are lower than the first reference potential Vref2, the delay adjustment circuit is controlled to delay the first signal relative to the second signal. The potential of one signal is lower than the first reference potential Vref1 and the second reference potential Vref2 at the rise of the differential signal, and the first reference potential Vref1 and the second reference at the fall of the differential signal. And a determination circuit that controls the delay adjustment circuit to cause the first signal to advance relative to the second signal when the potential is higher than the potential Vref2. In a differential circuit for inputting a first signal and a second signal transmitted in a differential format and outputting a differential signal corresponding to the potential difference,
A delay adjustment circuit for adjusting a delay time of at least one of the first signal and the second signal;
The first reference potential Vref1 and the second reference potential Vref2 set in a predetermined range sandwiching the intermediate potential of the first signal are input from the outside, and the first signal delay-adjusted by the delay adjustment circuit A comparison latch means for comparing the first reference potential Vref1 and the second reference potential Vref2 with each other, and latching the comparison result at the rising edge and falling edge of the differential signal, respectively.
The latch result of the comparison latch means is input, and the potential of the first signal is higher than the first reference potential Vref1 at the rising edge of the differential signal, and the second reference potential at the falling edge of the differential signal. When it is lower than Vref2, the delay adjustment circuit is controlled to delay the first signal relative to the second signal, and the potential of the first signal is changed at the rising edge of the differential signal. 2 is lower than the second reference potential Vref2 and higher than the first reference potential Vref1 at the falling edge of the differential signal, the first signal is relative to the delay adjustment circuit relative to the second signal. A differential circuit comprising: a determination circuit that performs a control to move forward. The comparison latch means
First comparison latch means for comparing the potential of the first signal with the first reference potential Vref1, and latching the comparison result at the rising edge of the differential signal;
A second comparison latch means for comparing the potential of the first signal with a second reference potential Vref2, and latching the comparison result at the rising edge of the differential signal;
Third comparison latch means for comparing the potential of the first signal with the first reference potential Vref1, and latching the comparison result at the falling edge of the differential signal;
The fourth comparison latch means for comparing the potential of the first signal and the second reference potential Vref2 and latching the comparison result at the falling edge of the differential signal. Differential circuit.

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