JP3876894B2 - Power supply - Google Patents

Description

  The present invention relates to a power supply apparatus that receives a DC power supply voltage and outputs a predetermined voltage.

  2. Description of the Related Art There has been a power supply apparatus having a regulator circuit having an AC transformer and a DCDC converter circuit that receives a power supply voltage of a regulator circuit at a subsequent stage and stably supplies a predetermined DC voltage. Thus, by providing a DCDC converter circuit in the subsequent stage of the regulator circuit and converting it to a predetermined DC voltage, it is possible to efficiently generate a plurality of power supply voltages, and it is easy to control the power supply voltage, for example, on / off of power supply generation In addition, there is an advantage that the AC transformer of the regulator circuit can be reduced in size.

  In recent years, digital home appliances require a plurality of types of power supply voltages such as a drive system power supply voltage (for example, 12 V or 5 V) and a control system power supply voltage (for example, 3.3 V or 2.5 V). In such a case, the power supply voltage (12 V or 5 V) of the driving system that is not worrisome such as ripple is generated by the regulator circuit, and the power supply voltage (3.3 V or 2.5 V) of the control system that requires the stability of the potential. Is generated by a DCDC converter circuit based on the power supply voltage of the regulator circuit.

Conventionally, as a technique using a plurality of power supplies, a technique of outputting a load while switching a plurality of power supplies when driving a load with large power consumption has been proposed (Patent Documents 1 to 3).
Japanese Patent Laid-Open No. 01-227627 Japanese Patent Laid-Open No. 02-072638 JP 2002-271980 A

  In digital home appliances, for example, a video disc recorder, for example, even if the same type of device is used, many lineups may be provided with different storage device capacities, types of corresponding storage media, etc. Many.

  In such a case, when trying to apply the same power supply circuit between different lineups, even if the output power is sufficient for all power supply voltages in one lineup, a certain power supply voltage is output power in the other lineup. Although sufficient, there may be an unbalanced state where the output power is insufficient at a certain power supply voltage.

  In such a case, the above-mentioned imbalance can be corrected by changing the design of the power supply circuit. However, if the design is changed from the beginning, a new circuit design cost is generated, and the volume of the power supply circuit changes and the internal circuit changes. The design cost of the entire product will increase, such as the need to change the layout of the device and the exterior of the device. In such a case, the present inventors considered that it would be effective if there was a configuration capable of compensating for the power supply voltage in which the output power was excessive due to the power supply voltage having sufficient output power.

  An object of the present invention is to provide a power supply apparatus that can receive a current supply from a plurality of power supply voltages and generate a predetermined voltage.

In order to achieve the above object, the present invention provides a first power supply voltage terminal and a second power supply voltage terminal, a DCDC converter circuit that converts an input DC voltage into an AC voltage, converts the DC voltage into a predetermined DC voltage, and outputs the DCDC converter circuit. A switch circuit that switches a power supply voltage input to the DCDC converter circuit to either the voltage of the first power supply voltage terminal or the voltage of the second power supply voltage terminal; a delay circuit that delays the signal of the AC voltage; and A switching signal generation circuit that generates a control signal for switching the switch circuit at each timing obtained by dividing a period during which an input current flows in the DCDC converter circuit by a logic circuit that performs a logical operation on an AC voltage signal and a delay circuit signal It is provided with these .

  According to such means, for example, when there are a plurality of power supply voltages and another voltage is generated from these power supply voltages, it is said that the output power is insufficient with only one power supply voltage. By using two power supply voltages, their output powers can be combined to generate one voltage. At this time, since the switching of the two power supply voltages is performed using the AC voltage of the DCDC converter circuit, it is not necessary to perform a dedicated control for switching the input voltage, and the scale of the added circuit is small.

Further, when switching control of the power supply voltage based on the AC voltage of the DCDC converter, when the switching frequency of the DCDC converter is low, there is a period during which one power supply voltage is turned on and a period during which the input current is cut off by the DCDC converter. In some cases, the power supply is performed only from one of the power supply voltage terminals. In such a case, by adding a switching signal generation circuit as described above and shifting the switching timing of the power supply voltage, power can be supplied equally from the first power supply voltage terminal and the second power supply voltage terminal as appropriate. Can be done.

Specifically, voltages from different power sources may be supplied to the first power supply voltage terminal and the second power supply voltage terminal. The DCDC converter circuit may include a transistor that intermittently supplies current supplied from the power supply voltage terminal to the inductor, and a control circuit that generates a switching control signal for the transistor based on the output voltage.

With such a configuration, a constant voltage can be generated using voltages from a plurality of power supply circuits (which may be the same voltage or different voltages).

Preferably, a capacitor constituting a low-pass filter is connected to the input terminal of the DCDC converter circuit to which the power supply voltage is input.

  It is also possible to provide three or more power supply voltage terminals and switch the voltages of these three power supply voltage terminals by a switch circuit to supply them to the DCDC converter. In this case, the switching signal generation circuit may be configured to generate a control signal for switching the switch circuit at each timing obtained by dividing the period in which the input current flows in the DCDC converter circuit by the number of the power supply voltage terminals.

  As described above, according to the present invention, even when there are a plurality of power supply voltages and another voltage is generated from these power supply voltages, even if it is said that only one power supply voltage is insufficient, There is an effect that a plurality of power supply voltages can be used to generate a single voltage by combining their output powers.

  In addition, there is an effect that control for switching a plurality of power supply voltages can be performed by adding a simple circuit.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
FIG. 1 shows a configuration diagram of a power supply circuit according to a first embodiment of the present invention.

  The power supply circuit of this embodiment has a first power supply voltage terminal and a second power supply voltage terminal to which two kinds of power supply voltages Va (for example, 5 V) and Vb (for example, 3.3 V) are respectively supplied, and an input voltage is set to a predetermined value. A DCDC converter circuit 10 that converts and outputs a voltage of a magnitude (for example, 2.5 V), and a switch circuit 30 that switches the input of the DCDC converter circuit 10 to either the first power supply voltage Va or the second power supply voltage Vb, 40 and a low-pass filter 50 connected to the input terminal of the DCDC converter circuit 10.

  The DCDC converter circuit 10 includes a switching transistor Tr1 that allows current to flow intermittently from a power supply voltage, a controller 11 that performs switching control of the switching transistor Tr1 so that the output voltage Vo becomes a predetermined value, and an AC voltage Vsw that is generated by the switching operation. Is formed of a smoothing circuit including a Zener diode 12, an inductor 13, and a capacitor (for example, an electric field capacitor) 14.

  Although not particularly limited, the switching transistor Tr1 and the controller 11 are configured in the form of one IC device 10A, and the Zener diode 12, the inductor 13, and the capacitor 14 are connected as external elements.

  The controller 11 outputs a pulse signal for turning on and off the switching transistor Tr1 at a predetermined switching frequency (for example, 500 k to 1 MHz), and changes the pulse width based on the output voltage Vo that is fed back, thereby changing the output voltage Vo. The switching transistor Tr1 is controlled so as to be kept constant. An alternating voltage Vsw having the same frequency as the switching frequency is output to the output node N1 of the switching transistor Tr1.

  The switch circuit 30 includes a field effect transistor Tr31 that passes / cuts off current between the first power supply voltage terminal (Va) and the input terminal of the DCDC converter circuit 10, and a field effect transistor Tr31 that uses the first power supply voltage Va as an operation power supply. The transistor Tr30 and the resistor R30 that drive the gate of the transistor DC, and the inverter INV30 that receives the AC voltage Vsw from the DCDC converter circuit 10 and drives the transistor Tr30.

  The switch circuit 40 includes a field effect transistor Tr41 that passes / cuts off current between the second power supply voltage terminal (Vb) and the input terminal of the DCDC converter circuit 10, and a field effect transistor Tr41 using the second power supply voltage Vb as an operation power supply. The transistor Tr40 and the resistor R40 that drive the gate of the transistor, and the buffer circuit B40 that receives the AC voltage Vsw from the DCDC converter circuit 10 and drives the transistor Tr40.

  The low-pass filter 50 is obtained by connecting a resistor R50 and a capacitor (for example, an electric field capacitor) C50 in parallel between the input terminal of the DCDC converter circuit 10 and the ground.

  The operation of the power supply circuit configured as described above will be described below.

  FIG. 2 shows waveform diagrams of the AC voltage Vsw and the output voltage Vo of the DCDC converter circuit 10.

  According to the power supply circuit configured as described above, the switching transistor Tr1 is controlled to be turned on / off by the controller 11 of the DCDC converter circuit 10, and the voltage Vsw of the node N1 is turned to the high level (input voltage Vi) during the ON period. During this period, the voltage Vsw of the node N1 is set to a low level (a potential slightly lower than the ground potential). The AC voltage Vsw is smoothed by the smoothing circuit (12, 13, 14), and a constant output voltage Vo (for example, 2.5 V) is output.

  At this time, the controller 11 controls the switching transistor Tr1 to have a long ON period when the output current is large, and shortens the ON period of the switching transistor Tr1 when the output current is small. The voltage Vo is kept constant.

  On the other hand, the AC voltage Vsw is output to the switch circuits 30 and 40 and used for switching control of the power supply voltage. That is, when the AC voltage Vsw becomes high level, the field effect transistor Tr41 is turned on and the second power supply voltage Vb is supplied to the converter circuit 10 side. On the other hand, when the AC voltage Vsw becomes low level, the field effect transistor Tr41 is turned off and the first power supply voltage Vb is supplied to the DCDC converter circuit 10 side.

  Here, when the switching frequency of the DCDC converter circuit 10 is as high as 500 kHz or 1 MHz, for example, the fluctuation of the input voltage due to the switching of the power supply voltage is moderated by the capacitor C50 connected to the input terminal of the DCDC converter circuit 10. In addition, while the transistor Tr1 is off, the current from the power supply voltage terminal is drawn into the capacitor C50, and the charge is temporarily stored. The stored charge is supplied to the DCDC converter circuit 10 when the transistor Tr1 is turned on. Therefore, the currents from the first power supply voltage terminal and the second power supply voltage terminal are supplied to the DCDC converter circuit 10 and used to generate the output voltage Vo regardless of the on / off state of the transistor Tr1.

  Therefore, for example, if the pulse waveform of the switching control signal of the controller 11 has a duty ratio of about 50%, current is supplied half by half from the first power supply voltage terminal and the second power supply voltage terminal. Compared with the case where current is supplied from the voltage terminal, the current load and heat generation of each power supply circuit supplying the power supply voltages Va and Vb are halved.

As described above, according to the power supply circuit of this embodiment, the new voltage Vo can be generated using the two power supply voltages Va and Vb. Therefore, there are a plurality of power supply voltages and the new voltage Vo ( 2.5V), even when the output power becomes excessive with only one power supply voltage, the output power can be compensated using another power supply voltage. As a result, even when the design of the power supply circuit is changed in accordance with the change in the output load of each power supply voltage, it is possible to flexibly cope with the change in the output load with a small change.
[Modification]
FIG. 3 is a circuit diagram showing a DCDC converter circuit 10B applied when generating a boosted voltage, and FIG. 4 is a waveform diagram of the AC voltage Vsw and the output voltage Vo when this DCDC converter circuit 10B is applied. Show.

  The power supply circuit in FIG. 1 can be a boost type power supply circuit or an inversion type power supply circuit that generates a negative voltage by changing the DCDC converter circuit 10.

  In the case of a step-up power supply circuit, for example, a step-up DCDC converter circuit 10B shown in FIG. 3 is applied. That is, the inductor 16 and the Zener diode 17 are connected in series between the input terminal and the output terminal, the capacitor 18 is connected between the output terminal and the ground terminal, and the connection node N2 of the inductor 16 and the Zener diode 17 is grounded. This is a DCDC converter circuit 10B in which a switching transistor Tr2 is connected between the potential.

  Then, the AC voltage output to the connection node N2 is output to the switch circuits 30 and 40. In FIG. 3, a controller for controlling the switching transistor Tr2 is omitted.

  According to such a circuit, as shown in FIG. 4, the output waveform of the connection node N2 is high level (input voltage Vi) when the switch transistor Tr2 is turned off, and low level (grounded) when the switch transistor Tr2 is turned on. The pulse waveform becomes (potential). The output voltage Vo is boosted to a voltage higher than the input voltage Vi.

  FIG. 5 is a circuit diagram showing a DCDC converter circuit 10C applied when generating a negative voltage, and FIG. 6 is a waveform diagram of the AC voltage Vsw and the output voltage Vo when this DCDC converter circuit 10C is applied. Show.

  In the case of a power supply circuit that generates a negative voltage, for example, an inverting DCDC converter circuit 10C shown in FIG. 5 is applied. That is, the inductor 21 is connected in parallel with the ground terminal, the diode is connected in series, and the capacitor 23 is connected in parallel with the ground terminal in the subsequent stage of the switching transistor Tr3 that turns on and off the current supply from the input terminal. This is a connected DCDC converter circuit 10C.

  Then, the AC voltage Vsw output to the output node N3 of the switching transistor Tr3 is output to the switch circuits 30 and 40. In FIG. 5, a controller for controlling the switching transistor Tr3 is omitted.

According to such a circuit, as shown in FIG. 6, the output waveform of the output node N3 has a high level (input voltage Vi) when the switch transistor Tr2 is turned on, and a low level (negative voltage) when the switch transistor Tr2 is turned off. The pulse waveform becomes the voltage Vo). The output voltage Vo is inverted to a negative voltage lower than the ground potential.
[Second Embodiment]
FIG. 7 shows an overall configuration diagram of a power supply circuit according to the second embodiment.

  The power supply circuit of this embodiment is useful when the switching frequency of the DCDC converter circuit 10 is relatively low, and a switching signal for generating a control signal for switching the switch circuits 30 and 40 to the power supply circuit of FIG. A generation circuit 60 is added. The same components as those of the circuit of FIG.

  The switching signal generation circuit 60 includes, for example, a first AND circuit 62 and a second AND circuit 63, an inverter circuit 64, and a delay circuit 61. The switching signal generation circuit 60 divides a period during which a current is input to the DCDC converter into two. Thus, a signal for switching the switch circuits 30 and 40 is generated.

  Specifically, the AC voltage Vsw of the DCDC converter circuit 10 is input to one input terminal of the first AND circuit 62, and the AC voltage Vs is input to the other input terminal via the delay circuit 61. The output of the AND circuit 62 is configured to be input to the base of the transistor Tr40 of the switch circuit 40. Further, the AC voltage Vsw of the DCDC converter circuit 10 is input to one input terminal of the second AND circuit 63, and the output of the first AND circuit 63 is inverted and input to the other input terminal by the inverter circuit 64. The output of the second AND circuit 63 is configured to be input to the base of the transistor Tr30 of the switch circuit 30.

  FIG. 8 shows a specific circuit diagram of the delay circuit 61.

  The delay circuit exerts a delay of about 1/10 to 1/3 of the switching cycle. For example, as shown in FIG. 8A, a plurality of inverter circuits INV1 to INV4 are connected in cascade, or It can be constituted by an integrating circuit comprising a resistor R60 and a capacitor C60.

  FIG. 9 shows potential waveform diagrams of the nodes A, B, C, and D of the switching signal generation circuit 60.

  According to the switching signal generation circuit 60 as described above, when the AC voltage Vsw (pulse waveform) of the DCDC converter circuit 10 is input at the node A, this signal is delayed via the delay circuit 61 and is supplied to the node B. Is output.

  In the first AND circuit 62, the signals of the nodes A and B are input to the two input terminals, respectively, so that the signal of the node C, which is the output of the first AND circuit 62, divides the high level period of the pulse signal of the node A into two. The pulse signal becomes a high level only for a period. Further, since the signals of the nodes A and C are respectively input to the two input terminals of the second AND circuit 63, the signal of the node D which is the output is the remaining of the two divided by the signal of the node C. The pulse signal becomes a high level during this period.

  Then, the second switch circuit 40 is turned on in the high level period by the pulse signal of the node C and the second power supply voltage Vb is supplied to the DCDC converter circuit 10, and in the high level period by the pulse signal of the node D. The first switch circuit 30 is turned on and the first power supply voltage Va is supplied to the DCDC converter circuit 10.

As described above, according to the power supply circuit of this embodiment, the operation of storing the drive current by the input capacitor C50 during the period when the switching frequency of the DCDC converter circuit 10 is relatively low and the input of the DCDC converter circuit 10 is cut off. Even when the above is not obtained, the effect of being able to distribute the power supply to the two power supply voltages can be achieved. That is, in the state where the switching frequency is low as described above, for example, if the on period of one switch circuit 30 or 40 overlaps with the off period of the transistor Tr1, the power supply voltage on the switch circuit 30 or 40 side There will be almost no power supply. However, according to the power supply circuit of the present embodiment, the switching signal generation circuit 60 sets the switching timing of the switch circuits 30 and 40 to divide the high voltage period of the AC voltage Vsw into two. Even when the frequency is low, power is supplied in a distributed manner from both power supply voltages Va and Vb.
[Third Embodiment]
FIG. 10 is an overall configuration diagram of the power supply circuit according to the third embodiment.

  The power supply circuit of this embodiment generates one output voltage Vo using three power supply voltages Va, Vb, and Vc, and is accompanied by the addition of one power supply voltage terminal (Vc). In addition to adding one switch circuit 70 that supplies and cuts off the power supply voltage Vc to the DCDC converter circuit 10 side, a switching signal generation circuit 80 that generates a switching signal for appropriately switching the three switch circuits 30, 40, and 70 is provided. It is a thing.

  The switching signal generation circuit 80 includes first to third AND circuits 81 to 83, two inverter circuits 84 and 85, and two delay circuits 86 and 87, and current is supplied to the DCDC converter circuit 10. A signal for switching the switch circuits 30, 40, and 70 is generated at a timing of dividing the input period by 3 minutes.

  Specifically, the AC voltage Vsw of the DCDC converter circuit 10 is input to one input terminal of the first AND circuit 81, and the AC voltage Vsw is input to the other input terminal via the delay circuit 86 and the inverter circuit 84. Connect as follows. The AC voltage Vs is input to one input terminal of the second AND circuit 82 via the delay circuit 86, and the AC voltage Vsw is input to the other input terminal via the two delay circuits 86 and 87 and the inverter circuit 85. Connect so that is input. The third AND circuit 83 is connected so that the AC voltage Vsw is input to one input terminal of the third AND circuit 83 via the two delay circuits 86 and 87 and the AC voltage Vsw is directly input to the other input terminal. Then, the output terminals of these three AND circuits 81 to 83 are output to the transistors Tr30, Tr40, Tr70 of the three switch circuits 30, 40, 70, and power supply voltage terminals for supplying current to the DCDC converter circuit 10 are provided. Switch from one of the three power supply voltage terminals (Va, Vb, Vc).

  FIG. 11 shows potential waveform diagrams of the nodes A to F of the switching signal generation circuit 80.

  According to the switching signal generation circuit 80 as described above, when the AC voltage Vsw (pulse waveform) of the DCDC converter circuit 10 is input at the node A, this signal is delayed via the delay circuit 86 and is supplied to the node B. Is output. Further, the signal of the node B is delayed through the delay circuit 87 and output to the node C.

In the first AND circuit 81, the signal of the node A and the inverted signal of the node B are input to the two input terminals, respectively, so that the output node D of the first AND circuit 81 has the delay amount of the delay circuit 86. A pulse signal whose period is at a high level is output. Further, since the signal of the node B and the inverted signal of the node C are respectively input to the two input terminals of the second AND circuit 82, the output node E of the second AND circuit 82 is connected to the delay circuit 87. A pulse signal having a high delay level is output. Further, since the signals of the node A and the node C are respectively input to the two input terminals of the third AND circuit 83, the output node F of the third AND circuit 83 is
Of the high level period of the AC voltage Vsw, a pulse signal is output in which the remaining period is high except for the period in which the outputs of the first and second AND circuits 81 and 82 are high.

  As described above, according to the power supply circuit of this embodiment, it is possible to generate one output voltage by supplying currents from the three power supply voltage terminals in a distributed manner.

  Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made. For example, the switching signal generation circuits 60 and 80 in FIG. 7 and FIG. 10 have the switch circuits 30 and 40 (or 30, 40, and so on) at the timing of dividing the high level period of the AC voltage Vsw of the DCDC converter circuit 10 to 2 minutes or 3 minutes. 70), but when the type in which the input current flows to the DCDC converter circuit 10 while the AC voltage Vsw is at the low level is employed, the switch circuit is at a timing for dividing the low level period by 2 or 3 minutes. Should be switched.

  In addition, the number of power supply voltage terminals for supplying current is not limited to two or three. By increasing the number of switch circuits and the number of switching signal dividing signals of the switching signal generation circuit, current can be supplied from more power supply voltage terminals. Can be distributed. In addition, voltages are supplied to each power supply voltage terminal from a plurality of power supply circuits, but these voltages may be different in magnitude or may be the same magnitude.

  Further, as shown in FIG. 12, an inductor L50 may be connected in series to the input terminal of the DCDC converter circuit in addition to the capacitor C50 of FIG. 1, thereby smoothing the input voltage of the DCDC converter circuit 10. In addition, averaging of the power supplied from the first power supply voltage terminal and the power supplied from the second power supply voltage terminal can be further increased.

  In addition, the specific configurations of the DCDC converter circuit, the switching signal generation circuit, and the switch circuit can be variously changed.

  Further, as shown in FIG. 13, by separately preparing a pulse generator 90 that generates a signal for switching the switch circuits 30 and 40, switching control of the power supply voltage is performed at a timing unrelated to the switching frequency of the DCDC converter circuit 10. You can also Alternatively, in this case, voltage generation can be performed using various constant voltage circuits 100 without using a DCDC converter circuit for voltage generation.

It is a block diagram which shows the whole power supply circuit of embodiment of this invention. It is a wave form diagram which shows the change of the electric potential of each part of the DCDC converter circuit of a power supply circuit. It is a figure which shows an example of the DCDC converter circuit applied when producing | generating the boosted voltage. It is a wave form diagram which shows the change of the electric potential of each part when the pressure | voltage rise type DCDC converter circuit of FIG. 3 is used. It is a figure which shows an example of the DCDC converter circuit applied when producing | generating a negative voltage. FIG. 6 is a waveform diagram showing a change in potential of each part when the inverting DCDC converter circuit of FIG. 5 is used. It is a block diagram which shows the whole power supply circuit of the 2nd Embodiment of this invention. FIG. 8 is a circuit diagram illustrating an example of a delay circuit in FIG. 7. FIG. 8 is a waveform diagram showing potential changes at each node of the power supply circuit of FIG. 7. It is a block diagram of the power supply circuit of the 3rd Embodiment of this invention. FIG. 11 is a waveform diagram showing potential changes at each node of the power supply circuit of FIG. 10. It is a figure which shows the other example of the circuit connected to the input terminal of a DCDC converter circuit. It is a block diagram which shows the other example of the power supply circuit which produces | generates a predetermined power supply voltage using a some power supply voltage.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 DCDC converter circuit 11 Controller 13 Inductor 30, 40 Switch circuit 60 Switching signal generation circuit 61 Delay circuit C50 Capacitor Tr1 Switching transistor Vsw AC voltage

Claims (5)

A first power supply voltage terminal and a second power supply voltage terminal to which voltages from different power sources are respectively supplied;
Wherein a transistor to flow intermittently the current in the inductor to be supplied from the first power supply voltage terminal and said second power supply voltage terminal, and a control circuit which is fed back the output voltage to generate a switching control signal of the transistor, A DCDC converter circuit that converts an input DC voltage into an AC voltage and then converts the DC voltage into a predetermined DC voltage and outputs the DC voltage;
A switch circuit for switching a voltage input to the DCDC converter circuit to either the voltage of the first power supply voltage terminal or the voltage of the second power supply voltage terminal;
A capacitor connected to an input terminal of the DCDC converter circuit and constituting a low-pass filter ;
The delay circuit that delays the AC voltage signal and the logic circuit that performs a logical operation on the AC voltage signal and the delay circuit signal each time the input current flows in the DCDC converter circuit is divided into a plurality of timings. A switching signal generation circuit for generating a control signal for switching the switch circuit;
Power supply, characterized in that it comprises a. A plurality of power supply voltage terminals;
A DCDC converter circuit that converts an input DC voltage into an AC voltage and then converts the DC voltage into a predetermined DC voltage and outputs the DC voltage;
A switch circuit that switches a power supply voltage input to the DCDC converter circuit to one of the voltages of the plurality of power supply voltage terminals ;
The delay circuit that delays the AC voltage signal and the logic circuit that performs a logical operation on the AC voltage signal and the delay circuit signal each time the input current flows in the DCDC converter circuit is divided into a plurality of timings. A switching signal generation circuit for generating a control signal for switching the switch circuit;
Power supply, characterized in that it comprises a.   The power supply apparatus according to claim 2, wherein voltages from at least two power supplies are supplied to the plurality of power supply voltage terminals.   The power supply device according to claim 2, wherein a capacitor constituting a low-pass filter is connected to an input terminal of the DCDC converter circuit.   The DCDC converter circuit includes a transistor that intermittently supplies a current supplied from any one of the plurality of power supply voltage terminals to an inductor, and a control circuit that generates a switching control signal for the transistor in accordance with an output voltage. The power supply device according to claim 2, wherein the power supply device is a power supply device.

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