JP3875345B2 - Nonvolatile memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile memory device, and more particularly to a nonvolatile memory device capable of electrically writing and erasing data.
[0002]
[Prior art]
Conventionally, there is an EEPROM that can electrically write and erase information as one of nonvolatile storage devices.
[0003]
FIG. 11 is a block diagram schematically showing a basic configuration of a main part of a conventional nonvolatile memory device (EEPROM) 900. Referring to FIG. 11, nonvolatile storage device 900 includes a memory cell array 70, an X decoder 71, a Y gate 69, a data output buffer 68, and a Y decoder 72.
[0004]
Memory cell array 70 includes a plurality of memory cells arranged in a matrix in the row direction and the column direction. The memory cell array 70 is connected to the X decoder 71 and the Y gate 69. A Y decoder 72 and a data output buffer 68 are connected to the Y gate 69.
[0005]
X decoder 71 and Y gate 69 select the row direction and column direction of memory cell array 70, respectively. The Y decoder 72 controls selection in the column direction. The data output buffer 68 has a read circuit (sense amplifier) and is connected to an external output terminal (not shown).
[0006]
Next, the structure of the nonvolatile memory element 910 constituting the memory cell in the conventional nonvolatile memory device 900 will be described.
[0007]
FIG. 12 is a partial cross-sectional view showing a basic configuration of a nonvolatile memory element 910 that constitutes a conventional nonvolatile memory device 900.
[0008]
A nonvolatile memory element 910 illustrated in FIG. 12 is a memory element that configures an FLOTOX type (Floating gate Tunnel Oxide) EEPROM. Referring to FIG. 12, nonvolatile memory element 910 includes floating gate electrode layer 51, control gate electrode layer 53, interlayer insulating film 54, insulating film 55, tunnel oxide film 52, source / drain regions 56, 57, 58, And an impurity diffusion region 59.
[0009]
Source / drain regions 56, 57, 58 and impurity diffusion region 59 are formed on the main surface of P-type silicon substrate 40 at a predetermined interval.
[0010]
Floating gate electrode layer 51 is formed on the region from source / drain region 56 to impurity diffusion region 59 with insulating film 55 interposed.
[0011]
The control gate electrode layer 53 is formed on the floating gate electrode layer 51 with an interlayer insulating film 54 interposed.
[0012]
Further, the floating gate electrode layer 51 has a protruding portion. This protruding portion is formed on impurity diffusion region 59 with tunnel oxide film 52 interposed.
[0013]
Referring to FIG. 12, nonvolatile memory element 910 further includes select gate 50 and bit line 61.
[0014]
The select gate 50 is formed on a region from the source / drain region 57 to the source / drain region 58. A region sandwiched between the source / drain region 57 and the source / drain region 58 becomes conductive / non-conductive in response to a signal applied to the select gate 50.
[0015]
On the source / drain region 58, a contact hole 62 for taking out a potential is formed. Source / drain region 58 is connected to bit line 61 via contact hole 62. Information held in the memory transistor having the floating gate electrode layer 51 and the control gate electrode layer 53 as constituent elements is output from the bit line 61 to an external peripheral circuit via the Y gate 69 shown in FIG.
[0016]
Next, the operation of the nonvolatile memory element 910 illustrated in FIG. 12 will be described. The nonvolatile memory element 910 has three operation modes: writing, erasing, and reading. The nonvolatile memory element 910 stores information (written or erased state) according to the charged state of the floating gate electrode layer 51. Charges are injected into and discharged from the floating gate electrode layer 51 by using an FN (Fowler-Nordheim) tunnel current passing through the tunnel oxide film 52.
[0017]
In the erase operation, an erase voltage VPP (high voltage) is applied to the control gate electrode layer 53 and the select gate 50. At the same time, the bit line 61 is grounded, and the source / drain region 58 is set to the ground potential. As a result, electrons are injected from the impurity diffusion region 59 into the floating gate electrode layer 51, and the floating gate electrode layer 51 is negatively charged.
[0018]
When the floating gate electrode layer 51 is negatively charged, the threshold voltage Vth of the memory transistor formed below the control gate electrode layer 53 increases. This state is called an erased state (“1” state).
[0019]
In the write operation, the control gate electrode layer 53 is set to the ground potential, and a high voltage is applied to the select gate 50 and the source / drain region 58. As a result, electrons accumulated in the floating gate electrode layer 51 are emitted to the impurity diffusion region 59, and the floating gate electrode layer 51 is positively charged.
[0020]
When the floating gate electrode layer 51 is positively charged, the threshold voltage Vth decreases. This state is referred to as a write state (“0” state).
[0021]
In the read operation, a voltage intermediate between the threshold voltage Vth in the erase state and the write state is supplied to the control gate electrode layer 53. If the floating gate electrode layer 51 is positively charged (“0”), a channel is formed in the region ER 3 between the impurity diffusion region 59 and the source / drain region 56. On the other hand, if the floating gate electrode layer 51 is negatively charged (“1”), a channel is not formed in the region ER3.
[0022]
Therefore, when a voltage is applied to the control gate electrode layer 53, information of “0” (the region ER3 is in a conductive state) or “1” (the region ER3 is in a nonconductive state) is read by the current flowing through the bit line 61. It is.
[0023]
[Problems to be solved by the invention]
As described above, the conventional nonvolatile memory element 910 stores information by changing the charged state of the floating gate electrode layer 51 using the tunnel current.
[0024]
However, in order to inject and emit electrons to the floating gate electrode layer 51, it is necessary to apply a high voltage as described above. For this reason, when writing and erasing are performed many times, the tunnel oxide film 52 is deteriorated or broken due to high voltage stress.
[0025]
As a result, there is a problem that electrons injected into the floating gate electrode layer 51 escape through a minute leak in the tunnel oxide film 52, that is, a data retention failure occurs.
[0026]
FIG. 13 is a diagram showing the relationship between the failure rate of the conventional nonvolatile memory element 910 and the usage frequency. FIG. 13 is called a bathtub curve, where the horizontal axis indicates the usage time, and the vertical axis indicates the failure rate.
[0027]
Referring to FIG. 13, the period T0 is called an initial failure period. A failure that occurs relatively early immediately after the start of use, and is caused by a manufacturing process or the like.
[0028]
The period T1 is called an accidental failure period. It is a failure that occurs sporadically after the initial failure period. The failure rate is determined by design and represents a product-specific reliability.
[0029]
The period T2 is called a wear failure period. This failure increases with time, and is caused by wear and fatigue (including damage to the tunnel oxide film 52).
[0030]
As shown in a period T2 in FIG. 13, failures due to damage or the like of the tunnel oxide film 52 of the conventional nonvolatile memory element 910 increase rapidly according to the frequency of use.
[0031]
That is, as the frequency of use increases, the frequency of occurrence of data retention failures increases, and the reliability of the nonvolatile memory device 900 including the conventional nonvolatile memory element 910 as a constituent element is drastically reduced with use. There was a problem.
[0032]
Accordingly, the present invention has been made to solve these problems, and an object of the present invention is to provide a nonvolatile memory device including a highly reliable nonvolatile memory element that suppresses occurrence of data retention failure. It is to provide.
[0033]
It is another object of the present invention to provide a nonvolatile memory device that can determine the data retention state (occurrence of failure) of a nonvolatile memory element.
[0034]
Another object of the present invention is to provide a highly reliable non-volatile memory device that can accurately read stored information based on the result of determining the data holding state of the non-volatile memory element.
[0035]
[Means for Solving the Problems]
The nonvolatile memory device according to claim 1 is a nonvolatile memory device including a nonvolatile memory element that stores data by changing a threshold voltage of a transistor, and includes a plurality of nonvolatile memory elements. The nonvolatile memory element includes a first floating gate electrode layer for charging a charge, a first floating gate, and a determination unit that determines a storage state of the first storage unit. A second floating gate electrode layer for charging electric charges, insulated from the electrode layer, and an insulating film interposed above the first floating gate electrode layer and the second floating gate electrode layer A control gate electrode layer, and the first floating gate electrode layer and the second floating gate electrode layer are electrically connected to the transistor. Are arranged along the direction of flow of the determination means determines a charge state of the first floating gate electrode layer and the second floating gate electrode layer.
[0036]
The nonvolatile memory device according to claim 2 is the nonvolatile memory device according to claim 1, and further generates a voltage to be supplied to the control gate electrode layer of the nonvolatile memory element based on the determination result of the determining means. Voltage generating means, and when receiving the determination result that the charging state is the first state, the voltage generating means generates a predetermined voltage and is in a second state different from the first state. When the determination result is received, a voltage lower than a predetermined voltage is generated.
[0037]
The non-volatile storage device according to claim 3 is the non-volatile storage device according to claim 1, and is further stored in a second storage unit that stores a determination result of the determination unit, and a second storage unit Based on the determination result, voltage generation means for generating a voltage to be supplied to the control gate electrode layer of the nonvolatile memory element is provided, and the voltage generation means determines that the charged state from the second storage means is the first state. When a result is received, a predetermined voltage is generated, and when a determination result that the second state is different from the first state is received, a voltage lower than the predetermined voltage is generated. Item 10. The nonvolatile memory device according to Item 1.
[0038]
The nonvolatile memory device according to claim 4 is the nonvolatile memory device according to claim 2 or 3, wherein the first state is the first floating gate electrode layer and the second floating gate electrode layer. Are both charged, and the second state is a state in which the charge is released from either the first floating gate electrode layer or the second floating gate electrode layer.
[0039]
The non-volatile memory device according to claim 5 is the non-volatile memory device according to claim 1, further comprising device means for comparison, and the determining means compares the non-volatile memory element with the device means. By doing so, the storage state of the first storage means is determined.
[0040]
A nonvolatile memory device according to a sixth aspect is the nonvolatile memory device according to the fifth aspect, wherein the electrical characteristics of the nonvolatile memory element of the first memory means are different from the electrical characteristics of the device means.
[0041]
A nonvolatile memory device according to a seventh aspect is the nonvolatile memory device according to the fifth aspect, wherein the device means is configured such that one of the first floating gate electrode layer and the second floating gate electrode layer is charged. It is equivalent to a nonvolatile memory element in a state of having lost.
[0042]
DETAILED DESCRIPTION OF THE INVENTION
[Embodiment 1]
The first embodiment of the present invention is a nonvolatile memory device that includes a highly reliable nonvolatile memory element and makes it possible to determine its reliability (occurrence of data retention failure).
[0043]
A nonvolatile memory device according to Embodiment 1 of the present invention will be described. FIG. 1 is a diagram showing an example of a basic configuration of the nonvolatile memory device 100 according to Embodiment 1 of the present invention. The same components as those of the nonvolatile memory device 900 of FIG.
[0044]
Referring to FIG. 1, nonvolatile memory device 100 includes a memory cell array 70, an X decoder 71, a Y decoder 72, a Y selection circuit 73, a reference voltage generation circuit 74, and a read determination circuit 75.
[0045]
The memory cell array 70 is connected to the X decoder 71 and the Y selection circuit 73. Y selection circuit 73 is connected to Y decoder 72, reference voltage generation circuit 74, and read determination circuit 75. Read determination circuit 55 is connected to a data output buffer (not shown).
[0046]
The memory cell array 70 shown in FIG. 1 will be described. Referring to FIG. 1, memory cell array 70 of nonvolatile memory device 100 includes a transistor T and a memory cell M (i). The memory cell M (i) is composed of a nonvolatile memory element shown in FIGS.
[0047]
FIG. 2 is a cross-sectional view showing an example of the configuration of the nonvolatile memory element 110 used in Embodiment 1 of the present invention, and FIG. 3 shows the nonvolatile memory element 110 along the line ZZ ′ of FIG. Sectional drawing obtained when cutting is shown.
[0048]
2 to 3, the nonvolatile memory element 110 includes floating gate electrode layers 1, 2, a control gate electrode layer 3, an interlayer insulating film 4, an insulating film 5, source / drain regions 30, 31, 32, And impurity diffusion regions 33, 34, and 35.
[0049]
Source / drain regions 30, 31, 32 and impurity diffusion regions 33, 34, 35 are formed on the main surface of P-type silicon substrate 40 at a predetermined interval.
[0050]
Floating gate electrode layer 2 is formed on a region from impurity diffusion region 34 to impurity diffusion region 35 with insulating film 5 interposed.
[0051]
Floating gate electrode layer 1 is formed on the region reaching impurity diffusion regions 33, 34 and 35 with insulating film 5 interposed.
[0052]
Control gate electrode layer 3 is formed on floating gate electrode layers 1 and 2 with interlayer insulating film 4 interposed.
[0053]
Further, both floating gate electrode layers 1 and 2 have protruding portions. The protruding portion of floating gate electrode layer 1 is formed on impurity diffusion region 35 with tunnel oxide film 20 interposed. The protruding portion of the floating gate electrode layer 2 is also formed on the impurity diffusion region 35 with the tunnel oxide film 21 interposed therebetween.
[0054]
With reference to FIGS. 2 to 3, the nonvolatile memory element 110 further includes a select gate 10, a bit line 11, and an insulating film 13.
[0055]
The select gate 10 is formed on a region from the source / drain region 31 to the source / drain region 32.
[0056]
On the source / drain region 32, a contact hole 12 for taking out an electrode is formed. The source / drain region 32 is connected to the bit line 11 through the contact hole 12.
[0057]
The insulating film 13 is formed so as to cover the control gate electrode layer 3.
Subsequently, an operation of the nonvolatile memory element 110 according to Embodiment 1 of the present invention will be described.
[0058]
The nonvolatile memory element 110 stores information (written or erased state) according to the charged state of the floating gate electrode layers 1 and 2. Charges are injected into and released from the floating gate electrode layers 1 and 2 by using an FN tunnel current flowing through the tunnel oxide films 20 and 21.
[0059]
In the erase operation, electrons are injected into the floating gate electrode layers 1 and 2. First, erase voltage VPP is applied to control gate electrode layer 3 and select gate 10. At the same time, the bit line 11 is grounded, and the source / drain region 32 is set to the ground potential.
[0060]
As a result, electrons are injected (negatively charged) into the floating gate electrode layers 1 and 2 by the FN tunnel current flowing from the impurity diffusion region 35.
[0061]
Thus, when a read voltage is supplied to control gate electrode layer 3 during a read operation, region ER1 sandwiched between impurity diffusion region 33 and impurity diffusion region 34, and region sandwiched between impurity diffusion region 34 and impurity diffusion region 35. Both ER2 are in a non-conductive state. That is, the nonvolatile memory element 110 holds “1” (erased state) as information.
[0062]
Here, it is assumed that in one of the floating gate electrode layers 1, a data retention failure (electron escape) occurs. When a voltage is applied to the control gate electrode layer 3 in a state where electrons have escaped from the floating gate electrode layer 1, the region ER1 becomes conductive.
[0063]
However, if the other floating gate electrode layer 2 is normal, it holds a negatively charged state. Therefore, even when a voltage is applied to the control gate electrode layer 3, the region ER2 remains in a non-conductive state.
[0064]
As a result, even when a read voltage is supplied to the control gate electrode layer 3 during the read operation, the nonvolatile memory element 110 is not turned on and holds “1” (erased state) as information. Although not particularly described, even when a data retention failure occurs in the floating gate electrode layer 2, the nonvolatile memory element 110 can retain “1” as information.
[0065]
That is, even if electrons escape from the floating gate electrode layer 1, if the other floating gate electrode layer 2 is normal, the memory cell M (i) can hold information of “1” as a whole. By using the nonvolatile memory element 110 for the memory cell M (i), the reliability of the nonvolatile memory device 100 can be made higher than usual.
[0066]
For reference, FIG. 4 shows a connection relationship between the memory cell M (i) and each wiring. The symbols in FIG. 4 correspond to the control gate electrode layer 3, the floating gate electrode layers 1 and 2, and the select gate 10 of the nonvolatile memory element shown in FIGS. 2 to 4, control gate electrode layer 3 is connected to one conduction terminal of transistor T, and is connected to sense line SLj (j is an integer) from the other conduction terminal. One conduction terminal of the memory transistor composed of the floating gate electrode layers 1 and 2 and the control gate electrode layer 3 is connected to the array source ASG. Furthermore, one conduction terminal of the selection transistor formed of the selection gate 10 is connected to the bit line BLn (n is an integer). The selection gate 10 is connected to a word line WLm (m is an integer).
[0067]
Next, the Y selection circuit 73 shown in FIG. 1 will be described. The Y selection circuit 73 is connected to the bit lines BL0, BL1,... Of the memory cell array 70, and is further connected to the sense lines SL0, SL1,. The Y selection circuit 73 selects a predetermined bit line BL0 (or BL1,...) And a predetermined sense line SL0 (or SL1,...) Under the control of the Y decoder 72.
[0068]
The reference voltage generation circuit 74 generates a predetermined reference voltage Vref to be supplied to the control gate electrode layer 3 of the memory cell M (i).
[0069]
Read determination circuit 75 sends data read from memory cell array 70 to a data output buffer (not shown), and determines a data holding state of a predetermined memory cell M (i) when receiving a determination signal from the outside.
[0070]
The read determination circuit 75 is configured to verify the conduction state of the memory cell M (i) according to the current read from the memory cell M (i), for example, using a bias current.
[0071]
Next, with reference to FIGS. 1 to 4, a determination operation for determining a data retention failure in the nonvolatile memory device 100 according to Embodiment 1 of the present invention will be described. When receiving the determination signal from the outside, the nonvolatile memory device 100 determines the data retention state of the predetermined memory cell M (i).
[0072]
It is assumed that the word line WL0 is selected by the control of the X decoder 71, and the bit line BL0 and the sense line SL0 are respectively selected by the control of the Y decoder 72. In this case, memory cell M (1) of memory cell array 70 is selected, and data stored in memory cell M (1) is read.
[0073]
The reference voltage Vref output from the reference voltage generation circuit 74 is supplied to the control gate electrode layer 3 of the memory cell M (1). Inside the memory cell M (1), channels are formed in the regions ER1 and ER2 based on the charged state of the floating gate electrode layers 1 and 2. The memory cell M (1) has an impedance corresponding to the channel.
[0074]
Here, if electrons are injected into at least one of the floating gate electrode layers 1 and 2, a channel is difficult to be formed (it is difficult to be in a conductive state). Accordingly, the impedance is increased. On the other hand, if electrons are removed from the floating gate electrode layers 1 and 2, a channel is easily formed (becomes conductive). Therefore, the impedance is reduced.
[0075]
Read determination circuit 75 receives the current output from memory cell M (1) via Y selection circuit 73 and verifies it. Then, this result is output as a determination result (whether or not the data is held).
[0076]
The configurations of read determination circuit 75 and reference voltage generation circuit 74 are not limited to those shown above. According to the method described above, it is impossible to confirm the occurrence of electron loss (data retention failure) in either one of the floating gate electrode layers 1 and 2.
[0077]
Therefore, the following method may be used to check for data retention failure that occurs in one of floating gate electrode layers 1 and 2.
[0078]
FIG. 5 is a block diagram showing an example of the basic configuration of the nonvolatile memory device 200 according to Embodiment 1 of the present invention. The same components as those in the nonvolatile memory device 100 in FIG.
[0079]
Referring to FIG. 5, nonvolatile memory device 200 includes a reference voltage generation circuit 76 and a read determination circuit 77.
[0080]
When receiving the determination signal, the reference voltage generation circuit 76 shown in FIG. 5 outputs a reference voltage Vref having a value VH higher than the value V0 in the normal operation. For example, this value VH is set to a value that makes the memory cell M (i) in the “1” state (erased) conductive.
[0081]
When receiving the determination signal, read determination circuit 77 shown in FIG. 5 is set to a bias current and sensitivity different from those during normal operation.
[0082]
Next, with reference to FIG. 5, a determination operation for determining a data retention failure in the nonvolatile memory device 200 according to Embodiment 1 of the present invention will be described. When receiving the determination signal from the outside, the nonvolatile memory device 200 determines the data holding state of the predetermined memory cell M (i).
[0083]
It is assumed that the memory cell M (1) is in a selected state. For example, when no electron leakage occurs in any of the floating gate electrode layers 1 and 2 of the memory cell M (1) (normal state), the reference voltage Vref having a high value VH is set to the memory cell M (( 1). As a result, the memory cell M (1) becomes conductive. On the other hand, when any one of the electrons is lost, the impedance of the memory cell M (1) is lower than that in the normal state. This makes it easier for current to flow from the memory cell M (1).
[0084]
Read determination circuit 77 receives a current from memory cell M (1) in either a normal state or a state in which an electron loss has occurred. On the other hand, the read determination circuit 77 receives the determination signal and makes the sensitivity higher than that in the normal operation. Thereby, the charged state of the memory cell M (1) can be determined.
[0085]
It is also possible to replace the read determination circuit 77 with the read determination circuit 75 and change only the reference voltage Vref of the reference voltage determination circuit 76 for determination.
[0086]
As described above, the nonvolatile memory devices 100 and 200 according to the first embodiment of the present invention are configured with highly reliable nonvolatile memory elements, have a determination function, and have reliability in the nonvolatile memory elements ( Data retention failure) can be determined.
[0087]
[Embodiment 2]
Embodiment 2 of the present invention provides a nonvolatile memory device that includes a highly reliable nonvolatile memory element and accurately reads stored information even when a data retention failure occurs in part. It is possible.
[0088]
A nonvolatile memory device 300 according to Embodiment 2 of the present invention will be described. FIG. 6 is a block diagram showing an example of the basic configuration of the nonvolatile memory device 300 according to Embodiment 2 of the present invention. The same components as those in the nonvolatile memory device 100 in FIG.
[0089]
Referring to FIG. 6, nonvolatile memory device 300 includes a reference voltage generation circuit 78 and a read determination circuit 77.
[0090]
Read determination circuit 77 determines the data holding state of memory cell array 70 as described above, and outputs a determination result.
[0091]
The reference voltage generation circuit 78 generates a predetermined reference voltage Vref to be supplied to the control gate electrode layer 3 of the memory cell M (i) based on a control signal received from the outside. Here, the control signal is a signal having a one-to-one correspondence with the determination result output from the read determination circuit 75. Specifically, when the reference voltage generation circuit 78 receives a signal indicating a data retention failure as a control signal, the reference voltage generation circuit 78 generates and outputs a reference voltage Vref having a value VL (<V0) lower than that during normal operation.
[0092]
Next, with reference to FIG. 6, a read operation in nonvolatile memory device 300 according to Embodiment 2 of the present invention will be described. Note that the memory cell M (1) is in a selected state.
[0093]
When receiving the control signal, the reference voltage generation circuit 78 generates a reference voltage Vref to be supplied to the control gate electrode layer 3 of the memory cell M (1). For example, when an electron drop occurs in one of the floating gate electrode layers 1 and 2 inside the memory cell M (1), the value of the reference voltage Vref is VL.
[0094]
As a result, the memory cell M (1) becomes non-conductive although the impedance is low, so that “1” can be output as information. That is, information can be read from the floating gate electrode layer 1 (or 2) in a normal state in which no electrons are missing.
[0095]
As described above, the nonvolatile memory device 300 according to the second embodiment of the present invention includes a highly reliable nonvolatile memory element including two floating gates, and data retention failure occurs in any one of the floating gate electrode layers. Even if this occurs, the stored information can be read accurately based on the charged state of the other floating gate electrode layer.
[Embodiment 3]
Embodiment 3 of the present invention includes a memory for storing a result of determining a data retention failure in a nonvolatile storage device, and the stored information is accurately read out by adjusting the voltage using the stored determination result. It is possible to do that.
[0096]
FIG. 7 is a block diagram showing an example of a basic configuration of a main part of the nonvolatile memory device 400 according to Embodiment 3 of the present invention. Referring to FIG. 7, nonvolatile storage device 400 includes nonvolatile storage device 300, determination result storage unit 80, determination result writing circuit 81, and high voltage generation circuit 82.
[0097]
As described above, the reference voltage generation circuit 78 of the nonvolatile memory device 300 adjusts and outputs the reference voltage Vref in response to an instruction from the outside.
[0098]
As described above, the read determination circuit 77 of the nonvolatile memory device 300 determines the data holding state of the memory cell array 70 in response to an instruction from the outside.
[0099]
The determination result writing circuit 81 is connected to the read determination circuit 77. Determination result writing circuit 81 receives an output of read determination circuit 77 and a determination signal as inputs.
[0100]
High voltage generation circuit 82 is connected to the output side of determination result writing circuit 81. The determination result storage unit 80 is connected to the determination result writing circuit 81, the high voltage generation circuit 82, and the reference voltage generation circuit 78.
[0101]
Next, the operation of the nonvolatile memory device 400 according to Embodiment 3 of the present invention will be described with reference to FIG. It is assumed that the memory cell M (1) of the memory cell array 70 is in a selected state.
[0102]
At the time of data retention failure determination operation, read determination circuit 77 determines the data retention state of memory cell M (1) and outputs the determination result. When receiving the determination signal, the determination result writing circuit 81 performs control for writing the determination result output from the nonvolatile storage device 300 into the determination result storage unit 80. When receiving a write instruction from the determination result writing circuit 81, the high voltage generation circuit 83 supplies a voltage to the determination result storage unit 80.
[0103]
On the other hand, the determination result storage unit 80 stores a determination result upon receiving a write instruction from the determination result writing circuit 81 and further receiving a high voltage from the high voltage generation circuit 82.
[0104]
During the read operation, the determination result storage unit 80 outputs the stored determination result. The reference voltage generation circuit 78 receives this determination result as a control signal, and adjusts and outputs the reference voltage Vref based on this control signal.
[0105]
For example, when electrons are lost in the floating gate electrode layer 1 (or 2) of the memory cell M (1), the reference voltage Vref having a value VL lower than the normal value V0 is supplied as described above. As a result, the memory cell M (1) becomes non-conductive although the impedance is low. As a result, information “1” is read from the memory cell M (1).
[0106]
As described above, the nonvolatile memory device 400 according to Embodiment 3 of the present invention can store the determination result of the data holding state, and adjusts the voltage supplied to the memory cell M (i) based on this storage Therefore, the stored information can be read out accurately.
[0107]
[Embodiment 4]
Embodiment 4 of the present invention includes a device for comparison and determination in a nonvolatile memory device, and makes it possible to determine the occurrence of a data retention failure by comparing a memory cell and a device that are originally used. Is.
[0108]
FIG. 8 is a block diagram showing an example of a basic configuration of a main part of the nonvolatile memory device 500 according to Embodiment 4 of the present invention. The same components as those of the nonvolatile memory device 100 of FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted.
[0109]
Referring to FIG. 8, nonvolatile storage device 500 includes a read determination circuit 83 and an equivalent circuit 84.
[0110]
The equivalent circuit 84 is composed of memory cells DM. The impedance of the memory cell DM is lower than the impedance of the memory cell M (i). Specifically, the impedance is equivalent to a state in which electrons are removed from one of the floating gate electrode layers 1 (or 2) of the nonvolatile memory element 110 shown in FIGS.
[0111]
As such a memory cell DM, for example, the nonvolatile memory element 110 shown in FIGS. 2 to 3 that does not have the tunnel oxide film 20 (or 21), or one region ER1 (or And those not having one floating gate electrode layer 1 (or 2).
[0112]
Read determination circuit 83 is connected to memory cell array 70 and equivalent circuit 84. Read determination circuit 83 compares the data read from memory cell array 70 with the data read from equivalent circuit 84.
[0113]
FIG. 9 is a block diagram illustrating an example of a basic configuration of a main part of the read determination circuit 83 according to the fourth embodiment of the present invention. Referring to FIG. 9, read determination circuit 83 includes a differential amplifier AMP. One input of the differential amplifier AMP is connected to the memory cell array 70, and the other input is connected to the equivalent circuit 84.
[0114]
The differential amplifier AMP amplifies and outputs the difference between the current output from the memory cell M (i) and the current output from the memory cell DM. Note that symbols I0 and I1 in FIG. 9 indicate a bias current for the memory cell M (i) and a bias current for the memory cell DM, respectively.
[0115]
Next, with reference to FIG. 9, a determination operation for determining a data retention failure of the nonvolatile memory device 500 will be described. Here, “1” is stored by injecting electrons into the memory cell M (1) of the memory cell array 70 and the memory cell DM of the equivalent circuit 84 in advance.
[0116]
Assume that the memory cell M (1) and the memory cell DM are in a selected state during the determination operation. A reference voltage Vref having the same value is supplied to the memory cell M (1) and the memory cell DM from a reference voltage generation circuit (not shown). Read determination circuit 83 receives a determination signal from the outside, receives currents output from each of memory cell M (1) and memory cell DM, and compares them.
[0117]
As described above, since the memory cell DM has a high impedance, it is difficult to be in a conductive state. The memory cell M (1) has a higher impedance than the memory cell DM and is less likely to be conductive unless electrons are lost. Therefore, if the current output from memory cell M (1) is less than the current output from memory cell DM, read determination circuit 83 determines that memory cell M (1) is in the data holding state. On the other hand, if there is no difference in the amount of current, it is determined that electron leakage has occurred in the floating gate electrode layer 1 or 2 of the memory cell M (1).
[0118]
As described above, the nonvolatile memory device 500 according to the fourth embodiment of the present invention includes the dummy memory cell, so that the data holding state of the originally used memory cell array can be determined.
[0119]
Note that various states of the memory cell M (i) can be further detected by shifting the balance of the bias currents I0 and I1 in the differential amplifier AMP of the read determination circuit 83.
[0120]
For example, there is a method of increasing the bias current I0 corresponding to the memory cell array 70 by increasing the bias current I1 corresponding to the equivalent circuit 84.
[0121]
[Embodiment 5]
Embodiment 5 of the present invention includes a device for comparison and determination in a nonvolatile memory device, and determines the state in which electrons are gradually removed from the memory cell by comparing the originally used memory cell and the device. It is possible to do.
[0122]
As described with reference to FIG. 13, in the nonvolatile memory element, even when data is normally written and stored, electrons are gradually lost over time, and data retention failure may occur later. The nonvolatile memory device 600 according to the fifth embodiment of the present invention can determine such a state where electrons are gradually removed.
[0123]
FIG. 10 is a block diagram showing an example of the basic configuration of the main part of the nonvolatile memory device 600 according to Embodiment 5 of the present invention. The same components as those of the nonvolatile memory device 100 of FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted.
[0124]
Referring to FIG. 10, nonvolatile storage device 600 includes a read determination circuit 85 and an equivalent circuit 86.
[0125]
The equivalent circuit 86 is composed of memory cells DN. The memory cell DN is composed of two storage elements X1 and X2 connected in parallel. Here, the memory element X2 corresponds to the nonvolatile memory element 110 having the floating gate electrode layers 1 and 2 shown in FIG. 2, and the memory element X1 is a nonvolatile memory composed of one floating gate electrode layer 51 shown in FIG. This corresponds to the memory element 910. X1 may be an equivalent circuit 84.
[0126]
Here, the impedance Z0 of the memory cell DN is expressed by the following equation (1).
[0127]
Z0 = (Z1 + Z2) / 2 (1)
Z1 represents the impedance of the memory element X1, and Z2 represents the impedance of the memory element X2.
[0128]
The read determination circuit 85 includes a differential amplifier AMP. A symbol I0 in FIG. 10 indicates a bias current. The bias current for the memory cell M (i) is I0, and the bias current for the memory cell DN is 2 × I0. The differential amplifier AMP amplifies and outputs the difference between the current output from the memory cell M (i) and the current output from the memory cell DN (i).
[0129]
Next, with reference to FIG. 10, a determination operation for determining a data retention failure of the nonvolatile storage device 600 will be described. Here, it is assumed that the memory cell M (1) of the memory cell array 70 and the memory cell DN of the equivalent circuit 86 are preliminarily injected with “1”.
[0130]
Assume that the memory cell M (1) and the memory cell DN are selected during the determination operation. A reference voltage Vref having the same value is supplied to the memory cell M (1) and the memory cell DN (1) from a reference voltage generation circuit (not shown). Read determination circuit 85 receives a determination signal from the outside, receives currents output from memory cell M (1) and memory cell DN, and compares them.
[0131]
As described above, the impedance of the memory cell DN is an intermediate value between the impedance of the memory element X1 and the impedance of the memory element X2. On the other hand, the impedance of the memory cell M (1) is equivalent to the impedance of the memory element X2 immediately after writing. When electrons gradually escape from one floating gate electrode layer 1 (or 2), the impedance approaches the impedance of the memory cell DN.
[0132]
Therefore, by comparing the output current of the memory cell M (1) with the output current of the memory cell DN using the read determination circuit 85, one floating gate electrode layer 1 (or the memory cell M (1)) (or In 2), a state in which half of the electrons are missing can be detected.
[0133]
Note that the configuration of the memory cell DN is not limited to that shown above. That is, it is possible to further determine various states of the memory cell M (i) by shifting the characteristics (impedance) of the memory cell M (i) to be determined and the characteristics of the memory cell DN.
[0134]
【The invention's effect】
As described above, according to the nonvolatile memory device of the present invention, the reliability can be improved by including the nonvolatile memory element having the plurality of floating gate electrode layers.
[0135]
Furthermore, according to the present invention, it is possible to determine the data retention state (occurrence of failure) of the nonvolatile memory element.
[0136]
Furthermore, according to the present invention, the stored information can be accurately read by adjusting the voltage using the result of determining the data retention state of the nonvolatile memory element.
[Brief description of the drawings]
FIG. 1 is a diagram showing an example of a basic configuration of a nonvolatile memory device 100 according to a first embodiment of the present invention.
FIG. 2 is a plan view schematically showing an example of a basic configuration of a nonvolatile memory element 110 according to Embodiment 1 of the present invention.
FIG. 3 is a cross-sectional view schematically showing an example of the basic configuration of the nonvolatile memory element 110 according to Embodiment 1 of the present invention.
4 is a diagram showing a relationship between the nonvolatile memory element 110 and each wiring in the memory cell according to the first embodiment of the present invention. FIG.
FIG. 5 is a block diagram showing an example of a basic configuration of the nonvolatile memory device 200 according to Embodiment 1 of the present invention.
FIG. 6 is a block diagram showing an example of a basic configuration of a nonvolatile memory device 300 according to Embodiment 2 of the present invention.
FIG. 7 is a block diagram showing an example of a basic configuration of a main part of a nonvolatile memory device 400 according to Embodiment 3 of the present invention.
FIG. 8 is a block diagram showing an example of a basic configuration of a main part of a nonvolatile memory device 500 according to Embodiment 4 of the present invention.
FIG. 9 is a block diagram illustrating an example of a basic configuration of a main part of a read determination circuit 83 according to a fourth embodiment of the present invention.
FIG. 10 is a block diagram illustrating an example of a basic configuration of a main part of a read determination circuit 85 according to a fifth embodiment of the present invention.
11 is a diagram illustrating an example of a basic configuration of a main part of a conventional nonvolatile memory device 900. FIG.
12 is a plan view schematically showing an example of a basic configuration of a conventional nonvolatile memory element 910. FIG.
FIG. 13 is a diagram for explaining a failure rate in a conventional nonvolatile memory element.
[Explanation of symbols]
100-600, 900 Nonvolatile memory device
1, 2 Floating gate electrode layer
3 Control gate electrode layer
4 Interlayer insulation film
5, 13 Insulating film
10 Selection gate
11 bit line
20, 21 Tunnel oxide film
30, 31, 32 Source / drain regions
33, 34, 35 Impurity diffusion region
40 P-type silicon substrate
68 Data output buffer
69 Y gate
70 memory cell array
71 X decoder
72 Y decoder
73 Y selection circuit
74, 76, 78 Reference voltage generation circuit
75, 77, 83, 85 Read determination circuit
80 judgment result storage
81 Judgment result writing circuit
82 High voltage generator
84, 86 Equivalent circuit
110,910 Nonvolatile memory element
M (i), DM, DN Memory cell

Claims (7)

A non-volatile memory device composed of a non-volatile memory element that stores data by changing a threshold voltage of a transistor,
First storage means including a plurality of the nonvolatile storage elements;
Determination means for determining a storage state of the first storage means,
The nonvolatile memory element is
A first floating gate electrode layer for charging the charge;
A second floating gate electrode layer for charging a charge, insulated from the first floating gate electrode layer;
A control gate electrode layer formed above the first floating gate electrode layer and the second floating gate electrode layer with an insulating film interposed therebetween,
The first floating gate electrode layer and the second floating gate electrode layer are disposed along a direction of current flow of the transistor,
The non-volatile memory device, wherein the determination unit determines a charged state of the first floating gate electrode layer and the second floating gate electrode layer. And a voltage generating means for generating a voltage to be supplied to the control gate electrode layer of the nonvolatile memory element based on the determination result of the determining means.
The voltage generation means generates a predetermined voltage when receiving a determination result that the charging state is the first state, and determines that the second state is different from the first state. The nonvolatile memory device according to claim 1, wherein when receiving the result, a voltage lower than the predetermined voltage is generated. And second storage means for storing the determination result of the determination means;
Voltage generating means for generating a voltage to be supplied to the control gate electrode layer of the nonvolatile memory element based on the determination result stored in the second memory means is provided, and the voltage generating means includes the second memory. When the determination result that the charging state is the first state is received from the means, a predetermined voltage is generated and the determination result that the second state is different from the first state is received. The nonvolatile memory device according to claim 1, wherein a voltage lower than the predetermined voltage is generated. The first state is a state in which the first floating gate electrode layer and the second floating gate electrode layer are both charged with the charge.
4. The nonvolatile state according to claim 2, wherein the second state is a state in which the electric charge is released from either the first floating gate electrode layer or the second floating gate electrode layer. 5. Storage device. Furthermore, it comprises device means for comparison,
The nonvolatile memory device according to claim 1, wherein the determination unit determines a storage state of the first storage unit by comparing the nonvolatile storage element with the device unit. The nonvolatile memory device according to claim 5, wherein electrical characteristics of the nonvolatile memory element of the first memory unit are different from electrical characteristics of the device unit. 6. The device means according to claim 5, wherein the device means is equivalent to the nonvolatile memory element in a state in which either the first floating gate electrode layer or the second floating gate electrode layer has lost the charge. Non-volatile storage device.

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