JP3873055B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device, and in particular, a magnetic random access memory (MRAM) using an MTJ (Magnetic Tunnel Junction) element utilizing a tunneling magnetoresistive effect as a memory cell. The configuration of the magnetic memory cell and the configuration of the memory cell array in FIG.

  MRAM is a device that stores information using the tunnel magnetoresistive effect, and is expected to be a memory device that can be replaced from DRAM, EEPROM, etc. because it combines non-volatility, high-speed operation, high integration, and high reliability. The development is underway (see Non-Patent Documents 1 to 3 and Patent Documents 1 to 4).

  An MTJ element used in an MRAM memory cell has a structure in which one ferromagnetic film is sandwiched between two ferromagnetic films, and the spin directions of the ferromagnetic films are parallel to each other. It has a tunneling magnetoresistive effect, in which the magnitude of the tunneling current changes when it becomes antiparallel.

  When the spin direction is parallel, the tunnel current increases, so the resistance value of the MTJ element is low. When the spin direction is antiparallel, the tunnel current decreases, and the resistance value of the MTJ element is low. Becomes higher. In the MRAM, information is stored as “0” data when the resistance value of the MTJ element is low and as “1” data when the resistance value is high.

  FIG. 37 is an equivalent circuit diagram showing a typical 1Tr-1MTJ memory cell of the MRAM disclosed in FIG. 8.2.1 (b) of Non-Patent Document 1, for example.

  In the figure, 11 is a memory cell, 12 is an MTJ element, 13 is a selection transistor, GND is a ground electrode, BL is a bit line, WWL is a write word line, and RWL is a read word line.

  FIG. 38 is a diagram schematically showing a layout in the vertical plane of the cross-sectional structure of the 1Tr-1MTJ type memory cell shown in FIG.

  The semiconductor substrate 14 is divided into a plurality of element regions by an element isolation region 15 made of STI (Shallow Trench Isolation). The selection transistor 13 is formed in one element region. Reference numeral 16 denotes a gate oxide film of the selection transistor 13, reference numerals 17 and 17 denote diffusion layers which are also sources and drains, and reference numeral 18 denotes a gate electrode. M0 is the first wiring layer, M1 is the second wiring layer, M2 is the third wiring layer, CD is the contact connecting the first wiring layer M0 and the diffusion layer 17, and C1 is the second wiring layer M1 and the second wiring layer. A contact connecting one wiring layer M0, MX is a wiring layer for MTJ connection, and CX is a contact connecting the wiring layer MX for MTJ connection and the second wiring layer M1. In FIG. 38, WWL, RWL, BL, and GND indicate the use of each wiring layer, WWL indicates a write word line, RWL indicates a read word line, BL indicates a bit line, and GND indicates a ground electrode. . As shown in FIG. 38, the bit line BL and the write word line WWL are arranged to extend in directions orthogonal to each other.

  When data is written to the memory cell 11, data is written by generating a combined magnetic field in the MTJ element 12 by passing a current through the bit line BL and the write word line WWL. When reading data from the memory cell 11, the read word line RWL is activated, a current is passed from the bit line BL to the ground electrode GND, and the data is read by a sense amplifier connected to the bit line BL.

  Consider a case where data is read from the conventional magnetic memory cell shown in FIG.

  FIG. 39A is a conceptual diagram of a system in which a constant current is passed through a magnetic memory cell and data from the magnetic memory cell is converted into a voltage and read.

  In FIG. 39A, 21 is a constant current source, 22 is a voltmeter, 11 is a magnetic memory cell, Rmc is a resistance value of the magnetic memory cell 11, and i is a current flowing through the magnetic memory cell 11. The voltage value Vsignal indicated by the voltmeter 22 is Vsignal = Rmc × i, that is, the product of the current i flowing through the magnetic memory cell 11 and the resistance value Rmc of the magnetic memory cell 11.

  FIG. 39B is a conceptual diagram of a method of reading data by applying a constant voltage to the magnetic memory cell and converting data from the magnetic memory cell into current.

  In FIG. 39B, 23 is a constant voltage source, 24 is an ammeter, 11 is a magnetic memory cell, Rmc is a resistance value of the magnetic memory cell 11, and v is a voltage applied to the magnetic memory cell 11.

  The current value Isignal indicated by the ammeter 24 is Isignal = v / Rmc, that is, the quotient of the voltage v applied to the magnetic memory cell 11 and the resistance value Rmc of the magnetic memory cell 11.

  As can be seen from these read voltage or read current equations, in the conventional read method, the amount of signal read from the magnetic memory cell depends on the absolute value of the resistance value Rmc of the magnetic memory cell. Accordingly, when the resistance value of the magnetoresistive element varies between the memory chips, there is a problem that the variation amount directly affects the read signal amount.

  In addition, there is a problem in that the amount of read signal varies depending on the parasitic resistance of a path through which a current flows to the magnetic memory cell or a path through which a voltage is applied. That is, because the distance between the constant current source or constant voltage source and the sense amplifier differs depending on the position of the MRAM cell in the memory cell array, for example, the absolute value of the read signal differs between different magnetic memory cells even in the same column. There is a problem that.

  On the other hand, an MRAM having a 1Tr + 2MTJ configuration as shown in FIGS. 22 and 23 of Patent Document 5 has been proposed as a method for reading the resistance ratio of two MTJ elements. In this example, two MTJ elements are connected in series, and a memory cell configuration is adopted in which the drain of a transistor is connected to an intermediate node thereof. The source of the transistor is connected to a sense amplifier via a bit line. In this example, since the resistance ratio of the two MTJ elements is read, there is an advantage that the resistance to variations in resistance of the MTJ elements is high.

  However, the current path between the pair of bit lines cannot be interrupted. Therefore, there is a problem in that the effective applied voltage to the memory cell is lowered during the read operation and the read signal amount is lowered. In addition, during the write operation, current flows from one bit line to the other bit line through all the memory cells connected in parallel between the bit lines, so that the effective write current decreases. However, there is a problem that the write current supplied from the write driver must be increased.

As described above, the conventional MRAM has a problem that when the resistance value of the magnetoresistive element of the MRAM cell varies, the variation amount directly affects the read signal amount. Further, there is a problem that the absolute value of the read signal differs depending on the position of the MRAM cell in the memory cell array.
Roy Scheuerlein et.al. "A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell", ISSCC2000 Technical Digest pp.128 to 129. ISSCC2000 Technical Digest pp.130-131 ISSCC2001 Technical Digest pp.122 to pp.123 JP 2002-25245 A U.S. Pat.No. 5,946,227 U.S. Pat.No. 5,986,925 U.S. Pat.No. 6,545,906 JP 2001-236781 A

  The present invention has been made to solve the above problems, and stabilizes the read signal amount of the MRAM cell regardless of variations in the resistance value of the magnetoresistive element of the MRAM cell and the position of the MRAM cell in the memory cell array. An object of the present invention is to provide a semiconductor memory device that enables a large-scale memory cell array configuration while preventing an increase in the read operation speed of the MRAM, and can reduce the chip area and the chip cost.

  The semiconductor memory device of the present invention includes a first magnetoresistive element and a second magnetoresistive element each having a tunnel magnetoresistive effect and holding data opposite to each other, and at least one transfer gate. A magnetic memory cell in which a second magnetoresistive element is inserted in series between both ends and the at least one transfer gate is connected in series to the first and second magnetoresistive elements; and the magnetic memory First and second bit lines respectively connected to both ends of the cell, a first word line for writing disposed in the magnetic memory cell, and a first data reading line connected to the magnetic memory cell 3 bit lines and a second word line for reading connected to the gate electrode of the at least one transfer gate.

  According to the semiconductor memory device of the present invention, the read signal amount of the magnetic memory cell is stabilized regardless of variations in the resistance value of the magnetoresistive element of the magnetic memory cell and the position of the magnetic memory cell in the memory cell array. While preventing an increase in the cell reading operation speed, a large-scale memory cell array configuration can be realized, and the chip area and the chip cost can be reduced.

<Principle of the present invention>
FIG. 1 is an equivalent circuit diagram showing one magnetic memory cell in a memory cell array in an MRAM used for explaining the principle of the present invention.

  The magnetic memory cell 31 has a configuration in which two MTJ elements MTJ [0] and MTJ [1] each having a tunnel magnetoresistive effect are connected in series between both ends. That is, the magnetic memory cell 31 of this MRAM is of 2MTJ type. In this case, the two MTJ elements MTJ [0] and MTJ [1] store data opposite to each other. In the following description, when the two MTJ elements MTJ [0] and MTJ [1] are expressed without distinction, they are simply denoted as MTJ.

  WBL [0] and WBL [1] are write bit lines for writing data to the magnetic memory cell 31. One write bit line WBL [0] is connected to one end of one MTJ element MTJ [0]. The other write bit line WBL [1] is connected to one end of the other MTJ element MTJ [1]. A write word line WWL is arranged in the magnetic memory cell 31. The write word line WWL is used for selecting the magnetic memory cell 31 at the time of data writing. The other ends of one and the other MTJ elements MTJ [0] and MTJ [1] are connected in common, and a read bit line RBL is connected to the common connection node. Data is read from the read bit line RBL when data is read from the magnetic memory cell 31.

  The write bit lines WBL [0] and WBL [1] are arranged in parallel to each other, and the write word line WWL is arranged in a direction perpendicular to them. When the write bit lines WBL [0] and WBL [1] and the write word line WWL are arranged so as to cross each other in this way, the write bit lines WBL [0], WBL [1] and the write word line WWL The MTJ elements MTJ [0] and MTJ [1] can be arranged corresponding to the respective intersections.

  Normally, one cell array unit is formed by a memory cell array in which a plurality of magnetic memory cells 31 are arranged in a matrix, a plurality of write word lines WWL, a plurality of pairs of write bit lines WBL [0], WBL [1], and the like. And a plurality of cell array units are stacked on a semiconductor substrate to form a cell array stacked structure.

  When writing data to the magnetic memory cell 31, a current is passed through the write word line WWL and the write bit lines WBL [0], WBL [1], and the MTJ element MTJ [0 is generated by a combined magnetic field generated by the current. ], MTJ [1] is achieved by reversing the spin directions of each other (parallel or antiparallel). In this case, a current that flows in a certain direction is supplied to the write word line WWL, and currents that are opposite to each other are supplied to the write bit lines WBL [0] and WBL [1] according to the write data.

  When reading data from the magnetic memory cell 31, a potential V0 is applied to one write bit line WBL [0], and a potential V1 different from V0 is applied to the other write bit line WBL [1]. As a result, a predetermined potential difference is given between both ends of the magnetic memory cell 31. At this time, the potential determined by the ratio of the resistance value of the MTJ element MTJ [0] or MTJ [1] and the combined resistance of the MTJ elements MTJ [0] and MTJ [1] is read as data to the read bit line RBL. .

  Next, the amount of read signal will be considered.

  The resistance value of the MTJ element in the state where “1” data is stored is Ra, and the resistance value of the MTJ element in the state where “0” data is stored is Rp, and a predetermined magnetic field is applied to the MTJ element. The change ratio MR ratio of the resistance value before and after is expressed by (Ra−Rp) / Rp = (Ra / Rp) −1. Here, Ra = (1 + MR) × Rp is defined.

Further, when the storage data of one MTJ element MTJ [0] is “0” and the storage data of the other MTJ element MTJ [1] is “1”, the data “1” is stored in the magnetic memory cell 31. “0” is stored in the magnetic memory cell 31 when the storage data of one MTJ element MTJ [0] is “1” and the storage data of the other MTJ element MTJ [1] is “0”. It is defined that When the storage data of the magnetic memory cell 31 is “1”, the potential Vsig1 of the read bit line RBL is
Vsig1 = {Ra / (Ra + Rp)} × (V0−V1) (1)
Given in. Similarly, when the data stored in the magnetic memory cell 31 is “0”, the potential Vsig0 of the read bit line RBL is
Vsig0 = {Rp / (Ra + Rp)} × (V0−V1) (2)
Given in. Rewriting these formulas 1 and 2 using the previous change rate MR,
Vsig1 = {(1 + MR) / (2 + MR)} × (V0−V1) (3)
Vsig0 = {1 / (2 + MR)} × (V0−V1) (4)
It becomes. Here, the average value of Vsig0 and Vsig1, that is, the reference potential Vref at the time of reading is given as follows.

Vref = (Vsig0 + Vsig1) / 2 = (V0−V1) / 2 (5)
That is, according to the magnetic memory cell 31 described above, two MTJ elements are connected in series, and data opposite to each other is stored in the two MTJ elements. When reading data from the magnetic memory cell 31, it is performed by giving a potential difference between both ends of the magnetic memory cell 31 and reading the potential of the connection node between the two MTJ elements. It depends on the resistance ratio of the two MTJ elements without depending on the absolute value of the resistance of the MTJ element.

  Due to this principle of operation, even if the resistance of the MTJ element varies between different memory chips, the absolute value of the read signal voltage does not change, and a constant read margin is secured. There is no need to adjust every time.

  Further, the reference potential input to the sense amplifier at the time of reading does not depend on the resistance value of the MTJ element, and is half of the potential difference applied to both ends of the memory cell, that is, between “1” data and “0” data. It can be a potential. For this reason, it is not necessary to adjust the reference potential for each chip even when the resistance value of the MTJ element varies between different chips.

  Further, in the read operation, a feedback system circuit such as a constant current source and a voltage clamp circuit required in the conventional example is not necessary. For this reason, the sense circuit is simplified, and the layout area of the core circuit can be reduced. For example, when a latch-type sense amplifier similar to that in the case of DRAM is employed, functions such as burst reading can be realized.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<First Embodiment>
FIG. 2A is an equivalent circuit diagram showing one magnetic memory cell in the memory cell array in the MRAM according to the first embodiment of the present invention.

  The magnetic memory cell of this embodiment is a cell selection transfer between the other end of one MTJ element MTJ [0] and the read bit line RBL, as compared with the 2MTJ type magnetic memory cell of FIG. A difference is that a gate 32 is inserted and a transfer gate 33 for cell selection is inserted between the other end of the other MTJ element MTJ [1] and the read bit line RBL. NMOSFETs are used as the two transfer gates 32 and 33, respectively, and each gate electrode is connected to the read word line RWL. A series connection node of the two cell selection transfer gates 32 and 33 serves as a data read node and is connected to the read bit line RBL.

  That is, the magnetic memory cell 31 of the MRAM according to the first embodiment is a 2Tr-2MTJ type memory cell composed of two MTJ elements and a MOSFET.

  In the operation of the magnetic memory cell 31 shown in FIG. 2A, the on / off states of the two cell selection transfer gates 32 and 33 are controlled by the read word line RWL as compared with the operation of the magnetic memory cell in FIG. Basically the same except for the points.

  In the first embodiment, if the on-resistances of the transfer gates 32 and 33 are sufficiently small, the value of the read signal is determined by the resistance ratio of the two MTJ elements as in the case of the MRAM in FIG.

  Thus, in the MRAM according to the first embodiment, one transfer gate is provided between the read word line RBL and each MTJ element. For this reason, a sneak current through the read bit line RBL is cut off between the activated memory cell in the cell array, that is, the selected magnetic memory cell, and the deactivated memory cell, that is, the unselected magnetic memory cell. Thus, a reliable read operation can be realized.

  FIG. 2B is a cross-sectional view schematically showing a part of the element structure of the 2Tr-2MTJ type memory cell shown in FIG.

  The cell selection transfer gate 32 or 33 is formed in an active region partitioned by an element isolation region 35 made of STI (Shallow Trench Isolation) formed in the semiconductor substrate 34. 36 is a gate oxide film of the transfer gate 32 or 33, 37 and 37 are diffusion layers which are also the source and drain, and 38 is a gate electrode. M0 is the first wiring layer, M1 is the second wiring layer, M2 is the third wiring layer, CD is the contact connecting the first wiring layer M0 and the diffusion layer 37, and C1 is the second wiring layer M1 and the second wiring layer. A contact connecting one wiring layer M0, MX is a wiring layer for MTJ connection, and CX is a contact connecting the wiring layer MX for MTJ connection and the second wiring layer M1.

  In FIG. 2B, WWL, RWL, WBL, and RBL indicate the use of each wiring layer, WWL is a write word line, RWL is a read word line, WBL is a write bit line, and RBL. Represents a read bit line.

  As shown in FIG. 2B, the write word line WWL and the write bit line WBL are arranged in directions orthogonal to each other, and at each crossing position of the write word line WWL and the write bit line WBL. Correspondingly, MTJ elements are arranged. In this case, an example in which the read bit line RBL is arranged in parallel with the write bit line WBL is shown.

  In FIG. 2B, the write word line WWL is constituted by the second wiring layer M1 which is the lower wiring routed below the MJT element, and writing is performed by the third wiring layer M2 which is the upper wiring of the MJT element. Although the case where the bit line WBL is configured is shown, the present invention is not limited to this, and the present invention can also be applied when other wiring structures are adopted.

  FIG. 3 shows an example of the planar layout of the contact C1 and the lower layer portion in FIG. 2B, and FIG. 4 shows an example of the planar layout of the contact C1 and the upper layer portion in FIG. 2B. Show. Note that AA in FIG. 3 is an active region divided by the element isolation region 35, and GC corresponds to the gate electrode 38 of the cell selection transfer gate 32 or 33.

<First Modification of First Embodiment>
5 and 6 show an example in which the magnetoresistive element disclosed in Patent Document 4 is applied to the magnetic memory cell of the first embodiment. FIG. 5 shows the contact in FIG. FIG. 6 shows an example of the planar layout of the contact C1 and the upper layer portion in FIG. 2B. The planar layout of FIG. 5 is the same as the planar layout of FIG. The difference between FIG. 6 and FIG. 4 is that the MTJ element is disposed at an inclination of 45 degrees with respect to two intersecting write wirings (WBL, WWL).

  As shown in Patent Document 4, the write operation in this example is performed by a magnetic field generated by passing a current in one direction through each of the write word line WWL and the write bit line WBL.

  Specifically, the write operation is performed by the following four-step write procedure. First, as a first step, a current flowing from the bottom to the top of the drawing is applied to the write word line WWL, and the two ferromagnetic layers forming the free layer rotate while maintaining antiferromagnetic coupling to synthesize them. The magnetic field is directed to the direction of the magnetic field due to the current flowing through the WWL. Next, as a second stage, the current is passed through the write word line WWL while the current is passed through the write bit line WBL from the right to the left in the drawing, and the two ferromagnetic layers forming the free layer are repulsive. The magnetic field is rotated while maintaining the magnetic coupling so that the resultant magnetic field faces the direction of the resultant magnetic field due to the current flowing through WWL and WBL. Next, as a third stage, the current flowing through the write word line WWL is stopped and only the current flowing through the write bit line WBL is rotated, while the two ferromagnetic layers forming the free layer rotate while maintaining antiferromagnetic coupling. Thus, the combined magnetic field is directed to the direction of the magnetic field due to the current flowing through the write bit line WBL. Finally, as the fourth stage, the current flowing through the write bit line WBL is stopped and the application of the magnetic field to the magnetoresistive element is terminated, so that the magnetization directions of the two ferromagnetic layers forming the free layer are stabilized. Align in a certain easy axial direction.

  As described above, the write operation of the magnetoresistive element in this example is performed by a special write procedure as compared with the conventional case. However, the magnetoresistance characteristics are the same as the conventional one, and the magnetoresistance value is determined by the relative relationship between the magnetization direction of the fixed layer and the magnetization direction of the free layer. Therefore, the read operation is the same as the conventional one. By replacing only the magnetoresistive element in the memory cell in the present embodiment with the magnetoresistive element described in Patent Document 4, the read operation similar to the first embodiment is performed. It can be performed.

<Second Modification of First Embodiment>
FIG. 7 is an equivalent circuit diagram showing one magnetic memory cell in the memory cell array in the MRAM according to the second modification of the first embodiment of the present invention.

  The magnetic memory cell shown in FIG. 7 has a cell selection transfer gate 32 on the write bit line WBL [0] side of one MTJ element MTJ [0] as compared with the magnetic memory cell shown in FIG. Is inserted, and the cell selection transfer gate 33 is inserted on the write bit line WBL [1] side of the other MTJ element MTJ [1], and two MTJ elements MTJ [0] and MTJ [1 ] Is a data read node, and the others are the same.

<Second Embodiment>
FIG. 8A is an equivalent circuit diagram showing one magnetic memory cell in the memory cell array in the MRAM according to the second embodiment of the present invention.

  The magnetic memory cell shown in FIG. 8A is a 3Tr-2MTJ type magnetic memory cell composed of two MTJ elements and three transfer gate NMOSFETs. In the magnetic memory cell 31, a cell selection transfer gate 39 is inserted between the MTJ elements MTJ [0] and MTJ [1], and the connection node between the MTJ element MTJ [0] and one end of the transfer gate 39 is connected to the first node. One end of one read transfer gate 40 is connected, and one end of a second read transfer gate 41 is connected to a connection node between the MTJ element MTJ [1] and the cell selection transfer gate 39, and these two readouts The other ends of the transfer gates 40 and 41 are connected to the read bit line RBL in common. The gate electrodes of the transfer gates 39, 40 and 41 are connected in common to the read word line RWL.

  The operation of the 3Tr-2MTJ type magnetic memory cell shown in FIG. 8A is the on / off operation of the three cell selection transfer gates 39, 40, 41 compared to the 2MTJ type magnetic memory cell shown in FIG. The state is basically the same except that the state is controlled by the read word line RWL.

  As described above, the transfer gate 39 is inserted between the MTJ elements MTJ [0] and MTJ [1], and the transfer gates 40 and 41 are provided between the MTJ elements MTJ and the read bit line RBL. Thus, the activated memory cell and the deactivated memory cell in the cell array can be separated so as to block the sneak current through the read bit line RBL, and a reliable read operation can be realized.

  FIG. 8B is a cross-sectional view schematically showing a part of the element structure of the 3Tr-2MTJ type memory cell shown in FIG. Here, the transfer gate 40 or 41 is formed in an active region partitioned by an element isolation region 35 formed in the semiconductor substrate 34.

  9 shows an example of the planar layout of the contact C1 and the lower layer portion in FIG. 8B, and FIG. 10 shows an example of the planar layout of the contact C1 and the upper layer portion in FIG. 8B. Show. As shown in FIG. 9, there is a region where the active region AA is not provided at a position where the first wiring layer M0 extends in the lateral direction between the two MTJ elements. Note that GC in FIG. 9 corresponds to the gate electrode 38 of the cell selection transfer gate 40 or 41.

  In this embodiment, the magnetoresistive element described in Patent Document 4 is applied by replacing the planar layout of the contact C1 and the upper layer portion in FIG. 8B with that of FIG. be able to.

<Modification of Second Embodiment>
FIG. 11 shows another example of the planar layout of the lower layer shown in FIG. In the planar layout of FIG. 11, compared with the planar layout of FIG. 9, the active area AA is continuously provided also at the position where the first wiring layer M0 is extended in the lateral direction between the two MTJ elements. The other points are the same, and the others are the same.

  The concave portion of the active area AA in FIG. 9 is expected to be difficult to lithography when the pattern is miniaturized. Therefore, it can be said that the layout without such a recess is a layout pattern more suitable for miniaturization.

  Also in this modification, the magnetoresistive element described in Patent Document 4 can be applied by replacing the layout of the upper layer portion from C1 with that of FIG.

<Third Embodiment>
FIG. 12A is an equivalent circuit diagram showing one magnetic memory cell in the memory cell array in the MRAM according to the third embodiment of the present invention.

  The magnetic memory cell shown in FIG. 12A differs from the magnetic memory cell shown in FIG. 8A in that the second read transfer gate 41 is omitted. That is, the magnetic memory cell shown in FIG. 12A is a 2Tr-2MTJ type magnetic memory cell.

  In other words, the 2Tr-2MTJ type magnetic memory cell of FIG. 12A is a transfer gate for cell selection between the MTJ elements MTJ [0] and MTJ [1] in the 2MTJ type magnetic memory cell of FIG. 39 is inserted, and a connection node between one MTJ element MTJ [0] and one end of the transfer gate 39 is connected to the read bit line RBL via the read transfer gate 40. NMOSFETs are used as the transfer gates 39 and 40, respectively, and the gates are commonly connected to the read word line RWL.

  In this embodiment, the transfer gate 40 is provided as a transfer gate for reading, but a transfer gate 41 in FIG. 8A may be provided instead.

  The operation of the 2Tr-2MTJ type magnetic memory cell shown in FIG. 12A is different from the 2MTJ type magnetic memory cell shown in FIG. 1 in that the two cell selection transfer gates 3 and 4 are turned on / off. This is basically the same except that it is controlled by the read word line RWL.

  As described above, the transfer gate 39 is provided between the MTJ elements MTJ [0] and MTJ [1], and the transfer gate 40 is provided between the magnetic memory cell and the read bit line RBL. The active memory cell and the inactive memory cell can be separated so as to block the sneak current through the read bit line RBL, and a reliable read operation is realized.

  FIG. 12B is a cross-sectional view schematically showing a part of the element structure of the 2Tr-2MTJ type memory cell shown in FIG. Here, the cell selection transfer gate 40 is formed in an active region partitioned by an element isolation region 35 formed in the semiconductor substrate 34.

  13 shows an example of the planar layout of the contact C1 and the lower layer portion in FIG. 12B, and FIG. 14 shows an example of the planar layout of the contact C1 and the upper layer portion in FIG. 12B. Show. Note that GC in FIG. 13 corresponds to the gate electrode 38 of the cell selection transfer gate 40. Here, an example is shown in which the read bit line RBL is arranged in parallel with the write bit line WBL.

  In this embodiment as well, the magnetoresistive element described in Patent Document 4 can be applied by replacing the layout of the upper layer portion from C1 with that of FIG.

<Fourth Embodiment>
FIG. 15 is an equivalent circuit diagram showing one magnetic memory cell and a read system circuit in a memory cell array in the MRAM according to the fourth embodiment of the present invention.

  The MRAM shown in FIG. 15 differs from the MRAM in FIG. 2A in that a read system circuit is added. This read circuit includes a sense amplifier 42. Further, a transfer gate is provided between the nodes of the voltages V0 and V1 applied to the write bit lines WBL [0] and WBL [1] during read and the write bit lines WBL [0] and WBL [1], respectively. The difference is that 43 and 44 are inserted. The sense amplifier 42 detects data by comparing the potential read to the read bit line RBL with the reference potential Vref, and outputs a signal Vsaout. The magnetic memory cell shown in FIG. 15 is the 2Tr-2MTJ type described above for the sake of simplicity, but the present invention is not limited to this, and the aforementioned 3Tr-2MTJ type can also be used.

  The reference potential Vref supplied to the sense amplifier 42 is generated by a reference potential generation circuit, and normally the value is an intermediate potential between V0 and V1, that is, a potential at which Vref = (V0 + V1) / 2.

  During the read operation, both the transfer gates 43 and 44 are turned on, and a potential difference of (V0−V1) is applied to both ends of the magnetic memory cell 31. Then, the read word line RWL is set to a potential higher than the threshold voltage Vth of the NMOSFET by a potential obtained by adding the read potential to the average value of V0 and V1. As a result, the cell selection transfer gates 32 and 33 in the magnetic memory cell 31 are turned on, and the signal read from the magnetic memory cell 31 is transferred to the read bit line RBL and input to the sense amplifier 42. . The sense amplifier 42 senses the potential of the read bit line RBL with the reference potential Vref as a reference.

  In this embodiment, it is only necessary to supply a certain potential to the write bit lines WBL [0] and WBL [1] during the read operation, and the reference potential Vref used in the sense amplifier 42 is also used for the write. Any potential between V0 and V1 applied to the bit lines WBL [0] and WBL [1] may be used.

  Therefore, there is no need to generate a constant voltage circuit including a feedback circuit or a special reference potential, and the circuit constituting the core portion of the MRAM can be simplified. The sense amplifier 42 can be realized by a simple latch circuit, and the sense amplifier 42 can be laid out at the same pitch as the arrangement pitch of the magnetic memory cells 31. Thereby, for example, burst reading can be realized.

<Fifth Embodiment>
FIG. 16 is an equivalent circuit diagram showing one magnetic memory cell in a memory cell array and a read system circuit in an MRAM according to the fifth embodiment of the present invention.

  The MRAM shown in FIG. 16 has a circuit for generating a reference potential Vref supplied to the sense amplifier 42, as compared with the MRAM of the fourth embodiment described above.

  In this example, the reference potential Vref is generated by the dummy magnetic memory cell 45. The reference potential Vref is an intermediate potential between V0 and V1, that is, (V0 + V1) / 2 as described above.

  The dummy magnetic memory cell 45 is configured to generate the reference potential Vref using a dummy MJT element similar to the MJT element in the magnetic memory cell 31. Then, the reference potential Vref generated in the dummy magnetic memory cell 45 is read out to the dummy read bit line DRBL and supplied to the sense amplifier 42.

  In FIG. 16, the magnetic memory cell 31 and the dummy magnetic memory cell 45 are the above-described 2Tr-2MTJ type magnetic memory cells in order to simplify the description. However, the present invention is not limited to this, and the aforementioned 3Tr-2MTJ type or the like can be used.

  Next, a specific example of the dummy magnetic memory cell 45 will be described.

  The dummy magnetic memory cell 45 includes first and second dummy cells 46 and 47. The first dummy cell 46 includes two dummy MJT elements DMJT [0L] and DMTJ [1L] holding data opposite to each other, and a dummy read transfer gate 32 corresponding to the read transfer gates 32 and 33, 33. The second dummy cell 47 includes two dummy MJT elements DMTJ [0R] and DMTJ [1R] which are data opposite to each other and hold data opposite to the first dummy cell 46, and a transfer gate for reading. And transfer gates 32 and 33 for dummy reading corresponding to 32 and 33. In this case, the dummy MJT elements DMTJ [0L] and DMTJ [0R] are each set to store reverse data. Then, the potentials read from the two dummy cells 46 and 47 via the transfer gates 32 and 33 are combined by the dummy cell read word line DRWL to generate the reference potential Vref. The In FIG. 16, DWWL [0] and DWWL [1] are dummy word write word lines.

  Thereby, when the read word line DRWL of the dummy cell is activated during the read operation, the reference potential represented by (V0−V1) / 2 is synthesized with the read bit line DRBL of the dummy cell.

  Next, a modification of the dummy magnetic memory cell 45 in FIG. 16 will be described.

  A dummy magnetic memory cell 45 shown in FIG. 17 includes first and second dummy cells 46 and 47. 16 differs from the dummy magnetic memory cell of FIG. 16 in that the first dummy cell 46 is provided with two dummy MJT elements DMJT [0L] and DMJT [0L] that hold the same data. Two dummy MJT elements DMJT [1R] and DMJT [1R] that hold the same data but the reverse data of the first dummy cell are provided. Then, the potentials read from the first and second dummy cells 46 and 47 via the dummy read transfer gates 32 and 33 are combined by the dummy read bit line DRBL to obtain the reference potential Vref. Generated.

  Thus, when the dummy read word line DRWL is activated during the read operation, the reference potential represented by (V0−V1) / 2 is output to the dummy read bit line DRBL.

  Here, an example in which dummy cells are arranged in the same column as a memory cell from which data is read has been described. However, the dummy cell can be arranged in a different column from the memory cell from which data is read.

  In FIG. 17, the magnetic memory cell 31 and the dummy magnetic memory cell 45 are the above-described 2Tr-2MTJ type for simplification of description, but are not limited to this, and the above-described 3Tr-2MTJ type, etc. Can also be used.

<Sixth Embodiment>
FIG. 18 is an equivalent circuit diagram showing one magnetic memory cell in the memory cell array and a part of the read circuit in the MRAM according to the sixth embodiment of the present invention.

  The MRAM shown in FIG. 18 is compared with the MRAM according to the first embodiment described above between the MTJ elements MTJ [0] and MTJ [1] during the first period during the operation of reading data from the magnetic memory cell 31. A difference is that a predetermined potential difference is given, and a switching circuit 50 is added between the MTJ elements MTJ [0] and MTJ [1] to give a potential difference of the same polarity and opposite polarity in the second period. That is, in FIG. 18, the potential read from the magnetic memory cell to the read bit line RBL in the first period is used as the reference potential of the sense amplifier in the read circuit 60, and from the magnetic memory cell in the second period. A pseudo self-reference type read system circuit that detects the MC data by comparing the potential read to the read bit line RBL with a reference potential by a sense amplifier and outputs a signal Vsaout is shown.

  18 shows the case where the magnetic memory cell 31 is of the 2Tr-2MTJ type described above for the sake of simplification of the description. However, the present invention is not limited to this, and the above-described 3Tr-2MTJ type or the like is used. It can also be used.

  The switching circuit 50 is inserted, for example, between the first group of switch elements 51 inserted between the node of the voltage V0 and the write bit line WBL [0], and between the voltage V1 and the WBL [0]. The second group of switch elements 52, the first group of switch elements 53 inserted between the node of voltage V1 and the write bit line WBL [1], the node of voltage V0 and the write bit line WBL [1] And a second group of switch elements 54 inserted between them. The two switch elements 51 and 53 of the first group are controlled to be turned on by the first switch control line Pa that is activated and controlled in the first period. The two switch elements 52 and 54 of the second group are controlled to be turned on by a second switch control line Pb that is activated and controlled in the second period.

  In the MRAM of this example, when data is read from the selected magnetic memory cell 31, the potential difference applied between the write bit lines WBL [0] and WBL [1] is determined based on the first read operation and the second read. The read operation is performed by switching between the operations.

That is, in the first read operation, the first switch control line Pa is activated and the two switch elements 51 and 53 of the first group are turned on. As a result, a potential difference is applied across the magnetic memory cell 31 so that the potential of one write bit line WBL [0] is V0 and the potential of the other write bit line WBL [1] is V1. Here, if data “1” is stored in the magnetic memory cell 31, the read bit line RBL has
Vsig [a] = {(1 + MR) / (2 + MR)} × (V0−V1) (6)
Is output.

In the second read operation, the second switch control line Pb is activated and the two switch elements 52 and 54 of the second group are turned on. As a result, the potentials of the write bit lines WBL [0] and WBL [1] are opposite to those of the first read operation, while the potential of one write bit line WBL [0] is V1 and the other The potential of the bit line WBL [1] becomes V0. At this time, the read bit line RBL has
Vsig [b] = {1 / (2 + MR)} × (V0−V1) (7)
Is output.

Here, the signal (potential difference) Vdiff inputted to the sense amplifier is obtained from the difference between the equations (6) and (7).
Vdiff = {(MR / (2 + MR)} × (V0−V1) (8)
It becomes.

On the other hand, in the case of the second embodiment, the signal (potential difference) Vdiff input to the sense amplifier is the difference between the expressions (3) and (5) or (4) and (5). From
Vdiff = {(MR / 2) / (2 + MR)} × (V0−V1) (9)
It becomes.

  Comparing the above equations (8) and (9), in the pseudo self-reference method as shown in this embodiment, the read signal amount can be doubled. As a result, effects such as a high-speed sensing operation and improved resistance to variations in characteristics of MTJ elements can be obtained.

  Note that the pseudo self-reference type read system circuit as described above does not require a write operation to the magnetic memory cell as compared with the conventional self-reference type read system circuit. Sense sensitivity does not deteriorate due to

<Seventh Embodiment>
FIG. 19 is an equivalent circuit diagram showing one magnetic memory cell and a part of a read system circuit in an MRAM according to the seventh embodiment of the present invention that embodies the read circuit 60 shown in FIG.

  The read circuit 60 is provided with a second switching circuit 61 that switches and outputs the potential read from the magnetic memory cell 31 to the read bit line RBL between the first period and the second period. . The sense amplifier 42 holds the potential read to the read bit line RBL in the first period with the input capacitance of the first input terminal (−) as the reference potential Vref, and reads out in the second period. The potential read to the bit line RBL is held by the input capacitance of the second input terminal (+), and then compared with the reference potential Vref to detect data and output the signal Vsaout. SAENBL is an activation signal for the sense amplifier 42. Further, in FIG. 19, the magnetic memory cell 31 is the above-described 2Tr-2MTJ type for the sake of simplicity, but the present invention is not limited to this, and the above-described 3Tr-2MTJ type may be used. it can.

  The second switching circuit 61 includes, for example, a switch element 62 inserted between the read bit line RBL and the first input terminal (−) of the sense amplifier 42, and the read bit line RBL and the first of the sense amplifier 42. And a switch element 63 inserted between the two input terminals (+). The switch element 62 is controlled to be turned on by the switch control line Pd that is activated and controlled in the first period, and the switch element 63 is turned on by the switch control line Pc that is activated and controlled in the second period. Switching control is performed.

  In the MRAM of this example, when reading data from the selected magnetic memory cell, the potential applied between the write bit lines WBL [0] and WBL [1] is set in the first read operation and the second read operation. The read operation is performed by switching between times. In the first read operation, the switch control line Pd is activated, and the signal output to the read bit line RBL is transferred to the first input terminal (−) of the sense amplifier 42 via the switch element 62. . Thereafter, the switch control line Pd is deactivated. During the second read operation, the switch control line Pc is activated, and the signal output to the read bit line RBL is transferred to the second input terminal (+) of the sense amplifier 42 via the switch element 63. Thereafter, the switch control line Pc is deactivated. Thereafter, the activation signal SAENBL is activated, the sense amplifier 42 is activated, and the signal Vsaout which is a sense result is output.

In this example, the difference between the signals input to the first and second input terminals of the sense amplifier 42 is from the above-described equations 6 and 7.
Vsig [a] −Vsig [b] = {MR / (2 + MR)} × (V0−V1) (10)
It is expressed. That is, a read signal amount twice that in the second embodiment can be obtained by two read operations.

<Eighth Embodiment>
By the way, in the MRAM of the seventh embodiment, for example, NMOSFETs or PMOSFETs are used as the switch elements 62 and 63 that constitute the second switching circuit 61. Since these NMOSFETs and PMOSFETs are gate-controlled by signals on the switch control lines Pc and Pd, when the switch elements 62 and 63 are on / off controlled, the first and second of the sense amplifier 42 are connected via the parasitic capacitance of the MOSFET. Switching noise is mixed in the input terminal. Since the switch element 62 is turned on during the first read operation, the switch element 63 is turned on and the switch element 62 is turned off during the second read operation, the sense amplifier is used during the first and second read operations. The change direction of the switching noise mixed in the first and second input terminals of 42 is reversed, thereby reducing the read margin of the sense amplifier 42.

  Therefore, in the MRAM of the eighth embodiment, the switch elements 62 and 63 inserted between the read bit line RBL and the sense amplifier 42 in the MRAM of the seventh embodiment performing the read operation twice. Thus, the influence of the switching noise mixed in the sense amplifier 42 is eliminated, and the decrease in the read margin of the sense amplifier 42 is prevented.

  FIG. 20 shows a partial configuration of the MRAM according to the eighth embodiment. The MCA is a memory cell array in which a plurality of magnetic memory cells 31 are provided. RDRV0 is a first read driver circuit that applies a predetermined read potential difference between the write bit lines WBL [0] and WBL [1] in the first period. RDRV1 is in the second period. , A second read driver circuit that applies a read potential difference of opposite polarity with the same potential difference (the same absolute value) as that of the first period between the write bit lines WBL [0] and WBL [1]. .

  The first read driver circuit RDRV0 includes a PMOSFET 111 having a source-drain connected between a node of the power supply potential Vcc and one write bit line WBL [0], a node of the ground potential Vss, and the other. An NMOSFET 112 having a source and a drain connected to each other is provided between the write bit line WBL [1]. Similarly, the second read driver circuit RDRV1 includes an NMOSFET 113 having a source-drain connected between the node of the ground potential Vss and one write bit line WBL [0], and a node of the power supply potential Vcc. And the other write bit line WBL [1] are provided with a PMOSFET 113 having a source-drain connected.

  In this example, NMOSFETs 115 and 116 are used as the first and second switch elements 62 and 63 in the readout circuit 60. Further, in the read circuit 60, an equalizing NMOSFET 117 for setting the read bit line RBL to the reference potential VREF is provided.

  In FIG. 20, the word line WWL for writing in the memory cell array MCA is not shown.

  Next, the data read operation in the MRAM of FIG. 20 will be described with reference to the waveform diagram of FIG. First, prior to data reading, the equalize signal EQL is set to “H” level in advance. At this time, the equalizing NMOSFET 117 is on, and the read bit line RBL is equalized to the reference potential VREF. Prior to the start of data reading, the control signals PT <0> and PT <1> are both at the “H” level, and both the NMOSFETs 115 and 116 in the reading circuit 60 are on. Accordingly, the first and second input terminals of the sense amplifier 42 are both set to the potential of VREF.

  Next, the equalize signal EQL becomes “L” level, and the equalizing NMOSFET 117 is turned off. Subsequently, the magnetic memory cell 31 is selected. For example, one read word line RWL <0> among the plurality of read word lines RWL <0>... RWL <n> is activated, and the magnetic memory cell 31 connected thereto is selected. Subsequently, the control signal RDSEL <0> for driving the first read driver circuit RDRV0 and the read enable signal RDENBL are activated, and the PMOSFET 111 and the NMOSFET 112 in the first read driver circuit RDRV0 are turned on. A potential difference such that one write bit line WBL [0] becomes Vcc and the other write bit line WBL [1] becomes Vss is supplied between the write bit lines, and the first time from the selected memory cell 31. Is read out. After the first data read, the control signal PT <0> is set to “L” level, and the NMOSFET 115 in the read circuit 60 is turned off.

  Next, the control signal RDSEL <1> for driving the second read driver circuit RDRV1 and the read enable signal RDENBL are activated, and the NMOSFET 113 and the PMOSFET 114 in the second read driver circuit RDRV1 are turned on. In this case, a potential difference is supplied between the write bit lines so that one write bit line WBL [0] becomes Vss and the other write bit line WBL [1] becomes Vcc. A second data read is performed. After the second data read, the control signal PT <1> is set to “L” level, and the NMOSFET 116 in the read circuit 60 is turned off.

  Thereafter, the activation signal SAENBL is activated, the sense amplifier 42 is activated, and the signal Vsaout which is a sense result is output.

  That is, in the first period when data is read from the magnetic memory cell 31, both the NMOSFETs 115 and 116 in the read circuit 60 are turned on, and the first read is performed when both the NMOSFETs 115 and 116 are both turned on. The driver circuit RDRV0 is activated, and the first potential difference (Vcc−Vss) is supplied to the write bit lines WBL [0] and WBL [1]. The selected magnetic memory cell 31 reads the first signal to the read bit line RBL after the first potential difference is supplied to the write bit lines WBL [0] and WBL [1]. After the first signal is read, the NMOSFET 115 is turned off, and the first input terminal of the sense amplifier 42 is disconnected from the read bit line RBL. After the NMOSFET 115 is turned off, the second read driver circuit RDRV1 is activated, and the second potential difference is supplied to the write bit lines WBL [0] and WBL [1]. The selected magnetic memory cell 31 reads the second signal to the read bit line RBL after the second potential difference is supplied to the write bit lines WBL [0] and WBL [1]. After the second signal is read, the NMOSFET 116 is turned off, the second input terminal of the sense amplifier 42 is disconnected from the read bit line RBL, and then the sense amplifier 42 is activated to sense data. Is done.

  In the eighth embodiment, during the data read period, each of the NMOSFETs 115 and 116 in the read circuit 60 is switched only once, and each is switched from the on state to the off state. For this reason, the coupling noise to the sense amplifier 42 by the control signals PT <0> and PT <1> for controlling both NMOSFETs 115 and 116 is in phase with the first and second input terminals and by the same amount. Join. Here, since the sense amplifier 42 senses data by amplifying the potential difference between the first and second input terminals, even if in-phase and the same amount of coupling noise is applied to the first and second input terminals. The read signal amount does not decrease. For this reason, it is possible to prevent a decrease in read margin due to switching noise caused by switching of the NMOSFETs 115 and 116.

  In the eighth embodiment, the case where NMOSFETs are respectively used as the switch elements 62 and 63 constituting the switch circuit 61 has been described. This is a CMOS transfer gate in which PMOSFETs or NMOSFETs and PMOSFETs are connected in parallel, respectively. May be modified to use.

<Ninth Embodiment>
In the MRAM of the eighth embodiment shown in FIG. 20, the signal read from the magnetic memory cell is held by the input capacitance existing at the first and second input terminals of the sense amplifier 42. At this time, the first and second input terminals of the sense amplifier 42 are in a floating state, and the sense amplifier 42 is electrically disconnected from the read bit line RBL, so that the input capacitance is small. For this reason, there is a risk that the signal charge held in the input capacitance of the sense amplifier 42 leaks through a PN junction or the like.

  Therefore, in the MRAM of the ninth embodiment, as shown in FIG. 22, by adding a capacitance circuit 120 to the input terminal of the sense amplifier 42, the input capacitance of the sense amplifier 42 is increased, and the signal charge leaks. This is designed to reduce the influence of.

  In this example, the capacitor circuit 120 is composed of a pair of NMOSFETs 121 and 122 whose source and drain are short-circuited. One NMOSFET 121 has a source / drain connected to a ground potential node and a gate connected to the first input terminal (−) of the sense amplifier 42. The other NMOSFET 122 has a source / drain connected to the ground potential node and a gate connected to the second input terminal (+) of the sense amplifier 42. That is, the capacitance circuit 120 is configured by a pair of MOS capacitors each formed of an NMOSFET. Of course, the pair of MOS capacitors may be composed of PMOSFETs.

  In the ninth embodiment, the case where the gate of the MOSFET constituting the MOS capacitor is connected to the input end side of the sense amplifier 42 and the source / drain is connected to the node side of the ground potential is explained. Conversely, the source / drain of the MOSFET may be connected to the input end side of the sense amplifier 42 and the gate may be connected to the node side of the ground potential.

<Tenth Embodiment>
If the capacitance circuit 120 is added to the input terminal of the sense amplifier 42 as in the ninth embodiment shown in FIG. 22, the read speed may be reduced. Therefore, in the MRAM of the tenth embodiment, as shown in FIG. 23, the control signal CAPCTRL is supplied instead of connecting the source and drain of the pair of NMOSFETs 121 and 122 in the capacitor circuit 120 to the ground potential node. Thus, the capacity of the MOS capacitor composed of the pair of NMOSFETs 121 and 122 is increased only when necessary so as to minimize the decrease in the reading speed at the time of reading. When the NMOSFETs 121 and 122 are used as MOS capacitors, the capacitance can be maximized by setting the control signal CAPCTRL to the “L” level, and minimized by setting the control signal CAPCTRL to the “H” level. When PMOSFET is used as the MOS capacitor, the reverse is true.

  Also in the tenth embodiment, the source / drain of the MOSFET constituting the MOS capacitor is connected to the input end side of the sense amplifier 42 and the gate is connected to the control line side of the control signal CAPCONTRL. Also good.

<Eleventh embodiment>
FIG. 24 is a circuit diagram showing another configuration example of the read circuit 60 shown in FIG.

  The reading circuit 60 shown in FIG. 24 includes two switch elements 64 and 65 and a differentiation circuit (DIFF) 66. One switch element 64 is inserted between the read bit line RBL and the input node of the differentiation circuit 66. The switch element 64 is switching-controlled by a switch control line Pc. The other switch element 65 is inserted between the input / output nodes of the differentiation circuit 66. The switch element 65 is switching-controlled by a switch control line Pd. In FIG. 24, the magnetic memory cell 31 is the 2Tr-2MTJ type described above for the sake of simplification of the description. However, the present invention is not limited to this, and the 3Tr-2MTJ type described above may be used. it can.

  In the MRAM of this example, when data is read from the selected magnetic memory cell 31, the potential applied between the write bit lines WBL [0] and WBL [1] by the first switching circuit 50 is the first read. It is switched between the operation and the second read operation.

  In the first read operation, the switch control lines Pc and Pd are activated and the switch elements 64 and 65 are turned on. As a result, the signal read to the read bit line RBL is transferred to the output node of the differentiation circuit 66 via the switch elements 64 and 65, and then the switch control line Pc is inactivated. When the switch element 64 is in the on state, the switch control line Pd is activated, the switch element 65 is in the on state, and the input / output node of the differentiation circuit 66 is short-circuited. At this time, the potential of the input node of the differentiation circuit 66 is set to the reference potential Vref.

  In the second read operation, after the signal is read to the read bit line RBL, the switch control line Pd is deactivated and the switch element 65 is turned off, and the input / output of the differentiation circuit 66 is turned off. The nodes are electrically isolated. Thereafter, the switch control line Pc is activated, the switch element 64 is turned on, and the signal read to the read bit line RBL is transferred to the input node of the differentiation circuit 66 via the switch element 64. At this time, the change in the potential of the input node is detected by the differentiation circuit 66, whereby the data in the magnetic memory cell 31 is detected, and the result is output as the signal Vsaout.

  According to the MRAM of this example, the reading circuit 60 performs the sensing operation only by the relative relationship between the resistance values of the MTJ elements MTJ [0] and MTJ [1] without depending on the absolute value of the resistance value of the MTJ element. For this reason, even when the resistance value of the MTJ element varies between memory chips, a reliable sensing operation can be realized.

<Twelfth Embodiment>
FIG. 25 is a circuit diagram showing an example of a part of the memory cell array and a part of the peripheral circuit in the MRAM according to the twelfth embodiment of the present invention.

  In the MRAM shown in FIG. 25, the magnetic memory cells 31 shown in any of the first to third embodiments described above are arranged in a matrix to form a memory cell array. In this example, the magnetic memory cell 31 is the 2Tr-2MTJ type described above for the sake of simplification, but is not limited to this, and the 3Tr-2MTJ type described above can be used.

  A plurality of read word lines RWL are arranged in the row direction of the memory cell array, and a plurality of read bit lines RBL are arranged in the column direction. A plurality of read word lines RWL are commonly connected to a plurality of magnetic memory cells 31 in each row, and a plurality of read bit lines RBL are connected to a plurality of magnetic memory cells 31 in each column. A sense amplifier 42 is connected to the read bit line RBL in each column of the memory cell array, and the read bit line RBL is arranged in parallel with the write word line WBL.

  A word line driver 71 is provided for each row of the memory cell array, and the output of each word line driver 71 is connected to the corresponding read word line RWL. A reference potential used in the sense amplifier 42 is generated by a reference potential generation circuit.

  Further, a bit line driver 72 is provided for each column of the memory cell array. These bit line drivers 72 supply a potential difference between a pair of write bit lines WBL [0] and WBL [1] in each column during a read operation. Each bit line driver 72 includes a first read potential supply source for supplying a first potential to one of the pair of write bit lines WBL, and a second to the other of the pair of write bit lines WBL. A second read potential supply source for supplying the first potential. The two read potential supply sources are arranged on one end side in the same direction of the pair of write bit lines WBL. In this example, a read potential supply PMOSFET 73 and an NMOSFET 74 are connected to a pair of write bit lines WBL.

  In this example, one word line driver 71 activates one row of read word lines RWL. By activating all the bit line drivers 72 connected to the same memory cell array, one row of data is read out to all the sense amplifiers 42 connected to the same memory cell array.

  In addition, since two read potential supply sources connected to the pair of write bit lines WBL are both connected to the write bit line WBL, the read potential supply source and the selected memory cell The wiring resistance of the write bit line WBL between them is equal between WBL [0] and WBL [1] making a pair. Thereby, it is possible to prevent the read margin from being reduced due to the wiring resistance of the write bit line WBL.

  Next, in each of the above-described embodiments, a precharge method for writing and reading bit lines WBL and RBL when reading data from a magnetic memory cell will be described. Basically, the write and read bit lines WBL and RBL are (a) precharged to potential Vaa, (b) precharged to potential Vbl = (Vaa + Vss) / 2, (c ) It is possible to adopt a method of precharging to the potential Vss. Here, Vaa and Vss represent two potentials of the write bit line WBL set during the read operation, and correspond to the potentials V0 and V1 described above.

  FIG. 26A shows the read operation when the method of precharging the write bit lines WBL (WBL [0], WBL [1]) to the first potential Vaa is used in the period before the read operation. An example of the potential waveform is shown.

  In FIG. 26B, the write bit line WBL (WBL [0], WBL [1]) is applied to the intermediate potential Vbl = (Vaa between the first potential Vaa and the second potential Vss in the period before the read operation. An example of a potential waveform at the time of a read operation when a precharge method of + Vss) / 2 is adopted is shown.

  FIG. 26C shows a case where a method of precharging the write bit lines WBL (WBL [0], WBL [1]) to the second potential Vss during the period before the read operation is employed. An example of a potential waveform is shown.

  26A, 26B, and 26C, READ indicates a potential waveform of a read drive signal, and SN indicates a potential waveform of a signal read node between two MTJ elements included in one memory cell. The solid line indicates the potential waveform when “0” data is read, and the broken line indicates the potential waveform when “1” data is read.

  FIG. 27A shows an example of a potential waveform during the read operation in the case where the method of precharging the read bit line RBL to the first potential Vaa is used in the period before the read operation.

  FIG. 27B shows a method of precharging the read bit line RBL to an intermediate potential Vbl = (Vaa + Vss) / 2 between the first potential Vaa and the second potential Vss in the period before the read operation. An example of a potential waveform during a read operation when employed is shown.

  FIG. 27C shows an example of a potential waveform during the read operation in the case where the method of precharging the read bit line RBL to the second potential Vss in the period before the read operation is employed.

  In FIGS. 27A, 27B, and 27C, RWL indicates the potential waveform of the read word line. When the read word line RWL is activated, the potential of RWL becomes the first potential Vaa or a potential higher than this.

  In the method of precharging the bit lines WBL and RBL to the potential Vaa, since the NMOSFET generally has a higher current drive capability than the PMOSFET, the bit line potential can be changed from Vaa to Vss during the read operation. The time required is reduced and a high-speed read operation can be realized.

  In the case where the bit lines WBL and RBL are precharged to the potential Vbl, the potential amplitude of the bit line during the read operation is small as Vaa−Vbl and Vbl−Vss, so that the read operation can be performed with low current consumption.

  In the case of a method in which the bit lines WBL and RBL are precharged to the potential Vss, it is not necessary to supply any potential during a period other than the read operation or during standby, so that the power consumption is low. In addition, it is not necessary to precharge the potential of the bit line when shifting from standby mode to active mode or during the read operation period. And low power consumption.

<13th Embodiment>
FIG. 28 is a circuit diagram showing an example of a part of the memory cell array and a part of the peripheral circuit in the MRAM according to the thirteenth embodiment of the present invention.

  The MRAM shown in FIG. 28 has a dummy magnetic memory for generating the reference potential Vref in the memory cell array in which the magnetic memory cells 31 shown in any of the first to third embodiments are arranged in a matrix. Cells (DMC) 75 are arranged for at least one row. In FIG. 28, the magnetic memory cell 31 is the 2Tr-2MTJ type described above for the sake of simplicity, but the present invention is not limited to this, and the 3Tr-2MTJ type described above may be used. it can.

  A read word line RWL is commonly connected to the magnetic memory cells 31 and dummy magnetic memory cells 75 in each row of the memory cell array, and a read bit line RBL is commonly connected to the magnetic memory cells 31 in each column of the cell array. . The read word line RWL is arranged in the row direction, and the read bit line RBL is arranged in the column direction.

  A dummy read bit line DRBL is commonly connected to one column of dummy magnetic memory cells 75, and the dummy read bit line DRBL is arranged in the column direction. Further, a sense amplifier 42 is connected to the read bit line RBL corresponding to each column of the memory cell array, and the read bit line RBL is arranged in parallel with the write bit line WBL.

  The word line driver 71 is provided in each row of the memory cell array, and each output is connected to the corresponding read word line RWL. The bit line driver 72 provided for each column also serves as a read driver, and is composed of a PMOSFET 73 and an NMOSFET 74, respectively. A sense amplifier 42 is provided for each column, and a potential read to the read bit line RBL of the corresponding column and a reference potential output to the dummy read bit line DRBL are supplied to each sense amplifier 42.

  In this example, the memory cell 31 from which data is read and the dummy cell 75 are activated by the same read word line RWL. Therefore, the wiring resistance in the bit line WBL between the bit line driver 72 and the memory cell 31 is equal to the wiring resistance in the bit line WBL between the bit line driver 72 and the dummy cell 75, and the resistance of the bit line WBL is reduced. The influence can be made equal between the memory cell 31 and the dummy cell 75, and a decrease in the sense margin in the sense amplifier can be prevented.

  Also in this example, the method for precharging the write and read bit lines WBL and RBL in the read operation can be performed in the same manner as described above.

<Fourteenth embodiment>
FIG. 29 is a circuit diagram showing an example of a part of the memory cell array and a part of the peripheral circuit in the MRAM according to the fourteenth embodiment of the present invention.

  The MRAM shown in FIG. 29 has a memory cell array in which the magnetic memory cells 31 shown in any of the first to third embodiments are arranged in a matrix. A read word line RWL is commonly connected to the magnetic memory cells 31 in each column of the memory cell array, and a read bit line RBL is commonly connected to the magnetic memory cells 31 in each row of the cell array. The read word line RWL is arranged in the column direction, and the read bit line RBL is arranged in the row direction. A sense amplifier 42 is provided corresponding to each row of the memory cell array, and the read bit line RBL of each row is connected to the corresponding sense amplifier 42. Here, the read bit line RBL and the write bit line WBL are arranged in directions orthogonal to each other.

  In this example, all the magnetic fields connected to one column are activated only by activating the bit line driver 72 corresponding to a pair of write word lines WBL and the word line driver 71 corresponding to one column of read word lines RWL. Data in the memory cell 31 can be read out.

  Also in this example, the method for precharging the write and read bit lines WBL and RBL in the read operation can be performed in the same manner as described above.

  Various applications of the MRAM according to the first to fourteenth embodiments of the present invention are possible. Some of these applications are described below.

<Application example 1>
FIG. 30 shows a DSL data path portion of a digital subscriber line (DSL) modem as one application example of MRAM. The modem includes a programmable digital signal processor (DSP) 151, an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC) 152, a transmission driver 153, and a receiver amplifier 154. In FIG. 30, the band-pass filter is omitted, and the MRAM 155 and EEPROM 156 of the present invention are shown as various types of optional memories that can hold the line code program instead.

  In this application example, two types of memory, MRAM and EEPROM, are used as memory for holding the line code program. However, EEPROM may be replaced with MRAM, that is, MRAM without using two types of memory. You may make it use only.

<Application example 2>
As another application example of the MRAM, FIG. 31 shows a part that realizes a communication function in the mobile phone terminal 300. As shown in FIG. 31, a part that realizes a communication function includes a transmitting / receiving antenna 201, an antenna duplexer 202, a receiving unit 203, a baseband processing unit 204, a digital signal processor (DSP) 205 used as an audio codec, a speaker 206, A microphone 207, a transmission unit 208, and a frequency synthesizer 209 are provided.

  In addition, as shown in FIG. 31, the mobile phone terminal 300 is provided with a control unit 200 that controls each unit of the mobile phone terminal. The control unit 200 is a microcomputer configured by connecting a CPU 221, a ROM 222, an MRAM 223 of the present invention, and a flash memory 224 through a CPU bus 225.

  Here, the ROM 222 stores programs to be executed by the CPU 221 and necessary data such as display fonts in advance. The MRAM 223 is mainly used as a work area. The CPU 221 stores data in the middle of calculation as necessary while the program is being executed by the CPU 221 or between the control unit 200 and each unit. This is used for temporarily storing data exchanged by the user. Further, the flash memory 224 stores, for example, the previous setting conditions even when the power of the mobile phone terminal 300 is turned off, and when using the same setting when the power is turned on next time, The setting parameters are stored. That is, the flash memory 224 is a non-volatile memory in which data stored therein is not lost even when the power of the mobile phone terminal is turned off.

  In this application example, the ROM 222, the MRAM 223, and the flash memory 224 are used. However, the flash memory 224 may be replaced with the MRAM of the present invention, and the ROM 222 may be replaced with the MRAM of the present invention.

  In FIG. 31, 211 is an audio data reproduction processing unit, 212 is an external terminal connected to the audio data reproduction processing unit 211, 213 is an LCD controller, 214 is an LCD connected to the LCD controller 213, 215 is a ringer, 231 Is an interface provided between the CPU bus 225 and the external memory slot 232, 233 is an interface provided between the CPU bus 225 and the key operation unit 234, and 235 is an interface between the CPU bus 225 and the external terminal 236. The external memory 240 is inserted into the external memory slot 232.

<Application example 3>
32 to 36 show an example in which the MRAM of the present invention is applied to a card (MRAM card) that stores media contents such as smart media.

  In the top view of FIG. 32, 400 is an MRAM card body, 401 is an MRAM chip, 402 is an opening, 403 is a shutter, and 404 is a plurality of external terminals. The MRAM chip 401 is housed inside the card body 400 and is exposed to the outside through the opening 402. When carrying the MRAM card, the MRAM chip 401 is covered with a shutter 403. The shutter 403 is made of a material having an effect of shielding an external magnetic field, such as ceramic. When transferring data, the shutter 403 is opened and the MRAM chip 401 is exposed. The external terminal 404 is for taking out content data stored in the MRAM card to the outside.

  33 and 34 show a top view and a side view of a card insertion type transfer device for transferring data to an MRAM card. The second MRAM card 450 used by the end user is inserted from the insertion portion 510 of the transfer device 500 and pushed in by the stopper 520 until it stops. The stopper 520 is also used as a member for aligning the first MRAM card 550 and the second MRAM card 450. Data stored in the first MRAM card 550 is transferred to the second MRAM card 450 in a state where the second MRAM card 450 is disposed at a predetermined position.

  FIG. 35 is a side view of the fitting type transfer device. As shown by the arrows in the figure, the second MRAM card 450 is placed on the first MRAM card 550 so as to be fitted with the stopper 520 as a target. Since the transfer method is the same as that of the card insertion type, description thereof is omitted.

  FIG. 36 is a side view of a slide type transfer device. Similar to a CD-ROM drive, DVD drive, or the like, a tray slide 560 is provided in the transfer device 500, and the tray slide 560 slides as indicated by a horizontal arrow in the figure. When the tray slide 560 moves to the state indicated by the broken line in the drawing, the second MRAM card 450 is placed on the tray slide 560. Thereafter, the tray slide 560 conveys the second MRAM card 450 into the transfer device 500. The point that the tip of the second MRAM card 450 is brought into contact with the stopper 520 and the transfer method are the same as those of the card insertion type, and the description thereof is omitted.

1 is an equivalent circuit diagram showing one magnetic memory cell in a memory cell array in an MRAM used for explaining the principle of the present invention. 2 is an equivalent circuit diagram showing one magnetic memory cell in the memory cell array in the MRAM according to the first embodiment of the present invention, and a cross-sectional view schematically showing a part of the element structure of the memory cell. FIG. FIG. 3 is a diagram showing an example of a planar layout of a lower layer of the memory cell shown in FIG. 2. FIG. 3 is a diagram showing an example of a planar layout of the upper layer of the memory cell shown in FIG. 2. The figure which shows an example of the planar layout of the lower layer of the memory cell of MRAM which concerns on the 1st modification of the 1st Embodiment of this invention. The figure which shows an example of the planar layout of the upper layer of the memory cell of MRAM which concerns on the 1st modification of the 1st Embodiment of this invention. FIG. 6 is an equivalent circuit diagram showing one magnetic memory cell in the memory cell array of the MRAM according to the second modification of the first embodiment of the present invention. FIG. 6 is an equivalent circuit diagram showing one magnetic memory cell in a memory cell array in an MRAM according to a second embodiment of the present invention, and a sectional view schematically showing a part of the element structure of the memory cell. FIG. 9 is a diagram showing an example of a planar layout of the lower layer of the memory cell shown in FIG. 8. FIG. 9 shows an example of a planar layout of the upper layer of the memory cell shown in FIG. 8. The figure which shows the other example of the planar layout of the lower layer shown in FIG. FIG. 6 is an equivalent circuit diagram showing one magnetic memory cell in a memory cell array in an MRAM according to a third embodiment of the present invention, and a sectional view schematically showing a part of the element structure of the memory cell. FIG. 13 is a diagram showing an example of a planar layout of the lower layer of the memory cell shown in FIG. 12. FIG. 13 is a diagram showing an example of a planar layout of the upper layer of the memory cell shown in FIG. 12. FIG. 10 is an equivalent circuit diagram showing one magnetic memory cell and a read circuit in a memory cell array in an MRAM according to a fourth embodiment of the present invention. FIG. 10 is an equivalent circuit diagram showing one magnetic memory cell in a memory cell array and a read system circuit in an MRAM according to a fifth embodiment of the present invention. FIG. 17 is an equivalent circuit diagram showing a modification of the dummy magnetic memory cell in FIG. 16. FIG. 10 is an equivalent circuit diagram showing one magnetic memory cell in a memory cell array and part of a read system circuit in an MRAM according to a sixth embodiment of the present invention. FIG. 19 is an equivalent circuit diagram showing one magnetic memory cell and a part of a read system circuit in an MRAM according to a seventh embodiment of the present invention in which the read circuit shown in FIG. 18 is embodied. FIG. 20 is an equivalent circuit diagram showing a part of a magnetic memory cell and a read system circuit in an MRAM according to an eighth embodiment of the present invention. FIG. 21 is a waveform diagram when data is read from the MRAM shown in FIG. 20. The equivalent circuit diagram which shows a part of magnetic memory cell and read-out system circuit in MRAM which concerns on the 9th Embodiment of this invention. The equivalent circuit diagram which shows a part of magnetic memory cell and read system circuit in MRAM which concerns on the 10th Embodiment of this invention. FIG. 20 is an equivalent circuit diagram showing a part of a magnetic memory cell and a read circuit in the MRAM according to the eleventh embodiment of the present invention, showing another configuration example of the read circuit shown in FIG. FIG. 30 is a circuit diagram showing an example of a part of a memory cell array and a part of peripheral circuits in an MRAM according to a twelfth embodiment of the present invention. FIG. 4 is a waveform diagram showing an example of a potential waveform of a main part including a write bit line when data is read from a magnetic memory cell in each of the embodiments. FIG. 4 is a waveform diagram showing an example of a potential waveform of a main part including a read bit line when reading data from a magnetic memory cell in each of the embodiments. FIG. 40 is a circuit diagram showing an example of a part of a memory cell array and a part of peripheral circuits in an MRAM according to a thirteenth embodiment of the present invention. FIG. 25 is a circuit diagram showing an example of a part of a memory cell array and a part of a peripheral circuit in an MRAM according to a fourteenth embodiment of the present invention. The block diagram which shows the DLS data path part of the modem for digital subscriber lines as the application example 1 of MRAM which concerns on this invention. The block diagram which shows the part which implement | achieves the communication function in a mobile telephone terminal as the application example 2 of MRAM based on this invention. The top view which shows the example which applied MRAM which concerns on this invention to the MRAM card which stores media contents, such as a smart media. The top view which shows an insertion type data transfer apparatus as an example of the electronic apparatus which uses the MRAM card | curd concerning this invention. FIG. 34 is a cross-sectional view corresponding to FIG. 33. Sectional drawing which shows a fitting type data transfer apparatus as another example of the electronic apparatus which concerns on this invention. Sectional drawing which shows the slide-type data transfer apparatus as another example of the electronic apparatus which concerns on this invention. The equivalent circuit diagram which shows the typical 1Tr-1MTJ type | mold memory cell of MRAM. FIG. 38 is a diagram schematically showing a layout in a vertical plane of a cross-sectional structure of the 1Tr-1MTJ type memory cell shown in FIG. 37. The circuit diagram which shows notionally the method of reading information from the conventional magnetic memory cell.

Explanation of symbols

DESCRIPTION OF SYMBOLS 31 ... Magnetic memory cell, 32, 33, 39 ... Transfer gate for cell selection, 34 ... Semiconductor substrate, 35 ... Element isolation region, 36 ... Gate oxide film, 37 ... Diffusion layer, 38 ... Gate electrode, 40 ... 1st Read gate, 42 ... second read transfer gate, 42 ... sense amplifier, 45 ... dummy magnetic memory cell, 46 ... first dummy cell, 47 ... second dummy cell, 50 ... switching circuit, 60 ... read Circuit: 71 ... Word line driver, 72 ... Bit line driver, 75 ... Dummy magnetic memory cell (DMC), MTJ [0] ... First magnetoresistive element, MTJ [1] ... Second magnetoresistive element, WBL [ 0], WBL [1] ... write bit line, WWL ... write word line, RBL ... read bit line.

Claims (35)

Each of the first and second magnetoresistive elements includes a first magnetoresistive element and a second magnetoresistive element each having a tunnel magnetoresistive effect and holding data opposite to each other, and at least one transfer gate. A magnetic memory cell inserted in series between both ends and having the at least one transfer gate connected in series to the first and second magnetoresistive elements;
First and second bit lines respectively connected to both ends of the magnetic memory cell;
A first word line for writing disposed in the magnetic memory cell;
A third bit line for data reading connected to the magnetic memory cell;
A second word line for reading connected to the gate electrode of the at least one transfer gate;
Each one end of the first and second magnetoresistive elements is connected to the first and second bit lines, respectively.
The at least one or more transfer gates have one end connected to the other end of the first magnetoresistive element and the other end connected to the third bit line, and one end connected to the first bit. A second transfer gate connected to the other end of the second magnetoresistive element and the other end connected to the third bit line;
The first, a semiconductor memory device which has both a gate electrode of the second transfer gate, characterized in that it is connected to the second word line. Each of the first and second magnetoresistive elements includes a first magnetoresistive element and a second magnetoresistive element each having a tunnel magnetoresistive effect and holding data opposite to each other, and at least one transfer gate. A magnetic memory cell inserted in series between both ends and having the at least one transfer gate connected in series to the first and second magnetoresistive elements;
First and second bit lines respectively connected to both ends of the magnetic memory cell;
A first word line for writing disposed in the magnetic memory cell;
A third bit line for data reading connected to the magnetic memory cell;
A second word line for reading connected to the gate electrode of the at least one transfer gate;
The at least one transfer gate includes first and second transfer gates each having one end connected to the first and second bit lines, respectively .
Both gate electrodes of the first and second transfer gates are connected to the second word line;
One end of the first magnetoresistive element is connected to the other end of the first transfer gate, the other end is connected to the third bit line, and one end of the second magnetoresistive element is connected to the second transfer gate. The other end of the semiconductor memory device is connected to the third bit line, and the other end is connected to the third bit line . Each of the first and second magnetoresistive elements includes a first magnetoresistive element and a second magnetoresistive element each having a tunnel magnetoresistive effect and holding data opposite to each other, and at least one transfer gate. A magnetic memory cell inserted in series between both ends and having the at least one transfer gate connected in series to the first and second magnetoresistive elements;
First and second bit lines respectively connected to both ends of the magnetic memory cell;
A first word line for writing disposed in the magnetic memory cell;
A third bit line for data reading connected to the magnetic memory cell;
A second word line for reading connected to the gate electrode of the at least one transfer gate;
The at least one transfer gate comprises a first transfer gate connected between the first magnetoresistive element and the second magnetoresistive element;
Furthermore, it has one end, the other end, and a gate electrode, and one end is connected to a connection point between the first magnetoresistive element and the first transfer gate, and the other end is connected to the third bit line. The second transfer gate has one end and the other end and a gate electrode, one end is connected to a connection point between the second magnetoresistive element and the first transfer gate, and the other end is the third bit. A third transfer gate connected to the line;
The semiconductor memory device, wherein the second word line is connected in common to the gate electrodes of the first to third transfer gates. Each of the first and second magnetoresistive elements includes a first magnetoresistive element and a second magnetoresistive element each having a tunnel magnetoresistive effect and holding data opposite to each other, and at least one transfer gate. A magnetic memory cell inserted in series between both ends and having the at least one transfer gate connected in series to the first and second magnetoresistive elements;
First and second bit lines respectively connected to both ends of the magnetic memory cell;
A first word line for writing disposed in the magnetic memory cell;
A third bit line for data reading connected to the magnetic memory cell;
A second word line for reading connected to the gate electrode of the at least one transfer gate;
The at least one transfer gate comprises a first transfer gate connected between the first magnetoresistive element and the second magnetoresistive element;
Further, a second transfer connected between a connection point between one of the first magnetoresistive element or the second magnetoresistive element and the first transfer gate and the third bit line. Have a gate,
The semiconductor memory device, wherein the second word line is commonly connected to both gate electrodes of the first and second transfer gates. The first and second bit lines give a predetermined potential difference to the both ends of the magnetic memory cell when reading data from the magnetic memory cell,
The magnetic memory cell has a potential determined by a ratio between a combined resistance of the first magnetoresistive element and the second magnetoresistive element and a resistance value of the first magnetoresistive element or the second magnetoresistive element. The semiconductor memory device according to claim 1 , wherein the data is read out to the third bit line. A first read driver circuit connected to the first and second bit lines and supplying a first potential difference between the first and second bit lines;
A second read driver circuit connected to the first and second bit lines and supplying a second potential difference having a polarity opposite to the first potential difference between the first and second bit lines;
First and second switch elements each having one end connected to the third bit line;
The other end of the first switch element is connected to one input terminal, further comprising a sense amplifier to which the other end of the second switching element is connected to the other input terminal,
In the first period when reading data from the magnetic memory cell, the first and second switch elements are both turned on,
The first driver circuit for reading is activated when both the first and second switch elements are in an on state, and the first potential difference with respect to the first and second bit lines is activated. Is supplied,
The magnetic memory cell reads the first signal to the third bit line by supplying the first potential difference to the first and second bit lines.
After the first signal is read, the first switch element is turned off, and one input terminal of the sense amplifier is disconnected from the third bit line,
The second read driver circuit is activated after the first switch element is turned off, and the second potential difference is supplied to the first and second bit lines.
The magnetic memory cell reads the second signal to the third bit line by supplying the second potential difference to the first and second bit lines,
After the second signal is read, the second switch element is turned off, the other input terminal of the sense amplifier is disconnected from the third bit line, and then the sense amplifier is activated. 5. The semiconductor memory device according to claim 1, wherein the data is sensed and the data is sensed. 7. The semiconductor memory device according to claim 6 , wherein the first and second potential differences have the same absolute value. A first capacitive element having one end connected to one input end of the sense amplifier;
The semiconductor memory device according to claim 6 , further comprising: a second capacitor element having one end connected to the other input terminal of the sense amplifier. 9. The semiconductor memory device according to claim 8 , wherein a control signal is supplied to the other ends of the first and second capacitive elements. 6. The semiconductor memory according to claim 5 , further comprising a sense amplifier connected to the third bit line and detecting the data of the magnetic memory cell by comparing the potential of the third bit line with a reference potential. apparatus. The reference potential is a first potential applied to one of the ends of the magnetic memory cell when reading data from the magnetic memory cell, and a second potential applied to the other of the ends of the magnetic memory cell. 11. The semiconductor memory device according to claim 10 , wherein the potential is an intermediate potential between. 11. The semiconductor memory device according to claim 10 , further comprising a reference potential generation circuit that generates the reference potential. The reference potential generating circuit is configured by using a magnetoresistive element similar to the magnetic memory cell, and a dummy magnetic memory cell that generates the reference potential;
13. The semiconductor memory device according to claim 12 , further comprising a fourth bit line from which a reference potential generated in the dummy magnetic memory cell is read. The dummy magnetic memory cell is
A first dummy magnetoresistive element having one end connected to the first node and holding the first data, connected in series with the first dummy magnetoresistive element, one end connected to the second node, A first dummy cell including a second dummy magnetoresistive element holding second data opposite to the first data;
One end of the third dummy magnetoresistive element connected to the first node and holding the second data is connected in series with the third dummy magnetoresistive element, and one end is connected to the second node. A second dummy cell comprising a fourth dummy magnetoresistive element holding the first data;
14. The semiconductor memory device according to claim 13, further comprising a potential synthesis circuit for synthesizing potentials read from the first and second dummy cells to generate the reference potential. The dummy magnetic memory cell is
The first dummy magnetoresistive element having one end connected to the first node and holding the first data, the first dummy magnetoresistive element connected in series, the one end connected to the second node, A first dummy cell comprising a second dummy magnetoresistive element holding 1 data;
A third dummy magnetoresistive element having one end connected to the first node and holding second data opposite to the first data, and one end connected in series with the third dummy magnetoresistive element Is connected to the second node, and a second dummy cell comprising a fourth dummy magnetoresistive element holding second data,
14. The semiconductor memory device according to claim 13, further comprising a potential synthesis circuit for synthesizing potentials read from the first and second dummy cells to generate the reference potential. At the time of reading data from the magnetic memory cell, a first potential difference is applied between the both ends of the magnetic memory cell in a first period, and the first potential is applied between the both ends of the magnetic memory cell in a second period. A switching circuit that provides a second potential difference of the same magnitude and opposite polarity as the potential difference;
Wherein from magnetic memory cell and the third reference potential to read potential to the bit line of the first period, read out from the magnetic memory cell in the second period to the third bit line the semiconductor memory device according to any one of claims 1 to 4, characterized by comprising a read circuit for detecting the data of the magnetic memory cell potentials compared to the reference potential. During an operation of reading data from the magnetic memory cell, a predetermined potential difference is applied between the both ends of the magnetic memory cell in a first period, and the potential difference between the both ends of the magnetic memory cell is applied in a second period. A first switching circuit for providing a potential difference of opposite polarity with the same magnitude;
A second switching circuit for switching and outputting the potential read from the magnetic memory cell to the third bit line between the first period and the second period;
The potential output from the second switching circuit in the first period is held as a reference potential, and the potential output from the second switching circuit in the second period is compared with the reference potential. the semiconductor memory device according to any one of claims 1 to 4, characterized by comprising a sense amplifier for sensing the data of the magnetic memory cell. During an operation of reading data from the magnetic memory cell, a first potential difference is applied between the both ends of the magnetic memory cell in a first period, and the second potential is applied between the both ends of the magnetic memory cell in a second period. A switching circuit for providing a second potential difference having the same magnitude as the potential difference of 1 and having a reverse polarity;
Having one end and the other end, one end being connected to the second bit line, being controlled to be temporarily turned on in the first period, and temporarily turned on in the second period A first switch element that is switching controlled by
A sense amplifier connected to the other end of the first switch element and detecting data of the magnetic memory cell by detecting a change in potential input via the first switch element;
A second switch element connected between the input and output nodes of the sense amplifier, controlled to be turned on in the first period, and temporarily switched to the on state in the second period; the semiconductor memory device according to any one of claims 1 to 4, characterized by comprising a. A plurality of magnetic memory cells are arranged in a matrix, and each magnetic memory cell has at least one of a first magnetoresistive element and a second magnetoresistive element each having a tunnel magnetoresistive effect and holding data opposite to each other. Including at least one transfer gate, wherein the first and second magnetoresistive elements are inserted in series between both ends of each of the magnetic memory cells, and the at least one transfer gate has the first and second magnetic gates. A memory cell array connected in series with a resistive element;
A plurality of first and second bit lines connected to both ends of a plurality of magnetic memory cells provided in each column of the memory cell array;
A plurality of first word lines for writing disposed in a plurality of magnetic memory cells provided in each row of the memory cell array;
A plurality of third bit lines for reading data connected to a plurality of magnetic memory cells provided in each column of the memory cell array;
A plurality of second word lines connected in common to each of the plurality of magnetic memory cells provided in each row of the memory cell array and activated when reading data from the magnetic memory cells;
A sense amplifier provided in each column of the memory cell array and connected to the third bit line in the corresponding column;
Each one end of the first and second magnetoresistive elements is connected to the first and second bit lines, respectively.
Before SL least one or more transfer gate has one end connected to the other end of the first magnetoresistive element, a first transfer gate whose other end is connected to the third bit line, one end of the A second transfer gate connected to the other end of the second magnetoresistive element, the other end connected to the third bit line;
The first, a semiconductor memory device which has both a gate electrode of the second transfer gate, characterized in that connected to each of the plurality of second word lines. A plurality of magnetic memory cells are arranged in a matrix, and each magnetic memory cell has at least one of a first magnetoresistive element and a second magnetoresistive element each having a tunnel magnetoresistive effect and holding data opposite to each other. Including at least one transfer gate, wherein the first and second magnetoresistive elements are inserted in series between both ends of each of the magnetic memory cells, and the at least one transfer gate has the first and second magnetic gates. A memory cell array connected in series with a resistive element;
A plurality of first and second bit lines connected to both ends of a plurality of magnetic memory cells provided in each column of the memory cell array;
A plurality of first word lines for writing disposed in a plurality of magnetic memory cells provided in each row of the memory cell array;
A plurality of third bit lines for reading data connected to a plurality of magnetic memory cells provided in each column of the memory cell array;
A plurality of second word lines connected in common to each of the plurality of magnetic memory cells provided in each row of the memory cell array and activated when reading data from the magnetic memory cells;
A sense amplifier provided in each column of the memory cell array and connected to the third bit line in the corresponding column;
The at least one transfer gate includes first and second transfer gates each having one end connected to the first and second bit lines, respectively .
Both gate electrodes of the first and second transfer gates are connected to the plurality of second word lines;
One end of the first magnetoresistive element is connected to the other end of the first transfer gate, the other end is connected to the third bit line, and one end of the second magnetoresistive element is connected to the second transfer gate. The other end of the semiconductor memory device is connected to the third bit line, and the other end is connected to the third bit line . A plurality of magnetic memory cells are arranged in a matrix, and each magnetic memory cell has at least one of a first magnetoresistive element and a second magnetoresistive element each having a tunnel magnetoresistive effect and holding data opposite to each other. Including at least one transfer gate, wherein the first and second magnetoresistive elements are inserted in series between both ends of each of the magnetic memory cells, and the at least one transfer gate has the first and second magnetic gates. A memory cell array connected in series with a resistive element;
A plurality of first and second bit lines connected to both ends of a plurality of magnetic memory cells provided in each column of the memory cell array;
A plurality of first word lines for writing disposed in a plurality of magnetic memory cells provided in each row of the memory cell array;
A plurality of third bit lines for reading data connected to a plurality of magnetic memory cells provided in each column of the memory cell array;
A plurality of second word lines connected in common to each of the plurality of magnetic memory cells provided in each row of the memory cell array and activated when reading data from the magnetic memory cells;
A sense amplifier provided in each column of the memory cell array and connected to the third bit line in the corresponding column;
The at least one transfer gate comprises a first transfer gate connected between the first magnetoresistive element and the second magnetoresistive element;
Furthermore, it has one end, the other end, and a gate electrode, and one end is connected to a connection point between the first magnetoresistive element and the first transfer gate, and the other end is connected to the third bit line. The second transfer gate has one end and the other end and a gate electrode, one end is connected to a connection point between the second magnetoresistive element and the first transfer gate, and the other end is the third bit. A third transfer gate connected to the line;
The semiconductor memory device, wherein the second word line is connected in common to the gate electrodes of the first to third transfer gates. A plurality of magnetic memory cells are arranged in a matrix, and each magnetic memory cell has at least one of a first magnetoresistive element and a second magnetoresistive element each having a tunnel magnetoresistive effect and holding data opposite to each other. Including at least one transfer gate, wherein the first and second magnetoresistive elements are inserted in series between both ends of each of the magnetic memory cells, and the at least one transfer gate has the first and second magnetic gates. A memory cell array connected in series with a resistive element;
A plurality of first and second bit lines connected to both ends of a plurality of magnetic memory cells provided in each column of the memory cell array;
A plurality of first word lines for writing disposed in a plurality of magnetic memory cells provided in each row of the memory cell array;
A plurality of third bit lines for reading data connected to a plurality of magnetic memory cells provided in each column of the memory cell array;
A plurality of second word lines connected in common to each of the plurality of magnetic memory cells provided in each row of the memory cell array and activated when reading data from the magnetic memory cells;
A sense amplifier provided in each column of the memory cell array and connected to the third bit line in the corresponding column;
The at least one transfer gate comprises a first transfer gate connected between the first magnetoresistive element and the second magnetoresistive element;
Further, a second transfer connected between a connection point between one of the first magnetoresistive element or the second magnetoresistive element and the first transfer gate and the third bit line. Have a gate,
The semiconductor memory device, wherein the second word line is commonly connected to both gate electrodes of the first and second transfer gates. When reading data from each of the plurality of magnetic memory cells, a predetermined potential difference is applied to both ends of each of the magnetic memory cells, and each of the plurality of magnetic memory cells includes the first magnetoresistive element and the first magnetoresistive element. 3. A potential determined by a ratio of a combined resistance of two magnetoresistive elements and a resistance value of the first magnetoresistive element or the second magnetoresistive element is read out to the third bit line. The semiconductor memory device according to any one of 19 to 22 . The semiconductor memory device according to any one of claims 19 to 22 prior Symbol plurality of sense amplifiers respectively, and detecting the data as compared to a reference potential the potential of the respective third bit line . The reference potential is an intermediate potential between a first potential applied to one of the both ends of the magnetic memory cell and a second potential applied to the other of the both ends of the magnetic memory cell when reading data. 25. The semiconductor memory device according to claim 24 , wherein: 25. The semiconductor memory device according to claim 24, comprising a plurality of reference potential generation circuits for generating the reference potential. Each of the plurality of reference potential generation circuits is configured using a magnetoresistive element similar to each of the plurality of magnetic memory cells, and is generated by a dummy magnetic memory cell that generates the reference potential and the dummy magnetic memory cell. 27. The semiconductor memory device according to claim 26, comprising a fourth bit line from which a reference potential is read. The dummy magnetic memory cell is
A first dummy magnetoresistive element having one end connected to the first node and holding the first data, connected in series with the first dummy magnetoresistive element, one end connected to the second node, A first dummy cell including a second dummy magnetoresistive element holding second data opposite to the first data;
A third dummy magnetoresistive element having one end connected to the first node and holding second data, and a third dummy magnetoresistive element connected in series, and one end connected to the second node. A second dummy cell comprising a fourth dummy magnetoresistive element holding the first data;
28. The semiconductor memory device according to claim 27 , further comprising: a potential synthesis circuit for synthesizing potentials read from the first and second dummy cells to generate the reference potential. The dummy magnetic memory cell is
A first dummy magnetoresistive element having one end connected to the first node and holding the first data, connected in series with the first dummy magnetoresistive element, one end connected to the second node, A first dummy cell comprising a second dummy magnetoresistive element holding 1 data;
A third dummy magnetoresistive element having one end connected to the first node and holding second data opposite to the first data, and one end connected in series with the third dummy magnetoresistive element; Is connected to the second node, and a second dummy cell comprising a fourth dummy magnetoresistive element holding second data,
28. The semiconductor memory device according to claim 27 , further comprising: a potential synthesis circuit for synthesizing potentials read from the first and second dummy cells to generate the reference potential. 27. The semiconductor memory device according to claim 26 , further comprising a reference potential generation circuit that generates the reference potential. 31. The semiconductor memory device according to claim 30, wherein the reference potential generating circuit is composed of a plurality of dummy magnetic memory cells for one column provided in the memory cell array. A plurality of drivers provided for each column of the memory cell array, for supplying the predetermined potential difference between the both ends of each of the plurality of magnetic memory cells in each column of the memory cell array when reading data from the magnetic memory cell; 24. The semiconductor memory device according to claim 23, comprising: Each of the plurality of drivers includes a first transistor that applies a first potential to one of the ends of each of the plurality of magnetic memory cells in each column of the memory cell array, and a plurality of magnetic memories in each column of the memory cell array. 33. The semiconductor memory device according to claim 32, comprising: a second transistor that applies a second potential to the other of the both ends of each cell. 33. The semiconductor memory device according to claim 32, wherein each of the plurality of drivers is disposed at one end in the column direction of the memory cell array. Each of the plurality of drivers, before data is read from the magnetic memory cell, according to claim 32, wherein the precharging the ends to a predetermined potential of a plurality of magnetic memory cells of each column of said memory cell array Semiconductor memory device.

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