JP5915121B2 - Variable resistance nonvolatile memory - Google Patents

Description

  The present invention relates to a nonvolatile memory using a resistance variable element.

  In place of flash memory or DRAM, where miniaturization has become apparent, in recent years, resistance change that stores data using resistance variable elements such as MTJ (Magnetic Tunnel Junction) elements as next-generation nonvolatile memory Type memory is attracting attention. Non-volatile memories using this resistance change element include MRAM (Magnetoretic Random Access Memory), PRAM (Phase change Random Access Memory), ReRAM (Resistivity Random RAM resistance type). ) And the like. A memory using such a resistance variable element does not require a complicated process like a flash memory, is compatible with a standard logic process, is suitable for miniaturization, and operates at a low voltage. The future is promising.

  An element configuration, characteristics, and array configuration of a memory using this type of variable resistance element are disclosed in, for example, Patent Document 1 or Non-Patent Documents 1 and 2. In particular, Patent Document 1 has proposed a configuration in which the area of the memory cell can be reduced as compared with the configuration of the memory array described in Non-Patent Document 2.

JP 2008-016098 A

ISSCC Digest of Technical Papers, pp. 258, Feb. 2010. The Institute of Electronics, Information and Communication Engineers IEICE Technical Report ICICE Technical Report ICD2010-7 p35-p40.

  However, the technique of Patent Document 1 has the following drawbacks. A circuit diagram of Patent Document 1 is shown in FIG. In FIG. 23, when the memory cell M00 is selected and “0” is written, the selected bit line BL0 is 0.6V, the row selection line WL0 is 0.6V, the common source line COMSL and the source line branched therefrom. When 0 V is applied to SL01 to SL45, a current flows from the bit line BL0 to the source line SL01 and the common source line COMSL, and the resistance element of the memory cell M00 is set to “0” to be low resistance. At this time, the unselected bit lines BL1, BL2,. When open, the voltage is normally 0 V, so there is no particular problem even if the row selection line WL0 is 0.6 V and the non-selected bit line is connected to the 0 V source line SL.

  However, in the case of writing “1”, the selected bit line BL0 is 0V, the common source line COMSL is 0.6V, and a current flows from the common source line COMSL to the bit line BL0. Is written and becomes high resistance.

  Here, since the unselected bit lines BL1, BL2,... Are open, the memory cell selection transistors of the memory cells M01, M02,... Connected to the row selection line WL0 are turned on. . Then, a charging current flows from the common source line COMSL to the unselected bit lines BL1, BL2,. This charging current stops when the unselected bit lines BL1, BL2,. However, there is a problem that wasteful power is consumed to charge the extra unselected bit lines.

  In addition, although temporarily, the bit line charging current flows through the non-selected memory cells M01, M02,..., A weak write state occurs while the charging current flows. Therefore, there has been a problem that there is a concern that if this state is repeated, data is erroneously written.

  In order to solve this erroneous writing problem, it can be improved by charging the unselected bit lines BL1, BL2,... From the bit line side to 0.6 V which is the same potential as the common source line COMSL. However, even with such improvement, there is a problem in that excessive power consumption cannot be avoided because the charge / discharge of the unselected bit line BL is repeated each time the memory cell is rewritten.

  Therefore, an object of the present invention is to reduce the area of the memory cell of the variable resistance nonvolatile memory and to reduce power consumption.

In order to solve the above problems, the present invention provides a memory cell having a circuit in which a memory cell selection transistor having a local row selection line connected to a gate terminal and a resistance variable element connected in series as a memory cell. A variable resistance nonvolatile memory having a memory cell array configured to be connected to a bit line and a source line, wherein the source line is wired in parallel to the local row selection line, and the bit line is connected to the local row selection line The memory cell array is divided into a plurality of memory blocks, and each memory block includes a circuit that outputs a source voltage lower than a data line voltage to the source line. A partial decoder for controlling only the local row selection line, selecting the memory block, and selecting a partial decoder in the memory block; Only having a first column decoder for transmitting a row selection signal to the local row selection line, selecting a memory block selected by the first column decoder, and operating only a precharge circuit in the memory block. And a second column decoder for connecting the source line to the bit line to precharge the source voltage to the bit line, and a third column decoder for selecting the bit line. And having a row decoder for instructing the partial decoder to select a local row selection line to be selected, applying the source voltage to the source line to write and read data to the memory cell, and to the bit line, wherein the writing and the data line voltage, the data of different values by adding switching between voltage lower than the source voltage to the memory cell It is a variable resistance nonvolatile memory.

  According to such an invention, the source line voltage is kept constant at both the time of writing and the time of reading, so that charging current does not flow to the non-selected bit line, thereby eliminating energy waste and power consumption. There is an effect that can be reduced.

  According to this invention, since the source line is shared between two consecutive rows of the memory cell array, the dimension between the elements in the vertical direction of the memory cell can be shortened. Therefore, there is an effect that the area of the memory cell can be reduced. And by keeping the voltage of the source line constant at both the time of writing and the time of reading, no charging current flows to the unselected bit line, so energy is wasted and power consumption is reduced. There is an effect that can.

  Further, the present invention is the above-described variable resistance nonvolatile memory, wherein the source terminal of the memory cell selection transistor is connected to the source line, and the variable resistance element is connected to the drain terminal of the memory cell selection transistor. A resistance change type nonvolatile memory connected between the bit lines.

  Further, the present invention is the resistance variable nonvolatile memory described above, wherein a circuit in which the memory cell selection transistor of the memory cell and the resistance variable element are connected in series includes a first transistor and a first resistor. A first circuit in which variable-type elements are connected in series, and a second circuit in which a second transistor and a second variable resistance-type element are connected in series, which are connected in parallel; The first variable resistance element is connected between the drain terminal of the first transistor and the bit line, and the second variable resistance element of the second circuit is connected to the drain terminal of the second transistor and the inverted bit line. A variable resistance nonvolatile memory characterized in that one of the first variable resistance element and the second variable resistance element of the memory cell is connected with a low resistance and the other is set to a high resistance to store data. It is memory.

  In the present invention, since the voltage of the source line is not changed by constantly maintaining the voltage of the source line SL at the time of writing or reading, the energy of the energy by changing the voltage of the conventional source line is not changed. There is an effect that waste can be eliminated.

Further, according to the present invention, the precharge circuit precharges the constant source line voltage to the bit line, thereby reducing the time required for the current to flow into the bit line when reading data from the bit line. This is advantageous in that the data can be saved and the data reading speed can be increased.

  Furthermore, by dividing the memory cell array of the present invention into memory blocks and allowing the partial decoder to access a local row selection line limited only within the memory block, there is an effect that power consumption can be reduced.

It is a circuit diagram which shows the structure of 1 bit of the non-volatile memory of 1st Embodiment. 1 is a block diagram illustrating an overall configuration of a nonvolatile memory according to a first embodiment. FIG. 3 is a circuit diagram of a column gate CMOS circuit of a column gate portion according to the first embodiment. It is a block diagram which shows the structure of the power supply circuit of 1st Embodiment. FIG. 3 is a circuit diagram illustrating a configuration of one memory cell according to the first embodiment. It is a figure which shows the structure and operation | movement of the MTJ element of 1st Embodiment. 2 is a plan view showing a layout of the memory cell array in the first embodiment. FIG. It is sectional drawing which shows the cross section of the non-volatile memory cell of 1st Embodiment. It is a figure which shows the operating condition of the memory cell of 1st Embodiment. 10 is a circuit diagram illustrating a configuration of one memory cell according to Modification 1. FIG. FIG. 10 is a diagram illustrating operating conditions of a memory cell according to Modification 1. It is a timing chart showing the operation waveform of a 1st embodiment. It is a circuit diagram which shows the structure of 1 bit of the non-volatile memory of 2nd Embodiment. It is a block diagram which shows the whole structure of the non-volatile memory of 2nd Embodiment. It is a circuit diagram of the partial decoder of 2nd Embodiment. It is a circuit diagram which shows the structure of 1 bit of the non-volatile memory of the modification 2 of 3rd Embodiment. It is a block diagram which shows the whole structure of the modification 2 non-volatile memory of 3rd Embodiment. It is a circuit diagram which shows the structure of 1 bit of the non-volatile memory of 3rd Embodiment. It is a block diagram which shows the whole structure of the non-volatile memory of 3rd Embodiment. It is a circuit diagram which shows the structure of one memory cell of 3rd Embodiment. It is a figure which shows the operating condition of the memory cell of 3rd Embodiment. It is a timing chart showing the operation waveform of a 3rd embodiment. It is a circuit diagram which shows the memory cell array of the conventional non-volatile memory.

  Embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, the transistor refers to a MOSFET (Metal Oxide Semiconductor Field Effect Transistor; field-effect transistor having a metal-oxide film-semiconductor structure).

<First Embodiment>
FIG. 1 is a circuit diagram of a 1-bit memory block and a circuit portion of the 16-bit nonvolatile memory according to the first embodiment. FIG. 2 is a block diagram of a circuit of a 16-bit nonvolatile memory having 16 I / O (× 16) for simultaneously writing to 16 memory cells. As shown in FIG. 2, the memory cell array 100 is divided into 16 blocks of memory blocks 100-0 to 100-15. The memory block 100-0 constitutes a memory cell connected to the 0th bit output bit terminal Dout0. Similarly, the memory block 100-15 constitutes a memory cell connected to the 15th bit output bit terminal Dout15. Reference numerals 400-0 to 400-15 denote column gate blocks corresponding to the memory blocks in the column gate unit 400.

  As shown in the circuit diagram of FIG. 1, one bit of the nonvolatile memory is used to select and drive one memory cell Mkj from the array of memory cells M00 to Mmn included in the memory block 100-0 of the memory cell array 100. The decoder system circuit and other control circuits. The decoder system circuit includes a row decoder 200, a column decoder 300, and a column gate unit 400.

  In the nonvolatile memory according to the present embodiment, m + 1 row selection lines WL0 to WLm cross the memory block 100-i (i = 0 to 15) of the memory cell array 100 in the row direction as shown in FIG. In addition, one source line SL crosses the two row selection lines WLk in the row direction. Each row selection line WLk (k = 0 to m) corresponds to each row of all the memory blocks 100-i (i = 0 to 15) of the memory cell array 100. The row selection line WLk corresponding to the row k is a signal line that transmits a row selection signal to the memory cell Mkj (j = 0 to n) in the kth row of the memory block 100-i (i = 0 to 15). is there.

  The row decoder 200 selects one of the m + 1 row selection lines WL0 to WLm according to the row address, outputs a row selection signal for data writing or data reading to the selected row selection line, and outputs the other row. This circuit outputs a 0V row selection signal to a selection line.

  In the nonvolatile memory according to the present embodiment, n + 1 bit lines BLj (j = 0 to n) cross the memory block 100-0 corresponding to the 0th bit in the column direction. Here, the bit line BLj corresponding to the j-th column is a signal line for transmitting a bit voltage for the memory cell Mkj (k = 0 to m) in the j-th column in the memory block 100-0.

  The column decoder 300 is a circuit that is supplied with a column address and outputs column selection signals COL0 to COLn for selecting a column of the memory cell array of the memory block 100-0 to the column gate unit 400 according to the column address. As shown in FIG. 3, each of the column selection signals COL0 to COLn sets a set of the column selection signal COL and the inverted column selection signal COLB toward the column gate CG of the CMOS (complementary type) circuit of the column gate unit 400. Output. In the following description, a set of the column selection signal COL and the inverted column selection signal COLB is described by representing only the column selection signal COL.

  A circuit corresponding to the memory block 100-0 in the column gate unit 400 includes column gates CG0 to CGn. The column gates CG0 to CGn are a group of MOS switches for switching signals for driving the columns of the memory block 100-0 of the memory cell array 100 according to the column selection signals COL0 to COLn. The column gates CG0 to CGn are 16 times the number of elements shown in the circuit of FIG. 1 corresponding to the circuits of the memory blocks 100-0 to 100-15 shown in FIG.

  As shown in FIG. 3, each column gate CG connects the column selection signal COL to the gate terminal of the N channel MOS transistor of the CMOS circuit, and connects the inverted column selection signal COLB to the gate terminal of the P channel MOS transistor of the CMOS circuit. The N channel MOS transistor and the P channel MOS transistor are connected in parallel between the data lines DL0 to DL15 and the bit lines BL0 to BLn.

  As described above, the column gate CG is formed of a CMOS circuit. In the following description, only the NMOS transistor of one gate circuit of the CMOS circuit is displayed, and the NMOS transistor is represented by the NMOS transistor.

  The same applies to the other memory blocks 100-1 to 100-15 of the memory cell array 100, and n + 1 bit lines BLj (j = 0 to n) cross the memory block 100-i corresponding to the i-th bit in the column direction. ing.

  Like the layout of the semiconductor element shown in the circuit block diagram of FIG. 2, the memory blocks 100-0 to 100-15 have memory block regions arranged in order in the horizontal direction of FIG. In the column gate 400, each gate circuit is arranged above each memory block.

  As other control circuits, a write voltage generation circuit (Write Driver) 500, 16 sense amplifiers 600 (SA0 to SA15) connected to the data lines DL0 to DL15, and an output circuit 700 provided in the subsequent stage of the sense amplifier 600 are provided. (OUT0 to OUT15), a write control circuit 800, a precharge circuit 900 for biasing the bit line BL, and a power supply circuit 1000 (FIG. 4).

(Power circuit)
FIG. 4 is a block diagram illustrating a configuration example of the power supply circuit 1000. The power supply circuit 1000 includes a control circuit 1001, booster circuits 1002 and 1003, step-down circuits 1004 and 1005, and output adjustment circuits 1006 to 1009. The booster circuits 1002 and 1003 are circuits that boost and output the power supply voltage of the nonvolatile memory under the control of the control circuit 1001. The step-down circuits 1004 and 1005 are circuits that step down and output the power supply voltage of the nonvolatile memory under the control of the control circuit 1001.

The output adjustment circuit 1006 of the power supply circuit 1000 outputs a row drive voltage VWL of 1.5V when writing data to the memory cell Mkj, and outputs a row drive voltage VWL of 1.2V when reading data. To do. The output adjustment circuit 1007 outputs a column drive voltage VCOL of 1.5V, and the output adjustment circuit 1008 outputs a data line voltage VWD of 1.2V. The output adjustment circuit 1009 is a circuit that outputs a source voltage VSL of 0.6 V, which is about half the data line voltage VWD .

  Since the output adjustment circuits 1006 and 1007 need to output a voltage higher than the power supply voltage VDD of the nonvolatile memory in order to supply the row drive voltage VWL or the data line voltage VWD, the booster circuit 1002 or 1003 in the previous stage must be output. Use that to generate that voltage. Further, when the output adjustment circuits 1008 and 1009 need to output a voltage lower than the power supply voltage VDD of the nonvolatile memory as the data line voltage VWD of 1.2 V or the source voltage VSL of 0.6 V, the step-down circuit in the previous stage The voltage is generated using 1004 or 1005.

  The general operation of the power supply circuit 1000 is to supply a row drive voltage VWL of 1.5 V, which is the basis of the voltage of the row selection signal, to the row decoder 200 from the output adjustment circuit 1006 under the control of the write control circuit 800. From the output adjustment circuit 1007, the column drive voltage VCOL of 1.5V, which is the basis of the voltage of the column selection signal, is supplied to the column decoder 300. In addition, the output adjustment circuit 1008 supplies the write voltage generation circuit 500 with a data line voltage VWD of 1.2 V that is a basis of a voltage output from the write voltage generation circuit 500 to the data line DL to be connected to the bit line BLj. Then, the output adjustment circuit 1008 supplies the source voltage VSL of 0.6 V to the common source line COMSL. Further, the power supply circuit 1000 supplies the power supply of the precharge circuit 900 with a row drive voltage VWL of 1.5 V that controls the gates of the precharge transistors PR0 to PRn.

(Operation of power supply circuit when writing data)
The power supply circuit 1000 supplies a row drive voltage VWL of 1.5 V from the output adjustment circuit 1005 to the row decoder 200 when data is written (WE = “1”). As a result, the row decoder 200 outputs a row selection signal of 1.5V to the row selection line WLk of the selected row k, and outputs 0V to the other row selection line WLk ′.

  In addition, the control circuit 1001 generates a data line voltage VWD of 1.2 V from the output adjustment circuit 1008 and supplies it to the write voltage generation circuit 500. As a result, the write voltage generation circuit 500 outputs the data line voltage VWD of 1.2 V to the data line DLi when the write data input signal Dini is “0”. The write voltage generation circuit 500 outputs 0 V to the data line DLi when the write data input signal Dini is “1”.

  In addition, the control circuit 1001 outputs a 0.6V source voltage VSL from the output adjustment circuit 1009. The 0.6V source voltage VSL is supplied to the common source line COMSL, and the common source line COMSL is branched to the source line SL. The common source line COMSL is always maintained at the source voltage VSL of 0.6 V even when data is read.

(Operation of power supply circuit when reading data)
When the power supply circuit 1000 reads data (WE = “0”), the control circuit 1001 supplies the row driving voltage VWL of 1.2 V to the row decoder 200 from the output adjustment circuit 1006. A row selection signal having a row driving voltage VWL of 2V is output to the row selection line WLk.

  In the data read operation, the row drive voltage VWL is set to 1.2 V, which is lower than 1.5 V at the time of data write, because an excessive current that destroys the memory content of the resistance variable element R changes in resistance. This is to prevent it from flowing into the mold element R.

  The feature of this embodiment is that the source voltage VSL of 0.6 V is supplied to the common source line COMSL and the common source line COMSL is branched to the source line SL. Thus, the feature of this embodiment is that the voltage of the source line SL is always held at 0.6 V, both at the time of writing and at the time of reading.

  The write control circuit 800 is a circuit that receives the write data input signal Din and the write control signal WE and delivers the write control signal WE and the data input signals Din0 to Din15 to the write voltage generation circuit 500.

The write voltage generation circuit 500 includes a three-state buffer that drives the data lines DL0 to DL15. Then, the write data input signal Din and the write control signal WE are received from the write control circuit 800, and a write voltage is output to the data lines DL0 to DL15. Here, the write voltage generation circuit 500 outputs 0V to the data line DL when the write data input signal Din is High, and the 1.2V data line to the data line DL when the write data input signal Din is Low. The configuration is such that the voltage VWD is output.
At the time of reading, the write voltage generating circuit 500 is turned off and the output is set to HiZ (high impedance).

  Data lines DL0 to DL15 of the write voltage generation circuit 500 are signal lines for transmitting data to be written to the memory cell array 100 or data read from the memory cell array 100.

  The sense amplifier 600 is connected to the data line DL, and an output circuit 700 is provided after the sense amplifier 600. The sense amplifier 600, the output circuit 700, and the write voltage generation circuit 500 perform operations for reading data.

In the memory block 100-0 of the memory cell array 100, memory cells M00 to Mmn are arranged in a matrix of m + 1 rows and n + 1 columns as shown in FIG. As shown in FIG. 2, 16 memory blocks 100-0 to 100-15 are arranged to form a 16-bit memory cell array 100. As such, matrix memory cells Mkj of m + 1 rows and n + 1 columns are arranged for each memory block.

  As shown in FIG. 1, in the 1-bit memory block 100-0, the row selection line WL0 of the row decoder 200 is connected to the gates of the memory cells M00 to M0n arranged in the row direction and arranged in the row direction. A row selection line WL1 is commonly connected to the gates of the memory cells M10 to M1n.

  The two groups of memory cells share one source line SL01, memory cells M00 to M0n connected to the row selection line WL0 are disposed on the source line SL01, and the row selection line WL1 is disposed below the source line SL01. Memory cells M10 to M1n to be connected are arranged.

  Similarly, for the memory cells M20 to M3n sharing one source line SL23, the memory cells M20 to M2n having the gate connected to the row selection line WL2 are arranged on the source line SL23, and below the source line SL23. The memory cells M30 to M3n connected to the row selection line WL3 are arranged at the gate.

  Thus, the row selection line WLk that runs in the row direction is connected to the n + 1 memory cells Mkj (j = 0 to n) forming one row. A row selection signal is transmitted from the row decoder 200 to these row selection lines WLk (k = 0 to m), whereby a row of memory cells is selected.

  The m + 1 memory cells Mkj (k = 0 to m) forming one column are connected to a common bit line BLj running in the column direction. The bit line BLj (j = 0 to n) is a signal line for transmitting data to be read / written to / from the memory cell Mkj in the memory block 100-0.

  FIG. 5 is a circuit diagram showing a configuration of the memory cell Mkj. As shown in FIG. 5, in the nonvolatile memory cell Mkj according to the present embodiment, the resistance variable element R is connected to the bit line BLj, and the source terminal of the N-channel memory cell selection transistor TN is connected in series to the source line SL. The gate terminal is connected to the row selection line WLk. The bit line BLj is a signal line for transmitting data to be read / written to the memory cell Mkj.

  More specifically, in the present embodiment, the MTJ element shown in FIG. 6 is used as the resistance variable element R, and as shown in the circuit diagram of FIG. 6, the free layer of the resistance variable element R that is an MTJ element is the bit line BLj. The pin layer is connected to the drain terminal of the N-channel memory cell selection transistor TN, and the source terminal of the N-channel memory cell selection transistor TN is connected to the source line SL.

  The transistor circuit connected to the resistance variable element R is represented in FIG. 6 as a representative example of an N-channel memory cell selection transistor TN. However, this transistor circuit is preferably composed of a CMOS circuit. That is, it is desirable that an N-channel MOS transistor and a P-channel MOS transistor of the CMOS circuit are arranged in parallel between the MTJ element and the source line SL to control the current flowing through the MTJ element. In the memory cell selection transistor TN formed of a CMOS circuit, a voltage drop corresponding to the threshold value of the transistor (so-called threshold drop) does not occur. Therefore, the difference between the voltage applied to the common source line COMSL and the voltage applied to the bit line BLj is determined as an MTJ element. There is an effect that data can be written into the memory cell only by applying only the applied voltage to the resistance variable element. Thereby, there exists an effect which can reduce power consumption.

6A and 6B show the configuration and operation of a memory cell when an MTJ (Magnetic Tunnel Junction) element is used as the resistance variable element R of the nonvolatile memory cell Mkj in FIG. . As shown in FIGS. 6A and 6B, the MTJ element is composed of a pinned layer having a constant magnetic direction, a tunnel barrier film, and a free layer whose magnetic direction changes.

  As shown in FIG. 6A, when a current in a direction from the free layer to the pinned layer of the MTJ element is passed, the magnetization direction of the free layer becomes the same as that of the pinned layer, the MTJ element becomes low resistance, and data “0” Is stored.

  Conversely, as shown in FIG. 6B, when a current in the direction from the pinned layer toward the free layer is passed, the magnetization direction of the free layer is opposite to that of the pinned layer, the MTJ element becomes high resistance, and data “1” "Is stored. When a memory cell is configured with such an MTJ element, an N-channel memory cell selection transistor TN is used as a switch for selecting the MTJ element as illustrated in FIGS. 6A and 6B. The MTJ element is connected in series.

(3D structure of memory cell)
FIG. 7 is a plan view showing a layout example of the memory cell array 100 when the MTJ element MTJ is used as the resistance variable element R in this embodiment, and FIG. 8 is a cross-sectional view showing the cross-sectional structure thereof. The three-dimensional structure of the memory cell array 100 is shown by the plan view of FIG. 7 and the cross-sectional view of FIG.

  As shown in the plan view of FIG. 7 and the cross-sectional view of FIG. 8, the row selection line WLk and the source line SL arranged in the row direction are arranged in parallel to each other and orthogonal to both the source line SL and the row selection line WLk. A bit line BLj which is a signal line for transmitting data to be read / written to the memory cell Mkj is arranged in the column direction.

  FIG. 7 is a diagram showing a layout example of the memory cell array 100 in FIG. As shown in FIG. 7, in the memory cell array 100, a plurality of rectangular source / drain diffusion regions (N-type impurity regions) are arranged in a matrix. In this layout example, three source / drain diffusion regions arranged in the column row direction are taken as a set, and two row selection lines WLk made of a polysilicon layer are provided in two gaps in the column direction between the source / drain diffusion regions. , WL (k + 1) crosses in the row direction. Then, one source line SLk (k + 1) of the first metal layer Mt1 on the center source / drain diffusion region crosses in the row direction. In FIG. 7, a region surrounded by a broken line is a region in which one memory cell M00 including one N-channel memory cell selection transistor TN is formed.

  That is, a single source line SLk (k + 1) is wired between two sets of row selection lines WLk and WL (k + 1) in parallel to the row selection line, so that the polylines of the row selection lines WLk and WL (k + 1) can be obtained. The source terminals of the two memory cell selection transistors TN formed by the gaps between the source / drain diffusion regions under the silicon layer are connected to a common source line SLk (k + 1).

  In this layout example, since the source line SLk (k + 1) is shared between two consecutive rows of the memory cell array 100, the vertical inter-element dimensions of the memory cells Mkj and M (k + 1) j can be shortened. Therefore, there is an effect that the area of the memory cell can be reduced. As a result, the resistance variable nonvolatile memory can be speeded up and manufactured at low cost.

The N-channel memory cell selection transistor TN of the memory cell Mkj functions as a selection switch for selecting the resistance variable element R (MTJ element MTJ) at the time of data reading and data writing, and its gate terminal is the row selection line WLk. And a row selection signal is applied from the row selection line WLk. Then, the column selection signal COLj is applied to the column gate CGj, and the selected column gate CGj connects the bit line BLj to the data line DL.

  The circular mark in FIG. 7 indicates a portion of the through hole CS that connects the source terminal of the N-channel memory cell selection transistor TN to the source line SL wired in the first metal layer Mt1. As shown in the cross-sectional view of FIG. 8, in order from the top layer, the through hole CS connected to the source line SL wired in the first metal layer Mt1, and the n-channel diffusion of the source of the N-channel memory cell selection transistor TN of the semiconductor substrate Layers overlap.

  As shown in FIG. 7, the memory terminal of the memory cell selection transistor TN of the N channel of the memory cell M00 selected by the row selection line WL0 and the memory of the memory cell selected by the row selection line WL1 described below in the figure. The source terminal of the cell selection transistor TN is connected to the source line SL01 wired in the first metal layer Mt1 through a common through hole CS.

  The square mark in FIG. 7 is a portion of the MTJ element MTJ, and as shown in the cross-sectional view of FIG. 8, the through hole V1 connected to the bit line BL0 wired in the second metal layer Mt2 in order from the upper layer, The through hole CS connected to the first metal layer Mt1 of the MTJ element overlaps the n-channel diffusion layer of the drain of the N-channel memory cell selection transistor TN of the semiconductor substrate.

  The cross-sectional view of FIG. 8 is a cross-sectional view of the semiconductor substrate SUB along the column direction perpendicular to the row selection line WLk. The memory cell M20 including the N-channel memory cell selection transistor TNa formed on the semiconductor substrate SUB , A memory cell M30 including an N-channel memory cell selection transistor TNb.

  The memory cell selection transistor TNa is a transistor for selecting the memory cell M20, and the memory cell selection transistor TNb is a transistor for selecting the memory cell M30. The row selection line WL2 is connected to the gate of the N-channel memory cell selection transistor TNa to select the row of the memory cell M20, and the row selection line WL3 is connected to the gate of the transistor TNb to select the row of the memory cell M30. The The source terminals of the memory cells M20 and M30 are connected to a common source line SL23.

(Basic unit consisting of two memory cells)
Hereinafter, the configuration and operation of the memory cell array 100 will be described with reference to FIG. The memory cell M20 is configured by connecting a resistance variable element R1 and a memory cell selection transistor TNa in series. The configuration of the memory cell M30 is the same as that of M20, and is configured by connecting the resistance variable element R2 and the memory cell selection transistor TNb in series.

  The source terminals of the memory cell selection transistor TNa of the memory cell M20 and the memory cell selection transistor TNb of the memory cell M30 are connected to a common source line (SL23). The ends of the resistance variable elements R1 and R2 of the memory cells M20 and M30 are connected to the bit line BL0.

(Operation of memory cell Mkj)
FIG. 9 shows operating conditions for data writing and reading with respect to the resistance variable element R of the memory cell Mkj when the memory cell Mkj is selected. The feature of this operating condition is that the voltage of the source line SL is always held at 0.6 V at the time of writing and reading as described below.

(Write operation)
(Write “0”)
First, data writing to the resistance variable element R of the memory cell Mkj will be described. When “0” is written to the resistance variable element R, a data line voltage VWD of 1.2 V is applied to the bit line BLj, a source voltage VSL of 0.6 V is applied to the source line SL, and 1 is applied to the row selection line WLk. A row drive voltage VWL of .5 V is transmitted and used as a row selection signal.

  In this state, a voltage of about 0.6 V, which is the difference between the 1.2 V data line voltage VWD and the 0.6 V source voltage VSL, is applied to both ends of the variable resistance element R of the MTJ element, and from the bit line BLj. A current of about 49 μA flows through the source line SL. That is, current flows from the free layer of the MTJ element to the pinned layer, and the resistance variable element R of the MTJ element has a low resistance. That is, the resistance variable element R is in a “0” write state.

(Write “1”)
When “0” is written to the resistance variable element R of the memory cell Mkj, 0 V is applied to the bit line BLj, a source voltage VSL of 0.6 V is applied to the source line SL, and 1.5 V is applied to the row selection line WLk. A row driving voltage VWL is transmitted and used as a row selection signal.

  In this state, a voltage of −0.6 V, which is a difference between the 0 V voltage of the bit line BLj and the 0.6 V source voltage VSL, is applied to both ends of the resistance change element R of the MTJ element, and the voltage from the source line SL is increased. A current of about 49 μA flows through the bit line BLj. That is, current flows from the pinned layer to the free layer of the MTJ element, and the resistance variable element R of the MTJ element has a high resistance. That is, the resistance variable element R is in a “1” write state.

  In this way, data is written to the resistance variable element R of the memory cell Mkj while maintaining the voltage of the source line SL at a constant source voltage VSL, and a voltage higher than the voltage of the source line SL is applied to the bit line BLj. By switching between 1.2V and low voltage 0V, different values of data are written into the memory cell Mkj.

(Read operation)
Next, data reading from the resistance variable element R of the memory cell Mkj will be described. When reading data, the write voltage generation circuit 500 puts the three-state buffer connected to the data line DL into a floating state. The sense amplifier 600 connected to the data line DL is provided with a data line bias circuit for biasing the data line DL to 0.45V, and the data line DL is biased to 0.45V. For other circuit nodes, 0.6 V is applied to the source line SL23, and a row driving voltage VWL of 1.2 V is transmitted to the row selection line WL. The sense amplifier 600 detects the voltage of the data line DL connected to the bit line BLj, thereby reading the data in the memory cell Mkj.

  In the data read operation, the row drive voltage VWL is set to 1.2 V, which is lower than 1.5 V at the time of data write, because an excessive current that destroys the memory content of the resistance variable element R changes in resistance. This is to prevent it from flowing into the mold element R.

  Here, when the resistance variable element R stores data “0” and has a low resistance, a current of 15 μA flows from the bit line BLj to the source line SL. On the other hand, when the resistance variable element R stores data “1” and has a high resistance, a current of 10 μA flows from the bit line BLj to the source line SL. Therefore, a threshold value (for example, 12.5 μA) is generated between the current 15 μA that flows when data “0” is read and the current 10 μA that flows when data “1” is read, and from the bit line BLj to the source line SL when data is read. By comparing the current flowing in the direction with this threshold value, it is possible to determine whether the data stored in the resistance variable element R1 is “0” or “1”.

  As described above, the voltage of the source line SL is always kept at 0.6 V both at the time of writing and at the time of reading, so that the voltage of the source line is not changed, so that the voltage of the conventional source line is changed. There is an effect that waste of energy can be eliminated.

(Modification 1)
FIG. 10 is a circuit diagram showing a configuration of the memory cell Mkj of the first modification. As shown in FIG. 10, in the nonvolatile memory cell Mkj of Modification 1, the resistance variable element R is connected to the source line SL, and the source terminal of the N-channel memory cell selection transistor TN is connected in series to the bit line BLj. The gate terminal is connected to the row selection line WLk. More specifically, the free layer of the resistance variable element R is connected to the source line SL, and an N-channel transistor TN is interposed between the pin layer of the resistance variable element R and the bit line BLj.

(Operation of Memory Cell Mkj of Modification 1)
FIG. 11 shows operating conditions for data writing and reading with respect to the resistance variable element R of the memory cell Mkj of the first modification. Also in this operating condition, the voltage of the source line SL is always held at 0.6 V at the time of writing and reading, as in FIG. 9 of the operating condition in the case of the memory cell Mkj having the circuit configuration of FIG.

(Timing chart)
FIG. 12 shows operation waveforms of the timing chart of the nonvolatile memory of the present embodiment. In particular, the source voltage VSL of 0.6 V of the power supply circuit 1000 is supplied to the common source line COMSL, and is branched to the source line SL, and the voltage of the source line SL is maintained at the source voltage VSL of 0.6 V.

(Precharge mode)
As shown in FIG. 12, the nonvolatile memory of the present embodiment is in a precharge mode in the initial state. That is, the write control signal WE = Low, the precharge activation signal PRE applied to the precharge circuit 900 is High, and the precharge signal output from the precharge circuit 900 is High. Therefore, all the precharge transistors PRj (j = 0 to n) of the precharge circuit 900 are turned on, and all the bit lines BLj (j = 0 to n) are connected to the source line SL by the precharge transistors PRj. A source voltage VSL of 0.6V is precharged. During precharge, Low is supplied to the row selection line WLk and the column selection signal COLj.

(Write mode)
Next, the write control signal WE is set to High to enter the data write mode, and the write voltage generation circuit 500 sets the 3-state buffer that drives the data line DL to the output enable state.

  Before setting the write control signal WE to High, the address ADD is specified, and the write data input signal Din is transmitted to the write control circuit 800. Next, the write control signal WE is set to High to transmit it, the 3-state buffer of the data line DL is set to the output enable state, and the precharge activation signal PRE is switched from High to Low, whereby the gates of the precharge transistors PR0 to PRn are switched. Then, the connection between the bit line BL and the common source line COMSL having a voltage of 0.6 V is disconnected to finish the precharge.

The address ADD is broken down into a row address and a column address. By outputting a column drive voltage VCOL of 1.5 V to the column selection signal COLj from the column decoder 300, the column gate CGj is opened and the data line DL is connected to the bit line BLj. Further, a row selection line W is sent from the row decoder 200.
By outputting 1.5V to Lk, a row is selected and a memory cell Mkj is selected.

(When writing “0”)
Here, when “0” is written to the memory cell Mkj, the write data input signal Din = Low is set. Then, the write voltage generation circuit 500 outputs 1.2 V to the data line DL. As a result, the voltage of the bit line BLj connected to the data line DL becomes 1.2 V, a forward current flows through the resistance variable element R of the selected memory cell Mkj, and the resistance is set to a low resistance.

(When “1” is written)
Here, when “1” is written to the memory cell Mkj, the write data input signal Din = High is set. Then, the write voltage generation circuit 500 outputs 0V to the data line DL. As a result, the voltage of the bit line BLj connected to the data line DL becomes 0 V, a reverse current flows through the resistance variable element R of the memory cell Mkj, and the resistance is set to a high resistance.

(Unselected bit line)
Here, since the non-selected bit line BLj ′ is precharged to be connected to the common source line COMSL and charged to the source voltage VSL of 0.6 V while the precharge activation signal PRE is High, Even after the connection is disconnected, the source voltage VSL of 0.6 V is maintained. Therefore, even when a selection voltage of 1.5V is transmitted to the selected row selection line WLk, in the non-selected memory cell Mkj ′, a charging current flows to the resistance variable element R via the memory cell selection transistor TN. There is no effect. That is, there is an effect that the problem of erroneous writing, which has been a concern in the prior art circuit, does not occur.

  Even if the voltage of the bit line BLj ′ is disconnected from the source line SL, it is always precharged to the source voltage VSL of 0.6V. Therefore, even if the bit line BLj ′ is connected to the source line SL again, a wasteful charging current does not flow from the source line SL to the bit line BLj ′ because the voltage of the bit line BLj ′ is the same voltage as the source line SL. The current consumption can be reduced.

(Read mode)
Next, in the read mode, the write control signal WE is set to Low to enter the data read mode, and the write voltage generation circuit 500 puts the three-state buffer that drives the data line DL into a floating state. Here, all the bit lines BLj are always precharged to the potential of the source voltage VSL of 0.6 V, as in the writing. When the address ADD is determined, the precharge activation signal PRE is switched from the High state to Low.

  By switching the precharge activation signal PRE from High to Low, the gates of the precharge transistors PR0 to PRn are closed, and the bit line BLj is disconnected from the common source line COMSL having a voltage of 0.6V. On the other hand, by outputting 1.2 V to the column selection signal COLj, the column gate CGj is opened and the data line DL is connected to the bit line BLj.

(Unselected bit line)
When the precharge activation signal PRE is set to Low, the non-selected bit line BLj ′, that is, the bit line BLj ′ that is not connected to the data line DL is in a floating state, but when the precharge activation signal PRE is High first, 0.6V Since the source voltage VSL is precharged, the voltage of the bit line BLj ′ is always maintained at 0.6V.

(Selected bit line)
On the other hand, the data line DL is connected to the bit line BLj selected by the column selection signal COLj of 1.2V. Also, the selected row selection line WLk becomes 1.2V, the gate of the memory cell selection transistor TN of the memory cell Mkj selected by the row selection line WLk is opened, and the resistance variable element R becomes 0.6V. Are connected to the source line SL of the source voltage VSL.

  Thereby, from the source line SL having a voltage of 0.6 V, the resistance change element R of the selected memory cell Mkj, the bit line BLj connected thereto, and the data connected to the bit line BLj via the column gate CGj. A current flows through the line DL, and a current flows into the sense amplifier 600 connected to the data line DL.

(When reading “0”)
Here, when the memory cell Mkj to be accessed stores data “0”, a current of 15 μA is generated from the source line SL → the resistance variable element R1 of the memory cell Mkj → the bit line BLj → the data line DL → the sense amplifier. It follows the route 600.

(When reading “1”)
On the other hand, when the memory cell Mkj to be accessed stores data “1”, a current of 10 μA flows along the same path. Therefore, the sense amplifier 600 compares the current I flowing into the data line DL with an intermediate threshold value Iref (reference current: Reference) between 10 μA and 15 μA, and if I> Iref, the data “0”, and if I <Iref, the data “0”. Outputs “1”. The output circuit 700 outputs the output data of the sense amplifier 600 to the outside.

<Second Embodiment>
A second embodiment will be described with reference to FIGS. The circuit of FIG. 14 is an overall circuit diagram of the circuit of the second embodiment having a 16-bit × 8-page configuration that operates in the page mode. FIG. 13 shows one of the memory blocks 110-0 and its periphery. The circuit of is shown. FIG. 15 shows a partial decoder 230 and its peripheral circuits, which are characteristic parts of the second embodiment different from those of the first embodiment. Also in the second embodiment, as in the first embodiment, the voltage of the source line SL is always held at 0.6 V when writing to and reading from the memory cell Mkj.

  In FIG. 13, 500 is a write voltage generation circuit, 600 is a sense amplifier, 330 is a third column decoder that receives a page address P and selects a page, and 450 is a selection gate transistor that selects a page. In other circuits, 310 and 320 are a first column decoder and a second column decoder for selecting a memory block, 210 is a main row decoder, 220 is a sub row decoder, 700 is an output circuit, and 800 is a write It is a control circuit.

  In FIG. 13, the first column decoder 310 receives the column address C, selects the memory block 110-j, selects the memory block 110-j, the column selection signal COLj, and its inverted signal COLBj (j = 0 to 0). n) is output. That is, the column selection signal COLj opens the column gate CG that connects all the bit lines BL0 to BLh of the memory block 110-j to all the data lines DL0 to DLh among the column gates CG of the column gate unit 410. 110-j is selected. Here, h can be about 127, for example, when all the data lines DL0 to DLh are 128, or when h is more than that.

Similar to the first column decoder 310, the second column decoder 320 receives the column address C and activates a precharge circuit 910-j that precharges only the selected memory block 110-j. That is, when the column address is determined and the memory block 110-j is selected, the precharge starts. At that time, the precharge current flows, but after that, the page address changes while it is wasted. No precharge current flows, and in particular, no precharge current flows in a memory block that is not selected, so that it is possible to achieve low power consumption.

  The third column decoder 330 receives the column address P, divides all bit lines BLj (j = 0 to h) in the memory block into eight blocks, and selects one bit line from each block. Data is output to the output circuit 700.

  In the second embodiment, as shown in FIG. 14, the memory cell array 100 is divided into memory blocks 110-0 to 110-n, and each memory block, for example, the memory block 110-0 is divided into memory cells M00 to Mmh (h = 127), and the circuit configuration is such that the memory block is selected by the first column decoder 310.

  Then, the power is consumed only by one memory block including the memory cell Mkj for reading / writing the stored data, and the power is hardly consumed for most other memory blocks. In this embodiment, a main row decoder 210 that operates in response to the row address A and a sub-row decoder 220 that operates in response to the row address B are provided.

  Main row decoder 210 outputs an access signal to global row selection lines GWL0 to GWLg, and global row selection lines GWL0 to GWLg are connected to partial decoders 230 of all memory blocks.

  Sub-row decoder 220 outputs sub-decode signals φ0 and φ1, and this sub-decode signal φ is a partial decoder selection column gate provided for each memory block in a part of column gate section 410 as shown in FIG. Via 410a, the local decode signal lines φj0 and φj1 of each memory block are connected. Partial decoder selection column gate 410a is also connected to local decode signal lines φBj0 and φBj1 that transmit inverted signals of φj0 and φj1. These local decode signal lines are connected to the partial decoder 230 of each memory block. The partial decoder selection column gate 410a for each memory block transmits a selection signal only to the local decode signal lines φj0 and φj1 of the memory block selected by the column selection signal COLj output from the first column decoder 310.

  When the local decode signal line φj0 = High and φBj0 = Low, the partial decoder 230 connected thereto, for example, the buffer 235-0 of the partial decoder 230-0 is selected and operated. When the local decode signal line φj1 = High and φBj1 = Low, the partial decoder 230 connected thereto, for example, the buffer 235-1 of the partial decoder 230-0 is selected and operated.

  In addition, the memory block 110-j ′ that has not been selected is output Low from the partial decoder selection column gate 410a to the local decode signal lines φj′0 and φj′1, so that the memory block 110-j that has not been selected is selected. The j partial decoder 230 is prevented from operating.

  Thus, the signal for controlling the partial decoder 230 connects the global row selection line GWL from the main row decoder 210, and in addition, the subdecode signal φ from the sub row decoder 220 is sent via the partial decoder selection column gate 410a. To the partial decoder 230. Only the memory block selected by the column selection signal COLj operates the partial decoder 230 connected to the partial decoder selection column gate 410a.

  The partial decoder 230 in the memory block is connected to a plurality of local row selection lines LWL that are wired only in the memory block. Only the partial decoder 230 of the memory block selected by the column selection signal COLj transmits a row selection signal to the local row selection line LWL selected by the subdecode signal φ among the local row selection lines LWL connected thereto. .

  The partial decoder 230 is configured as follows. That is, the partial decoder 230-0 of FIG. 15 includes the buffer 235-0 of the local row selection line LWL0 by the transistors 231, 232, and 233. Similarly, 235-1 is a buffer for outputting a signal to the local row selection line LWL1. 235-0 and 235-1 constitute one partial decoder 230-0.

  The partial decoder 230-0 is selected by the output of the global row selection line GWL0 of the main row decoder 210. Further, the partial decoder selection column gate 410a of the memory block 110-0 is activated by the column selection signal COL0 of the first column decoder 310, and the partial decoder selection column gate 410a is set to the local decode signal lines φ00, φB00, φ01, and φB01. Output a signal. The signals on the local decode signal lines φ00, φB00, φ01, and φB01 select the buffer 235-0 or the buffer 235-1 of the partial decoder 230-0.

  When the selection signal (φ00 = High) is transmitted to the local decode signal lines φ00 and φB00 of the memory block 110-0 selected by the selection signal COL0, the buffer of the partial decoder 230-0 selected by the global row selection line GWL0 235-0 is selected. When the selection signal (φ01 = High) is transmitted from the local decode signal lines φ01 and φB01 to the partial decoder 230-0 selected by the global row selection line GWL0, the buffer 235-1 is selected.

  Specifically, the global row selection line GWL0 is selected, the L level is output to that line, the global row selection line GWL1 is not selected, and the High level is output. In this state, the buffers 235-0 and 235-1 of the partial decoder 230-0 connected to the global row selection line GWL0 are selected, and the buffers 235-2 and 235 of the partial decoder 230-1 connected to the global row selection line GWL1. -3 is not selected.

  The local decode signal lines φ00 = High and φB00 = Low of the selected memory block 110-0 are selected. On the other hand, the local decode signal lines φ01 and φB01 are not selected, and φ01 = Low and φB01 = High. Become. For this reason, the buffer 235-0 of the partial decoder 230-0 is selected. Therefore, the local row selection line LWL0 is selected and becomes LWL = High, and other local row selection lines are not selected, and LWL1 = LWL2 = LWL3 = Low. It becomes.

  In short, one of the memory blocks is selected by the output of the first column decoder 310, the partial decoder 230 is selected by the main row decoder 210, and only the partial decoder 230 of the selected memory block among the selected partial decoders 230 is activated. Is done. Then, one of the local row selection lines connected to the activated partial decoder 230 is selected by subdecode signals φ0 and φ1 output from the subrow decoder 220.

With such a configuration, current consumption can be reduced by dividing the memory block into a plurality of memory blocks. That is, the row selection decoder includes a main row decoder 210 common to all memory blocks, a sub row decoder 220, and a partial decoder 230 provided for each memory block. Then, the partial decoder 230 is selected by the main row decoder 210 and the first column decoder 310, and only the selected partial decoder 230 is operated. The local row selection line LWL controlled by the partial decoder 230 is selected and designated by the sub row decoder 220.

  By doing so, the main row decoder 210 receives the row address A, outputs an access signal to the global row selection line GWL that accesses the set of rows, and selects the partial decoder 230. Then, the sub row decoder 220 receives the row address B and outputs an access signal to the local row selection line of the partial decoder 230-k. The partial decoder 230-k is selected by the first column decoder 310 that selects the memory block 110-j, and only the partial decoder 230-k of the selected memory block 110-j is activated.

  The local row selection line LWL connected to the partial decoder 230-k is wired only in one memory block. As a result, the partial decoder 230-k transmits a row selection signal only within the selected memory block. Therefore, there is an effect that power consumption can be reduced.

  Here, the decode signals output from sub-row decoder 220 are not limited to two types of φ0 and φ1, and sub-row decoder 220 is configured to output two or more types of sub-decode signals φ0, φ1,. You may do it. In that case, local decode signal lines φj0, φj1,... Φjd are drawn out from the partial decoder selection column gate 410a. The partial decoder 230 connected to each global row selection line GWL of each memory block is configured to have buffers 235-0 to 235-m of local row selection lines LWL0 to LWLm.

  Eventually, in the second embodiment, the first column decoder 310 receives the column address C, selects the memory block 110-j, and selects all the bit lines BL0 to BLh of the memory block 110-j. COLj and its inverted signal COLBj (j = 0 to n) are output. The column selection signal COLj is connected to all the column gates CGr (r) connected to the selected memory block 110-j, for example, the bit line BLr (r = 0 to h) of the memory block 110-0. r = 0 to h) are opened, and all the bit lines BL0 to BLh are connected to the data lines DL0 to DLh.

  Further, the column selection signal COLj opens the column gate of the partial decoder selection column gate 410a of the selected memory block in the column gate unit 410, and the subdecode signal φ from the sub row decoder 220 is selected as the selected memory block. To the partial decoder 230.

  Similar to the first embodiment, this embodiment also includes a second column decoder 320 that receives the column address C and selects the precharge circuit 910-j for the memory block selected by the first column decoder 310. . The second column decoder 320 selects and operates the precharge circuit 910-j, for example, the precharge circuit 910-0 for the memory block 110-0, so that the precharge circuit 910-0 operates in the memory block 110-0. All bit lines BLj (j = 0 to h) are precharged. In the second embodiment, as in the first embodiment, the voltage of the source line SL is always held at 0.6 V when writing to and reading from the memory cell Mkj.

The present embodiment is characterized in that only one memory block in the memory cell array 100 is selected and operated by being configured in this way. That is, only the selected memory block, for example, the memory block 110-0 is selectively precharged. In addition, the row selection signal is transmitted only to the local row selection line LWL only in the selected memory block. In this embodiment, since only the selected memory block in the memory cell array 100 is operated as described above, the power consumption can be reduced.

(Modification 2)
As a modification (modification 2) of the second embodiment, a circuit may be configured as shown in FIGS. In the second modification, the selection signal of the precharge circuit 910-j from the second column decoder 320 is connected to each partial decoder 230 of each memory block. The partial decoder 230 is further connected to sub-decode signals φ0 and φ1 from the sub-row decoder 220. Partial decoder 230 is activated by a selection signal from second column decoder 320 and transmits a row selection signal to local row selection line LWL connected to sub row decoder 220 by sub decode signals φ0 and φ1 from sub row decoder 220. To do.

(Modification 3)
As a third modification, the second column decoder 320 is deleted, and instead, the precharge circuit 910-j of the selected memory block 110-j is changed by the selection signal of the memory block 110-j from the first column decoder 310. to start. The selection signal of the memory block 110-j from the first column decoder 310 can be configured to activate the partial decoder 230 in the selected memory block 110-j.

<Third Embodiment>
The third embodiment is characterized in that the circuit configuration of the memory cell Mkj is a high-speed differential memory cell. Also in the third embodiment, as in the first embodiment, the voltage of the source line SL is always held at 0.6 V when writing to and reading from the memory cell Mkj.

  FIG. 18 is a circuit diagram of a 1-bit circuit portion of the 16-bit nonvolatile memory according to the third embodiment. As in the first embodiment, the third embodiment is a 16-bit non-volatile memory having 16 I / O (× 16) for simultaneously writing to 16 memory cells. The memory cell array 100 is divided into 16 blocks of memory blocks 100-0 to 100-15. Reference numerals 420-0 to 420-15 are column gate blocks corresponding to the memory blocks in the column gate unit 420.

  As shown in FIG. 18, the source lines SL of all the memory cells are connected to the common source line COMSL. The memory block 100-0 constitutes a memory cell connected to the 0th bit output bit terminal Dout0. Similarly, a memory block 150-15 connected to the output bit terminal Dout15 of the 15th bit is configured. The row decoder 200 receives a row address and selectively outputs a row selection line WLk (k = 0 to m). The column decoder 300 receives a column address and outputs a column selection signal COLj (j = 0 to n).

  The memory cell Mjk of this embodiment constitutes a high-speed differential memory cell as shown in FIG. A bit line BLj and an inverted bit line BLBj are connected to the memory cell Mkj in FIG. As shown in FIG. 18, the bit line BLj (j = 0 to n) of the memory block 100-0 is connected to the data line DL0 via the column gate CGj of the column gate unit 420, and the inverted bit line BLBj is connected to the column gate unit 420. Is connected to the inverted data line DLB0 via the column gate CGBj.

Further, as shown in FIG. 19, the bit line BLj (j = 0 to n) of the memory block 100-16 is connected to the data line DL15 via the column gate CGj of the column gate unit 420, and the inverted bit line BLBj is connected to the column gate. The column 420 is connected to the inverted data line DLB15 via the column gate CGBj of the unit 420. That is, the bit line BLj of the memory block 100-u (u = 0 to 15)
Are connected to the data line DLu via the column gate CGj of the column gate section 420, and the inverted bit line BLBj is connected to the inverted data line DLBu via the column gate CGBj of the column gate section 420.

  In the memory cell Mkj, as shown in FIG. 20A, a resistance change element R1 and a memory cell selection transistor TN1 are connected in series between a bit line BLj and a source line SL, and an inverted bit line BLBj and a source line SL are connected. The resistance variable element R2 and the memory cell selection transistor TN2 are connected in series between the two. That is, the source terminals of the memory cell selection transistors TN1 and TN2 are connected to the common source line SL. A row selection line WLk is connected to the gates of the memory cell selection transistors TN1 and TN2. Opposite data is written in the resistance variable elements R1 and R2, and the differential operation is performed.

  As a modification, FIG. 20B shows a memory cell circuit in which the resistance change element R1 and the memory cell selection transistor TN1 and the resistance change element R2 and the memory cell selection transistor TN2 in FIG. Show.

  As shown in FIG. 18, the precharge circuit 900 receives the precharge signal PRE, opens all the bit lines BLj (j = 0 to n) and the inverted bit lines BLBj by opening the gates of the precharge transistors PRj and PRBj. Connect to voltage VSL. As a result, all the bit lines BLj (j = 0 to n) and the inverted bit lines BLBj are precharged to a source voltage VSL of 0.6V.

  As in the first embodiment, the write voltage generation circuit 500 outputs a data line voltage VWD of 1.2 V to the data line DL when the write data input signal Din is High, and also outputs to the inverted data line DLB. Outputs a voltage of 0V. When the write data input signal Din is Low, a voltage of 0V is output to the data line DL, and a data line voltage VWD of 1.2V is output to the inverted data line DLB.

  When the sense amplifier 600 reads data from the memory cell Mkj, the sense amplifier 600 determines the difference between the resistance values of the resistance variable elements R1 and R2 of the memory cell Mkj to determine “0” or “1” data. The output circuit 700 amplifies the output of the sense amplifier 600 and outputs it to the output bit terminal Dout. The write control circuit 800 receives the write control signal WE and the write data input signal Din and controls writing.

FIG. 21A shows the operation of the memory cell Mkj in FIG.
(When writing “0”)
When writing “0” into the memory cell Mkj, the write data input signal Din is set to Low. As a result, the write voltage generation circuit 500 outputs 0 V to the data line DL, and outputs a data line voltage VWD of 1.2 V to the inverted data line DLB. Then, the voltage of the bit line BLj connected to the data line DL becomes 0V, and the inverted bit line BLBj = 1.2V. On the other hand, 0.6 V is applied to the source line SL, and a voltage of 1.5 V is applied to the row selection line WLk to select the memory cell Mkj.

  As a result, a current flows from the 0.6V source line SL to the 0V bit line BL, and the resistance variable element R1 changes to a high resistance because a current flows in the opposite direction. At the same time, a current flows from the 1.2V inverted bit line BLB to the 0.6V source line SL, and a current flows in the resistance variable element R2 in the forward direction, so that the resistance changes. This state is defined as “0” writing.

(When “1” is written)
Here, when “1” is written to the memory cell Mkj, the write data input signal Din
Set High to. As a result, the write voltage generation circuit 500 outputs the data line voltage VWD of 1.2V to the data line DL, and outputs 0V to the inverted data line DLB. Then, the voltage of the bit line BLj connected to the data line DL becomes 1.2V, and the inverted bit line BLBj = 0V. On the other hand, 0.6 V is applied to the source line SL, and a voltage of 1.5 V is applied to the row selection line WLk to select the memory cell Mkj.

  As a result, a current flows from the 1.2V bit line BL to the 0.6V source line SL, and a current flows in the resistance variable element R1 in the forward direction, so that the resistance changes. At the same time, a current flows from the 0.6V source line SL to the 0V inverted bit line BLB, and the resistance variable element R2 changes to a high resistance because a current flows in the opposite direction. This state is defined as “1” write.

(Read operation)
Next, data reading from the resistance variable elements R1 and R2 of the memory cell Mkj will be described. When reading data, the write voltage generation circuit 500 puts the three-state buffer connected to the data line DL into a floating state. The sense amplifier 600 connected to the data line DL is provided with a data line bias circuit for biasing the data line DL to 0.45V, and the data line DL is biased to 0.45V. For other circuit nodes, 0.6 V is applied to the source line SL, and a 1.2 V row selection signal is transmitted to the row selection line WLk. Then, the sense amplifier 600 reads the data of the memory cell Mkj by differentially detecting the voltage of the data line DL and the inverted data line DLB.

  Here, when the memory cell Mkj stores “0”, reading of the data is performed as follows. By supplying the column selection signal COLj, the bit line BLj is selected via the column gate CGj of the column gate unit 420 and connected to the data line DL, and the inverted bit line BLBj is selected via the column gate CGBj. Connected to DLB. In this way, a column is selected, and a memory cell Mkj is selected by supplying a row selection signal of 1.2 V to the row selection line WLk and selecting a row.

  Bit line BLj and inverted bit line BLBj are connected to data line DL and inverted data line DLB via column gates CGj and CGBj, and data line DL and inverted data line DLB are connected to sense amplifier 600. Then, a current is supplied from the source line SL to the data input terminal of the sense amplifier via the resistance change element R1, and a current is supplied from the source line SL to the inverted data input terminal of the sense amplifier via the resistance change element R2.

  Here, when the memory cell Mkj stores “0”, since the resistance variable element R1 has a high resistance and the resistance variable element R2 has a low resistance, from the source line SL of the high resistance resistance variable element R1. The potential at which the far terminal is connected to the bit line BLJ is low, and the potential at which the far terminal from the source line SL of the low resistance variable resistance element R2 is connected to the inverted bit line BLBj is high. Therefore, the potential relationship between the bit line BLj and the inverted bit line BLBj is BLj <BLBj. The sense amplifier detects this potential difference and determines that “0” data is stored in the memory cell Mkj.

  Conversely, when the memory cell Mkj stores “1”, since the resistance variable element R1 has a low resistance and the resistance variable element R2 has a high resistance, the source line SL of the low resistance resistance variable element R1 is used. The potential at which the far terminal is connected to the bit line BLJ is high, and the potential at which the far terminal from the source line SL of the high resistance variable resistance element R2 is connected to the inverted bit line BLBj is low. Therefore, the potential relationship between the bit line BLj and the inverted bit line BLBj is BLj> BLBj. The sense amplifier detects this potential difference and determines that “1” data is stored in the memory cell Mkj.

  Similarly to the first embodiment, the memory cell Mkj according to the present embodiment always has a source voltage at the time of data writing, “0” writing, “1” writing, and data reading. Is a constant voltage of 0.6V. Therefore, there is no need to charge / discharge the source line SL at the time of data writing / reading, and there is an effect that high-speed reading is possible. In addition, since such a useless current for charging / discharging the source line SL does not flow, there is an effect that power consumption can be reduced.

  FIG. 21B shows the operation of the memory cell Mkj in FIG. In the memory cell Mkj of FIG. 20B, the resistance variable elements R1 and R2 are connected between the memory cell selection transistors TN1 and TN2 and the source line. Therefore, the relationship between the voltage applied to the bit line BLj and the inverted bit line BLBj and the voltage to be read is opposite to that in FIG. Also in the memory cell Mkj of FIG. 20B, the selection of the memory cell Mkj by applying 0.6 V to the source line SL and applying the voltage of 1.5 V to the row selection line WLk is shown in FIG. The circuit is the same as (a).

(Timing chart)
FIG. 22 shows operation waveforms of a timing chart of the nonvolatile memory of FIG.
(Precharge mode)
In the initial state, the precharge mode is set, the write control signal WE = Low, the precharge activation signal PRE applied to the precharge circuit 900 is High, and the precharge signal output from the precharge circuit 900 is High. is there. Therefore, the precharge transistors PRj (j = 0 to n) and PRBj of the precharge circuit 900 are all turned on, and all the bit lines BLj (j = 0 to n) and the inverted bit lines BLBj are turned on by the precharge transistors PRj and PRBj. Connected to the common source line COMSL. Accordingly, the 0.6V source voltage VSL of the common source line COMSL is supplied to the bit line BLj and the inverted bit line BLBj to be precharged.

(Write mode)
Next, the write control signal WE is set to High to enter the data write mode, and the write voltage generation circuit 500 sets the 3-state buffer that drives the data line DL to the output enable state.

  Before setting the write control signal WE to High, the address ADD is specified, and the write data input signal Din is transmitted to the write control circuit 800. Next, the write control signal WE is set to High to transmit it, the 3-state buffer of the data line DL is set to the output enable state, and the precharge activation signal PRE is switched from High to Low, whereby the gates of the precharge transistors PR0 to PRn are switched. Then, the connection between the bit line BL and the common source line COMSL having a voltage of 0.6 V is disconnected to finish the precharge.

  The address ADD is broken down into a row address and a column address. By outputting 1.5 V to the column selection signal COLj from the column decoder 300, the column gates CGj and CGBj are opened, the data line DL is connected to the bit line BLj, and the inverted data line DLB is connected to the inverted bit line BLBj. In addition, a row is selected by outputting 1.5 V from the row decoder 200 to the row selection line WLk, and the memory cell Mkj is selected.

(When writing “0”)
Here, when “0” is written to the memory cell Mkj, the write data input signal Din = Low is set. Then, the write voltage generation circuit 500 outputs 0V to the data line DL and outputs 1.2V to the inverted data line DLB. As a result, the voltage of the bit line BLj connected to the data line DL becomes 0V, and the bit line BLBj connected to the inverted data line DLB.
Becomes 1.2V.

  As a result, a current flows from the common source line COMSL of 0.6 V to the bit line BLj of 0 V via the memory cell selection transistor TN1 and the resistance variable element R1 of the selected memory cell Mkj, and the resistance variable element R1 , Current flows in the opposite direction, resulting in high resistance. Further, a current flows from the 1.2 V inversion bit line BLBj to the 0.6 V common source line COMSL via the resistance change element R2 and the memory cell selection transistor T2, and a current flows in the resistance change element R2 in the forward direction. Flows and becomes low resistance. That is, “0” data is written into the memory cell Mkj.

(When “1” is written)
Here, when “1” is written to the memory cell Mkj, the write data input signal Din = High is set. Then, the write voltage generation circuit 500 outputs 1.2V to the data line DL and outputs 0V to the inverted data line DLB. As a result, the voltage of the bit line BLj connected to the data line DL becomes 1.2V, and the voltage of the bit line BLBj connected to the inverted data line DLB becomes 0V.

  As a result, a current flows from the 1.2V bit line BLj to the 0.6V common source line COMSL via the resistance change element R1 of the selected memory cell Mkj and the memory cell selection transistor T1, and the resistance change type. A current flows through the element R1 in the forward direction, resulting in a low resistance. Further, a current flows from the common source line COMSL of 0.6V to the inverted bit line BLBj of 0V via the memory cell selection transistor TN2 and the resistance variable element R2, and the current flows in the resistance variable element R2 in the reverse direction. Flows and becomes high resistance. That is, “1” data is written into the memory cell Mkj.

(Unselected bit line)
At this time, the non-selected bit line BLj ′ and the inverted bit line BLBj ′ are precharged to 0.6 V in advance during the precharge period. Therefore, the non-selected bit line BLj and the inverted bit line BLBj are connected to the common source of 0.6 V even if a row selection signal is input from the row selection line WLk selected to the gate terminals of the memory cell selection transistors TN1 and TN2. A charging current does not flow from the source line connected to the line COMSL via the memory cell selection transistors TN1 and TN2. Therefore, a low current consumption can be realized without an extra current flowing in the memory cell of the non-selected memory cell Mkj ′.

(Read mode)
Next, in the read mode, the write control signal WE is set to Low to enter the data read mode, and the write voltage generation circuit 500 sets a three-state buffer for driving the data line DL (and the inverted data line DLB). Float so that the voltage can be set to any value. Here, all the bit lines BLj and the inverted bit lines BLBj are always precharged to the VSL level of 0.6 V, as in the writing. When the address ADD is determined, the precharge activation signal PRE is switched from the High state to Low.

  By switching the precharge activation signal PRE from High to Low, the gates of the precharge transistors PR0 to PRn and PRB0 to PRBn are closed to disconnect the bit line BLj and the inverted bit line BLBj from the common source line COMSL, By outputting 1.5 V to the column selection signal COLj, the column gates CGj and CGBj are opened, the data line DL is connected to the bit line BLj, and the inverted data line DLB is connected to the inverted bit line BLBj.

(Unselected bit line)
When the precharge activation signal PRE is set to Low, the unselected bit line BLj ′ and the inverted bit line BLBj ′ that are not connected to the data line DL and the inverted data line DLB are in a floating state, but when the precharge activation signal PRE is first High. In addition, since the bit line BLj ′ and the inverted bit line BLBj ′ are precharged to 0.6V, the bit line BLj ′ is always maintained at 0.6V, and useless charge / discharge current does not flow.

(Selected bit line)
On the other hand, the data line DL and the inverted data line DLB are connected to the bit line BLj and the inverted bit line BLBj selected by the column selection signal COLj of 1.2V. Also, the selected row selection line WLk becomes 1.2 V, the gates of the memory cell selection transistors TN1 and TN2 of the memory cell Mkj selected by the row selection line WLk are opened, and the resistance variable elements R1 and R2 thereof are opened. Is connected to the source line SL having a voltage of 0.6V.

  Thereby, from the source line SL connected to the common source line COMSL having a voltage of 0.6 V, the resistance change elements R1 and R2 of the selected memory cell Mkj, the bit line BLj connected thereto, and the bit line BLj are connected. A current flows through the data line DL and the inverted data line DLB connected via the column gates CGj and CGBj, and a current flows out to the sense amplifier 600 connected to the data line DL and the inverted data line DLB.

(When reading “0”)
Here, when the memory cell Mkj to be accessed stores data “0”, since the resistance variable element R1 has a high resistance and the resistance variable element R2 has a low resistance, the data input to the sense amplifier 600. The voltage of the line DL (bit line BLj) becomes lower than the voltage of the inverted data line DLB (inverted bit line BLBj (DL <DLB)), and the sense amplifier 600 determines that the data in the memory cell Mkj is “0”. “0” is output to the output bit terminal Dout.

(When reading “1”)
On the other hand, when the memory cell Mkj to be accessed stores data “1”, since the resistance variable element R1 is low resistance and the resistance variable element R2 is high resistance, the data line input to the sense amplifier 600 The voltage of DL (bit line BLj) becomes higher than the voltage of inverted data line DLB (inverted bit line BLBj (DL> DLB), and sense amplifier 600 determines that the data in memory cell Mkj is “1” and outputs it. “1” is output to the bit terminal Dout.

  According to the present embodiment, a large difference can be generated between the resistance value of the resistance variable element R1 and the resistance value of R2 when data is written to the memory cell Mkj. For this reason, a signal indicating the magnitude relationship between the resistance values of the two can be read from the nonvolatile memory cell at high speed, and the reading of the memory cell Mkj can be speeded up.

  The same operation can be realized even if the memory cell Mkj in the circuit of FIG. 18 uses the memory cell having the circuit configuration of FIG.

  In the present embodiment, reverse data is written to the resistance variable elements R1 and R2, differential operation is performed, and the signal from the memory cell Mkj is detected differentially by the sense amplifier 600. Even if the current value flowing through the cell and the discharge time are location dependent, the data stored in the memory cell Mkj can be read accurately in a balanced manner and the data can be written accurately in a balanced manner. Therefore, there is an effect that data can be read at high speed.

Note that the resistance change element R used in the nonvolatile memory cell of the present invention is not limited to the MTJ element. For example, CER (Collective Elec) used in the memory cell of ReRAM.
It is also possible to use a resistance change element R of tro-Resistance (electric field induced giant resistance change).

100: Memory cell arrays 100-0, 100-1, 100-n ... Memory blocks 110-0, 110-1, 110-n ... Memory block 200 ... Row decoder 210 ... Main row Decoder 220 ... sub-row decoders 230, 230-k, 230-0, 230-1 ... partial decoders 231, 232, 233 ... transistors 235-0 to 235-m ... buffer 300 ... Column decoder 310 ... first column decoder 320 ... second column decoder 330 ... third column decoders 400, 410, 420 ... column gate sections 400-0 to 400-15, 420-0 to 420 -15... Column gate block 410a... Partial decoder selection column gate 500, WD... Write voltage generation circuit 600, SA. Samp 700, OUT ... Output circuit 800 ... Write control circuit 900, 910-0 to 910-n ... Precharge circuit 1000 ... Power supply circuit 1001 ... Control circuit 1002, 1003 ... Step-up circuits 1004, 1005 ... Step-down circuits 1006, 1007, 1008, 1009 ... Output adjustment circuit AY0 ... Column address signal AY0B ... Inverted column address signals BL, BL0-BLn ... Bit lines CG, CG0 to CGn, CGB, CGB0 to CGBn ... column gates COL, COL0, COL1, COL2, COL3, COLn-1, COLn ... column selection signal COLB ... inverted column selection signal COMSL ... common source line CS: Through hole Din, Din0 to Din15, write data input signal D DL0 to DL15, DL0 to DLh, data line DLB, inverted data lines Dout0 to Dout15, output bit terminals GWL, GWL0 to GWLg, global row selection lines LWL, LWL0 to LWLm, local Row selection lines Mkj, M00, M01, M03 to Mm (n + 1)... Memory cell Mt1... First metal layer Mt2... Second metal layer n... N channel diffusion layer p. Region PRE ... Precharge activation signals PR0-PRn, PRB0-PRBn ... Precharge transistors R, R1, R2, MTJ ... Variable resistance elements SL, SL01-SLn (n + 1) ... Source line SUB ... Semiconductor substrate TN, TNa, TNb, TN1, TN2 ... Memory cell selection transistor VCOL ... Column drive voltage VSL ... Source voltage VWD ... Data line voltage VWL ... Row drive voltage V1 ... Through hole WE ... Write control signals WL, WLk, WL0 to WLm ... Row selection lines φ, φ0, φ1... Subdecode signal φ00, φ01, φB00, φB01... Local decode signal line

Claims (3)

A memory configured by connecting a memory cell selection transistor having a local row selection line connected to a gate terminal and a resistance variable element in series as a memory cell, and connecting the terminal of the memory cell to a bit line and a source line A variable resistance nonvolatile memory having a cell array,
The source line is wired parallel to the local row selection line, and the bit line is wired perpendicular to the local row selection line,
A circuit for outputting a source voltage lower than a data line voltage to the source line;
The memory cell array is divided into a plurality of memory blocks;
A partial decoder for controlling only a local row selection line in each memory block;
A first column decoder that selects the memory block and causes only a partial decoder in the memory block to transmit a row selection signal to the local row selection line;
The memory block selected by the first column decoder is selected, only the precharge circuit in the memory block is operated, the source line is connected to the bit line in the precharge circuit, and the source voltage is set to the bit A second column decoder for precharging the line;
A third column decoder for selecting the bit line;
A row decoder for instructing the partial decoder to select a local row selection line;
Applying the source voltage to the source line to write and read data to the memory cell,
A variable resistance nonvolatile memory, wherein different data values are written to the memory cell by switching and applying the data line voltage and a voltage lower than the source voltage to the bit line. 2. The variable resistance nonvolatile memory according to claim 1 , wherein a source terminal of the memory cell selecting transistor is connected to the source line, and the variable resistance element is connected to a drain terminal of the memory cell selecting transistor. A variable resistance nonvolatile memory characterized by being connected between bit lines. 3. The variable resistance nonvolatile memory according to claim 2 , wherein a circuit in which the memory cell selection transistor and the variable resistance element of the memory cell are connected in series includes a first transistor and a first resistance change. A first circuit in which type elements are connected in series, and a second circuit in which a second transistor and a second variable resistance element are connected in series, which are connected in parallel. One resistance change element is connected between the drain terminal of the first transistor and the bit line, and the second resistance change element of the second circuit is connected between the drain terminal of the second transistor and the inverted bit line. A variable resistance nonvolatile memory characterized in that one of the first variable resistance element and the second variable resistance element of the memory cell has a low resistance and the other has a high resistance to store data. .