JP3869777B2 - Liquid crystal display device and driving method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly to a liquid crystal display device used as a monitor of a personal computer and a driving method thereof.
[0002]
[Prior art]
In recent years, it is a well-known fact that information electronic devices such as mobile phones are widely used in the world. It is also well known that information electronic equipment has a liquid crystal display device as its display equipment. It is also well known that a plurality of display driver ICs are used to drive such a liquid crystal display device.
[0003]
Furthermore, liquid crystal display devices using a plurality of display drive ICs (hereinafter abbreviated as LCD panels) have increased in screen size and resolution, and display image signals with different resolutions when used as monitors for personal computers. Things are required.
[0004]
Such an LCD panel is disclosed in Patent Document 1 or Patent Document 2, for example.
[0005]
However, the LCD panel has a fixed resolution (data line, scanning line) for each device due to its structure. If an image signal having a resolution different from the resolution of the device is displayed as it is, a part of the same image as shown in FIG. There is a problem that (for example, graphic ABC) is repeatedly displayed.
[0006]
In response to this problem, when displaying an image signal with a different resolution, display driving is performed to enlarge or reduce the image signal according to the resolution of the apparatus, or to display the image signal at the center of the screen at the same magnification (equal magnification centering display). Processing other than IC.
[0007]
That is, in the conventional LCD panel, the main CPU performs the above-mentioned processing by time-sharing control, but the burden on the CPU is drastically increased due to the increase in processing data due to the higher resolution of the LCD panel and the higher functionality of the set itself. Therefore, in order to realize the dispersion of processing without increasing the number of chips, it has been desired to provide the display driver IC with the processing function.
[0008]
Among them, Patent Document 1 discloses a technique for changing the number of pixels to be displayed by the display driver IC when performing the same-size centering display with a plurality of display resolutions.
[0009]
In general, in an LCD panel, a plurality of display drive ICs having the same number of drive outputs, that is, displayable pixels and scanable lines are mounted side by side to display an image. When displaying with different resolutions in this configuration, display pixels can be switched only in units of the number of drive outputs of one display drive IC. Therefore, in the above conventional example, a plurality of display drive ICs with different numbers of drive outputs are prepared so that the display drive ICs can be separately arranged at the boundary between display and non-display when the display resolution is changed.
[0010]
These display drive ICs are mounted in combination to realize the same-size centering display with a plurality of resolutions.
[0011]
[Patent Document 1]
Japanese Patent Laid-Open No. 9-055909 (paragraph numbers 0002 to 007, FIGS. 25 and 26)
[Patent Document 2]
Japanese Patent Laid-Open No. 10-260657 (paragraph numbers 0007 to 009, FIG. 14)
[0012]
[Problems to be solved by the invention]
However, in the conventional example, a plurality of types of display drive ICs having different drive output numbers must be prepared, which lacks versatility. That is, in order to use the above technique, it is necessary to set a state corresponding to the resolution for all the display drive ICs mounted on the LCD panel. Moreover, as the LCD panel has a higher resolution, the number of display drive ICs to be mounted also increases, and the lower display resolution (low resolution) to be supported also increases. Therefore, the number of state setting data increases.
[0013]
In general, when the refresh rate is the same, the frequency decreases as the resolution decreases (= the clock decreases), and it becomes difficult to set the control mode for all the mounted display drive ICs during the blanking period.
[0014]
In order to solve this problem, a display driver IC having a circuit configuration capable of controlling a block to be driven in accordance with the display resolution can be used for a simple configuration.
[0015]
An object of the present invention is to provide a circuit that can be manufactured with a simple component configuration, and can quickly set the state of a display driver IC, which is a problem when an equal-size centering display is performed on an LCD panel.
[0016]
[Means for Solving the Problems]
The liquid crystal display device of the present invention is a first signal substrate in a liquid crystal display device in which a plurality of scanning lines and a plurality of data lines are arranged in a matrix, receives image data, and displays the image data on a display panel. A first H driver group including a plurality of H drivers disposed on the left side of the display panel from the center of the display panel on the first signal board; and from the center of the display panel. And a second H driver group including a plurality of H drivers arranged on the right side of the display panel, and the H driver includes an arrangement identification terminal for identifying an arrangement position on the first signal board. The mode data of the image data is input to the head H driver of the first H driver group and the head H driver of the second H driver group, and then the first H driver group The mode data is serially transferred to the H driver at the stage, and the second H driver group sequentially transfers the mode data serially to the H driver at the next stage, and is displayed at the same magnification centering display. In some cases, the number of pixels to be displayed with respect to the center of the screen of the display panel is the same on the left and right sides by the mode data and the arrangement identification terminal.
[0017]
Further, the mode data of the image data of the liquid crystal display device of the present invention is configured to include state setting data at the time of the same-size centering display.
[0018]
Furthermore, the state setting in the liquid crystal display device according to the present invention at the same magnification centering display is determined by the mode data. In addition, the state setting of the liquid crystal display device of the present invention at the time of the same size centering display is determined by the signal level of the arrangement identification terminal.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
In the present invention, the number of pixels to be displayed with respect to the center of the screen is the same on the left and right sides at the same centering display. That is, the left and right arrangement (mounting) state with respect to the screen is identified, and information on the number of pixels to be displayed is counted from the center of the screen so that the H drivers in the same place on the left and right are the same.
[0020]
Next, the present invention will be described with reference to the drawings. Referring to FIG. 1, the H driver 104 of the LCD panel 100 according to the embodiment of the present invention determines the state setting of the equal centering display based on the mode data 204 and the signal level of the arrangement identification terminal 208.
[0021]
In the example shown in FIG. 1, mode data 204 is input from the center of the LCD panel 101 on the first signal board 103 to the H drivers 104-4 and 104-5 of the present invention, and then the left side of the screen. H driver (arrangement terminal 208 is at H level) is arranged in the previous stage H driver 104, and H driver arranged on the right side of the screen (arrangement terminal 208 is at L level) is in the next stage H driver. The mode data 204 is sequentially transferred to the driver 104 serially.
[0022]
As described above, the present invention is also characterized in that the mode data 204 is serially transferred from the center of the screen simultaneously to the left and right in order to reduce the transfer period compared to the method of transferring the mode data 204 serially one chip at a time. .
[0023]
Next, the present invention will be described in detail with reference to the drawings.
[0024]
FIG. 1 is a block diagram schematically showing the configuration of the LCD panel according to the first embodiment of the present invention.
[0025]
The LCD panel 100 according to the first embodiment of the present invention includes a glass substrate 101 sandwiching liquid crystal, an H driver 104 that drives the horizontal direction of the screen, a first signal substrate 103 on which they are mounted, and a vertical direction of the screen. A V driver 106 (to scan), a second signal board 105 on which the V driver 106 is mounted, and a timing controller 102 for controlling display of the H driver 104 and the V driver 106 are provided.
[0026]
A first control signal line 107 is connected between the timing controller 102 and the first signal board 103, and a second control signal line 108 is connected between the timing controller 102 and the second signal board 105. Has been. Since the connection with the V driver on the second signal board 105 is related to the present invention, the description thereof is omitted.
[0027]
Next, the configuration of the first signal board 103 will be described. In the example shown in FIG. 1, eight H drivers 104-1 to 104-8 are mounted on the first signal board 103, and the arrangement identification terminal 208 of the H drivers 104-1 to 104-4 is the first. Are connected to the identification wiring 213 connected to the H level on the signal board 103, and the arrangement identification terminals 208 of the H drivers 104-5 to 104-8 are connected to the identification wiring 213 connected to the L level. ing.
[0028]
The second mode input / output 211-X of each H driver 104-X (X: an integer from 1 to 7) is connected to the first mode input / output 212- (X + 1) of the next stage H driver 104- (X + 1). Has been. However, the first mode input / output 212-1 of the H driver 104-1 and the second mode input / output 211-8 of the H driver 104-8 disposed on both sides of the first signal board 103 are connected to each other. Because there is no, it is open.
[0029]
In addition, from the central portion of the first signal board 103, the mode data 204 sent from the timing controller 102 is the second mode input / output 211-4 of the H driver 104-4 and the H driver 104-5. It is connected to the wiring between the first input / output 212-5.
[0030]
Next, with reference to FIG. 2, the H drivers 104-1 and 104-2 will be described as an example of a connection configuration between the H drivers on the first signal board 103 and a signal from the timing controller 102. To do.
[0031]
Each of the display data 203, the clock 206, and the enable 207 signal output from the timing controller 102 is input to each H driver 104 on the first signal board 103 via the first control signal wiring 107. .
[0032]
The start pulse 205 output from the timing controller 102 is connected to the start pulse terminal 210-1 of the H driver 104-1 on the first signal substrate 103 via the first control signal wiring 107. The cascade output terminal 209-1 of the H driver 104-1 is serially connected to the start pulse terminal 210-2 of the next stage H driver 104-2.
[0033]
Although not shown, the cascade output terminal (209-X) of each H driver is connected to the start pulse terminal 210- (X + 1) of the next stage H driver 104- (X + 1). The cascade output terminal 209-8 of the final stage H driver 104-8 is open because there is no connection destination.
[0034]
Next, a block configuration for holding display data 203 and mode data 204 of the H driver 104 will be described with reference to FIG.
[0035]
This block includes a shift register 202 that generates a sampling pulse SP that holds display data 203, a display register 307 that holds display data 203, and a mode register 201 that holds mode data.
[0036]
First, the configuration of the shift register 202 will be described. The shift register 202 includes n FFs 303 and n first selectors 302, and the start pulse 205 is connected to the second input 402 of each first selector 302. The cascade output is connected to the second output 403 of each selector 302. A switch 306 is arranged between the start pulse 205 and the cascade output 305.
[0037]
The first input 401 of the first first selector 302-1 is grounded, and the f-th (f: integer from 2 to n) first, excluding the first first selector 302-1. The first input 401 of the selector 302 is connected to the output 503 of the (f−1) -th FF 303.
[0038]
The first input 501 of each FF 303-t (t: integer from 1 to n) is connected to the first output 404 of each first selector 302-t. The second input 502 of each FF 303 -t is connected to the clock 206.
[0039]
Next, the configuration of the display register 307 will be described. The display register 307 includes n latch circuits 301, and the output 503 of each FF 303-t is connected.
[0040]
Next, the configuration of the mode register 201 will be described. The mode register 201 includes two (in this embodiment) FF 303 and two second selectors 310. First, in the second selector 310 -A, the first terminal 601 is connected to the first mode input / output 212, and the second terminal 602 is connected to the second mode input / output 211. . On the other hand, in the second selector 310 -B, the first terminal 601 is connected to the second mode input / output 211, and the second terminal 602 is connected to the first mode input / output 212. .
[0041]
The first input 501 of the FF 303-A is connected to the third terminal 603 of the second selector 310-A. Further, a CL signal 308 obtained by ANDing the clock 206 and the enable 207 is connected to the second input 502 of the FF 303 -A. The output 503 of the FF 303-A is connected to the first input 501 of the FF 303-B. An inverted signal of the CL signal 308 is connected to the second input 502 of the FF 303-B. The output 503 of the FF 303-B is connected to the third terminal 603 of the second selector 310-B.
[0042]
FIG. 4 shows the configuration of the first selector 302. Referring to FIG. 4, the first selector 302 has a first input 401 and a second input 402, and a first output 404 and a second output 403. The selection switch selects any one of the first input 401, the second input 402, and GND and connects it to the first output 404. The switch 405 is disposed between the first input 401 and the second output 403.
[0043]
FIG. 5 shows the configuration of the FF 303. The FF 303 has a first input 501 and a second input and output 503.
[0044]
FIG. 6 shows the configuration of the second selector 310. The second selector 310 connects either the first terminal 601 or the second terminal 602 to the third terminal 603 with a selection switch.
[0045]
Next, the operation of the present invention will be described step by step.
[0046]
In the embodiment of the present invention, the case where the resolution state to be displayed is four (2 bits) will be described.
[0047]
As shown in FIG. 1, the mode data 204 of the LCD panel 100 according to the first embodiment of the present invention has a second mode input / output 211 of the H driver 104-4 from the center of the first signal board 103. -4 and the first mode input / output 212-5 of 104-5. The first mode input / output 212 and the second mode input / output of each H driver 104 have input / output attributes determined by the level of the arrangement identification signal 208 and are located on the left side of the first signal board 103.
The arrangement identification terminals 208 of the H drivers 104-1 to 104-4 are connected to the H level, the second mode input / output 211 is an input attribute, and the first mode input / output 212 is an output attribute. The second terminal 310 selects the first terminal.
[0048]
On the other hand, the arrangement identification terminals 208 of the H drivers 104-5 to 104-8 on the right side of the first signal board 103 are connected to the L level, the first mode input / output 212 has the input attribute, and the second The mode input / output 211 is an output attribute.
[0049]
Further, the transfer timing of the mode data 204 of the present embodiment in which the second selector 310 selects the second terminal is as shown in FIG.
[0050]
Since the first mode input / output 212 and the second mode input / output 211 of each H driver 104 are connected between the front and rear H drivers, the shift of the mode data 204 is also shifted between the H drivers. Is done. Therefore, the mode data 204 output from the timing controller 102 in synchronization with the clock 206 is sequentially transferred to the first signal board 103 at the change timing of the CL signal 308 obtained by ANDing the clock 206 and the enable 207 in the H driver 104. The mode data 204 of the H driver 104 arranged on the center side of the first signal board 103 is transferred from the mode data 204 of the H driver 104 at both the left and right ends.
[0051]
In the case of the present embodiment, 2-bit data (M4 [1: 0]) initially set in the H drivers 104-1 and 104-8 is transferred. Second, 2-bit data (M3 [1: 0]) set in 104-2 and 104-7 is transferred.
[0052]
Third, 2-bit data (M2 [1: 0]) set in 104-3 and 104-6 is transferred, and finally, 2-bit data (M1 [1: 0]) set in 104-4 and 104-5. Is transferred, and the transfer is completed at the timing when the enable 207 becomes inactive L level.
[0053]
In the H driver 104 of the present invention, the states of the first selector 302 and the switch 306 are determined by the data held in the mode register 201 and the signal level of the arrangement identification terminal 208. And there are the following four ways of holding the display data 204.
[0054]
First, the first holding method is a case where display data is held in all the display latches 301 of the H driver 104. In this case, the state of the first selector 302 is as follows. First, the second input 402 is selected in the first stage selector 302-1, and the first input 401 is selected in the remaining 302-2 to 302-n. Has been. The switch 405 of the first selector 302-n at the final stage is turned on and connected to the cascade output 305. In this state, the switch 306 is always open.
[0055]
In this operation, first, when a start pulse 205 is input, a signal is transmitted to the first input 501 of the FF 303-1 via the first selector 302-1, and the output of the FF 303-1 is output at the rising timing of the clock 206. 503 changes. The output 503 of the FF 303-1 is a sampling pulse SP 1 of the latch circuit 301-1 of the display register 307 and a signal to the first selector 302-2 of the next stage. The latch circuit 301-1 holds the display data 203 when the sampling pulse SP <b> 1 is input.
[0056]
At the next rising edge of the clock 206, the output 503 of the output 503 of the FF 303-2 changes to generate the sampling pulse SP2, and the latch circuit 301-2 holds the display data. Thereafter, the sampling pulse SP is sequentially generated by the shift register 202, and the display circuit 203 holds the latch circuit 301 corresponding to the sampling pulse SP. In the first selector 302-n in the n-th stage, the switch 405 is turned on, and SP (n−1) of the output 503 of the FF 303- (n−1) in the (n−1) -th stage is Output to the cascade output 305.
[0057]
The first holding method described above is equivalent to the display holding operation of a conventional general H driver.
[0058]
Next, the second holding method will be described. The second holding method is a case where the display data 203 is held from the latch circuit (301-m) at the m (m: 2 to n) stage.
[0059]
As for the state of each first selector 302, GND is selected from the first stage to the (m−1) th stage, and the second input 402 is selected from the mth stage. The first input 401 is selected in the selectors 302 from the (m + 1) th stage to the nth stage. The n-th selector (302-n) has the switch 405 turned on and is connected to the cascade output 305.
[0060]
In this operation, the start pulse 205 changes the output 503 of the m-th stage FF (303-m) via the m-th stage selector (302-m). The output 503 of the FF (303-m) is a signal to the sampling pulse SPm of the latch circuit (301-m) of the display register 307 and the first selector (302- (m + 1)) of the next stage.
[0061]
Since the operation of the latch circuit 301 and the operation of the cascade output are the same as in the first holding method, detailed description thereof is omitted.
[0062]
Next, the third holding method will be described. The third holding method is a method of holding the display data 203 up to the j-th latch circuit (301-j).
[0063]
In the state of each first selector 302, the second input 402 is selected in the first stage (302-1), and the first selector 302 from the second stage to the j-th stage Input 401 is selected. GND is selected for the first selector 302 from the (j + 1) -th stage to the n-th stage. The first selector (302− (j + 1)) at the (j + 1) th stage has the switch 405 turned on and is connected to the cascade output 305.
[0064]
However, since it is not necessary to output a cascade signal to the next stage H driver 104 only in the third holding method, the switch 405 of the first selector 302 in the (j + 1) th stage does not have to be turned on. .
[0065]
In this operation, first, when a start pulse 205 is input, a signal is transmitted to the first input 501 of the FF (303-1) via the first selector (302-1), and the rising edge of the clock 206 is detected. The output 503 of the FF (303-1) changes at the timing. The output 503 of the FF (303-1) becomes a sampling pulse SP1 of the latch circuit (301-1) of the display register 307 and a signal to the first selector (302-2) at the next stage.
[0066]
Since the operation of the latch circuit 301 and the operation of the cascade output are the same as in the first holding method, detailed description thereof is omitted.
[0067]
When the j-th sampling SPj is output and the j-th latch circuit (301-j) finishes holding the display data 204, the FF 303 after the (j + 1) -th stage does not shift the signal, so the sampling pulse SP Is not output, and the display data 203 is held only in the latch circuits 301 up to the j-th stage.
[0068]
Next, a fourth holding method will be described. The fourth holding method is a case where no display data 204 is held.
[0069]
As for the state of each first selector 302, GND is selected. The switch 306 is always on.
[0070]
In this operation, when the start pulse 205 is input, it is output to the cascade output 305 via the switch 306. In operation, since no sampling pulse SP is generated, the display data 203 is not held at all.
[0071]
Next, the holding operation of the display data 203 when performing the display of the present embodiment shown in FIG. 1 will be described with reference to FIG.
[0072]
Referring to FIG. 8, setting is performed from the H driver (104-1) to the H driver (104-8) on the first signal board 103 by the mode data 204 setting method described above.
[0073]
Next, when the start pulse 205 is input from the timing controller 102, the display data 203 of the first stage H driver (104-1) is held in the fourth holding method, so the display data 203 is not held. The start pulse 205 is directly output from the cascade output 305.
[0074]
This signal becomes the start pulse 205 of the second stage H driver (104-2). Since the display data 203 of the second stage H driver (104-2) is held in the second holding method, the latch circuit (301-n) in the nth stage is changed from the latch circuit (301-m) in the m stage. The display data is held and output from the cascade output 305.
[0075]
This signal becomes the start pulse 205 of the third stage H driver (104-3). Holding display data 203 from the third-stage H driver (104-3) to the sixth-stage H driver (104-6) is the first holding method, and all display data 203 is held in the display register 307. The signal output from the cascade output 305 becomes the start pulse 205 of the next stage H driver 104.
[0076]
The seventh-stage H driver (104-7) is the third holding method, and holds the display data 203 up to the j-th latch circuit (301-j). At this time, the cascade output 305 is not output.
[0077]
The eighth stage H driver (104-8) is the first operation and does not hold display data 203 at all.
[0078]
By this series of operations, only the display data 203 in the effective display area can be held, and the same size centering display can be performed.
[0079]
Next, a liquid crystal display device according to a second embodiment of the present invention will be described.
[0080]
In the first embodiment of the present invention, an example has been described in which mode transfer is performed by serial 1 bit. However, when the resolution of the LCD panel becomes higher in the future, the data transfer time may be insufficient even if the first embodiment of the present invention is used. Therefore, the liquid crystal display device according to the second embodiment of the present invention uses nbit (n is an arbitrary integer) for the data wiring (see FIG. 7) that has been transferred serially 1 bit according to the first embodiment of the present invention. ), The data can be transferred at a data amount that is n times that of the first embodiment or at a speed that is n times that of the first embodiment of the present invention.
[0081]
【The invention's effect】
As described above, according to the present invention, the mode setting of the display drive IC can be performed simultaneously from the center of the screen and the image signals with different resolutions can be displayed at the same magnification centering display. In addition, since the same display driving IC is used, there is an effect that versatility is high and productivity can be improved.
[0082]
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a liquid crystal display device according to a first embodiment of the present invention.
FIG. 2 is a connection diagram of an H driver on a first signal substrate of the liquid crystal display device according to the first embodiment of the present invention.
FIG. 3 is a configuration diagram of an H driver of the liquid crystal display device according to the first embodiment of the present invention.
FIG. 4 is a block diagram of a selection switch of the liquid crystal display device according to the first embodiment of the present invention.
FIG. 5 is a block diagram of another selection switch of the liquid crystal display device according to the first embodiment of the present invention.
FIG. 6 is a block diagram of still another selection switch of the liquid crystal display device according to the first embodiment of the present invention.
FIG. 7 is a mode data transfer timing chart of the liquid crystal display device according to the embodiment of the present invention;
FIG. 8 is an operation timing chart of the H driver of the liquid crystal display device according to the embodiment of the present invention.
FIG. 9 is an example in which an image signal having a resolution different from that of a conventional liquid crystal display device is displayed.
[Explanation of symbols]
100 LCD panel
101 Glass substrate with liquid crystal
102 Timing controller
103 first signal board
104 H driver that drives the horizontal direction of the screen
105 Second signal board
106 V driver that drives (scans) the vertical direction of the screen
107 first control signal wiring
108 Second control signal wiring
201 Mode register holding mode data
202 Shift register
203 Display data
204 mode data
208 Location identification terminal
213 Identification wiring
307 Display register for holding display data
900 Display screen of conventional liquid crystal display device

Claims (2)

In a liquid crystal display device in which a plurality of scanning lines and a plurality of data lines are arranged in a matrix, receive image data, and display the image data on a display panel.
A first signal board; a first H driver group including a plurality of H drivers disposed on a left side of the display panel from a central portion of the display panel on the first signal board; and the display panel A second H driver group which is arranged on the right side of the display panel from the center of the H panel and includes a plurality of H drivers,
The H driver includes an arrangement identification terminal for identifying an arrangement position on the first signal board,
The mode data of the image data is input to the first H driver of the first H driver group and the first H driver of the second H driver group, and then the first H driver group The mode data is serially transferred to the H driver, and the second H driver group serially transfers the mode data to the next stage H driver,
At the same magnification centering display, the mode data and the arrangement identification terminal make the same number of pixels to be displayed with respect to the center of the screen of the display panel,
A shift register for generating a sampling pulse for holding the image data, a display register for holding the image data, and a mode register for holding the mode data,
The shift register receives a start pulse at its second input, and a plurality of first selectors each having a cascade output connected to the second output;
A plurality of flip-flops having a first input connected to a first output of the first selector and receiving a clock at the second input;
A liquid crystal display device comprising the start pulse and a switch disposed between the cascade outputs. The liquid crystal display device according to claim 1 , wherein the display register includes a plurality of latch circuits that receive outputs of the plurality of flip-flops.

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