JP3865921B2

JP3865921B2 - Apparatus and method for suppressing harmonic current

Info

Publication number: JP3865921B2
Application number: JP06307398A
Authority: JP
Inventors: 正人池田; 貢饗庭
Original assignee: Nippon Soda Co Ltd
Current assignee: Nippon Soda Co Ltd
Priority date: 1998-03-13
Filing date: 1998-03-13
Publication date: 2007-01-10
Anticipated expiration: 2018-03-13
Also published as: JPH11262178A

Description

【０００１】
【発明の属する技術分野】
この発明は、交流電源へと結合されたひとつの母線に接続された複数の給電線を通り該母線に流れる総合高調波電流を抑制する装置および方法に関する。
【０００２】
【従来の技術】
近年、例えば工場において同一の三相交流電源系統の受電側に単機大容量のサイリスタ変換装置を複数接続し、負荷に整流された直流電流を供給するシステムが構築されている。図６は工場の電力供給システムの一例を示し、電力は三相交流電源１から給電線２₁、２₂、…、２_kを介して工場３内の需要設備４₁、４₂、…、４_kにそれぞれ供給される。各需要設備には、変圧器５、サイリス夕整流器６、定電流制御装置７および負荷８がそれぞれ設けられ、変圧器５により低減された電圧がサイリスタ整流器６により直流に変換され、負荷８に供給される。定電流制御装置７は負荷８に供給される電流が一定になるようにサイリスタ整流器６の制御角αを日勤的に制御している。サイリスク整流器６はその電力変換動作において高調波を発生し、このため給電線２₁、２₂、…、２_kに流れる交流電流には高調波電流を含むことになる。また、需要設備が複数個（この例ではｋ個）、同一の三相交流電源系統に接続されている場合は、各需要設備４₁、４₂、…、４_kでは独立した別個のサイリスタ制御が行われるため、各給電線２₁、２₂、…、２_kに流れる交流電流はそれぞれ異なる大きさ、位相角の高調波電流を含むことになる。そして、給電線２₁、２₂、…、２_kを接続する母線２に流れる総合電流は、各需要設備４₁、４₂、…、４_kで発生する各高調波電流のベクトル和を含むことになる。即ち、同一次数の各高調波電流の太きさは、その位相が同相に近ければスカラ和に、逆位相に近付くとスカラ差に近くなる。
【０００３】
母線２に流れる総合電流に含まれる高調波電流のベクトル和は各サイリスタ整流器６の運転状況により異なるからその予測は困難である。そこで、総合高調波電流の低減として、サイリスタ整流器の整流相数を増すこと、最も高調波電流が太きくなる運転状態を想定して高調波電流を吸収する高調波フィルタを設置することが一般に行われている。
【０００４】
【発明が解決しょうとする課題】
母線に流れる総合高調波電流の低減としてサイリスタ整流器の整流相数を増すことは、既存の設備を置き換えることになり経済的負担が大きい。また、高調波フィルタを設置することも常に過剰の高調波吸収設備を設けることになり経済的ではないうえに、基本波に対する進相容量を絶えず供給することになるから、場合によっては需要設備全体としては過剰の進み容量になる問題もある。
本発明は、受電側の状態とは無関係に、母線に流れる総合高調波電流を抑制できる高調波電流抑制装置および方法を提供することである。
また本発明は、母線に流れる総合高調波電流を抑制するための制御プログラムを記録した記録媒体を提供することである。
【０００５】
【課題を解決するための手段】
本発明の高調波電流抑制装置は、交流電源に接続されたひとつの母線と、母線に接続され、それぞれ高調波電流を含む交流電流を受電側へ供給する複数の給電線と、複数の給電線のうちの特定のひとつの基準給電線を除いた各給電線に接続され、該各給電線に流れる高調波電流の前記交流電源側と受電側との間の位相を位相指示信号に従って変動する位相調整器と、各給電線に流れる前記各交流電流から各基本波電流を除いた各高調波電流を高調波電流の次数ごとに分離して検出する高調波電流検出手段と、母線の電圧と、前記各高調波電流の各次数の高調波電流との間の位相差を初期位相角として各次数の高調波電流ごとに検出する初期位相角検出手段と、高調波電流検出手段により検出された次数ごとの各高調波電流と、前記初期位相角検出手段により検出された各次数の高調波電流の初期位相角を受信し、前記次数ごとの各高調波電流の初期位相角に加算される位相パラメータの値を各給電線に流れる高調波電流ごとに変えることにより各給電線に流れる高調波電流を演算し、さらに各給電線から前記母線に流れ込む総合高調波電流を前記各給電線ごとに位相パラメータの関数として求めて該総合高調波電流が最小となる最小位相パラメータを各給電線ごとに求め、該各最小位相パラメータの値に対応する位相指示信号を位相調整器に出力する制御手段と、を含む。
【０００６】
また、本発明の高調波電流抑制方法は、各給電線に流れる各交流電流から各基本波電流を除いた各高調波電流を高調波電流の次数ごとに分離して検出する段階と、母線の電圧と、前記各高調波電流の各次数の高調波電流との間の位相差を初期位相角として各次数の高調波電流ごとに検出する段階と、給電線に流れる各高調波電流の次数ごとに分離された各次数の高調波電流と、該次数の高調波電流の初期位相角を受信する段階と、次数ごとの各高調波電流の初期位相角に加算される位相パラメータ値を各給電線に流れる高調波電流ごとに変えることにより各給電線に流れる高調波電流を演算する段階と、各給電線から前記母線に流れ込む総合高調波電流が最小となる前記各給電線ごとの最小位相パラメータ値を求める段階と、各最小位相パラメータ値に対応する位相指示信号を前記位相調整器に出力する段階と、を含む。
【０００７】
また、本発明の総合高調波電流を抑制するための制御プログラムを記録した記録媒体は、給電線に流れる各高調波電流の次数ごとに分離された各次数の高調波電流と、該次数の高調波電流の初期位相角を受信し、次数ごとの各高調波電流の初期位相角に加算される位相パラメータ値を各給電線に流れる高調波電流ごとに変えることにより各給電線に流れる高調波電流を演算し、各給電線から前記母線に流れ込む総合高調波電流が最小となる前記各給電線ごとの最小位相パラメータ値を決定し、記各最小位相パラメータ値に対応する位相指示信号を前記位相調整器に出力し、所定時間後に前記の受信、演算、決定及び出力の各段階を繰り返すことを特徴とする。
【０００８】
【発明の実施の形態】
以下に本発明の好適な一実施形態について説明する。図１は、工場の電力供給システムの慨略図を示し、図６と同一部分は同一符号を付しその説明を省略し、また説明を簡単にするために二相の電力供給システムうち一相分のみを例示している。図１において、新たに高調波電流抑制装置１１が三相交流電源１と需要設備４₁、４₂、…、４_kとの間に設けられている。高調波電流抑制装置１１は、需要設備４₁、４₂、…、４_kの動作において発生した給電線２₁、２₂、…、２_kに流れる各高調波電流が合流する母線２に流れる総合高調波電流の実効値が最小になるように動作する。
【０００９】
次に、図１に基づいて高調波電流抑制装置１１の構成についてその概略を説明する。給電線２₁、２₂、…、２_i、…、２_kにはそれぞれ対応して変流器ＣＴ₁、ＣＴ₂、…、ＣＴ_i、…、ＣＴ_kが、母線２には計器用変圧器ＰＴがそれぞれ設けられている。また、給電線２₁を除く給電線２₁、２₂、…、２₁、…、２_kには移相器１２₂、…、１２_i、…、１２_kがそれぞれ設けられている。変流器ＣＴ₁、…、ＣＴ_kから取込まれた給電線２₁、…、２_kの交流電流と、計器用変圧器ＰＴから取り込まれた母線２の交流電圧はそれぞれ制御装置１３に送られる。また、制御装置１３は、移相器１２₂、…、１２_i、…、１２_kに対して総合高調波電流の実効値を最小にする最適制御位相角θ_2min、…、θ_kmin、を出力する。各移相器１２₂、…、１２_kは最適制御位相角の指示に従って、各給電線２₁、…２_kに流れる高調波電流の各位相角を高調波電流発生源である受電側と電源側の間においてそれぞれ対応して位相角θ₂、…、θ_kだけ変位する。
【００１０】
次に、図１に示す高調波電流抑制装置１１の抑制原理について説明する。ここで、前記サイリスタ整流器６を６相整流装置とし、直流、偶数調波およびＡ巻線を整流する３の倍数調波は発生していないとすると、理論高調波の発生次数ｎはｎ＝６ｍ±１（ｍは正の整数）となる。なお、サイリスタ整流器６を１２相整流装置とした場合には、理論高調波の発生次数ｎはｎ＝１２ｍ±１（ｍは正の整数）となる。説明を簡略化するためにある給電線および該給電線に接続された移相器、かつ三相交流の一相分（ｒ相〉について着目し、サイリスタ整流器６を６相整流装置とすると、給電線に流れるｎ次の高調波電流の初期位相角（Φ_n＋６ｍθ）は移相器の位相角θにより６ｍθだけ移相させることができる。Φ_nはθが零の場合のｎ次の高調波電流の初期位相角である。該給電線に流れる交流電流ｉ_rは、
【数１】

により表される。ここで、給電線に流れる高調波電流ｉ_rhは交流電流ｉ_rから基本波電流を除いた電流であるから、
【数２】

により表される。そして、各給電線２₁、…、２_kに流れる高調波電流の合計である総合高調波電流（母線２に流れる高調波電流）ｉ_rhtは、
【数３】

により表される。さらに、θ₁＝０として各時刻における総合高調波電流ｉ_rhtの実効値Ｉ_rhtは、
【数４】

により表される。総合高調波電流ｉ_rhtは、各給電線２₂、…、２_kに設置してある移相器１２₂、…、１２_kの位相角θ₂、…、θ_kの関数として、
【数５】
ｉ_rht＝ｆ（θ₂、…、θ_k）
として表される。従って、各時刻における総合高調波電流の実効値Ｉ_rht、が最小になる各位相角θ₂、…、θ_kを求めれば良い。
【００１１】
使用される前記移相器１２₂、…、１２_kの種類は、各給電線に存在する高調波電流の初期位相角が時間の変化に対してどの程度安定しているかに依存する。時間変化に対して高調波電流の初期位相角がほとんど変化しない場合は機械式タップ移相器を使用できる。高調波電流の初期位相角が１秒以下の速い変化の場合は静止形高速移相器を使用する。秒単位の変化の場合は静止形切替移相器が適切である。
前記移柑器の位相調整範囲は、６０度を必要とする。この理由は、サイリスタ整流器６を６相整流装置とすると、理論高調波の発生次数ｎはｎ＝６ｍ±１であり、ｍ＝１のときの高調波電流の初期位相角を３６０度制御するために必要な最大位相角は３６０／６ｍ＝６０となるからである。
【００１２】
図２は、図１の制御装置１３をさらに詳細に説明するブロック図である。前記変流器ＣＴ₁、ＣＴ₂、…、ＣＴ_i、…、ＣＴ_kにより検出された各給電線２₁、２₂、…、２_i、…、２_kに流れる交流電流ｉ₁、１₂、…、ｌ_i、…、ｉ_kはそれぞれ対応した信号変換器２１₁、２１₂、…、２１_i、…、２１_kに送られ、ここで各電流信号に変化されてそれぞれ対応して電流値・位相検出回路２２₁、２２₂、…、２２_i、…、２２_kに出力される。一方、前記計器用変圧器ＰＴにより検出された母線２の交流電圧は信号変換器２３に送られ、ここで電圧信号に変換されて各電流値・位相検出回路２２₁、２２₂、…、２２₁、…、２２_kに出力される。各電流値・位相検出回路２２₁、２２₂、…、２２_i、…、２２_kはそれぞれ受信された電流信号と電圧信号から５、７、…、２５次の各高調波電流に分離するとともに各次数ごとの高調波電流の電流値Ｉと初期位相角Φを求め、それぞれ電気信号（光信号として送信するように構成しても良い）としてインターフェース２４へ送る。例えば、電流値・位相検出回路２２_iは、５、７、…、２５次の各高調波電流値Ｉ_i（５）、Ｉ_i（７）、…、Ｉ_i（２５）および５、７、…、２５次の各初期位相角Φ_i（５）、Φ_i（７）、…、Φ_i（２５）を求める。なお、各電流値・位相検出回路は、理論的には無限の各高調波電流に分離するとともに各次数ごとの高調波電流の電流値Ｉと初期位相角Φを求めるように周知の技術により構成することが可能である。インターフェース２４は、受信された各高調波電流値Ｉと初期位相角Φの電気信号をそれぞれディジタル信号に変換し、ＣＰＵ２５に送る。
【００１３】
ＣＰＵ２５は、ディジタル化された各給電線２₁、…、２_kに対応する各高調波電流値Ｉ_i、…、Ｉ_kの各次数ごとの電流値と、各給電線２₁、…、２_kに対応する初期位相角Φ₁、…、Φ_kの各次数ごとの初期位相角を各給電線２₁、…、２_kごとにＲＡＭに記憶し、そして一定の時間△ｔ（この例では１秒）ごとにその内容を更新する。時間△ｔは、本高調波電流抑制装置の使用環境に応じた値に変更可能である。さらに、ＣＰＵ２５のＲＯＭには、総合高調波電流を最小にするために移相器１２₂、…、１２_kの位相角θ₂、…、θ_kの最適制御位相角θ_2min、…、θ_kminを求めるプログラムを記憶しており、前記時間△ｔごとに各最適制御位相角を求め、それをインターフェース２６に出力する、高調波抑制制御動作を実行する。インターフェース２６は、各最適制御位相角θ_2min、…、θ_imin、…、θ_kminのディジタル信号をアナログの電気信号（光信号として送信するように構成しても良い）に変換し、それぞれ対応した信号変換器２７₂、…、２７_i、…、２７_kへ送信する。各信号変換器は受信した電気信号に対応し、移相器１２₂、…、１２_kの位相角の設定が可能な電圧信号にそれぞれ変換し、変換された各電圧信号をそれぞれ対応した位相角設定装置２８₂、…、２８₁、…、２８_kへ出力する。各位相角設定装置は人力した電圧信号の値に従って対応する移相器１２₂、…１２_kの位相角θ₂、…、θ_kを最適制御位相角θ_2min、…、θ_kminへ設定する。
【００１４】
次に、ＣＰＵ２５において実行される高調波抑制制御動作について図３のフローチャートに従って説明する。図３のステップＳ１において、各給電線２₁、…２_kに対応する各高調波電流値Ｉ₁、…、Ｉ_kの各次数ごとの電流値（図３ではＩ_i（ｎ）として代表している；ｎは次数を表す〉と、各給電線２₁、…、２_kに対応する初期位相角Φ₁、…、Φ_kの各次数ごとの初期位相角（図３ではΦ_i（ｎ）として代表している；ｎは次数を表す）が読み込まれてＲＡＭに記憶される。次にステップＳ２に移り、初期設定が行われる。即ち、移相器１２₂、…、１２_i、１２_kの各位相角θ₂、…、θ_i、…、θ_kの値を指示する位相パラメータ（各位相角と対応するため同じ記号を用いている）が全てゼロに、総合高調波電流ｉ_rhtの実効値Ｉ_rhtが最小値であることを示す総合高調波最小電流パラメータＩ_rhtminを無限大（該当する記憶領域を最大値にする）に、最適制御位相角θ_2min、…、θ_kminを指示する最小位相パラメータ（各最適制御位相角と対応するため同じ記号を用いている）が全てゼロにそれぞれ設定される。次にステップＳ３に移り、各位相パラメータθ₂、…、θ_i、…、θ_kをそれぞれ０から１（１度を示す〉ずつ６０まで変化させた場合の全ての組み合わせの位相パラメータθ₂、…、θ_i、…、θ_kを順次に作成する。ステップＳ４においてステップ３の実行により指定された位相パラメータにおいて総合高調波電流ｉ_rhtの実効値Ｉ_rhtが演算される。次にステップＳ５に移り、総合高調波電流パラメータＩ_rhtminと演算された実効値Ｉ_rhtとが比較され、Ｉ_rhtmin＞Ｉ_rhtの場合は演算された総合高調波電流ｉ_rhtの実効値Ｉ_rhtが新たに総合高調波最小電流パラメータＩ_rhtminとして更新され、このときの位相パラメータθ₂、…、θ_i、…、θ_kの各値が最小位相パラメータθ_2min、…、θ_imin、…、θ_kminにそれぞれ対応して記憶される。Ｉ_rhtmin＞Ｉ_rhtでない場合は前回までの最小位相パラメータが維持される。次にステップＳ６に移り、位相パラメータθ₂、…、θ_i、…、θ_kの全ての組み合わせにつきステップＳ４とＳ５の実行が行われたか杏か判断される。
【００１５】
即ち、ステップＳ３−ｋ、Ｓ４、Ｓ５、Ｓ６‐ｋのループが位相パラメータθ_kを０から６０まで１ずつ変え、他の位相パラメータを変えずに６１回繰り返された後、位相パラメータθ_kを０から６０まで１ずつ変えるごとに前記ステップＳ３−ｋ、Ｓ４、Ｓ５、Ｓ６‐ｋのループが位相パラメータθ_kを０から６０まで１ずつ変えて６１回繰り返され、同様な動作が位相パラメータθ₂に至るまで繰り返されてステップＳ６−２において終了するまで、合計６１^k-1回の演算、比較が繰り返される。この動作の結果、総合高調波最小電流パラメータＩ_rhtminを生じる最小位相パラメータθ_2min、…、θ_imin、…、θ_kminが求められ、ステップＳ７において移相器１２₂、…、１２_kを最適制御位相角θ_2min、…、θ_kminに設定するため該最小パラメータが前記インターフェース２６に出力される。次にステップＳ８に移り、ステップＳ１のデータの読み込みから△ｔ（１）秒経過した後ステップＳ１に戻り、そして新たに各給電線の電流値と初期位相角が読込まれてステップＳ２〜ステップＳ８が実行される。
【００１６】
図４は給電線が３本、基本波電流が２０％の太ささの差を有しかつ初期位相角が無作為（３０事例）である場合に発生する総合高調波電流の非制御時と制御時をシミュレートして比較した結果を示す。図５は給電線が４本、基本波電流が２０％の大きさの差を有しかつ初期位相角が無作為（５事例）である場合に発生する総合高調波電流の非制御時と制御時をシミュレートして比較した結果を示す。なお、各次の高調波電流値は基本波電流を高調波の次数で際した値を使用している。図４および図５に示すように、給電線が３本の場合は非制御時２０．７９〜８７．１１Ａ（変化幅６６．８２Ａ）が制御時には３４．７４Ａ以下に（変化幅１７．３９Ａ）に、給電線が４本の場合は非制御時３７．２４〜１０４．５３Ａ（変化幅６７．２９Ａ）が制御時には２７．９０Ａ以下に（変化幅１４．０５Ａ）に制御される。各給電線に流れる高調波電流値と初期位相角はさまざまな値をとり、非制御時には総合高調波電流も大きな幅の間を変化する。しかし、位相制御することにより総合高調波電流の値を抑制でき、その効果は給電線数が多いほど顕著である。
【００１７】
前記移相器１２₂、…、１２_kへの位相制御の時間的変化は緩やかな方が電力系統には優しいが、移相器の位相制御時間が遅すぎるとＣＰＵ２５からの最適制御位相角の出力と移相器の実際の位相角の間の偏差が大きくなり高調波の抑制効果を低下させる。このため、ステップＳ８における△ｔの時間を適切に調整し、この結果、最適制御位相角θ_iminの出力間隔が調整されることにより位相制御の時間的変化を制御できる。
【００１８】
なお、上述の実施形態では、複数の給電線に６相のサイリスタ整流器が接続されて直流、偶数調波およびＡ巻線を還流する３の倍数調波は発生していない場合について説明したが、本発明はこの実施形態に限定されるものではなく、複数の給電線にそれぞれ別個に異なる高調波電流を含む交流電流が流れている場合に普遍的に適用できる。従って、検出、演算される各高調波電流の次数は６ｍ±１または１２ｍ±１の式により求められる次数に限定されるものでなく、基本波電流を除く２次以降の偶数、奇数の高調波に適用可能である。どの次数の高調波電流を検出、演算するかは適用される工場の負荷の状況、各給電線に流れる高調波の状態に応じて適宜定めることができ、また制御位相角の制御範囲も０〜６０度に限定されず状況に応じて制御角範囲の増減が可能である。この場合、ＣＰＵ２５を含む制御装置１８の構成は上述した実施形態に倣って容易に設計変更できる。また上記実施形態においては各給電線の高調波電流値および総合高調波電流値を実効値として求めたが、振幅値として計算しても同じ結果を得ることができる。
【００１９】
【発明の効果】
本発明の高調波電流抑制装置によれば、受電側の負荷に流れる高調波電流の状態とは無関係に、複数の給電線から母線に流入する総合高調波電流を確実にかつ顕著に抑制することができる。従って、複数の給電線から母線に流入する総合高調波電流の抑制を必要とする、工場等のあらゆる状況に適用することができる。しかも、複数の給電線に生じる高調波電流の次数、電流値とは無関係に対処することができるので、汎用性に優れている。また、位相制御時間の間隔を調整することにより電力系統の時間的変動の安定性にも対処できる。
【００２０】
また本発明の位相制御オペレーションは、母線に流れる総合高調波電流を抑制するための制御プログラムを記録した記録媒体として提供することができるので必要なデータを提供することにより移相器の最適制御位相値を得ることができる。
【図面の簡単な説明】
【図１】本発明の高調波電流抑制装置の概略構成図ある。
【図２】図１の制御装置の一実施形態を説明するブロック図である。
【図３】本発明の高調波電流抑制動作を説明するフローチャートである。
【図４】３給電線の場合における総合高調波電流の非制御時と制御時のシミュレーション結果を示す図である。
【図５】４給電線の場合における総合高調波電流の非制御時と制御時のシミュレーション結果を示す図である。
【図６】従来の工場の電力供給システムの概略構成図ある。
【符号の説明】
１三相交流電源
２母線
２₁、２₂、…、２_i、…、２_k 給電線
１１高調波電流抑制装置
１２₂、…、１２_i、…、１２_k 移相器
１３制御装置
２１₁、２１₂、…、２１_i、…、２１_k 信号変換器
２２₁、２２₂、…、２２_i、…、２２_k 電流値・位相検出回路
２３信号変換器
２５ＣＰＵ
２７₂、…、２７_i、…、２７_k 信号変換器
２８₂、…、２８_i、…、２８_k 位相角設定回路
ＣＴ₁、ＣＴ₂、…、ＣＴ_i、…、ＣＴ_k 変流器
ＰＴ計器用変圧器
θ₂、…、θ_i、…、θ_k 位相角
θ_2min、…、θ_imin、…、θ_kmin 最適制御位相角[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an apparatus and a method for suppressing a total harmonic current flowing through a plurality of feeders connected to a single bus connected to an AC power source.
[0002]
[Prior art]
In recent years, for example, a system has been constructed in which a plurality of single-unit large-capacity thyristor converters are connected to the power receiving side of the same three-phase AC power supply system to supply a rectified DC current to a load. Figure 6 shows an example of a power supply system of the plant, the power feed line 2 ₁ from the three-phase

AC power source

1, 2 _2, ..., demand equipment 4 ₁ in the plant 3 through 2 _k, 4 _2, ..., 4 _k respectively. Each demand facility is provided with a transformer 5, a thyristor rectifier 6, a constant current control device 7, and a load 8, and the voltage reduced by the transformer 5 is converted into a direct current by the thyristor rectifier 6 and supplied to the load 8. Is done. The constant current control device 7 controls the control angle α of the thyristor rectifier 6 on a daily basis so that the current supplied to the load 8 is constant. Sairisuku rectifier 6 generates harmonics in its power conversion operation, and thus power supply lines 2 _1, 2 _2, ..., the alternating current flowing through the 2 _k will contain harmonic current. Further, (k pieces in this example) a plurality demand equipment, if it is connected to the same three-phase AC power system, each customer equipment _{_{4 1, 4 2, ...,}} 4 k in independent separate thyristor control Therefore, the alternating currents flowing through the

feeders

2 ₁ , 2 ₂ ,..., 2 _k include harmonic currents having different magnitudes and phase angles. The feed line 2 _1, 2 _2, ..., the total current flowing through the bus 2 to connect the 2 _k, each demand facility 4 _1, 4 _2, ..., includes a vector sum of the harmonic currents generated in the 4 _k It will be. That is, the thickness of each harmonic current of the same order is close to a scalar sum if the phase is close to the same phase, and close to a scalar difference if the phase is close to the opposite phase.
[0003]
Since the vector sum of the harmonic currents included in the total current flowing through the bus 2 varies depending on the operating conditions of each thyristor rectifier 6, it is difficult to predict the vector sum. Therefore, in order to reduce the total harmonic current, it is common practice to increase the number of rectifier phases of the thyristor rectifier and to install a harmonic filter that absorbs the harmonic current assuming the operating state where the harmonic current is the thickest. It has been broken.
[0004]
[Problems to be solved by the invention]
Increasing the number of rectifying phases of the thyristor rectifier as a reduction of the total harmonic current flowing in the busbar replaces existing facilities and has a large economic burden. In addition, installing a harmonic filter is not economical because it always installs excessive harmonic absorption equipment, and also provides a constant phase advance capacity for the fundamental wave. As a result, there is a problem of excessive capacity.
An object of the present invention is to provide a harmonic current suppressing device and method capable of suppressing the total harmonic current flowing in the bus bar regardless of the state on the power receiving side.
Moreover, this invention is providing the recording medium which recorded the control program for suppressing the total harmonic current which flows into a bus-line.
[0005]
[Means for Solving the Problems]
The harmonic current suppression device of the present invention includes a single bus connected to an AC power source, a plurality of feed lines connected to the bus, each supplying an AC current including a harmonic current to the power receiving side, and a plurality of feed lines A phase that is connected to each of the power supply lines excluding a specific one of the reference power supply lines, and that changes the phase of the harmonic current flowing in each of the power supply lines between the AC power supply side and the power reception side according to the phase indication signal A harmonic current detection means for separating and detecting each harmonic current obtained by removing each fundamental current from each AC current flowing through each feeder line for each order of the harmonic current, and a voltage of the bus; An initial phase angle detecting means for detecting each harmonic current of each order as an initial phase angle with a phase difference between each harmonic current and each order of harmonic current, and the order detected by the harmonic current detecting means Each harmonic current for each and the initial phase angle The initial phase angle of each order harmonic current detected by the output means is received, and the value of the phase parameter added to the initial phase angle of each harmonic current for each order is added to each harmonic current flowing through each feeder line. To calculate the harmonic current flowing in each feeder line and calculating the total harmonic current flowing from each feeder line to the bus as a function of the phase parameter for each feeder line. Control means for obtaining a minimum phase parameter for each feeder line and outputting a phase indication signal corresponding to the value of each minimum phase parameter to the phase adjuster.
[0006]
Further, the harmonic current suppression method of the present invention includes a step of separately detecting each harmonic current obtained by removing each fundamental wave current from each AC current flowing through each feeder line for each order of the harmonic current, Detecting the phase difference between the voltage and each harmonic current of each harmonic current as an initial phase angle for each harmonic current of each order, and for each harmonic current flowing through the feeder line Each of the harmonic currents of the respective orders separated in the order, the initial phase angle of the harmonic current of the order, and the phase parameter value added to the initial phase angle of each harmonic current for each order for each feeder line The step of calculating the harmonic current flowing through each feeder line by changing the harmonic current flowing through each of the feeder lines, and the minimum phase parameter value for each feeder line that minimizes the total harmonic current flowing from each feeder line into the bus And the minimum phase parameter Comprising the steps of outputting a phase instruction signal corresponding to the over data value to the phase adjuster, a.
[0007]
Further, the recording medium on which the control program for suppressing the total harmonic current of the present invention is recorded, the harmonic current of each order separated for each order of each harmonic current flowing through the feeder line, and the harmonics of the order. Harmonic current flowing in each feed line by receiving the initial phase angle of wave current and changing the phase parameter value added to the initial phase angle of each harmonic current for each order for each harmonic current flowing in each feed line To determine a minimum phase parameter value for each feed line that minimizes the total harmonic current flowing from each feed line to the bus, and to adjust the phase indication signal corresponding to each minimum phase parameter value And receiving, calculating, determining, and outputting each step after a predetermined time.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
A preferred embodiment of the present invention will be described below. FIG. 1 is a schematic diagram of a power supply system in a factory. The same parts as those in FIG. 6 are denoted by the same reference numerals and the description thereof is omitted. In order to simplify the description, one phase of a two-phase power supply system is shown. Only an example. In FIG. 1, a harmonic current suppression device 11 is newly provided between the three-phase AC power source 1 and the

demand facilities

4 ₁ , 4 ₂ _,. Harmonic current suppression apparatus 11, demand equipment 4 _1, 4 _2, ..., 4 feed line 2 ₁ generated in the operation of _k, 2 _2, ..., flows through the bus 2 to the harmonic current flowing to the 2 _k merge It operates so that the effective value of the total harmonic current is minimized.
[0009]
Next, the outline of the configuration of the harmonic current suppressing device 11 will be described with reference to FIG. Power supply lines 2 _1, ₂ 2, ..., 2 _i, ..., current transformer in the 2 _k respectively corresponding _{_{CT 1, CT 2, ...,}} CT i, ..., CT k is potential transformers in bus 2 Each device PT is provided. Furthermore, power supply lines 2 _1, ₂ 2, except the feed line 2 _1, ..., 2 _1, ..., the 2 _k phase shifter 12 _2, ..., 12 _i, ..., 12 _k, respectively. The AC currents of the feeders 2 ₁ ,..., 2 _k taken from the current transformers CT ₁ ,..., CT _k and the AC voltage of the bus bar 2 taken from the instrument transformer PT are respectively sent to the control device 13. It is done. Further, the control unit 13, the phase shifter _{_{12 2, ..., 12 i,}} ..., 12 optimal control phase angle theta _2min to minimize the rms value of the total harmonic current to _k, ..., theta _kmin, the output To do. Each phase shifter 12 _2, ..., 12 _k is optimally controlled in accordance with the instructions of the phase angle, the power supply lines 2 _1, ... the power receiving side and power of each phase angle is harmonic current source of harmonic current flowing to the 2 _k Correspondingly, the phase angles θ ₂ ,..., Θ _k are displaced between the sides.
[0010]
Next, the suppression principle of the harmonic current suppression device 11 shown in FIG. 1 will be described. Here, assuming that the thyristor rectifier 6 is a six-phase rectifier and no DC, even harmonics and multiple harmonics of 3 that rectify the A winding are generated, the generation order n of theoretical harmonics is n = 6 m. ± 1 (m is a positive integer). When the thyristor rectifier 6 is a 12-phase rectifier, the theoretical harmonic generation order n is n = 12 m ± 1 (m is a positive integer). For simplification of description, paying attention to a certain power supply line, a phase shifter connected to the power supply line, and one phase (r phase) of a three-phase alternating current, if the thyristor rectifier 6 is a six-phase rectifier, the initial phase angle of the n order harmonic current flowing through the electric wire (Φ _n + 6mθ) is n-order harmonic when .Fai _n is θ is zero, which may be phase shifted by 6Emushita by the phase angle θ of the phase shifter is the initial phase angle of the current. AC current i _r flowing in the fed-wire,
[Expression 1]

It is represented by Here, because the harmonic current i _rh flowing through the feed line a current excluding the fundamental wave current from the alternating current i _r,
[Expression 2]

It is represented by Then, the feeding line 2 _1, ..., is the sum of the harmonic currents flowing to the 2 _k total harmonic current (harmonic current flowing through the bus 2) i _rht is
[Equation 3]

It is represented by Further, assuming that θ ₁ = 0, the effective value I _rht of the total harmonic current i _rht at each time is
[Expression 4]

It is represented by Total harmonic current i _rht, each feed line 2 _2, ..., 2 phase shifter 12 ₂ that is installed in _k, ..., the phase angle theta ₂ of 12 _k, ..., as a function of theta _k,
[Equation 5]
i _rht = f (θ ₂ ,..., θ _k )
Represented as: Therefore, each phase angle θ ₂ ,..., Θ _k that minimizes the effective value I _rht of the total harmonic current at each time may be obtained.
[0011]
The type of the phase shifters 12 ₂ ,..., 12 _{k used} depends on how stable the initial phase angle of the harmonic current present in each feeder line is with respect to time changes. If the initial phase angle of the harmonic current hardly changes with time, a mechanical tap phase shifter can be used. If the initial phase angle of the harmonic current is a fast change of 1 second or less, use a static high-speed phase shifter. A static switching phase shifter is appropriate for changes in seconds.
The phase adjustment range of the citrus device requires 60 degrees. This is because when the thyristor rectifier 6 is a six-phase rectifier, the generation order n of theoretical harmonics is n = 6 m ± 1, and the initial phase angle of the harmonic current when m = 1 is controlled by 360 degrees. This is because the maximum phase angle necessary for this is 360 / 6m = 60.
[0012]
FIG. 2 is a block diagram for explaining the control device 13 of FIG. 1 in more detail. The current transformer _{_{CT 1, CT 2, ...,}} CT i, ..., the feeding line 2 ₁ detected by _{_{CT k, 2 2, ...,}} 2 i, ..., the alternating current flowing through the 2 _k

i

_1, 1 ₂ _{, ..., l i, ...,} i k signal converter 21 ₁ corresponding _{_{respectively, 21 2, ..., 21 i}} , ..., sent to 21 _k, where in correspondence is changed to the current signal current The value /

phase detection circuits

22 ₁ , 22 ₂ ,..., 22 _i _,. On the other hand, the AC voltage of the bus 2 detected by the instrument transformer PT is sent to the signal converter 23, where it is converted into a voltage signal and each current value /

phase detection circuit

22 ₁ , 22 ₂ ,. _1, ..., it is output to the 22 _k. Each of the current value /

phase detection circuits

22 ₁ , 22 ₂ ,..., 22 _i ,..., 22 _k is separated from the received current signal and voltage signal into respective harmonic currents of the fifth, seventh,. The current value I and the initial phase angle Φ of the harmonic current for each order are obtained and sent to the interface 24 as an electrical signal (which may be configured to be transmitted as an optical signal). For example, the current value / phase detection circuit 22 _i includes the fifth, fifth, 25th harmonic current values I _i (5), I _i (7),..., I _i (25) and 5, 7, ..., 25th initial phase angles Φ _i (5), Φ _i (7), ..., Φ _i (25) are obtained. Each current value / phase detection circuit is theoretically divided into infinite harmonic currents and is constructed by a known technique so as to obtain the current value I and the initial phase angle Φ of the harmonic current for each order. Is possible. The interface 24 converts each received electrical signal of the harmonic current value I and the initial phase angle Φ into a digital signal and sends it to the CPU 25.
[0013]
CPU25, each feed line 2 ₁ is digitized, ..., each harmonic current value I _i which corresponds to 2 _k, ..., a current value for each order of I _k, the power supply lines 2 _1, ..., 2 _The initial phase angle for each order of φ ₁ ,..., Φ _k corresponding to _k is stored in RAM for each feed line 2 ₁ ,..., 2 _k , and for a certain time Δt (in this example The content is updated every 1 second). The time Δt can be changed to a value according to the usage environment of the harmonic current suppressing device. Further, the ROM of the CPU 25, the phase shifter 12 ₂ to the total harmonic current to a minimum, ..., the phase angle theta ₂ of 12 _k, ..., theta _k optimal control phase angle theta _2min, ..., theta _kmin Is stored, and each harmonic control phase angle is obtained for each time Δt and output to the interface 26 to execute a harmonic suppression control operation. Interface 26, the optimal control phase angle _{_{θ 2min, ..., θ imin,}} ..., converts the digital signal of theta _kmin into an analog electrical signal (may be configured to transmit an optical signal), respectively corresponding Transmit to signal converters 27 ₂ ,..., 27 _i _,. Each signal converter converts the voltage signal corresponding to the received electrical signal into a voltage signal capable of setting the phase angle of the phase shifters 12 ₂ ,..., 12 _k , and each converted voltage signal has a corresponding phase angle. Output to setting devices 28 ₂ ,..., 28 ₁ _,. Phase shifter 12 _2, ... 12 the phase angle of the _k theta ₂ Each phase angle setting device corresponding according to the value of the voltage signal manpower, ..., optimal control phase angle theta _2min the theta _k, ..., set the theta _kmin.
[0014]
Next, the harmonic suppression control operation executed in the CPU 25 will be described with reference to the flowchart of FIG. In step S1 of FIG. 3, the current values of the respective harmonic current values I ₁ ,..., I _k corresponding to the respective feeders 2 ₁ ,... 2 _k (represented as I _i (n) in FIG. 3). and it has; n and represents the order>, the feeding line 2 _1, ..., the initial phase angle [Phi ₁ corresponding to 2 _k, ..., initial phase angles for each order of [Phi _k (in FIG. 3 Φ _i (n ) is representative as;.. n represents a degree) is stored in the read and RAM then proceeds to step S2, initialization is performed that is, the phase shifter _{_{12 2, ..., 12 i,}} 12 _The phase parameters indicating the values of the phase angles θ ₂ ,..., θ _i ,..., θ _k of _k are all zero, and the total harmonic current i _rht is set to zero. of the effective value I _rht is infinite total harmonic minimum current parameter I _Rhtmin indicating the minimum value (the corresponding storage area to the maximum value) Optimal control phase angle θ _2min, ..., minimum phase parameter indicating theta _kmin (uses the same symbols for corresponding to each optimal control phase angle) are respectively set all to zero. Next, the processing proceeds to step S3, each phase parameter _{_{θ 2, ..., θ i,}} ..., θ phase parameter theta ₂ of all combinations in the case _k a was changed to 60 by> represents 0 to 1 (one degree, respectively, ..., θ _i, ..., to create a theta _k sequentially. effective value I _rht the total harmonic current i _rht is calculated in the phase parameters specified by the execution of step 3 in step S4. Next, the processing proceeds to step S5, total harmonic current parameters It is compared with the effective value I _rht computed as _I rhtmin, updated as _I rhtmin> I total harmonic minimum current parameter I _Rhtmin newly the effective value I _rht the total harmonic current i _rht computed in the case of _rht The Is, phase parameter theta ₂ at this time, ..., theta _i, ..., each value is a minimum phase parameter theta _2min of _{_{θ k, ..., θ imin,}} ..., .I are correspondingly stored respectively in the _θ _kmin rhtmin> If not I _rht minimum phase parameters up to the last time is maintained. Next, the processing proceeds to step S6, the phase parameter _{_{θ 2, ..., θ i,}} ..., θ all combinations per row execution of steps S4 and S5 of the _k It is judged whether it was apricot or apricot.
[0015]
That is, after the loop of steps S3-k, S4, S5, and S6-k changes the phase parameter θ _k by 1 from 0 to 60 and is repeated 61 times without changing the other phase parameters, the phase parameter θ _k is changed. The loop of steps S3-k, S4, S5, and S6-k is repeated 61 times by changing the phase parameter θ _k by 1 from 0 to 60 each time the value is changed by 1 from 0 to 60, and a similar operation is performed. The calculation and comparison are repeated for a total of 61 ^k-1 times until the number of repetitions reaches ₂ and the process ends in step S6-2. Minimum phase parameter theta _2min result of operation, resulting in total harmonic minimum current parameter _{_{I rhtmin, ..., θ imin,}} ..., θ kmin is determined, the phase shifter 12 ₂ in step S7, ..., optimal control 12 _k phase angle θ _2min, ..., said minimum parameters for setting the theta _kmin is outputted to the interface 26. Next, the process proceeds to step S8. After Δt (1) seconds have elapsed from the reading of the data in step S1, the process returns to step S1, and the current value and initial phase angle of each feeder line are newly read and steps S2 to S8 are performed. Is executed.
[0016]
Fig. 4 shows the non-control and control of the total harmonic current generated when there are three feeder lines, the fundamental current has a thickness difference of 20%, and the initial phase angle is random (30 cases) The result of simulating and comparing time is shown. Fig. 5 shows the control and control of the total harmonic current that occurs when there are four feeder lines, the fundamental current has a difference of 20%, and the initial phase angle is random (5 cases). The result of simulating and comparing time is shown. In addition, the harmonic current value of each order uses a value obtained by dividing the fundamental wave current by the harmonic order. As shown in FIGS. 4 and 5, when there are three feeder lines, 20.79 to 87.11A (variation range 66.82A) during non-control is 34.74A or less (variation range 17.39A) during control. On the other hand, when there are four feeder lines, the non-control 37.24 to 104.53 A (change width 67.29 A) is controlled to 27.90 A or less (change width 14.05 A) during control. The value of the harmonic current flowing through each feeder line and the initial phase angle take various values, and the total harmonic current also varies between large ranges when not controlled. However, by controlling the phase, the value of the total harmonic current can be suppressed, and the effect becomes more prominent as the number of feeder lines increases.
[0017]
The gradual change of the phase control to the phase shifters 12 ₂ ,..., 12 _k is gentler to the power system, but if the phase control time of the phase shifter is too slow, the optimum control phase angle from the CPU 25 is increased. The deviation between the output and the actual phase angle of the phase shifter increases, reducing the harmonic suppression effect. For this reason, the time of Δt in step S8 is appropriately adjusted, and as a result, the time change of the phase control can be controlled by adjusting the output interval of the optimum control phase angle θ _imin .
[0018]
In the above-described embodiment, a case has been described in which a six-phase thyristor rectifier is connected to a plurality of power supply lines, and direct current, even harmonics, and multiple harmonics of 3 that circulate through the A winding are not generated. The present invention is not limited to this embodiment, and can be universally applied when AC currents including different harmonic currents are separately flowing through a plurality of feeder lines. Therefore, the order of each harmonic current detected and calculated is not limited to the order obtained by the formula of 6m ± 1 or 12m ± 1, and even and odd harmonics after the second order excluding the fundamental current. It is applicable to. The order of harmonic current to be detected and calculated can be determined as appropriate according to the applied factory load conditions and the state of the harmonics flowing through each feeder line, and the control range of the control phase angle is also 0 to It is not limited to 60 degrees, and the control angle range can be increased or decreased depending on the situation. In this case, the configuration of the control device 18 including the CPU 25 can be easily changed in design according to the above-described embodiment. Moreover, in the said embodiment, although the harmonic current value and total harmonic current value of each feeder were calculated | required as an effective value, even if it calculates as an amplitude value, the same result can be obtained.
[0019]
【The invention's effect】
According to the harmonic current suppressing device of the present invention, it is possible to reliably and significantly suppress the total harmonic current flowing from the plurality of feeders to the bus bar regardless of the state of the harmonic current flowing through the load on the power receiving side. Can do. Therefore, the present invention can be applied to all situations such as factories that require suppression of the total harmonic current flowing into the bus from a plurality of feeders. In addition, since it can be dealt with regardless of the order and current value of the harmonic current generated in the plurality of feeder lines, it is excellent in versatility. In addition, it is possible to cope with stability of temporal fluctuation of the power system by adjusting the interval of the phase control time.
[0020]
Further, the phase control operation of the present invention can be provided as a recording medium on which a control program for suppressing the total harmonic current flowing in the bus is recorded, so that the optimum control phase of the phase shifter can be provided by providing necessary data. A value can be obtained.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram of a harmonic current suppressing device of the present invention.
FIG. 2 is a block diagram illustrating an embodiment of the control device of FIG.
FIG. 3 is a flowchart illustrating a harmonic current suppressing operation of the present invention.
FIG. 4 is a diagram showing simulation results during non-control and control of the total harmonic current in the case of three feeder lines.
FIG. 5 is a diagram showing simulation results during non-control and control of the total harmonic current in the case of four feeder lines.
FIG. 6 is a schematic configuration diagram of a conventional factory power supply system.
[Explanation of symbols]
1 three-phase AC power source 2 bus _{_{2 1, 2 2, ...,}} 2 i, ..., 2 k power supply line 11 higher harmonic current suppressing device _{_{12 2, ..., 12 i,}} ..., 12 k phase shifter 13 control device 21 ₁ _{_{, 21 2, ..., 21 i}} , ..., 21 k signal converter _{_{22 1, 22 2, ...,}} 22 i, ..., 22 k current-phase detection circuit 23 the signal converter 25 CPU
_{_{27 2, ..., 27 i,}} ..., 27 k signal converter _{_{28 2, ..., 28 i,}} ..., 28 k the phase angle setting circuit _{_{CT 1, CT 2, ...,}} CT i, ..., CT k current transformer PT instrument transformer _{_{θ 2, ..., θ i,}} ..., θ k phase angle _{_{θ 2min, ..., θ imin,}} ..., θ kmin optimal control phase angle

Claims

One bus connected to the AC power supply,
A plurality of power supply lines connected to the busbars, each supplying an alternating current including a harmonic current to the power receiving side;
Phase indication of the phase between the AC power supply side and the power reception side of the harmonic current that is connected to each of the power supply lines excluding one specific reference power supply line of the plurality of power supply lines and that flows through each of the power supply lines A phase adjuster that varies according to the signal;
Harmonic current detecting means for separating and detecting each harmonic current obtained by removing each fundamental current from each AC current flowing through each power supply line for each order of the harmonic current;
An initial phase angle detection means for detecting a phase difference between the voltage of the bus and each order harmonic current of each harmonic current as an initial phase angle for each order harmonic current;
Receiving each harmonic current for each order detected by the harmonic current detection means and the initial phase angle of each order harmonic current detected by the initial phase angle detection means, and for each harmonic for each order A harmonic current that flows through each feeder line is calculated by changing the value of the phase parameter added to the initial phase angle of the current for each harmonic current that flows through each feeder line. A harmonic current is determined as a function of a phase parameter for each of the feed lines, a minimum phase parameter that minimizes the total harmonic current is determined for each of the feed lines, and a phase indication corresponding to the value of each of the minimum phase parameters Control means for outputting a signal to the phase adjuster,
Harmonic current suppression device.

The harmonic current suppression device according to claim 1, wherein the phase adjuster is a static high-speed phase shifter.

The harmonic current suppression device according to claim 1, wherein the phase adjuster is a static tap switching phase shifter.

The AC power supply is a three-phase AC power supply, the power receiving side includes a power converter, and the order of the harmonic current is represented by 6m ± 1 (m is a positive integer). A harmonic current suppressing device according to claim 1.

The harmonic current suppression device according to claim 4, wherein the phase parameter changed for each harmonic current flowing through each of the power supply lines changes in a range of 0 degrees to 60 degrees.

AC power supply of harmonic current flowing in each power supply line connected to each power supply line except for one specific reference power supply line among a plurality of power supply lines connected to one bus connected to the AC power supply By controlling the phase of the phase adjuster that fluctuates the phase between the power supply side and the power receiving side according to the phase indication signal, a method of suppressing harmonic current flowing from each of the power supply lines to the bus line,
Separating and detecting each harmonic current obtained by removing each fundamental current from each alternating current flowing through each of the feeder lines for each order of the harmonic current;
Detecting the phase difference between the voltage of the bus and the harmonic current of each order of each harmonic current as an initial phase angle for each harmonic current of each order;
Receiving each order harmonic current separated for each order of each harmonic current flowing in the feed line, and an initial phase angle of the order harmonic current;
Calculating the harmonic current flowing in each feeder by changing the phase parameter value added to the initial phase angle of each harmonic current for each order for each harmonic current flowing in each feeder;
Obtaining a minimum phase parameter value for each feed line that minimizes the total harmonic current flowing from each feed line to the bus;
Outputting a phase indication signal corresponding to each minimum phase parameter value to the phase adjuster;
Harmonic current suppression method including:

AC of harmonic currents flowing through each of the feeder lines connected to each of the feeder lines excluding one specific reference feeder line among a plurality of feeder lines connected to a single bus connected to the AC power source Records a control program for suppressing harmonic currents flowing from the feeders to the buses by controlling the phase of the phase adjuster, which varies the phase between the power supply side and the power receiving side according to the phase indication signal, by a computer. Recording medium,
The control program is
Receiving the harmonic current of each order separated for each order of each harmonic current flowing in the feeder line, and the initial phase angle of the harmonic current of the order;
Calculating the harmonic current flowing in each feeder by changing the phase parameter value added to the initial phase angle of each harmonic current for each order for each harmonic current flowing in each feeder;
Determining the minimum phase parameter value for each feed line that minimizes the total high-acoustic current flowing from the feed line to the bus;
Outputting a phase indication signal corresponding to each minimum phase parameter value to the phase adjuster;
A recording medium on which a control program for suppressing harmonic currents is recorded, characterized in that the steps of reception, calculation, determination and output are repeated after a predetermined time.

The control program according to claim 7, wherein the predetermined time can be freely changed.