JP3860179B2 - Semiconductor device and voltage monitoring method for internal power supply line - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an internal voltage down converter and a potential monitoring method for an internal power supply line.

  In recent years, the internal power supply voltage is stepped down to a predetermined internal power supply voltage for the purpose of relaxing the electric field applied to the gate oxide film of the transistor and reducing the current consumption in order to improve the reliability. An internal step-down circuit that supplies power is being developed.

(1) First prior art (FIGS. 35-39)
FIG. 35 is a block diagram showing a conventional MOS-DRAM (Dynamic Random Access Memory) incorporating an internal step-down circuit. This DRAM is disclosed in SSDM86 lecture number B-6-4, “On-Chip Supply Voltage Conversion System and Its Application to a 4Mb DRAM”.

  The semiconductor device CH of FIG. 35 includes internal step-down circuits 1a and 1b, a DRAM 3, a peripheral circuit 4, and an output buffer 5. Semiconductor device CH has a power supply terminal P1 for receiving external power supply voltage Vcc and a ground terminal P2 for receiving ground potential Vss. Internal step-down circuit 1a steps down external power supply voltage Vcc to internal power supply voltage IVcc1 and supplies it to peripheral circuit 4. The peripheral circuit 4 includes an address buffer, a data input buffer, a control circuit, and the like. Internal voltage down converter 1b steps down external power supply voltage Vcc to internal power supply voltage IVcc2 and supplies it to DRAM 3. DRAM 3 includes a memory array MA and a CMOS sense amplifier SA. The output buffer 5 is driven by the external power supply voltage Vcc.

  The memory array MA includes a plurality of word lines, a plurality of bit lines crossing the word lines, a plurality of memory cells provided at intersections of the bit lines and the word lines, a row decoder for selecting any of the plurality of word lines, and A column decoder for selecting one of the plurality of bit lines is included. The CMOS sense amplifier includes a plurality of sense amplifiers that amplify data read out to the plurality of bit lines.

  Internal voltage down converting circuit 1a is controlled by control signal φ1, and internal voltage down converting circuit 1b is controlled by control signal φ2.

  FIG. 36 shows the configuration of the internal step-down circuits 1a and 1b. The internal voltage down converter includes a reference voltage generation circuit 10, a differential amplifier circuit 20, and a driver circuit 30. The reference voltage generation circuit 10 receives the external power supply voltage Vcc and generates a reference voltage VR1 almost independent of the external power supply voltage Vcc. The reference voltage VR1 is input to the differential amplifier circuit 20, and the differential amplifier circuit 20 and the driver circuit 30 generate the internal power supply voltage IVcc independent of the fluctuations in the power supply voltage Vcc and the load current. To be supplied. External power supply voltage Vcc is, for example, 5V, and internal power supply voltage IVcc is, for example, 4V.

  FIG. 37 shows a specific circuit configuration of the internal voltage down converter. Reference voltage generating circuit 10 includes P channel MOS transistors Q11-Q15. Transistors Q11-Q13 divide external power supply voltage Vcc, and the divided voltage appears at node N1. When external power supply voltage Vcc rises, the voltage at node N1 also rises and transistor Q24 is turned off. Thereby, the rise of the voltage of the node N2 is prevented. On the other hand, when external power supply voltage Vcc decreases, the voltage at node N1 also decreases and transistor Q24 is turned on. This prevents a decrease in the voltage at node N2. In this way, the reference voltage VR1 is generated from the node N2 that hardly depends on the fluctuation of the external power supply voltage Vcc.

  Differential amplifier 20 includes a current mirror circuit composed of P channel MOS transistors Q21 and Q22 and N channel MOS transistors Q23 and Q24. A large P channel MOS transistor Q25 and a small P channel MOS transistor Q26 are connected between node N3 and power supply terminal P1. These transistors Q25 and Q26 are added to reduce the power consumption of the current mirror circuit.

  During the active period in which the DRAM 3 and the peripheral circuit 4 operate, the control signal φi (i = 1, 2) becomes “L” and the transistor Q25 is turned on. This improves the response of the current mirror circuit. In the standby period in which only a small amount of current is consumed in the DRAM 3 and the peripheral circuit 4, the control signal φi becomes “H” and the transistor Q25 is turned off. In this case, only the small-sized transistor Q26 through which a minute current flows is turned on. Therefore, the sensitivity of the current mirror circuit is reduced, but power consumption is suppressed.

  Driver circuit 30 includes a P-channel MOS transistor Q35. The gate of transistor Q22 of the current mirror circuit is connected to node N4. Transistor Q35 is connected between power supply terminal P1 and node N4. Transistor Q35 has its gate connected to node N5 of the current mirror circuit.

  If internal power supply voltage IVcc output from node N4 is higher than reference voltage VR1, the value of the current flowing through transistor Q21 is greater than the value of the current flowing through transistor Q22. Thereby, the potential of the node N5 rises. Therefore, transistor Q35 is in a shallow conductive state or a non-conductive state. As a result, supply of current from power supply terminal P1 to node N4 is stopped or reduced, and internal power supply voltage IVcc is lowered.

  Conversely, when internal power supply voltage IVcc becomes lower than reference voltage VR1, the value of the current flowing through transistor Q21 becomes smaller than the value of the current flowing through transistor Q22. As a result, the potential of the node N5 decreases. Therefore, transistor Q35 is turned on, and sufficient current is supplied from power supply terminal P1 to node N4. As a result, internal power supply voltage IVcc rises.

  In this way, a constant internal power supply voltage IVcc that does not depend on fluctuations in the external power supply voltage Vcc or load is obtained.

  FIG. 38 shows the characteristics of the internal voltage down converter. Internal power supply voltage IVcc is set to 4V. When external power supply voltage Vcc is 4 V or less, internal power supply voltage IVcc is equal to external power supply voltage Vcc. However, when external power supply voltage Vcc is 4 V or more, internal power supply voltage IVcc does not depend on the value of external power supply voltage Vcc. It becomes constant at 4V.

  FIG. 39 shows the control timing of internal voltage down converters 1a and 1b in FIG. A period corresponding to a period in which the row address strobe signal / RAS applied from the outside is “H” is called a standby period, and a period corresponding to a period in which the row address strobe signal / RAS is “L” is called an active period. . During the active period, the DRAM 3 and the peripheral circuit 4 operate and current is consumed.

  In response to the fall of row address strobe signal / RAS, control signal φ1 attains "L". Thereby, transistor Q25 (see FIG. 37) in internal voltage down converting circuit 1a is turned on, the current supply capability of internal voltage down converting circuit 1a is increased, and internal power supply voltage IVcc1 is kept constant.

  Thereafter, sense amplifier activation signal SE rises to "H". Thereby, the sense amplifier SA in the DRAM 3 is activated. In response to the rise of the sense amplifier activation signal SE, the control signal φ2 becomes “L”. Thereby, transistor Q25 (see FIG. 37) in internal voltage down converter 1b is turned on, the current supply capability of internal voltage down circuit 1b is increased, and internal power supply voltage IVcc2 is kept constant.

  In FIG. 39, a row-related set current is a current generated by activation of each circuit between the input of an address signal and the rise of the potential of the word line. The sense amplifier system current is a current generated by the activation of the CMOS sense amplifier SA. The column system current is a current generated by the activation of each circuit between the activation of the CMOS sense amplifier SA and the output of data. The row reset current is a current generated when the row address strobe signal / RAS rises.

  The control signal φ1 for the internal step-down circuit 1a is “L” during the active period. On the other hand, the control signal φ2 for the internal step-down circuit 1b is “L” for a certain period from the activation of the CMOS sense amplifier SA. This is because the sense amplifier system current flows only when the bit line is charged / discharged, that is, when the sense amplifier is active.

(2) Second prior art (FIGS. 40 to 42)
FIG. 40 is a block diagram showing a conventional internal voltage down converting circuit using a level shift circuit. The level shift circuit 90 shifts the level of the internal power supply voltage IVcc output from the driver circuit 30 from 4V to 2.4V and applies it to the differential amplifier circuit 20 in order to increase the sensitivity of the differential amplifier circuit 20. In this case, the reference voltage VR1 generated from the reference voltage generation circuit 10 is also set to 2.4V.

  FIG. 41 shows detailed configurations of the differential amplifier circuit 20, the driver circuit 30, and the level shift circuit 90. Differential amplifier circuit 20 includes a current mirror circuit including P channel MOS transistors Q27 and Q28 and N channel MOS transistors Q29 and Q30. Control signal φi or power supply voltage Vcc is applied to the gate of N channel MOS transistor Q31. The differential amplifier circuit 20 compares the voltage at the node N6 with the reference voltage VR1, and turns on / off the transistor Q35 of the driver circuit 30. From the characteristics of the transistors Q29 and Q30, the sensitivity of the differential amplifier circuit 20 increases as the voltage level applied to the transistors Q29 and Q30 decreases. Therefore, internal power supply voltage IVcc supplied to node N4 is converted to 2.4V by level shift circuit 90 and applied to node N6.

  The level shift circuit 90 is a resistance dividing circuit composed of P-channel MOS transistors Q90 and Q91 as shown in FIG. 41 or a resistance dividing circuit composed of resistors R1 and R2 as shown in FIG.

  Next, the operation of the circuit of FIG. 41 will be described. When the internal power supply voltage IVcc becomes 4V or less, the output of the level shift circuit 90 becomes 2.4V or less. At this time, since the voltage of the node N6 is lower than the reference voltage VR1, the output of the node N5 of the differential amplifier circuit 20 becomes “L”. As a result, transistor Q35 of driver circuit 30 is turned on, and external power supply voltage Vcc is supplied to node N4.

  When the internal power supply voltage IVcc becomes 4V or higher, the output of the level shift circuit 90 becomes 2.4V or higher. Therefore, since the voltage at the node N6 becomes higher than the reference voltage VR1, the output at the node N5 of the differential amplifier circuit 20 becomes “H”. As a result, transistor Q35 of driver circuit 30 is turned off, and external power supply voltage Vcc is not supplied to node N4.

  By repeating the above operation, the internal power supply voltage IVcc becomes equal to the external power supply voltage Vcc when the external power supply voltage Vcc is 4 V or less, and becomes constant at 4 V when the external power supply voltage Vcc is 4 V or more. . Since the level shift circuit 90 is a resistance dividing circuit, a through current flows from the power supply terminal P1 to the ground terminal when the transistor Q35 of the driver circuit 30 is turned on.

(3) Third prior art (FIGS. 43 to 46)
FIG. 43 is a circuit diagram showing another example of a conventional internal voltage down converter. A MOS DRAM incorporating this internal voltage down converter is disclosed in IEEE JSSCC, Vol. 23, no. 5, pp. 1128-1132, Oct. 1988.

  The voltage generation circuit 10a generates a reference voltage V1, and the voltage generation circuit 10b generates a reference voltage V2. The reference voltage generation circuit 10c receives the reference voltages V1 and V2 and generates a reference voltage VL. Reference voltages V1, V2, and VL have the characteristics shown in FIG.

  Similar to differential amplifier circuit 20 and driver circuit 30 shown in FIG. 41, differential amplifier circuit 20 and driver circuit 30 compare internal power supply voltage IVcc with reference voltage VL, and provide a constant internal power supply voltage IVcc by a feedback loop. Supply. In FIG. 43, J1 and J2 indicate current sources.

  FIG. 44 shows an example of the configuration of the reference voltage generation circuit 10c. The reference voltage generation circuit 10 c includes two current mirror amplifiers 11 and 12 and an output stage 13. Current mirror amplifier 11 includes P channel MOS transistors Q61 and Q62, N channel MOS transistors Q63 and Q64, and a current source J3. Current mirror amplifier 12 includes P channel MOS transistors Q65 and Q66, N channel MOS transistors Q67 and Q68, and a current source J4. Output stage 13 includes P channel MOS transistors Q69 and Q70 and resistors R3 and R4.

  The current mirror amplifier 11 compares the voltage at the node N7 of the output stage 13 with the reference voltage V1, and controls the transistor Q69. The current mirror amplifier 12 compares the voltage at the node N7 of the output stage 13 with the reference voltage V1, and controls the transistor Q70. A reference voltage VL is generated from node N8 of output stage 13.

  FIG. 46 shows the dependence of the reference voltage VL and the internal power supply voltage IVcc on the external power supply voltage. Until the external power supply voltage Vcc reaches 4V, the internal power supply voltage IVcc increases linearly. When the external power supply voltage Vcc is in the range of 4V to 7V, the internal power supply voltage IVcc is constant at 4V, and the external power supply voltage Vcc is 7V. If it becomes above, internal power supply voltage IVcc will increase linearly.

When performing a burn-in test (voltage application acceleration test) of a semiconductor device incorporating an internal step-down circuit having such characteristics, the internal power supply voltage IVcc is applied to an external power supply in order to apply a high voltage to the circuit elements of the internal circuit. It is necessary to apply a high external power supply voltage in a region that varies linearly according to voltage Vcc.
SSDM86 Lecture No. B-6-4, “On-Chip Supply Voltage Conversion System and Its Application to a 4Mb DRAM” IEEE JSSCC, Vol. 23, no. 5, pp. 1128-1132, Oct. 1988

  (1) In the internal circuits such as the DRAM 3 and the peripheral circuit 4 shown in FIG. 35, there is a current that is constantly consumed (current that is consumed in a direct current). When the internal power supply voltage decreases due to such a current, the transistor Q35 of the driver circuit 30 is turned on (see FIG. 37). As a result, the internal power supply voltage returns to 4V as shown in FIG. At this time, a through current flows from the power supply terminal P1 to the ground terminal P2 in the differential amplifier circuit 20, and a peak appears in the current consumption. Therefore, there is a problem that current consumption increases.

  In the internal voltage down converter of FIG. 37, as shown in FIG. 39, transistor Q25 is turned off during the standby period, and current is supplied only by transistor Q26. In this way, the current supply capability of the differential amplifier circuit 20 is lowered and the power consumption is reduced. However, there is a problem that power consumption can be reduced only to a certain extent.

  (2) Since the peripheral circuit 4 shown in FIG. 35 consumes current during the active period, the control signal φ1 is set to “L” during the active period, as shown in FIG. It is necessary to increase the current supply capability of the differential amplifier 20. Therefore, when the active period becomes longer, the power consumed by the differential amplifier 20 increases.

  In the internal voltage down converter 1b shown in FIG. 35, as shown in FIG. 39, the control signal φ2 becomes “L” for a certain period after the activation of the sense amplifier within the active period, and the current supply capability is increased. Thereafter, the current is supplied only by transistor Q26 shown in FIG. In this case, as described above, there is a problem that power consumption can be reduced only to a certain extent.

  (3) Since current consumption differs between the DRAM 3 and the peripheral circuit 4 even within the same active period, it is necessary to reduce power consumption for each internal circuit.

  (4) In the internal voltage down converter 1b shown in FIG. 35, as shown in FIG. 39, the current supply capability is increased only for a certain period after the activation of the sense amplifier within the active period. However, the current consumption in the refresh cycle is different from the current consumption in the normal cycle. In particular, when the refresh cycle time is lengthened, there is a problem that the operating current of the internal voltage down converting circuit 1b increases and the current flowing during the refreshing increases.

  (5) When a burn-in test is performed in the semiconductor device incorporating the internal voltage down converter of FIG. 43, a considerably high external power supply voltage of 7 V or more is applied to the external power supply terminal in order to apply a high voltage to the internal circuit. There is a need. In that case, the high external power supply voltage is applied as it is to an internal circuit such as the output buffer 5 which is originally driven directly by the external power supply voltage Vcc. Thereby, there is a risk that the circuit element of the internal circuit is destroyed.

  (6) In the internal step-down circuit shown in FIGS. 40 to 42, a through current flows through the level shift circuit 90 as described above. Therefore, it is necessary to set the current flowing through the level shift circuit 90 small in order to prevent an increase in power consumption. As a result, the response of the output of level shift circuit 90 to the fluctuation of internal power supply voltage IVcc is delayed.

  Further, since the fluctuation range of the internal power supply voltage IVcc is divided by resistance, the input amplitude of the differential amplifier circuit 20 is reduced. Therefore, there is a problem that the sensitivity of the internal step-down circuit is not so good despite having the level shift circuit 90.

  (7) A semiconductor device that does not have an internal step-down circuit has only one power supply line L1 on the chip ch as shown in FIG. Power supply line L1 is connected to power supply pad pVcc receiving external power supply voltage Vcc. Therefore, the potential of the power supply line L1 can be monitored from the power supply pad pVcc. CIR indicates a circuit area.

  However, a semiconductor device incorporating an internal voltage down converter has an external power supply line and an internal power supply line on the chip. The external power supply line is connected to the power supply pad, but the internal power supply line is not connected to the pad. Therefore, in order to monitor the potential of the internal power supply line, it is necessary to directly probe the internal power supply line. Therefore, the molded semiconductor device has a problem that the potential of the internal power supply line cannot be monitored.

  The present invention has been made to solve the above problems (1) to (7), and has the following objects (1) to (7).

  (1) An object of the present invention is to reduce power consumption of an internal step-down circuit while stably supplying an internal power supply voltage to the internal circuit.

  (2) Another object of the present invention is to sufficiently reduce the power consumption of the internal step-down circuit even when the active period of the internal circuit becomes long.

  (3) Still another object of the present invention is to minimize power consumption when supplying an internal power supply voltage to a plurality of internal circuits performing different operations.

  (4) Still another object of the present invention is to prevent an increase in refresh current when a refresh cycle period becomes long in a memory device driven by an internal power supply voltage.

  (5) Still another object of the present invention is to efficiently perform an acceleration test of a semiconductor device having an internal step-down circuit without destroying circuit elements.

  (6) Still another object of the present invention is to improve the sensitivity of the internal voltage down converter.

  (7) Still another object of the present invention is to monitor the potential without directly probing the internal power line.

  The method for monitoring the voltage of the internal power supply line according to the present invention is a semiconductor comprising an internal power supply line to which an internal power supply voltage is applied, an external pin, and a voltage transmission means for forming an electrical path between the external pin and the internal power supply line. This is a method for monitoring the voltage of the internal power supply line in the device, when the voltage applied to the external pin is changed, the standby current flowing between the external power supply voltage and the fixed voltage is detected, and the standby current starts to rise. Measure the internal power supply voltage based on the external pin voltage.

  Preferably, the voltage applied to the external pin is increased.

  Preferably, the voltage transfer means comprises a diode-connected transistor having at least one known threshold voltage, to the voltage of the external pin and the known threshold voltage of the transistor when the standby current begins to rise. Based on this, the voltage of the internal power supply line is calculated.

  In particular, the voltage transmission means includes n transistors, the voltage of the internal power supply line is VINT, the detected voltage of the external pin is VEXT, and the threshold voltage of the transistor is Vth. The voltage is calculated based on the formula of VINT = VEXT−n · Vth.

  According to the method for monitoring the voltage of the internal power supply line of the present invention, the first and second external pins, the internal power supply line to which the internal power supply voltage is applied, and the voltage of the second external pin have a predetermined threshold value than the internal power supply voltage. A method of monitoring a voltage of an internal power supply line in a semiconductor device including a switch element that becomes conductive when a voltage that is lower by a value voltage is provided, and includes a predetermined predetermined value for first and second external pins A voltage is applied, the voltage applied to the second external pin is dropped, and it is detected that a current starts to flow between the first external pin and the second external pin.

  The semiconductor device according to the present invention is electrically connected between an internal power supply line, an internal step-down circuit that receives an external power supply voltage and generates an internal power supply voltage to be supplied to the internal power supply line, an external pin, and the external pin and the internal power supply line. In the test mode, the standby current flowing between the external power supply voltage and the fixed voltage is detected, and the external current when the standby current starts to rise by applying a voltage to the external pin in the test mode. Allows internal power supply voltage to be measured based on pin voltage.

  Preferably, the voltage transmission means includes a plurality of transistors provided between the external pin and the internal power supply line and diode-connected.

  The semiconductor device of the present invention includes an external pin, an internal voltage down converter that receives an external power supply voltage and generates an internal power supply voltage lower than the external power supply voltage, an internal power supply line to which the internal power supply voltage is supplied, and a voltage of the internal power supply line The voltage transmission means includes at least one diode-connected transistor provided between the external pin and the internal power supply line and having a gate electrode and a drain electrode coupled to each other. It has the same known threshold voltage as the transistors constituting the internal step-down circuit, is coupled to the external pin and the drain electrode of one of the plurality of transistors, and is connected to the internal power line and the other one of the plurality of transistors. Coupled with the source electrode of two transistors.

  A semiconductor device according to the present invention includes an internal step-down circuit that receives an external power supply voltage and generates an internal power supply voltage lower than the external power supply voltage, an internal power supply line to which the internal power supply voltage is supplied, and voltage transmission of the voltage of the internal power supply line And a single external pin used exclusively for measuring the voltage of the internal power supply line, and the voltage transmission means includes a switch element that conducts in response to the instruction signal, and an external power supply voltage via the switch element. Provided between the external pin, the internal power supply line and the gate electrode are electrically coupled, and the conductive state is established when the voltage of the external pin is lower than the internal power supply voltage by a predetermined threshold voltage. A peripheral circuit having a predetermined function and a signal generation circuit for generating an instruction signal based on a plurality of control signals input from the outside used in the peripheral circuit Obtain.

  A semiconductor device according to the present invention includes first and second external pins, an internal voltage down converter that receives an external power supply voltage and generates an internal power supply voltage lower than the external power supply voltage, and an internal power supply line to which the internal power supply voltage is supplied. A voltage transmitting means for voltage of the internal power supply line, the voltage transmitting means being coupled between the internal power supply line and the gate electrode via the switch element, the switch element conducting in response to the instruction signal, and the source The electrode and the drain electrode are respectively coupled to the first and second external pins, and when a predetermined voltage is applied to the first external pin, the second external pin has a predetermined threshold voltage higher than the internal power supply voltage. A peripheral circuit having a predetermined function, and a plurality of control signals input from the outside used in the peripheral circuit, including a transistor connected so as to be in a conductive state when the voltage is low Further comprising a signal generating circuit for generating a No. 示信.

  A semiconductor device according to the present invention includes an internal step-down circuit that receives an external power supply voltage and generates an internal power supply voltage lower than the external power supply voltage, an internal power supply line to which the internal power supply voltage is supplied, and voltage transmission of the voltage of the internal power supply line And a single external pin used exclusively for measuring the voltage of the internal power supply line, and the voltage transmission means includes a switch element that conducts in response to the instruction signal, and an internal power supply line via the switch element. A transistor disposed between the external pin and diode-connected, the transistor having the same known threshold voltage as that of the transistor constituting the internal step-down circuit and having a predetermined function; and a peripheral circuit And a signal generation circuit for generating an instruction signal based on a plurality of control signals input from the outside used in the above.

  (1) The potential of the internal power supply line can be calculated based on the potential of the external pad and the threshold voltage of the transistor of the voltage transmission means. Thereby, the potential of the internal power supply line can be monitored without directly probing the internal power supply line.

  (2) It can be detected that a current starts to flow to an external pad to which a constant voltage is applied.

(1) First embodiment (FIGS. 1 to 21)
(A) Overall configuration and schematic operation (FIG. 1)
FIG. 1 is a block diagram showing a configuration of a semiconductor device according to a first embodiment of the present invention. Semiconductor device CH includes an internal voltage down converter 1, a DRAM 3, a peripheral circuit 4 and an output buffer 5. Internal voltage down converter 1 steps down external power supply voltage Vcc to internal power supply voltage IVcc and supplies it to both DRAM 3 and peripheral circuit 4. The output buffer 5 is driven by the external power supply voltage Vcc.

  Internal voltage down converting circuit 1 includes a reference voltage generating circuit 10, a differential amplifier circuit 20 and a driver circuit 30 for generating a reference voltage VR1, as well as a conventional internal voltage down converting circuit, and further includes an n channel driver circuit 40 and a reference voltage generating circuit. A circuit 45 is included. The reference voltage generation circuit 45 generates a reference voltage VR2 and supplies it to the n-channel driver circuit 40. As will be described later, n-channel driver circuit 40 receives reference voltage VR2 and generates internal power supply voltage IVcc.

  A burn-in mode setting circuit 50 is connected between the external power supply line L1 to which the external power supply voltage Vcc is applied and the internal power supply line L2 to which the internal power supply voltage IVcc is applied. Burn-in mode setting circuit 50 is controlled by a burn-in mode setting signal BVD generated from burn-in mode setting signal generation circuit 70.

  On the other hand, the differential amplifier circuit 20 is controlled by an activation signal ACT generated from the activation signal generation circuit 80. Activation signal generation circuit 80 generates activation signal ACT in response to control signal φX generated from control signal generation circuit 60 and burn-in mode setting signal BVD generated from burn-in mode setting signal generation circuit 70.

  In the normal mode (during normal operation), the burn-in mode setting circuit 50 is deactivated by the burn-in mode setting signal BVD. At this time, control signal φX from control signal generation circuit 60 is applied to differential amplifier circuit 20 as activation signal ACT. Therefore, the differential amplifier circuit 20 is controlled by the control signal φX. Normally, the internal power supply voltage IVcc is supplied by the n-channel driver circuit 40, the differential amplifier circuit 20 is activated during the operation of the DRAM 3 and the peripheral circuit 4, and the driver circuit 30 has insufficient supply capability of the n-channel driver circuit 40. Be compensated.

  In the burn-in mode (burn-in test), the burn-in mode setting circuit 50 is activated and the differential amplifier circuit 20 is deactivated. Thereby, the external voltage Vcc of the external power supply line L1 is directly supplied to the internal power supply line L2.

  The configurations of the reference voltage generating circuit 10 and the driver circuit 30 are the same as those shown in FIG. The configuration of the differential amplifier circuit 20 is the same as that shown in FIG. In this case, activation signal ACT is applied to the gate of transistor Q31.

  The configuration shown in FIG. 37 may be used as the configuration of the differential amplifier circuit 20. However, the transistor Q26 is not provided, and the logic of the control signal φX is reversed.

(B) Details of the internal step-down circuit 1 (FIGS. 2 to 4)
FIG. 2 shows the configuration of a part of the internal step-down circuit 1 in detail. N channel driver circuit 40 includes an N channel MOS transistor Q40. The transistor Q40 is a source follower transistor, and is connected in parallel with the transistor Q35 of the driver circuit 30. A reference voltage VR2 is applied to the gate of the transistor Q40. The reference voltage VR2 is set as follows:

VR2 = IVcc + Vth
Here, Vth is the threshold voltage of transistor Q40. On the other hand, since VR1 = IVcc is established, when the reference voltage VR1 is 4V, the reference voltage VR2 is set to (4 + Vth) V.

  Since the transistor Q40 operates in the saturation region, the current supply capability is small, but a constant internal power supply voltage IVcc can always be supplied. Thereby, it is possible to compensate for the current constantly consumed in the DRAM 3 and the peripheral circuit 4. During operation of DRAM 3 and peripheral circuit 4, differential amplifier circuit 20 is activated, and internal power supply voltage IVcc is supplied by both driver circuit 30 and n-channel driver circuit 40.

  As shown in FIG. 3, a level shift circuit 90 may be provided for level-shifting the output voltage of the driver circuit 30 and supplying it to the differential amplifier circuit 20. Further, as shown in FIG. 4, the activation signal ACT may be supplied to the level shift circuit 90 via the inverter 91. In this case, when the activation signal ACT becomes “H”, the output of the inverter 91 becomes “L”. Therefore, the level shift circuit 90 is activated. On the contrary, when the activation signal ACT becomes “L”, the output of the inverter 91 becomes “H”. Therefore, the level shift circuit 90 is deactivated.

  Thus, the level shift circuit 90 is also activated when the differential amplifier circuit 20 is activated, and the level shift circuit 90 is also deactivated when the differential amplifier circuit 20 is inactive. Therefore, power consumption can be further reduced by deactivating differential amplifier circuit 20 and level shift circuit 90 in the standby state.

(C) Control signal generation circuit 60 and control operation (FIGS. 5 to 8)
As shown in FIG. 5, refresh control circuit 61 provides a control signal to sense amplifier control circuit 62 in response to externally applied row address strobe signal / RAS and externally applied column address strobe signal / CAS. Sense amplifier control circuit 62 generates sense amplifier activation signal SE in response to the control signal. Control signal generating circuit 60 generates control signal φX in response to row address strobe signal / RAS, column address strobe signal / CAS and sense amplifier activation signal SE.

  The control operation of the control signal generation circuit 60 will be described with reference to the waveform diagrams of FIGS.

  First, the operation in the normal cycle of the normal mode (normal operation) will be described with reference to FIG. When the active period starts when the row address strobe signal / RAS becomes “L”, the control signal φX rises to “H”. As a result, differential amplifier circuit 20 is activated, and internal power supply voltage IVcc is supplied to DRAM 3 and peripheral circuit 4 by driver circuit 30. As a result, it is possible to compensate for the row system set current, the sense amplifier system current, the column system current, and the row system reset current.

  When row address strobe signal / RAS rises to “H” and the active period ends, control signal φX falls to “L”. As a result, differential amplifier circuit 20 is deactivated and internal power supply voltage IVcc is supplied only by n-channel driver circuit 40. During the standby period, the current consumption of the DRAM 3 and the peripheral circuit 4 is small, so that the internal power supply voltage IVcc can be kept constant.

  Next, the operation during the CAS-before-RAS refresh cycle in the normal mode will be described with reference to FIG. The column system does not operate during CAS before RAS refresh. Therefore, even when the row address strobe signal / RAS is “L”, the operations of the DRAM 3 and the peripheral circuit 4 can be terminated when the refresh of the memory cells is completed. In this case, if the DRAM 3 and the peripheral circuit 4 are reset at that time, no peak current is generated in the DRAM 3 and the peripheral circuit 4 even if the row address strobe signal / RAS is "L" thereafter.

  Therefore, the inside of the semiconductor device is in a standby state similarly to the standby period. Therefore, the control signal φX becomes “H” only during the period until the operation of the DRAM 3 and the peripheral circuit 4 is completed, and activates the differential amplifier circuit 20. Outside this period, the internal power supply voltage IVcc is supplied only by the n-channel driver circuit 40 even if the row address strobe signal / RAS is "L".

  As a result, even if the period during which the row address strobe signal / RAS is “L” in the CAS before RAS refresh cycle becomes longer, if the operations of the DRAM 3 and the peripheral circuit 4 are completed, the differential amplifier circuit 20 consumes them. Electric power can be reduced sufficiently.

  Next, another example of the operation during the CAS-before-RAS refresh cycle in the normal mode will be described with reference to FIG. When the DRAM 3 and the peripheral circuit 4 are not reset when the refresh is completed, but are reset when the row address strobe signal / RAS rises to “H”, the timing of the control signal φX is as shown in FIG. Become. The control signal φX becomes “H” only during the refresh operation and the reset operation, and activates the differential amplifier circuit 20. In other periods, the internal power supply voltage IVcc is supplied only by the n-channel driver circuit 40. Thereby, even when the period during which the row address strobe signal / RAS is “L” is long, the power consumption can be significantly reduced.

(D) Other control operations of the control signal generation circuit 60 (FIGS. 9 to 12)
First, the operation of the control signal generation circuit 60 in the auto refresh cycle will be described with reference to FIGS. In this case, the control signal generation circuit 60 is controlled by the refresh control circuit 61, the timer circuit 64, and the delay circuit 66.

  When an auto-refresh cycle starts in response to row address strobe signal / RAS and column address strobe signal / CAS, an activation signal is applied from refresh control circuit 61 to refresh address counter circuit 63, and an activation signal is output to timer circuit 64. TE is given. As a result, the refresh address counter circuit 63 and the timer circuit 64 are activated. As a result, the refresh address signal RA is supplied from the refresh address counter circuit 63 to the address buffer 65. The address buffer 65 is controlled by a control signal CN output from the timer circuit 64. Address buffer 65 provides address signal AD to memory array MA (see FIG. 1) in response to refresh address signal RA. The address to be refreshed is designated by this address signal AD.

  On the other hand, timer circuit 64 provides trigger signal A to delay circuit 66 and control signal generation circuit 60. In response to the rise of trigger signal A, control signal generation circuit 60 raises control signal φX to “H”. The delay circuit 66 delays the trigger signal A for a predetermined time and outputs a delay signal DA. Control signal generating circuit 60 causes control signal φX to fall to “L” in response to the rise of delay signal DA.

  The delay time by the delay circuit 66 is set in advance to a time sufficient for completing the restore operation in the memory cell to be refreshed. Using this control signal φX, differential amplifier circuit 20 shown in FIG. 1 is activated and deactivated. As a result, the differential amplifier circuit 20 is activated only while the memory cell is refreshed. Therefore, unnecessary current does not flow during refresh, and the refresh current can be reduced.

  In a normal cycle, an externally applied address signal ADD is applied as an address signal AD to the memory array MA (see FIG. 1) via the address buffer 65.

  Next, the operation during the CAS before RAS refresh cycle will be described with reference to FIGS. In this case, the control signal generation circuit 60 is controlled by a refresh control circuit 61, a refresh address counter circuit 63, an address buffer 65, a word line control circuit 66, a sense amplifier control circuit 67, and a delay circuit 68.

  When the CAS before RAS refresh cycle starts in response to the row address strobe signal / RAS and the column address strobe signal / CAS, an activation signal is applied from the refresh control circuit 61 to the refresh address counter circuit 63. As a result, the refresh address counter circuit 63 is activated, and the refresh address signal RA is applied to the address buffer 65.

  Address buffer 65 provides address signal AD to memory array MA (see FIG. 1) in response to refresh address signal RA, and also provides refresh address signal RA to word line control circuit 66 and sense amplifier control circuit 67. As a result, the word line control circuit 66 outputs the word line control signal RX, and the sense amplifier control circuit 67 outputs the sense amplifier activation signal SE. The delay circuit 68 delays the sense amplifier activation signal SE for a predetermined time and outputs a delay signal SED.

  Control signal generation circuit 60 raises control signal φX to “H” in response to the rise of word line control signal RX, and falls control signal φX to “L” in response to the rise of delay signal SED. The delay time by the delay circuit 68 is set to a time sufficient for completing the restore operation of the memory cell to be refreshed. Using this control signal φX, differential amplifier circuit 20 is activated and deactivated.

  In this way, since the differential amplifier circuit 20 is activated only while the memory cell is refreshed, unnecessary current does not flow during refresh, and the current during refresh can be reduced.

  The control operations of FIGS. 9 to 12 can also be applied to the internal voltage down converting circuit 1b shown in FIG. Also in this case, the current during refresh can be reduced.

(E) Details of burn-in mode setting circuit 50 (FIGS. 13 to 15)
FIG. 13 shows a detailed configuration of the burn-in mode setting circuit 50. Burn-in mode setting circuit 50 includes a P-channel MOS transistor Q50. The transistor Q50 is connected in parallel with the transistor Q35 of the driver circuit 30. Burn-in mode setting signal BVD is applied to the gate of transistor Q50.

  In the normal mode, the burn-in mode setting signal BVD becomes “H”. Thereby, the transistor Q50 is turned off. At this time, the control signal φX is supplied to the differential amplifier circuit 20 as the activation signal ACT. Thereby, internal power supply voltage IVcc is supplied by driver circuit 30.

  During the burn-in mode test, the burn-in mode setting signal BVD becomes “L”. Thereby, transistor Q50 is turned on. Therefore, external power supply voltage Vcc is directly applied to internal power supply line L2. As a result, Vcc = IVcc. At this time, the activation signal ACT becomes “L”. As a result, the differential amplifier circuit 20 is deactivated, and the output of the differential amplifier circuit 20 becomes “H”. Therefore, transistor Q35 is turned off.

  FIG. 14 shows another example of the burn-in mode setting circuit 50. Burn-in mode setting circuit 50 includes an N channel MOS transistor Q51 and an inverter 51. Transistor Q51 is connected between the gate of transistor Q35 of driver circuit 30 and the ground terminal. Burn-in mode setting signal BVD is applied to the gate of transistor Q51 via inverter 51.

  In the normal mode, the burn-in mode setting signal BVD becomes “H”, and the transistor Q51 is turned off. Thereby, differential amplifier circuit 20 and driver circuit 30 form a feedback loop, and internal power supply voltage IVcc is supplied.

  In the burn-in mode, the burn-in mode setting signal BVD becomes “L” and the transistor Q51 is turned on. Thereby, transistor Q35 of driver circuit 30 is turned on, and external power supply voltage Vcc is directly supplied to internal power supply line L2.

  FIG. 15 shows the characteristics of the internal power supply voltage IVcc. Since the external power supply voltage Vcc and the internal power supply voltage IVcc are equal in the burn-in mode, an excessive voltage is not applied to each circuit element more than necessary. In addition, since an accurate voltage can be applied to each circuit element regardless of variations in process parameters, a burn-in test with high accuracy and reproducibility can be performed.

  This burn-in mode setting circuit 50 can also be applied to the semiconductor device shown in FIG. Also in this case, a burn-in test with good accuracy and reproducibility can be performed.

(F) Details of burn-in mode setting signal generation circuit 70 (FIGS. 16 to 21)
FIG. 16 shows an example of burn-in mode setting signal generation circuit 70, and FIGS. 17 and 18 show signal waveform diagrams of a burn-in mode set cycle and a burn-in mode reset cycle, respectively.

  First, the burn-in mode set cycle will be described. The timing generator 71 generates a counter reset pulse φA if the column address strobe signal / CAS and the write enable signal / WE are “L” at the time of the fall of the row address strobe signal / RAS. As a result, the n-bit counter 72 starts counting.

  As an input of n-bit counter 72, column address strobe signal / CAS is applied. When the operation of changing column address strobe signal / CAS to “H” and “L” is repeated 2n times, counter signal φC output from n-bit counter 72 rises to “H”. In response to the rise of counter signal φC, burn-in mode setting signal BVD output from buffer 73 falls to “L”.

  Next, the burn-in mode reset cycle will be described. If the column address strobe signal / CAS is “L” and the write enable signal / WE is “H” at the fall of the row address strobe signal / RAS, the timing generator 71 generates a counter reset pulse φB. As a result, the n-bit counter 72 is reset, and the counter signal φC falls to “L”. In response to the fall of counter signal φC, burn-in mode setting signal BVD output from buffer 73 rises to “H”.

  Thus, in the above example, the burn-in mode is set by toggling the external column address strobe signal / CAS based on the WCBR (WE / CAS before RAS) test mode set cycle standardized by JEDEC in the 4M bit DRAM, and the CBR. The burn-in mode is reset by the (CAS before RAS) cycle or the ROR (RAS only refresh) cycle.

  In the above example, since the burn-in mode can be set by the timing method, a plurality of power sources are not required for the burn-in device during the burn-in test. Therefore, the burn-in mode can be set at a low cost. The timing for setting the burn-in mode is not limited to the above timing, but it is necessary to select a timing that is not normally described in the product specification, that is, a timing that can be distinguished from the timing of the normal cycle.

  FIG. 19 shows another example of the burn-in mode setting signal generation circuit 70, and FIGS. 20 and 21 show signal waveform diagrams of the burn-in mode set cycle and the burn-in mode reset cycle, respectively.

  First, the burn-in mode set cycle will be described. High voltage detection circuit 76 includes n stages of N channel MOS transistors Q71 to Q7n cascaded to an arbitrary address terminal. If the column address strobe signal / CAS and the write enable signal / WE are “L” at the time of falling of the row address strobe signal / RAS, the timing generator 74 generates a clock pulse φD. At this time, if a high voltage (Vcc + n · Vth) is applied to the address terminal, the signal φE is “H”. Buffer 75 lowers burn-in mode setting signal BVD to “L” if signal φE is “H” at the rise of clock pulse φD.

  Next, the burn-in mode reset cycle will be described. If the column address strobe signal / CAS is “L” and the write enable signal / WE is “H” at the fall of the row address strobe signal / RAS, the timing generator 74 generates a clock pulse φF. Buffer 75 raises burn-in mode setting signal BVD to “H” in response to the rise of clock pulse φF.

  In the above example, a burn-in mode setting signal is generated by combining the application of a high voltage set to be higher than the external power supply voltage Vcc in the product specifications to one or more address terminals and the WCBR test mode set cycle. The

  In other than the burn-in mode set cycle, a normal high level or low level voltage is applied to the address terminal as “H” or “L” instead of a high voltage. Instead of the normal high level voltage, the high voltage may be given as “H”.

  Further, in the burn-in mode set cycle, instead of using the address terminal, for example, a high level voltage applied to the data input terminal may be set to the above high voltage.

(2) Second embodiment (FIGS. 22 to 25)
(A) Overall configuration and schematic operation (FIG. 22)
FIG. 22 is a block diagram showing the configuration of the semiconductor device according to the second embodiment. This semiconductor device CH includes two internal step-down circuits 1A and 1B. Internal voltage down converter 1A steps down external power supply voltage Vcc to internal power supply voltage IVcc1 and supplies it to peripheral circuit 4. Internal voltage down converter 1B steps down external power supply voltage Vcc to internal power supply voltage IVcc2, and supplies it to DRAM 3. The activation signal generation circuit 60a generates two activation signals ACT1 and ACT2. The differential amplifier circuit 20 of the internal step-down circuit 1A is controlled by an activation signal ACT1, and the differential amplifier circuit 20 of the internal step-down circuit 1B is controlled by an activation signal ACT2.

  As shown in FIG. 23, activation signal generation circuit 60a generates activation signals ACT1 and ACT2 in response to row address strobe signal / RAS, column address strobe signal / CAS and sense amplifier activation signal SE.

  Next, the operation in the normal cycle of the normal mode will be described with reference to FIG. In response to the fall of row address strobe signal / RAS, activation signal ACT1 rises to "H". Thereby, the differential amplifier circuit 20 in the internal step-down circuit 1A is activated. Thereafter, sense amplifier activation signal SE rises to "H", and activation signal ACT2 rises to "H" in response to the rise. Thereby, the differential amplifier circuit 20 in the internal step-down circuit 1B is activated.

  The activation signal ACT2 falls to “L” after a predetermined time has elapsed. Thereby, the differential amplifier circuit 20 in the internal voltage down converter 1B is inactivated. The time when the activation signal ACT2 is “H” is set in advance to a time necessary for compensating the sense amplifier system current.

  When row address strobe signal / RAS rises to "H", activation signal ACT1 falls to "L". Thereby, the differential amplifier circuit 20 in the internal step-down circuit 1A is inactivated.

  Next, the operation during the CAS-before-RAS refresh cycle in the normal mode will be described with reference to FIG. In response to the fall of row address strobe signal / RAS, activation signal ACT1 rises to "H". Thereby, the differential amplifier circuit 20 in the internal step-down circuit 1A is activated. Thereafter, sense amplifier activation signal SE rises to "H", and activation signal ACT2 rises to "H" in response to the rise. Thereby, the differential amplifier circuit 20 in the internal step-down circuit 1B is activated.

  Thereafter, the sense amplifier activation signal SE falls to “L”. In response to the fall, activation signal ACT1 falls to "L", and activation signal ACT2 falls to "L". As a result, the differential amplifier circuit 20 in the internal step-down circuit 1A is deactivated, and the differential amplifier circuit 20 in the internal step-down circuit 1B is deactivated.

  In this way, power consumption can be reduced in the CAS before RAS refresh cycle.

(3) Other examples of internal voltage down converter 1 (FIGS. 26 to 27)
FIG. 26 is a block diagram showing another example of the internal voltage down converting circuit 1. In this internal voltage down converter 1, an amplifier circuit 100 for amplifying the output amplitude of the level shift circuit 90 is further provided. The output of the amplifier circuit 100 is given to the differential amplifier circuit 20. The amplifier circuit 100 is controlled by the reference voltage VR1.

  FIG. 27 shows a detailed configuration of a part of the internal voltage down converting circuit 1 of FIG. The configurations of the differential amplifier circuit 20, the driver circuit 30, and the level shift circuit 90 are the same as those shown in FIG. However, activation signal ACT is applied to the gate of transistor Q31 of differential amplifier circuit 20. Amplifier circuit 100 is a current mirror circuit composed of P-channel MOS transistors Q101 and Q102 and N-channel MOS transistors Q103 and Q104. A reference voltage VR1 is applied to the gate of transistor Q103, and the gate of transistor Q104 is connected to node N6 of level shift circuit 90. Activation signal ACT is applied to the gate of N channel MOS transistor Q105.

  Next, the operation of the circuit of FIG. 27 will be described. When the internal power supply voltage IVcc is 4V or less, the output of the level shift circuit 90 is 2.4V or less, which is lower than the reference voltage VR1. As a result, the output of the node N7 of the amplifier circuit 100 becomes “L” of about 1 to 2V.

  When the internal power supply voltage IVcc is 4V or higher, the output of the level shift circuit 90 is 2.4V or higher, which is higher than the reference voltage VR1. Thereby, the output of the node N7 of the amplifier circuit 100 becomes “H” of about 4V to 5V. Since the amplitude of the output voltage of the level shift circuit 90 is amplified by the amplifier circuit 100, the sensitivity of the internal step-down circuit is improved.

  This internal voltage down converter can be applied not only to the semiconductor device shown in FIG. 1, but also to the semiconductor device shown in FIG.

(4) Method for monitoring internal power supply line L2 (FIGS. 28 to 34)
FIG. 28 is a schematic diagram showing a configuration on a chip ch of a semiconductor device including an external power supply line L1 receiving external power supply voltage Vcc and an internal power supply line L2 receiving internal power supply voltage IVcc. As shown in FIG. 28, external power supply line L1 is connected to power supply pad pVcc. A monitor circuit 110 is connected between an arbitrary pad pa receiving a signal or a predetermined potential and the internal power supply line L2. The pad pa is connected to an external pin.

(A) First monitoring method (FIG. 29)
Monitor circuit 110 includes N channel MOS transistors QN1 to QN3. Transistors QN1-QN3 are connected in series between external pin EP and internal power supply line L2. The threshold voltage of transistors QN1 to QN3 is set to Vth.

  First, the standby current flowing between the power supply pin that receives the external power supply voltage Vcc and the ground pin that receives the ground potential is measured. Then, the potential of the external pin EP is gradually increased while monitoring the current flowing between the power supply pin and the ground pin. Assuming that the potential of the external pin EP when the current flowing between the power supply pin and the ground pin starts to rise is VEXT, the potential VINT of the internal power supply line L2 is calculated from the following equation.

VINT = VEXT-3 ・ Vth
Therefore, the potential of the internal power supply line L2 can be monitored without directly probing.

(B) Second monitoring method (FIG. 30)
Monitor circuit 110 includes N channel MOS transistors QN4 and QN5. The transistors QN4 and QN5 are connected in series between the constant voltage source V and an arbitrary external pin EP. Constant voltage source V is a power supply pin that receives external power supply voltage Vcc, for example. Transistor QN4 has its gate connected to internal power supply line L2. A special mode signal φ is applied from the special mode signal generation circuit 111 to the gate of the transistor QN5.

  Special mode generation circuit 111 generates special mode signal φ in response to row address strobe signal / RAS, column address strobe signal / CAS and write enable signal / WE. The threshold voltage of transistors QN4 and QN5 is set to Vth.

  First, the potential of the constant voltage source V and the external pin EP is set to 5V, and the potential of the special mode signal φ is set to 7V. Then, while monitoring the current flowing between the external pin EP and the constant voltage source V, the potential of the external pin EP is gradually lowered. Assuming that the potential of the external pin EP when current starts to flow between the external pin EP and the constant voltage source V is VEXT, the potential VINT of the internal power supply line L2 is calculated by the following equation.

VINT = VEXT + Vth
Therefore, the potential of the internal power supply line L2 can be monitored without directly probing.

(C) Third monitoring method (FIG. 31)
Monitor circuit 110 includes a P-channel MOS transistor QP1. The transistor QP1 is connected between the internal power supply line L2 and an arbitrary external pin EP. A special mode signal φ is applied to the gate of transistor QP1. N-channel MOS transistor QN6 is one transistor in the internal circuit.

  When the potential of special mode signal φ is set to 0 V, transistor QP1 is turned on, and external pin EP and internal power supply line L2 are electrically connected. Therefore, by monitoring the potential VEXT of the external pin EP, the potential VINT of the internal power supply line L2 can be calculated by the following equation.

VINT = VEXT
Therefore, the potential of the internal power supply line L2 can be monitored without directly probing.

(D) Fourth monitoring method (FIG. 32)
Monitor circuit 110 includes an N channel MOS transistor QN7 and a P channel MOS transistor QP2. Transistor QN7 is connected between any external pin EP1 and any external pin EP2. Transistor QP2 is connected between internal power supply line L2 and the gate of transistor QN7. A special mode signal φ is applied to the gate of transistor QP2.

  The threshold voltage of transistor QN7 is set to Vth. When the potential of special mode signal φ is set to 0 V, transistor QP2 is turned on, and the potential of internal power supply line L2 is applied to the gate of transistor QN7. The potential of the external pin EP1 is set to 5V. While monitoring the current flowing between the external pin EP1 and the external pin EP2, the potential of the external pin EP2 is gradually lowered. Then, assuming that the potential of the external pin EP2 when current starts to flow between the external pin EP1 and the external pin EP2, the potential VINT of the internal power supply line L2 is calculated by the following equation.

VINT = VEXT + Vth
Therefore, the potential of the internal power supply line L2 can be monitored without directly probing.

(E) Fifth monitoring method (FIG. 33)
Monitor circuit 110 includes an N channel MOS transistor QN8. Transistor QN8 is connected between internal power supply line L2 and arbitrary external pin EP. A special mode signal φ is applied to the gate of transistor QN8. N channel MOS transistor QN9 is one transistor in the internal circuit.

  When the potential of special mode signal φ is set to 7V, transistor QN8 is turned on, and external pin EP and internal power supply line L2 are electrically connected. Therefore, by measuring the potential VEXT of the external pin EP, the potential VINT of the internal power supply line L2 is calculated by the following equation.

VINT = VEXT
Therefore, the potential of the internal power supply line L2 can be monitored without directly probing.

(F) Sixth monitoring method (FIG. 34)
Monitor circuit 110 includes an N channel MOS transistor QN10 and a P channel MOS transistor QP3. Transistor QN10 and transistor QP3 are connected in series between internal power supply line L2 and arbitrary external pin EP. Transistor QN10 is diode-connected. A special mode signal φ is applied to the gate of transistor QP3. N channel MOS transistor QN11 is one transistor in the internal circuit. The threshold voltage of transistor QN10 is set to Vth.

  First, when the potential of the special mode signal φ is set to 0 V, the transistor QP3 is turned on, and the internal power supply line L2 and the external pin EP are connected via the transistor QN10. Therefore, by measuring the potential VEXT of the external pin EP, the potential VINT of the internal power supply line L2 is calculated by the following equation.

VINT = VEXT + Vth
Therefore, the potential of the internal power supply line L2 can be monitored without directly probing.

  In the third monitoring method of FIG. 31 described above, since the P-channel MOS transistor QP1 is used, the potential VINT of the internal power supply line L2 is output as it is to the external pin EP, and in the fifth monitoring method of FIG. Since a special mode signal φ of 7V is applied to the gate of channel MOS transistor QN8, potential VINT of internal power supply line L2 is output as it is to external pin EP. However, it is not preferable to use a P-channel MOS transistor in the final stage or to apply a high voltage to the gate of the transistor. In the first monitoring method of FIG. 29, the second monitoring method of FIG. 30, the fourth monitoring method of FIG. 32, and the sixth monitoring method of FIG. 34, the potential VINT of the internal power supply line L2 is the threshold value of the transistor. Although the voltage Vth drops, if the threshold voltage Vth of this transistor is known, the potential VINT of the internal power supply line L2 can be calculated by calculation.

  The first to sixth monitoring methods described above can be applied not only to the semiconductor device of FIG. 1 but also to various semiconductor devices having internal power supply lines.

  Note that as the configuration of the special mode signal generation circuit 111, a configuration similar to the configuration shown in FIG. 16 or FIG. 19 can be used.

1 is a block diagram showing a configuration of a semiconductor device according to a first embodiment of the present invention. It is a circuit diagram which shows the structure of a part of internal voltage step-down circuit. FIG. 6 is a circuit diagram showing another example of an internal voltage down converter. FIG. 10 is a circuit diagram showing still another example of an internal voltage down converter. It is a block diagram for demonstrating operation | movement of a control signal generation circuit. It is a wave form diagram for demonstrating the control action at the time of the normal cycle of normal mode. It is a wave form diagram for demonstrating the control action at the time of the CAS before RAS refresh cycle of a normal mode. It is a wave form diagram for demonstrating the other example of the control action at the time of the CAS before RAS refresh cycle of a normal mode. It is a block diagram for demonstrating other control operation | movement of a control signal generation circuit. It is a wave form diagram for demonstrating the timing of a control signal. FIG. 10 is a block diagram for explaining still another control operation of the control signal generating circuit. It is a wave form diagram for demonstrating the timing of a control signal. It is a circuit diagram which shows the structure of a burn-in mode setting circuit. It is a circuit diagram which shows the other example of a burn-in mode setting circuit. It is a figure which shows the characteristic of an internal power supply voltage. It is a block diagram showing an example of a configuration of a burn-in mode setting signal generation circuit. It is a wave form diagram for demonstrating a burn-in mode set cycle. It is a wave form diagram for demonstrating a burn-in mode reset cycle. It is a block diagram which shows the other example of a structure of the burn-in mode setting signal generation circuit. It is a wave form diagram for demonstrating a burn-in mode set cycle. It is a wave form diagram for demonstrating a burn-in mode reset cycle. It is a block diagram which shows the structure of the semiconductor device by 2nd Example of this invention. It is a block diagram for demonstrating operation | movement of the activation signal generation circuit. It is a wave form diagram for demonstrating the timing of the activation signal at the time of the normal cycle of normal mode. FIG. 6 is a waveform diagram for explaining the timing of an activation signal during a CAS before RAS refresh cycle in a normal mode. It is a block diagram which shows the other example of an internal step-down circuit. FIG. 27 is a circuit diagram showing a detailed configuration of a part of the internal voltage down converting circuit of FIG. 26; It is a schematic diagram which shows the structure on the chip | tip of the semiconductor device which has an internal power supply line. It is a circuit diagram which shows the 1st example of a monitor circuit. It is a circuit diagram which shows the 2nd example of a monitor circuit. It is a circuit diagram which shows the 3rd example of a monitor circuit. It is a circuit diagram which shows the 4th example of a monitor circuit. It is a circuit diagram which shows the 5th example of a monitor circuit. It is a circuit diagram which shows the 6th example of a monitor circuit. It is a block diagram which shows the structure of the conventional MOS * DRAM which incorporated the internal step-down circuit. It is a block diagram which shows an example of a structure of an internal step-down circuit. It is a circuit diagram which shows the detailed structure of an internal step-down circuit. It is a figure which shows the voltage characteristic of an internal step-down circuit. FIG. 36 is a waveform diagram for explaining the operation of the internal voltage down converting circuit of FIG. It is a block diagram which shows the other example of an internal step-down circuit. FIG. 41 is a circuit diagram showing a detailed configuration of a part of the internal voltage down converting circuit of FIG. 40. It is a circuit diagram which shows the other example of a structure of an internal step-down circuit. FIG. 6 is a circuit diagram showing a configuration of a conventional internal voltage down converting circuit capable of a burn-in test. It is a circuit diagram which shows the detailed structure of a reference voltage generation circuit. FIG. 44 is a diagram illustrating external power supply voltage dependency of a reference voltage in the internal voltage down converter of FIG. 43. FIG. 44 is a diagram showing characteristics of an internal power supply voltage in the internal voltage down converting circuit of FIG. 43. It is a figure for demonstrating the problem of the conventional internal voltage-down converter. It is a schematic diagram which shows the structure on the chip | tip of the semiconductor device which does not have an internal power supply line.

Explanation of symbols

  1 internal voltage down converter, 3 DRAM, 4 peripheral circuit, 10 reference voltage generation circuit, 20 differential amplifier circuit, 30 driver circuit, 40 n-channel driver circuit, 45 reference voltage generation circuit, 50 burn-in mode setting circuit, 60 control signal generation Circuit, 70 burn-in mode setting signal generation circuit, 80 activation signal generation circuit, L1 external power supply line, L2 internal power supply line, P1 power supply terminal, P2 ground terminal, 1A, 1B internal step-down circuit, 60a activation signal generation circuit, 90 Level shift circuit, 100 amplifier circuit, 110 monitor circuit, pVcc power supply pad, pa pad, Vcc external power supply voltage, IVcc internal power supply voltage, ACT activation signal, φX control signal, BVD burn-in mode setting signal, ACT1, ACT2 activation signal , VR1, VR2 reference voltage.

  In the drawings, the same reference numerals denote the same or corresponding parts.

Claims (11)

The voltage of the internal power supply line is monitored in a semiconductor device comprising an internal power supply line to which an internal power supply voltage is applied, an external pin, and voltage transmission means for forming an electrical path between the external pin and the internal power supply line. A method,
Change the voltage applied to the external pin,
Detecting a standby current flowing between the external power supply voltage and a fixed voltage;
A method for monitoring a voltage of an internal power supply line, wherein the internal power supply voltage is measured based on a voltage of the external pin when the standby current starts to rise.   The method of monitoring a voltage of an internal power supply line according to claim 1, wherein the voltage applied to the external pin is increased. The voltage transfer means includes at least one diode-connected transistor having a known threshold voltage;
2. The voltage of the internal power supply line according to claim 1, wherein the voltage of the internal power supply line is calculated based on a voltage of the external pin when the standby current starts to rise and a known threshold voltage of the transistor. Method. The voltage transmission means includes n transistors.
When the internal power line voltage is VINT, the detected external pin voltage is VEXT, and the threshold voltage of the transistor is Vth, the internal power line voltage is VINT = VEXT−n · Vth. The method for monitoring the voltage of the internal power supply line according to claim 3, wherein the voltage is calculated based on the formula: Conduction when the voltage of the first and second external pins, the internal power supply line to which the internal power supply voltage is applied, and the voltage of the second external pin are lower than the internal power supply voltage by a predetermined threshold voltage A method of monitoring a voltage of the internal power supply line in a semiconductor device including a switching element to be in a state,
Applying a predetermined voltage to the first and second external pins;
Dropping the voltage applied to the second external pin;
A method for monitoring a voltage of an internal power supply line, wherein a current starts to flow between the first external pin and the second external pin. An internal power line,
An internal step-down circuit that receives an external power supply voltage and generates an internal power supply voltage to be supplied to the internal power supply line;
An external pin,
Voltage transmission means for forming an electrical path between the external pin and the internal power line,
In the test mode, a standby current flowing between the external power supply voltage and a fixed voltage is detected, and the voltage is applied to the external pin, based on the voltage of the external pin when the standby current starts to rise. A semiconductor device capable of measuring an internal power supply voltage.   The semiconductor device according to claim 6, wherein the voltage transmission means includes a plurality of diode-connected transistors provided between the external pin and the internal power supply line. An external pin,
An internal step-down circuit that receives an external power supply voltage and generates an internal power supply voltage lower than the external power supply voltage;
An internal power supply line to which the internal power supply voltage is supplied;
Voltage transmission means for the voltage of the internal power line,
The voltage transmission means is
Including at least one diode-connected transistor provided between the external pin and the internal power line and having a gate electrode and a drain electrode coupled to each other;
Each of the transistors has the same known threshold voltage as the transistors constituting the internal step-down circuit,
The semiconductor device, wherein the external pin and the drain electrode of the transistor are coupled, and the internal power supply line and the source electrode of the transistor are coupled . An internal step-down circuit that receives an external power supply voltage and generates an internal power supply voltage lower than the external power supply voltage;
An internal power supply line to which the internal power supply voltage is supplied;
Voltage transmission means for the voltage of the internal power line;
A single external pin used exclusively for measuring the voltage of the internal power line,
The voltage transmission means is
A switch element that conducts in response to the instruction signal;
The switch is provided between the external power supply voltage and the external pin through the switch element, the internal power supply line and the gate electrode are electrically coupled, and the voltage of the external pin is lower than the internal power supply voltage. Including a transistor connected to become conductive when the voltage is lowered by a threshold voltage,
A peripheral circuit having a predetermined function;
A semiconductor device further comprising: a signal generation circuit that generates the instruction signal based on a plurality of externally input control signals used in the peripheral circuit . First and second external pins;
An internal step-down circuit that receives an external power supply voltage and generates an internal power supply voltage lower than the external power supply voltage;
An internal power supply line to which the internal power supply voltage is supplied;
Voltage transmission means for the voltage of the internal power line,
The voltage transmission means is
A switch element that conducts in response to the instruction signal;
The internal power supply line and the gate electrode are coupled via the switch element, the source electrode and the drain electrode are coupled to the first and second external pins, respectively, and a predetermined voltage is applied to the first external pin. A transistor connected to become conductive when the second external pin is at a voltage lower than the internal power supply voltage by a predetermined threshold voltage when given,
A peripheral circuit having a predetermined function;
A semiconductor device further comprising: a signal generation circuit that generates the instruction signal based on a plurality of externally input control signals used in the peripheral circuit . An internal step-down circuit that receives an external power supply voltage and generates an internal power supply voltage lower than the external power supply voltage;
An internal power supply line to which the internal power supply voltage is supplied;
Voltage transmission means for the voltage of the internal power line ;
A single external pin used exclusively for measuring the voltage of the internal power line,
The voltage transmission means is
A switch element that conducts in response to the instruction signal;
A diode-connected transistor disposed between the internal power supply line and the external pin via the switch element;
The transistor has the same known threshold voltage as the transistor constituting the internal step-down circuit,
A peripheral circuit having a predetermined function;
Further Ru and a signal generation circuit for generating the instruction signal based on the plurality of control signals input from the outside to be used in the peripheral circuit, the semiconductor device.

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