JP3857343B2 - Camera device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a defect correction method and apparatus suitable for use in, for example, a solid-state imaging device using a single-plate CCD.
[0002]
[Prior art]
For example, in a solid-state imaging device using a single-plate CCD, for example, as shown in FIG. 10, magenta, green, yellow, and cyan color filters configured in a mosaic shape are provided corresponding to each pixel to generate a color video signal. To be formed.
[0003]
That is, in FIG. 10, for example, a red color difference signal (R−Y) and a luminance signal (Y) can be formed from a magenta and yellow addition signal and a green and cyan addition signal. For example, a blue color difference signal (BY) and a luminance signal (Y) can be formed from the yellow and green addition signals and the cyan and magenta addition signals.
[0004]
Therefore, in the solid-state imaging device of FIG. 10, as shown on the right side of the drawing, the signals of the pixels constituting the two adjacent scanning lines are added and extracted in each of the even and odd fields. .
[0005]
That is, for example, in the even field, the signals of the respective pixels of the scanning line provided with the yellow and cyan color filters and the scanning line provided with the magenta, green or green and magenta color filters on the upper side thereof are added and extracted. . In the odd field, the signals of the respective pixels of the scanning line provided with the yellow and cyan color filters and the scanning line provided with the green, magenta or magenta and green color filters on the lower side are added and extracted. .
[0006]
Thus, for example, in the even field, the red color difference signal (R−Y) and the luminance signal (Y) are extracted in the first scanning line, and the blue color difference signal (B−Y) and the luminance signal are extracted in the next scanning line. (Y) is taken out. In the odd field, the blue color difference signal (B−Y) and the luminance signal (Y) are extracted on the first scanning line, and the red color difference signal (R−Y) and the luminance signal (Y) on the next scanning line. And are taken out. As a result, an arbitrary color video signal can be formed.
[0007]
At the same time, the scanning lines added in the respective fields are switched up and down, so that the effective scanning line position is shifted up and down at intervals of one scanning line, and an interlaced video signal in two fields is obtained. It is something that can be done.
[0008]
[Problems to be solved by the invention]
By the way, in the solid-state imaging device as described above, a defect occurring in a pixel is an unavoidable problem. Among such defects, for example, a black spot defect in which the level of a signal extracted from a pixel is low is hardly noticeable on the screen. On the other hand, a white spot defect in which the level of a signal extracted from a pixel rises becomes very noticeable on the screen, and it is necessary to correct such a defect.
[0009]
Therefore, conventionally, a pixel having a defect is detected and stored in advance, and the defect is corrected by using a previous value hold or the like at the position of the pixel at the time of imaging, for example. In such defect correction, for example, the position of the defect detected at the time of manufacture of the solid-state imaging device is stored in a ROM or the like, and the ROM or the like is distributed together with the solid-state imaging device to correct the pixels stored in the ROM or the like. To be done.
[0010]
However, in such a method, for example, a defect detected at the time of manufacturing a solid-state imaging device can be corrected, but a defect generated thereafter cannot be corrected. Further, the defect of the white spot as described above is increased or decreased depending on the ambient temperature or the like. Therefore, the present inventor previously proposed an apparatus for automatically detecting and correcting such defects.
(See JP-A-6-319084, JP-A-6-315112, etc.)
[0011]
However, in such a defect correction, for example, when a defect (x) occurs at the position of the odd field ((1), (3)) as shown in FIG. In either case, this occurs in the first scanning line to be taken out. However, for example, when a defect (x) occurs in the even field position (2) or (3) as shown in FIG. 11B, this defect occurs in the first scanning line to be extracted in the even field. However, in the odd field, this occurs at the second scanning line to be taken out.
[0012]
That is, depending on the position where the defect occurs, the extracted scanning line may differ depending on the field. For this reason, in the conventional defect correction, it is necessary to store the positions of the defective pixels in each of the odd and even fields, and there is a possibility that a large amount of storage capacity for storing these positions may be required.
[0013]
This application has been made in view of the above points, and the problem to be solved is that in the conventional defect correction, the position of a pixel in which a defect occurs is stored in each of even and odd fields. Therefore, there is a possibility that a large amount of storage capacity for storing these positions may be required.
[0014]
[Means for Solving the Problems]
Therefore, in the present invention, the address on the field of the pixel where the defect is detected and the identification signal of the field are stored, and the defect is corrected using the stored address and the identification signal. Thus, the storage capacity for storing the position of the defect can be reduced as compared with the conventional case.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
That is, the camera device of the present invention includes a solid-state imaging device having at least one frame of pixels, and a defect detection correction circuit provided between the solid-state imaging device and the output terminal. A defect detection circuit to which a signal read from a pixel in a frame readout mode is supplied from a solid-state imaging device, and a memory for storing a read address on the field and a field identification signal when a defective pixel is detected in the defect detection circuit and means, in the field read mode by the defect detection and correction circuit, and performs correction of the defect by using the identification signal of the read address and field on the field.
[0016]
The present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing the overall configuration of an example of a CCD camera to which a defect correction method and apparatus for a solid-state imaging device according to the present invention is applied.
[0017]
In FIG. 1, for example, image light incident through a lens system (not shown) is converted into an electrical signal by a CCD (solid-state imaging device) 1. This signal is supplied to the A / D conversion circuit 3 through the sample hold (S / H) and AGC circuit 2, and the converted digital video signal is supplied to the defect detection correction circuit 4. Then, the signal corrected by the defect correction circuit 41 of the defect detection correction circuit 4 is supplied to the signal processing circuit 5, and the above-described color difference signal and luminance signal are formed and taken out to the output terminal 6.
[0018]
In addition, a microcomputer (μ-COM) 7 that controls the entire apparatus is provided. A signal from the microcomputer 7 is supplied to the timing generation circuit 8 to generate various timing signals for operation. Further, a signal from the timing generation circuit 8 is supplied to the CCD drive circuit 9 to generate a drive signal for the CCD 1. A signal from the timing generation circuit 8 is supplied to the synchronization generation circuit 10 to generate horizontal and vertical synchronization signals and the like.
[0019]
Further, these synchronization signals are supplied to the signal processing circuit 5 and also supplied to the defect detection and correction circuit 4. In the defect detection correction circuit 4, the pixel clock signal from the timing generation circuit 8 is supplied to the horizontal counter 42. The horizontal counter 42 is reset by a horizontal synchronization signal from the synchronization generation circuit 10. As a result, a horizontal address on the screen of the pixel of the digital video signal taken out from the CCD 1 is formed in the horizontal counter 42.
[0020]
Further, a horizontal synchronization signal from the synchronization generation circuit 10 is supplied to the vertical counter 43. Further, the vertical counter 43 is reset by a vertical synchronization signal from the synchronization generation circuit 10. As a result, a vertical address on the screen of the pixel of the digital video signal taken out from the CCD 1 is formed in the vertical counter 43.
[0021]
Further, the vertical synchronization signal from the synchronization generation circuit 10 is supplied to the field identification (ID) circuit 44. Further, the identification circuit 44 is supplied with a field identification signal from the synchronization generation circuit 10. As a result, a field identification signal of the digital video signal extracted from the CCD 1 is formed in the identification circuit 44. The formed horizontal address, vertical address and field identification signal are supplied to the memories 45, 46 and 47.
[0022]
On the other hand, the digital video signal from the A / D conversion circuit 3 is supplied to the defect detection circuit 48. When the defect detection circuit 48 detects a pixel defect, this defect detection signal is supplied to the memories 45, 46 and 47, and the horizontal address, vertical address and field identification signal supplied at that time are supplied. Remembered. Accordingly, in these memories 45, 46 and 47, addresses and field identification signals on the horizontal and vertical fields of the pixels in which defects are detected are stored.
[0023]
Further, the field identification signal from the above-described identification circuit 44 and the identification signal stored in the memory 47 are supplied to the logical operation circuit 49. In this logical operation circuit 49, for example, a logical signal is output when the identification signal stored in the memory 45 is an even field and the field identification signal from the identification circuit 44 is an odd field. This logical output signal is supplied to the “1” addition circuit 50, and “1” is added to the vertical address stored in the memory 46.
[0024]
The vertical address to which “1” is added from the adding circuit 50 and the vertical address from the vertical counter 43 are supplied to the coincidence detecting circuit 51. Further, the horizontal address from the horizontal counter 42 and the address stored in the memory 45 are supplied to the coincidence detection circuit 52. These coincidence detection signals are supplied to the AND circuit 53, and an AND output is supplied to the defect correction circuit 41 when the horizontal and vertical addresses coincide with each other. Further, this AND output is also supplied to the signal processing circuit 5.
[0025]
Therefore, in this method and apparatus, the address on the field of the pixel where the defect is detected and the identification signal of the field are stored. Further, for example, “1” is added to the vertical address stored when the stored identification signal is an even (other) field and the field identification signal of the video signal is an odd (one) field. Then, using this calculated vertical address, it is possible to correct defects in both odd and even fields.
[0026]
Thus, conventionally, it is necessary to store the positions of defective pixels for each of the odd and even fields, and there is a possibility that a large amount of storage capacity for storing these positions may be required. According to the present invention, the address on the field of the pixel in which the defect is detected and the identification signal of the field are stored, and the position in each field is obtained by calculation. Therefore, the storage capacity for storing the position is reduced by half, For example, the circuit scale can be reduced to about 3/4.
[0027]
2 and 3 show basic operation algorithms for performing the above-described processing. This operation algorithm is based on the operation algorithm disclosed in the above-mentioned JP-A-6-319084.
[0028]
First, FIG. 2 shows an algorithm for processing when a defect is detected. In FIG. 2, when the detection operation is started in step [1], the iris 11 provided on the front surface of the imaging surface of the CCD 1, for example, is closed in step [2]. Further, in step [3], the timing generation circuit 8 (TG) is switched to the frame reading mode, and in step [4], the CCD 1 is driven by normal scan × 1.
[0029]
Further, in step [5], the readout pulse is stopped and the accumulation operation of the CCD 1 is performed. After a predetermined accumulation operation, the first field is read in step [6] and the second field is read in step [7]. Further, the defect of the pixel in the signal of each field read in step [8] is detected, and the level of the defect detected in step [9] is held.
[0030]
In step [10], the level of the held defect is compared. In step [11], the level is determined. In step [12], when this level is large, a field identification signal is stored. Further, in step [13], A data including the above-described horizontal address, vertical address, etc. at the position of the defect is stored, and level data is stored in step [14].
[0031]
In step [15], the level of the next defect is compared. In step [16], the level is determined. In step [17], if the level is high, a field identification signal is stored. In step [18], B data comprising the above-mentioned horizontal address, vertical address, etc. at the position of the defect is stored, and level data is stored in step [19]. Further, the same operation is performed for the C and D data, and the detection operation is terminated in step [20].
[0032]
FIG. 3 shows an algorithm for processing at the time of defect correction. In FIG. 3, the timing generation circuit 8 is switched to the field read mode at step [21], and the correction operation is started at step [22]. In step [23], the above-mentioned A, B, C, and D data are read out, and in step [24], the address of the defect is detected. Further, the vertical address is converted in step [25], a correction pulse is generated in step [26], and defect correction is performed in step [27].
[0033]
In this way, defect detection, defect address storage, and defect correction processing are performed. 2 and 3, the field identification signal storage shown in steps [12] and [17] and the vertical address conversion processing shown in step [25] are newly performed. It is a part performed in the invention.
[0034]
4 and 5 show the CCD drive timing and CCD output signal when a defect is detected. 4 shows the case where the accumulation period is 6 fields, and FIG. 5 shows the case where the accumulation period is n fields. This is a case where the CCD has a larger number of pixels than the number of pixels of the original effective screen frame in order to perform camera shake correction and the like.
[0035]
Therefore, in FIGS. 4 and 5, the signal MRST in each figure indicates the start-up state of the apparatus, and the signal SRT indicates the period during which the defect detection operation is performed. The signal FLD represents a field identification signal, the signal VD1 represents a vertical synchronization signal, and the signal VD0 represents a vertical synchronization signal provided in units of two fields in order to read out all the pixels larger than the above.
[0036]
4 and 5, the first and second field read pulses XSG1 and XSG2 are formed as shown. As a result, a 6-field accumulation operation is performed in FIG. 4, an n-field accumulation operation is performed in FIG. 5, and an output (out) is extracted from the CCD as illustrated. As a result, the signals of all the pixels in the first and second fields are extracted during the illustrated detection field. The signal END in each figure indicates the end of the defect detection operation period.
[0037]
FIGS. 6 and 7 show timings before and after the vertical blanking period of frame reading at the time of detection by the NTSC method, for example. FIG. 6 shows an odd field, and FIG. 7 shows an even field. 6 and 7, the signal FLD in each figure represents a field identification signal, the signal BLK / VD represents a vertical synchronization signal and a blanking period, and the signal HD represents a horizontal synchronization signal.
[0038]
In FIGS. 6 and 7, the read pulse SG is formed as shown in the figure, so that the signal ID and the signal VCLK are formed as shown in the figure, and output (out) from the CCD as shown in the figure. Is taken out. In the figure, the portion with a black belt indicates the optical black portion on the CCD. The signal PBLK is formed as shown in the figure, and the count (VCNT) of the vertical counter is performed as shown in the figure.
[0039]
Therefore, in the above-described apparatus, the defect detection / correction circuit 4 is specifically configured as shown in FIG. That is, in FIG. 8, for example, a digital video signal (inspection signal) from the above-described A / D conversion circuit 3 is supplied to a clamp and blanking (CLP / BLK) circuit 81, and the signal from this circuit 81 is a detection comparator 82. To be supplied. The comparison output (defect detection pulse) is supplied to the data storage control unit 83, and the above-described inspection signal is also supplied to the data storage control unit 83.
[0040]
The signal XV1 is supplied to the vertical counter 84, and the read pulse SG is supplied to the reset terminal. Further, for example, the master clock signal (CK) from the timing generation circuit 8 described above is supplied to the horizontal counter 85. These count values are supplied to the data storage control unit 83.
[0041]
Therefore, the data storage control unit 83 stores the defect level data of the inspection signal and the count values of the counters 84 and 85 when the above-described detection pulse is supplied. The stored count value and the count values of the counters 84 and 85 are supplied to the coincidence detection circuits 86 and 87. Further, a detection signal when these count values coincide is output.
[0042]
Further, FIG. 9 is a block diagram showing a specific example of the data storage control unit 83. In FIG. 9, the above-described defect level data is supplied to the level data storage banks A to D through the selector, and the above-described defect detection pulse is supplied to the level data storage banks A to D, and the detection pulse is supplied. Defective level data is stored in the level data storage banks A to D.
[0043]
At the same time, the supplied defect level data is supplied to the comparator and compared with the data stored in the level data storage banks A to D at the timing of the defect detection pulse. Control is performed so that the defect level data is always stored in the level data storage banks A to D in order from the largest. That is, the selector is controlled so that the data in the level data storage banks A to D are sequentially replaced.
[0044]
Further, the count values of the counters 84 and 85 are supplied to the vertical address data storage banks A to D and the horizontal address data storage banks A to D, respectively. The field identification (ID) signal described above is supplied to the field identification data storage banks A to D. Further, these storage banks A to D are connected in the same manner as the above-described level data storage banks A to D through selectors.
[0045]
By controlling these selectors at the same time, the storage data in the storage banks A to D for these vertical address, horizontal address and field identification is the maximum defect level data as in the level data storage banks A to D. The replacement control is performed so that the items are stored in order.
[0046]
Further, “1” is added to the data stored in these vertical address data storage banks A to D according to the data stored in the field identification data storage banks A to D by the incrementer, and the added data is detected as coincidence. This is supplied to the circuit 86. Data stored in the horizontal address data storage banks A to D is supplied to the coincidence detection circuit 87. When these data coincide with each other, a correction pulse output is taken out.
[0047]
Thus, according to the above-described defect correction method and apparatus for a solid-state imaging device, signals of pixels adjacent to each other in the vertical direction are added and output, and added in alternating fields. For a solid-state image pickup device that obtains an interlaced video signal by switching adjacent pixels up and down, a defect occurring in the pixel is detected, and an address on the field of the pixel where the defect is detected and an identification signal of an alternating field are stored. By correcting the defect using the stored address on the field and the field identification signal, the storage capacity for storing the position of the defect can be reduced as compared with the conventional case.
[0048]
【The invention's effect】
According to the present invention, the address on the field of the pixel where the defect is detected and the identification signal of the field are stored. Further, for example, “1” is added to the vertical address stored when the stored identification signal is an even (other) field and the field identification signal of the video signal is an odd (one) field. Using this calculated vertical address, it becomes possible to correct defects in both odd and even fields.
[0049]
Thus, conventionally, it is necessary to store the positions of defective pixels for each of the odd and even fields, and there is a possibility that a large amount of storage capacity for storing these positions may be required. According to the present invention, the address on the field of the pixel in which the defect is detected and the identification signal of the field are stored, and the position in each field is obtained by calculation. Therefore, the storage capacity for storing the position is reduced by half, For example, the circuit scale can be reduced to about 3/4.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an example of a defect correction apparatus for a solid-state imaging device to which the present invention is applied.
FIG. 2 is a diagram for explaining the operation;
FIG. 3 is a diagram for explaining the operation;
FIG. 4 is a diagram for explaining the operation;
FIG. 5 is a diagram for explaining the operation;
FIG. 6 is a diagram for explaining the operation;
FIG. 7 is a diagram for explaining the operation;
FIG. 8 is a configuration diagram of a specific example of a main part of a defect correction apparatus for a solid-state imaging device to which the present invention is applied.
FIG. 9 is a configuration diagram of a specific example of a further main part of a defect correction apparatus for a solid-state imaging device to which the present invention is applied.
FIG. 10 is a diagram for explaining a solid-state imaging device to which the present invention is applied.
FIG. 11 is a diagram for explaining the operation;
[Explanation of symbols]
1 CCD (solid-state imaging device)
2 Sample hold (S / H) and AGC circuit 3 A / D conversion circuit 4 Defect detection correction circuit 41 Defect correction circuit 42 Horizontal counter 43 Vertical counter 44 Field identification (ID) circuits 45, 46, 47 Memory 48 Defect detection circuit 49 Logical operation circuit 50 “1” addition circuit 51, 52 coincidence detection circuit 53 AND circuit 5 signal processing circuit 6 output terminal 7 microcomputer (μ-COM)
8 Timing generation circuit 9 CCD drive circuit 10 Synchronization generation circuit 11 Iris

Claims (2)

A solid-state imaging device having a number of pixels of at least one frame;
A defect detection correction circuit provided between the solid-state imaging device and the output terminal;
The defect detection correction circuit is
A defect detection circuit to which a signal read from the pixel is supplied in a frame read mode from the solid-state imaging device;
And a storage means for storing the read address and field identification signal on the field when the defective pixel is detected in the defect detection circuit,
In the defect detection and correction circuit by the field read mode, the camera apparatus, characterized in that to correct the defect by using the identification signal of the read address and the field on the field. When the pixel field where the defect is detected is one, the stored address is output in both fields,
Means for outputting the address stored in the other field and adding 1 to the vertical address of the address stored in the other field when the field of the pixel in which the defect is detected is the other; Have
The camera device according to claim 1.

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