JP3696069B2 - Method and apparatus for detecting defective pixels of solid-state image sensor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a defective pixel detection method and apparatus for a solid-state image sensor.
[0002]
[Prior art]
Among pixels constituting a CCD (solid-state imaging device), defective pixels that do not generate an electrical signal of a predetermined signal level may occur in the manufacturing stage. This defective pixel includes a so-called white spot defective pixel that outputs an electrical signal having a magnitude greater than or equal to a predetermined magnitude with respect to incident light, and a black spot defective pixel that outputs only an electrical signal not greater than a predetermined magnitude. In particular, if there is even one defective pixel with a white spot, it is conspicuous and the image quality is remarkably lowered, so that it is necessary to perform pixel defect correction.
[0003]
As a pixel defect correction method, a method in which a position of a defective pixel is detected and stored, and a signal of a defective pixel is corrected using a signal of a pixel adjacent to the defective pixel. For pixel defects occurring at the time of CCD manufacture, the position is stored in a nonvolatile external memory, and pixel defect correction is performed based on the position information. Since defective pixels may occur due to changes over time, it is necessary to detect and correct defective pixels even after manufacturing the CCD.
[0004]
FIG. 1 shows a configuration of a conventional CCD signal processing circuit having a pixel defect detection / correction function.
[0005]
The output signal of the CCD 1 is processed by a CDS (correlated double sampling circuit) 2 and an AGC (automatic gain control circuit) 3 and then converted into a digital signal by an A / D conversion circuit 4. The output data of the A / D conversion circuit 4 is sent to the pixel defect detection / correction circuit 10.
[0006]
The pixel defect detection / correction circuit 10 performs pixel defect correction on input data based on information in the external memory 7. The output data of the pixel defect detection / correction circuit 10 is sent to the camera signal processing circuit 5 for normal camera signal processing. The timing control circuit 6 controls the timing of each unit.
[0007]
The pixel defect detection / correction circuit 10 includes a defective pixel detection circuit 11, a pixel defect correction circuit 12, a selection circuit 13, an address comparison circuit 14, a horizontal address counter (H address counter) 15, a vertical address counter (V address counter) 16, and A plurality of defective pixel address memories 17 are provided.
[0008]
FIG. 2 shows the configuration of the defective pixel detection circuit 11. In this example, a circuit for detecting defective pixels of white spots is shown.
[0009]
The defective pixel detection circuit 11 detects a defective pixel in the defective pixel detection mode. The defective pixel detection circuit 11 includes two delay circuits 21 and 22 and a determination circuit 23. Each of the delay circuits 21 and 22 delays and outputs the input data by a time equal to the time required to transmit one pixel.
[0010]
The determination circuit 23 receives pixel data D1, D2, and D3 of three adjacent pixels. If the center pixel of the three pixels is the target pixel, the determination circuit 23 determines the absolute value (| D2-D1 |, difference between the pixel data D2 of the target pixel and the pixel data D1 and D3 of the pixels before and after the target pixel. | D3−D2 |) are obtained, and when both absolute values are larger than the predetermined value Th, the pixel of interest is regarded as a white point defective pixel, and the vertical address (V address) and horizontal address ( H address) is stored in the defective pixel address memory 17 as defective pixel address data. The defective pixel address data stored in the defective pixel address memory 17 is stored in the external memory 7.
[0011]
Conventionally, defective pixel address data detected in the odd field and defective pixel address data detected in the even field are distinguished and stored in the external memory 7. In the normal mode, when the odd field is input, the defective pixel address data detected in the odd field is set in the defective pixel address memory 17, and when the even field is input, the defect detected in the even field. Pixel address data is set in the defective pixel address memory 17.
[0012]
FIG. 3 shows the configuration of the pixel defect correction circuit 12.
[0013]
The pixel defect correction circuit 12 includes two delay circuits 31 and 32 and an addition averaging circuit 33. Each of the delay circuits 31 and 32 delays and outputs the input data by a time equal to the time required to transmit one pixel.
[0014]
Among the pixel data D1, D2, and D3 of the three adjacent pixels, the pixel data D1 and D3 of the pixels on both sides are input to the addition averaging circuit 33. When the center pixel of the three pixels is a defective pixel, the corrected pixel data D2 ′ of the center pixel is the average value {(D1 + D3) / 2 of the pixel data D1 and D3 of the previous and subsequent pixels. }.
[0015]
The selection circuit 13 (see FIG. 1) provided in the subsequent stage of the pixel defect correction circuit 12 has a defective pixel in which the horizontal address of the horizontal address counter 15 and the vertical address of the vertical address counter 16 are stored in the defective pixel address memory 17. When the address matches, the correction value corresponding to the defective pixel address calculated by the defect correction circuit 12 is selected and output.
[0016]
[Problems to be solved by the invention]
In the conventional example, it is difficult to accurately detect and correct white point defective pixels generated after manufacturing. In particular, it has been difficult to accurately detect pixel defects that can be recognized only when the AGC gain is large, in distinction from noise.
[0017]
Conventionally, since the defective pixel address is held in the external memory 7 separately for the odd field and the even field, a large capacity memory is required as the external memory 7.
[0018]
An object of the present invention is to provide a method and apparatus for detecting defective pixels of a solid-state imaging device capable of accurately detecting defective pixels of white spots.
[0019]
It is an object of the present invention to provide a defective pixel detection method and apparatus for a solid-state imaging device that can reduce the capacity of an external memory that stores position data of defective pixels.
[0021]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a method for detecting a defective pixel of a solid-state imaging device, by comparing an average value of pixel data around a target pixel with pixel data of the target pixel to determine whether the target pixel is a defective pixel. A defective pixel detection method for a solid-state imaging device, comprising: starting a defective pixel determination process for one set corresponding to a predetermined number of fields, and detecting pixels determined to be defective pixels for each field The address is stored in the defective pixel address memory, and every time defective pixel determination for one field is completed, the defective pixel address stored in the defective pixel address memory is read, and for each pixel determined to be a defective pixel, When an operation such as calculating the number of times a pixel is determined to be a defective pixel is repeated and one set of defective pixel determination processing is completed, A defective pixel in which the number of pixels determined to be a prime pixel is detected as a defective pixel and the number of pixels determined to be a defective pixel in the first set can be stored in the defective pixel address memory When the number of addresses is larger than the number of addresses, the defective pixel address is resumed from the defective defective pixel address stored in the defective pixel address memory for each field of the first set. The defective pixel determination process of the second set is performed as the position, and the number of pixels determined to be defective pixels after the second set is also based on the number of defective pixel addresses that can be stored in the defective pixel address memory. If there are too many, the next set of defective pixel determination processing is performed in the same manner.
[0024]
According to a second aspect of the present invention, there is provided a defective pixel device for a solid-state image sensor, comparing an average value of pixel data around a target pixel of the solid-state image sensor with the pixel data of the target pixel by comparing the pixel data of the target pixel. Includes defective pixel detection means for determining whether or not is a defective pixel, and the defective pixel detection means starts a defective pixel determination process for one set corresponding to a predetermined number of fields, and is defective for each field. The pixel address determined to be stored in the defective pixel address memory and the defective pixel address stored in the defective pixel address memory is read each time the defective pixel determination for one field is completed, and the pixel determined to be a defective pixel For each, the operation of calculating the number of times that the pixel is determined to be a defective pixel is repeated, and a defective pixel determination process for one set is performed. When the number of pixels determined to be defective pixels is not less than a predetermined value, the number of pixels determined to be defective pixels in the first set is determined as a defective pixel address. If there are more defective pixel addresses than can be stored in the memory, the smallest address in the first set among the largest defective pixel addresses stored in the defective pixel address memory for each field of the first set. As a defective pixel determination restart position, the second set of defective pixel determination processing is performed, and the number of pixels determined to be defective pixels can be stored in the defective pixel address memory after the second set. If there are more defective pixel addresses than the number of defective pixel addresses, the next set of defective pixel determination processing is performed in the same manner.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to FIGS.
[0027]
[1] Description of overall configuration [0028]
FIG. 4 shows a configuration of a CCD signal processing circuit having a pixel defect detection / correction function.
[0029]
In FIG. 4, the same components as those in FIG.
[0030]
As shown in FIG. 5, the CCD 1 includes a color filter array. In this example, in the odd-numbered rows, cyan (Cy) color filters and yellow (Ye) color filters are alternately arranged in the horizontal direction. In even-numbered rows, magenta (Mg) color filters and green (G) color filters are alternately arranged in the horizontal direction.
[0031]
A method of reading a signal from the CCD 1 having such a color filter array will be described.
[0032]
In the odd (ODD) field, the pixel values of the odd-numbered rows in the vertical direction and the pixel values of the even-numbered rows below the sum are output. That is, for the nth scanning line, D1 (= Cy + Mg), D2 (= Ye + G), D1, D2,... Signals are output in the order of….
[0033]
In the even (EVEN) field, the pixel value of the even-numbered row in the vertical direction and the pixel value of the odd-numbered row below the sum are output. That is, in the m-th scanning line, D1 (= Mg + Cy), D2 (= G + Ye), D1, D2,... Signals are output in the order of….
[0034]
Signals D1 to D4 output from the CCD 1 are processed by a CDS (correlated double sampling circuit) 2 and an AGC (automatic gain control circuit) 3 and then converted to a digital signal by an A / D conversion circuit 4. The output data of the A / D conversion circuit 4 is sent to the pixel defect detection / correction circuit 50.
[0035]
The pixel defect detection / correction circuit 50 performs pixel defect correction on the input data. The output data of the pixel defect detection / correction circuit 50 is sent to the camera signal processing circuit 5 for normal camera signal processing. The timing control circuit 6 controls the timing of each unit.
[0036]
The pixel defect detection / correction circuit 50 includes a defective pixel detection circuit 51, a pixel defect correction circuit 52, a selection circuit 53, an address comparison circuit 54, a horizontal address counter (H address counter) 55, a vertical address counter (V address counter) 56, A plurality of defective pixel address memories 57 and a plurality of detected defective pixel address memories 58 are provided.
[0037]
The defective pixel address memory 57 and the detected defective pixel address memory 58 are connected to the CPU 40. The CPU 40 includes an external memory 7.
[0038]
[2] Description of defective pixel detection circuit
FIG. 6 shows the configuration of the defective pixel detection circuit 51. In this example, a circuit for detecting defective pixels of white spots is shown.
[0040]
The detection of a pixel defect of a white spot is performed in a state where a black screen is imaged or in a state where an image is captured while a lens cap is fitted to a CCD camera.
[0041]
A circuit for detecting defective pixels of white spots includes two line memories 61 and 62, six delay circuits 63, 64, 65, 66, 67 and 68, and a determination circuit 69. Each of the line memories 61 and 62 delays and outputs the input data by a time equal to the time required to transmit one horizontal line. Each of the delay circuits 63 to 68 delays and outputs the input data by a time equal to the time required for transmitting one pixel.
[0042]
Therefore, as shown in FIG. 7, the determination circuit 69 receives pixel data D1 to D9 of each pixel in a 3 × 3 pixel block. Assuming that the center pixel of the nine pixels is the target pixel, the determination circuit 23 determines whether or not the condition of the following expression (1) is satisfied.
[0043]
{(D1 + D2 + D3 + D4 + D6 + D7 + D8 + D9) / 8} + Th <D5 (1)
[0044]
That is, the determination circuit 69 determines whether or not a condition that the pixel data D5 of the target pixel is larger than the value obtained by adding the predetermined value Th to the average value of the pixel data of the surrounding eight pixels. When this condition is satisfied, the determination circuit 69 determines that the target pixel is a white point defective pixel candidate, and detects a vertical address (V address) and a horizontal address (H address) for the target pixel. Stored in the pixel address memory 58. When such a determination is made, the defective pixel can be accurately detected even if there is noise around the defective pixel.
[0045]
[2-1] Description of Defective Pixel Detection Process (Part 1)
The defective pixel detection circuit 51 repeats such defective pixel detection processing over a plurality of fields. When the defective pixel detection process for the first field is completed, the CPU 40 reads the contents of the detected defective pixel address memory 58 and stores them in an internal memory (not shown) as a defective pixel address.
[0047]
Thereafter, every time defective pixel detection processing for one field is completed, the CPU 40 reads the content of the detected defective pixel address memory 58 and compares it with what has already been stored as a defective pixel address. If it is a new defective pixel address, the defective pixel address is stored in the internal memory. If the defective pixel address is the same as the defective pixel address already stored, the number of detections is stored in association with the defective pixel address already stored in the internal memory.
[0048]
In this way, when the defective pixel address storage and the detection count process corresponding to the predetermined number of fields by the CPU 40 are completed, the CPU 40 detects only defective pixel addresses whose detection count is equal to or greater than a predetermined count. The pixel is determined to be a pixel, and the defective pixel address determined to be a defective pixel is stored in the external memory 7.
[0049]
[2-2] Description of Defective Pixel Detection Process (Part 2)
It is also conceivable that the number of defective pixel candidates detected by the defective pixel detection circuit 51 in one field is greater than the maximum number k of defective pixel addresses stored in the detected defective pixel address memory 58. Therefore, in such a case, defective pixel detection is performed as follows.
[0051]
In the defective pixel detection process for the first field by the defective pixel detection circuit 51, if defective pixel candidates of the defective pixel address storage maximum number k or more in the detected defective pixel address memory 58 are detected, the detected defective pixel address memory 58 stores As shown in FIG. 8A, the defective pixel address corresponding to the first to kth detected defective pixel candidates is stored. In the example of FIG. 8, k = 8. The defective pixel address corresponding to the defective pixel candidate detected at the (k + 1) th transition is not stored in the detected defective pixel address memory 58.
[0052]
Assume that the defective pixel detection processing for N fields by the defective pixel detection circuit 51 and the accompanying defective pixel address storage and detection count processing by the CPU 40 are completed. Here, N = 4, and in the second field, the third field, and the fourth field, as shown in FIGS. 8B, 8C, and 8D, in the detected defective pixel address memory 58. Assume that a defective pixel address corresponding to the 1st to kth defective pixel candidates detected by the defective pixel detection circuit 51 is stored. 8A to 8D, the numbers in the squares indicating the defective pixels indicate the number of times that the pixels are detected as defective pixels.
[0053]
Similarly to the above, the CPU 40 performs the defective pixel address storage and the detection number counting process for each field, and when the N defective pixel address storage and the detection number counting processes are completed, the detection number is equal to or greater than a predetermined number of times. Only the defective pixel address is determined as the defective pixel, and the defective pixel address determined as the defective pixel is stored in the external memory 7.
[0054]
Thereafter, the detection start position is changed, and defective pixel detection processing for N fields is started. Since the 1st to kth defective pixel candidates detected in each field do not always match, as shown in FIGS. 8A to 8D, they are detected kth in each field. Usually, the addresses of the defective pixel candidates do not match.
[0055]
Therefore, as shown in FIG. 8E, in the previous defective pixel detection process for N fields, the defect address is determined using the smallest address among the kth defective pixel candidates detected in each field as the detection start position. The pixel detection process is started.
[0056]
Also in the defective pixel detection process for the second N fields, if defective pixel candidates of the defective pixel address storage maximum number k or more in the detected defective pixel address memory 58 are detected, the third N fields are similarly processed. The defective pixel detection process is performed.
[0057]
Then, in the defective pixel detection process for N fields, when the number of detected defective pixel candidates is less than the maximum defective pixel address storage number k in the detected defective pixel address memory 58, the defective pixel detection process ends. To do.
[0058]
According to the above method, even if the capacity of the detected defective pixel address memory 58 is small, defective pixels on the entire screen can be detected.
[0059]
[2-3] Description of improvement of defective pixel address data
By the way, as shown in FIG. 9, when the defective pixel of the CCD 1 has the same address in the odd (ODD) field and the even (EVEN) field depending on the position of the defective pixel (FIG. 9A), There is a case where the vertical address is shifted by one line between the (ODD) field and the even number (EVEN) field (FIG. 9B).
[0061]
Therefore, it is preferable to distinguish between the two states by using a 1-bit state flag F. That is, the defective pixel address data is constituted by the horizontal and vertical addresses in the odd field and the status flag F, and is stored in the external memory 7. Of course, the defective pixel address data may be configured by the horizontal and vertical addresses in the even field and the status flag F and stored in the external memory 7.
[0062]
In this way, as shown in FIG. 9B, even if the same defective pixel, even if the vertical address is shifted by one line between the odd field and the even field, only one defective pixel address data is externally transmitted. It can be stored in the memory 7. For this reason, the capacity of the external memory 7 can be reduced.
[0063]
In such a case, the CPU 40 obtains a defective pixel address (defective pixel address in the odd field, defective pixel address in the even field) corresponding to the input field based on the defective pixel address data in the external memory 7. The obtained defective pixel address is set in the defective pixel address memory 57 for each field.
[0064]
[2-4] Description of defective pixel detection start condition
A white point defective pixel is accurately detected when a black image is captured on the entire screen or when a cap is attached to a CCD camera and the gain of the AGC circuit 3 is not large. I can't. Therefore, if the detection condition is satisfied at the start of the defective pixel detection so that the defective pixel detection of the white spot is not performed under such detection conditions, the detection condition is satisfied. It is preferable to start defect pixel detection only.
[0066]
That is, only when the pixel defect detection command is input when the gain of the AGC circuit 3 is maximum and the average luminance level of all the areas divided into several areas in the screen is equal to or lower than a predetermined level, Start detection.
[0067]
[3] Description of pixel defect correction circuit
FIG. 10 shows the configuration of the pixel defect correction circuit 52.
[0069]
The pixel defect correction circuit 52 includes four delay circuits 71, 72, 73, 74, an addition averaging circuit 75, and a weighted addition circuit 76. Each of the delay circuits 71 to 74 delays and outputs the input data by a time equal to the time required to transmit one pixel.
[0070]
Therefore, pixel data D1 to D5 of five adjacent pixels can be obtained by the latest input data D5 and the four delay circuits 71 to 74. Assume that the center pixel among the five adjacent pixels is a defective pixel.
[0071]
The pixel data D1 and D5 of the pixels at both ends among the pixel data D1 to D5 of the five adjacent pixels are input to the addition averaging circuit 75, and the addition average value {(D1 + D5) / 2} is calculated. The weighted addition circuit 76 receives the output of the addition averaging circuit 75 and the pixel data D3 of the center pixel among the five pixels, and weights and adds them.
[0072]
The weighted addition circuit 76 calculates the following equation (2), assuming that K is a coefficient in the range of 0 ≦ K ≦ 1, and the corrected data of the image data D3 of the defective pixel is D3 ′. The image data D3 is corrected.
[0073]
D3 '= K. {(D1 + D5) / 2} + (1-K) .D3 (2)
[0074]
In other words, in order to prevent defective pixels from becoming noticeable even when colors are reproduced, the defective pixels are corrected using pixel data D1 and D5 of the same color filter as the defective pixels that exist before and after the defective pixels. In addition, although the white point defective pixel has a higher level than the normal pixel, it also includes a video signal. Therefore, by weighted addition of the pixel data D3 of the defective pixel and the addition average value of D1 and D5, The pixel information is also reproduced in the video while making the white spot noise inconspicuous.
[0075]
The selection circuit 53 (see FIG. 4) provided in the subsequent stage of the pixel defect correction circuit 52 has a defective pixel in which the horizontal address of the horizontal address counter 55 and the vertical address of the vertical address counter 56 are stored in the defective pixel address memory 57. When the address matches, the correction value corresponding to the defective pixel address calculated by the pixel defect correction circuit 52 is selected and output.
[0076]
【The invention's effect】
According to the present invention, it becomes possible to accurately detect defective pixels of white spots.
[0077]
In addition, according to the present invention, it is possible to reduce the capacity of the external memory that stores the position data of defective pixels.
[0078]
Further, according to the present invention, the pixel information detected by the defective pixel can be reproduced on the video while making the white point noise of the defective pixel of the white point inconspicuous.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a conventional CCD signal processing circuit having a pixel defect detection / correction function.
2 is a block diagram showing a configuration of the defective pixel detection circuit 11 of FIG.
3 is a block diagram showing a configuration of a pixel defect correction circuit 12 of FIG.
FIG. 4 is a block diagram showing a configuration of a CCD signal processing circuit having a pixel defect detection / correction function.
FIG. 5 is a schematic diagram showing a part of a color filter array provided in the CCD 1;
6 is a block diagram showing a configuration of the defective pixel detection circuit 51 of FIG. 4. FIG.
7 is a schematic diagram showing image data for 3 × 3 pixels input to a determination circuit 69 in FIG. 6;
FIG. 8 is a schematic diagram for explaining defective pixel detection processing;
FIG. 9 is a schematic diagram showing that an odd field and an even field may have the same address and a vertical address may be shifted by one line depending on the position of a defective pixel.
10 is a block diagram showing a configuration of a pixel defect correction circuit 52 of FIG.
[Explanation of symbols]
7 External memory 40 CPU
50 pixel defect detection / correction circuit 51 defective pixel detection circuit 52 pixel defect correction circuit 53 selection circuit 54 address comparison circuit 55 horizontal address counter 56 vertical address counter 57 defective pixel address memory 58 detected defective pixel address memory

Claims (2)

A defective pixel detection method for a solid-state imaging device, characterized by determining whether or not a target pixel is a defective pixel by comparing an average value of pixel data around the target pixel and pixel data of the target pixel There,
A set of defective pixel determination processing corresponding to a predetermined number of fields is started, the addresses of pixels determined to be defective pixels for each field are stored in the defective pixel address memory, and defective pixel determination for one field is completed. Each time, the defective pixel address stored in the defective pixel address memory is read, and the operation of calculating the number of times that the pixel is determined to be defective is repeated for each pixel determined to be defective. When a defective pixel determination process for one set is completed, a pixel whose number of times determined to be a defective pixel is a predetermined value or more is detected as a defective pixel,
In the first set, when the number of pixels determined to be defective pixels is larger than the number of defective pixel addresses that can be stored in the defective pixel address memory, the defective pixel address memory for each field of the first set. In the second set of defective pixel determination processing, the second set of defective pixel determination processing is performed using the minimum address in the first set as the defective pixel determination restart position.
In the second set and thereafter, if the number of pixels determined to be defective pixels is greater than the number of defective pixel addresses that can be stored in the defective pixel address memory, the next set of defective pixels is determined in the same manner. A defective pixel detection method for a solid-state imaging device, characterized by performing processing. Defective pixel detection means for determining whether or not a pixel of interest is a defective pixel by comparing a solid-state imaging device, an average value of pixel data around the pixel of interest of the solid-state imaging device, and pixel data of the pixel of interest With
The defective pixel detection means starts a defective pixel determination process for one set corresponding to a predetermined number of fields, stores an address of a pixel determined to be a defective pixel for each field in a defective pixel address memory, Each time defective pixel determination for a field is completed, the defective pixel address stored in the defective pixel address memory is read, and for each pixel determined to be a defective pixel, the number of times that the pixel is determined to be a defective pixel When a defective pixel determination process for one set is completed, a pixel whose number of times determined to be a defective pixel is a predetermined value or more is detected as a defective pixel.
In the first set, when the number of pixels determined to be defective pixels is larger than the number of defective pixel addresses that can be stored in the defective pixel address memory, the defective pixel address memory for each field of the first set. In the second set of defective pixel determination processing, the second set of defective pixel determination processing is performed using the minimum address in the first set as the defective pixel determination restart position.
In the second set and thereafter, if the number of pixels determined to be defective pixels is larger than the number of defective pixel addresses that can be stored in the defective pixel address memory, the next set of defective pixels is determined in the same manner. A defective pixel detection apparatus for a solid-state imaging device, characterized by performing processing.

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