JP3854517B2 - Membrane capacitor and manufacturing method thereof - Google Patents

Membrane capacitor and manufacturing method thereof Download PDF

Info

Publication number
JP3854517B2
JP3854517B2 JP2002029100A JP2002029100A JP3854517B2 JP 3854517 B2 JP3854517 B2 JP 3854517B2 JP 2002029100 A JP2002029100 A JP 2002029100A JP 2002029100 A JP2002029100 A JP 2002029100A JP 3854517 B2 JP3854517 B2 JP 3854517B2
Authority
JP
Japan
Prior art keywords
conductor layer
capacitor
layer
hole
dielectric layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2002029100A
Other languages
Japanese (ja)
Other versions
JP2003234236A (en
Inventor
良一 豊島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Mektron KK
Original Assignee
Nippon Mektron KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Mektron KK filed Critical Nippon Mektron KK
Priority to JP2002029100A priority Critical patent/JP3854517B2/en
Publication of JP2003234236A publication Critical patent/JP2003234236A/en
Application granted granted Critical
Publication of JP3854517B2 publication Critical patent/JP3854517B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Landscapes

  • Parts Printed On Printed Circuit Boards (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Description

【0001】
【発明の属する技術分野】
本発明は、膜状コンデンサとその為の製造法及びこれを有する回路基板に関するものであり、さらに詳細にいえば、本発明は電気・電子機器の小型・軽量化の要求に伴う部品の小型化に対応した膜状コンデンサとその製造法及びこれを有する回路基板に関する。
【0002】
【従来の技術とその問題点】
電気・電子機器の更なる小型・軽量化の要求のために配線の密度は年々高くなっている。このため回路基板に実装するコンデンサや抵抗などの部品のサイズも小さくなってきている。
【0003】
しかしながら部品を実装するためには実装用のランドが必要であり、これが回路基板の配線密度向上の阻害要因となっている。また、部品の小型化は、更なる位置合わせ精度の向上を要求するものであり、生産性において不利になる。
【0004】
【課題を解決するための手段】
電着手法は通電部すべてに成膜が可能な手法であり、表面保護層の形成のための電着も可能であり、回路基板の表面保護層の形成法として検討されている。
【0005】
そこで本発明では、絶縁性基材の所定の箇所に凹部あるいは貫通孔を設け、該凹部あるいは貫通孔内周に導体層を形成し、この導体層上に薄く誘電体層を形成し、更にこの誘電体層上にコンデンサにおける対向電極である導体層を形成することによって膜状のコンデンサを形成することが可能となる。
【0006】
このとき、誘電体層を形成する際、電着手法を用いるため、電着条件により任意に電着による誘電体の膜厚をコントロールすることで、形成される膜状コンデンサの静電容量を任意に設定することが可能になる。
【0007】
また、誘電体をラミネートなどの手法で形成する場合、凹部あるいは貫通孔が微細であると埋め込みが困難となり欠陥となるが、電着手法は通電部全てに膜を析出するため、欠陥がない。一方、ワニスにより誘電体層を形成する手法も考えられるが、ラミネート同様、微細化に対しては埋め込みが困難であり、材料が高価であるためにコスト的に不利である。
【0008】
また、凹部の内周に形成した導体層、及び誘電体層表面を適当な手段で粗化することにより、表面積を増大させ、対向面積を大きくしてコンデンサの静電容量を設定することも可能である。
【0009】
さらに、上記方法により形成されたコンデンサは配線の一部として形成されるので、従来のコンデンサよりもサイズを小さくすることが出来、また、基板に埋め込まれた構造を有するので、厚み方向の縮小が出来るため、例えば多層回路基板に於ける内層コンデンサへの適用などが可能となる。
【0010】
そして、基材として可撓性基板を適用すれば、コンデンサを有する可撓性回路基板の形成が可能となり、更なる軽量、小型化、及び屈曲性の付与による折り畳んでの実装が可能となる。
【0011】
【発明の実施の形態】
図1は本発明の一実施例による膜状コンデンサの製造工程図を示す。まず同図(1)のように適当な絶縁性基材1の上面にレーザ、プラズマ、リアクティブイオンエッチングなどのような乾式エッチング、または樹脂エッチングのような化学的な湿式エッチング、あるいはドリルやパンチなどのような機械的加工により凹部2を形成する。
【0012】
次いで同図(2)のようにアディティブの手法を用いて導体層としての回路配線パターン3を形成し、同時に凹部2の内周にも導体層4を形成する。あるいは凹部2を含む基板上面全面に導体層を形成し、サブトラクティブ法で回路配線パターン3及び凹部内周に導体層4を形成する。この後、必要に応じてブラスト等のような機械的手法、またはソフトエッチングなどの化学的手法により導体層表面を粗化する。
【0013】
次に同図(3)のように電着手法にて凹部2に形成した導体層4上に誘電体層5を薄く形成する。この後必要に応じてブラスト等のような機械的手法、あるいはソフト樹脂エッチングなどの化学的手法により誘電体層5の表面を粗化する。
【0014】
更に同図(4)のようにアディティブなどの手法を用いて導体層6を形成することにより膜状コンデンサを得る。
【0015】
図2は本発明の他の実施例による膜状コンデンサの製造工程図を示す。まず同図(1)のように適当な絶縁性基材7にレーザ、プラズマ、リアクティブイオンエッチングなどのような乾式エッチング、あるいは化学的な湿式エッチング、あるいはドリルやパンチなどのような機械的加工により貫通孔8を形成する。
【0016】
次いで同図(2)のようにアディティブの手法を用いて導体層としての回路配線パターン9を形成し、同時に貫通孔8の内周にも導体層10を形成する。あるいは貫通孔8を含む基板上面全面に導体層を形成し、サブトラクティブ法で回路配線パターン9及び貫通孔8の内周に導体層10を形成する。この後必要に応じてブラスト等のような機械的手法、あるいはソフトエッチングなどの化学的手法により導体層表面を粗化する。
【0017】
次に同図(3)のように電着手法にて貫通孔に形成した導体層10上に誘電体層11を形成する。この後必要に応じてブラスト等のような機械的手法、あるいはソフト樹脂エッチングなどの化学的手法により誘電体層表面を粗化する。
【0018】
更に同図(4)のようにアディティブなどの手法を用いて導体層12を形成することにより膜状コンデンサを得る。
【0019】
これらの実施例は基材として片面あるいは両面に導体層を既に有する基材を用いてサブトラクティブ法あるいはセミアディティブ法で配線を形成した後に凹部あるいは貫通孔を形成してから凹部あるいは貫通孔内周に導体層次いで誘電体層さらには対向する導体層を形成しても良い。
【0020】
【発明の効果】
本発明によれば、電着手法を用いるので微細な窪みあるいは貫通孔に形成した導体層に欠陥無く誘電体層を形成することが可能である。
【0021】
さらに、電着条件を制御することによって膜状コンデンサの静電容量を任意に設定できる。
【0022】
そして、上記方法により形成された膜状コンデンサは配線の一部として形成されるので、従来のコンデンサよりもサイズを小さくすることが出来、また、基板に埋め込まれた構造を有するので、厚み方向の縮小が出来るため、例えば多層回路基板に於ける内層コンデンサへの適用などが可能となる。この結果、製品の小型化、軽量化に貢献する。
【0023】
さらに、基材として可撓性基板を適用すれば、コンデンサを有する可撓性回路基板の形成が可能となり、更なる軽量、小型化、及び屈曲性の付与による折り畳んでの実装が可能となる。この結果、製品の小型化、軽量化に貢献する。
【図面の簡単な説明】
【図1】本発明の一実施例による膜状コンデンサの製造工程図。
【図2】本発明の他の実施例による膜状コンデンサの製造工程図。
【符号の説明】
1 絶縁性基材
2 凹部
3 回路配線パターン
4 凹部内周の導体層
5 誘電体層
6 誘電体層上に形成された対向導体層
7 絶縁性基材
8 貫通孔
9 回路配線パターン
10 貫通孔内周の導体層
11 誘電体層
12 誘電体層上に形成された対向導体層
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a film capacitor, a manufacturing method therefor, and a circuit board having the film capacitor. More specifically, the present invention relates to miniaturization of components in response to demands for miniaturization and weight reduction of electric / electronic devices. The present invention relates to a film capacitor corresponding to the above, a manufacturing method thereof, and a circuit board having the same.
[0002]
[Prior art and its problems]
Due to the demand for further miniaturization and weight reduction of electric and electronic devices, the density of wiring is increasing year by year. For this reason, the size of components such as capacitors and resistors mounted on a circuit board has also been reduced.
[0003]
However, in order to mount components, a land for mounting is required, which is an impediment to improving the wiring density of the circuit board. Further, the miniaturization of parts requires further improvement in alignment accuracy, which is disadvantageous in productivity.
[0004]
[Means for Solving the Problems]
The electrodeposition method is a method capable of forming a film on all current-carrying portions, and can be electrodeposited for forming a surface protective layer, and is being studied as a method for forming a surface protective layer on a circuit board.
[0005]
Therefore, in the present invention, a concave portion or a through hole is provided at a predetermined location of the insulating base material, a conductor layer is formed on the inner periphery of the concave portion or the through hole, and a thin dielectric layer is formed on the conductor layer. A film-like capacitor can be formed by forming a conductor layer which is a counter electrode of the capacitor on the dielectric layer.
[0006]
At this time, since the electrodeposition technique is used when forming the dielectric layer, the capacitance of the formed film capacitor can be arbitrarily controlled by arbitrarily controlling the film thickness of the dielectric by electrodeposition according to the electrodeposition conditions. It becomes possible to set to.
[0007]
In addition, when the dielectric is formed by a method such as laminating, if the concave portion or the through-hole is fine, embedding becomes difficult and a defect is caused. On the other hand, a method of forming a dielectric layer with a varnish is also conceivable. However, as with a laminate, embedding is difficult for miniaturization, and the material is expensive, which is disadvantageous in terms of cost.
[0008]
It is also possible to set the capacitance of the capacitor by increasing the surface area and roughening the surface of the conductor layer and dielectric layer formed on the inner periphery of the recess by appropriate means, and increasing the facing area. It is.
[0009]
Furthermore, since the capacitor formed by the above method is formed as a part of the wiring, the size can be made smaller than that of the conventional capacitor, and since it has a structure embedded in the substrate, it can be reduced in the thickness direction. Therefore, for example, it can be applied to an inner layer capacitor in a multilayer circuit board.
[0010]
When a flexible substrate is applied as a base material, a flexible circuit substrate having a capacitor can be formed, and further folding can be achieved by providing lighter weight, smaller size, and flexibility.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a manufacturing process diagram of a film capacitor according to an embodiment of the present invention. First, as shown in Fig. 1 (1), dry etching such as laser, plasma, reactive ion etching, etc., chemical wet etching such as resin etching, or drill or punch on the upper surface of an appropriate insulating substrate 1 The concave portion 2 is formed by mechanical processing such as.
[0012]
Next, as shown in FIG. 2 (2), the circuit wiring pattern 3 as a conductor layer is formed using an additive method, and at the same time, the conductor layer 4 is also formed on the inner periphery of the recess 2. Alternatively, a conductor layer is formed on the entire upper surface of the substrate including the recess 2, and the circuit wiring pattern 3 and the conductor layer 4 are formed on the inner periphery of the recess by a subtractive method. Thereafter, the surface of the conductor layer is roughened by a mechanical method such as blasting or a chemical method such as soft etching, if necessary.
[0013]
Next, a thin dielectric layer 5 is formed on the conductor layer 4 formed in the recess 2 by electrodeposition as shown in FIG. Thereafter, if necessary, the surface of the dielectric layer 5 is roughened by a mechanical method such as blasting or a chemical method such as soft resin etching.
[0014]
Further, a film capacitor is obtained by forming the conductor layer 6 using a method such as additive as shown in FIG.
[0015]
FIG. 2 is a manufacturing process diagram of a film capacitor according to another embodiment of the present invention. First, dry etching such as laser, plasma, reactive ion etching, etc., chemical wet etching, or mechanical processing such as drilling or punching is performed on an appropriate insulating substrate 7 as shown in FIG. Through holes 8 are formed by the above.
[0016]
Next, as shown in FIG. 2 (2), a circuit wiring pattern 9 as a conductor layer is formed by using an additive method, and at the same time, a conductor layer 10 is also formed on the inner periphery of the through hole 8. Alternatively, a conductor layer is formed on the entire upper surface of the substrate including the through hole 8, and the conductor layer 10 is formed on the inner periphery of the circuit wiring pattern 9 and the through hole 8 by a subtractive method. Thereafter, the surface of the conductor layer is roughened by a mechanical method such as blasting or a chemical method such as soft etching, if necessary.
[0017]
Next, a dielectric layer 11 is formed on the conductor layer 10 formed in the through hole by electrodeposition as shown in FIG. Thereafter, the surface of the dielectric layer is roughened by a mechanical method such as blasting or a chemical method such as soft resin etching, if necessary.
[0018]
Further, as shown in FIG. 4 (4), a film capacitor is obtained by forming the conductor layer 12 using a technique such as additive.
[0019]
In these embodiments, after forming a wiring by a subtractive method or a semi-additive method using a base material that already has a conductor layer on one side or both sides as a base material, a recess or a through hole is formed, and then the inner periphery of the recess or the through hole is formed. Further, a conductor layer, a dielectric layer, and an opposing conductor layer may be formed.
[0020]
【The invention's effect】
According to the present invention, since the electrodeposition technique is used, it is possible to form a dielectric layer without defects in a conductor layer formed in a fine depression or through hole.
[0021]
Furthermore, the capacitance of the film capacitor can be arbitrarily set by controlling the electrodeposition conditions.
[0022]
Since the film capacitor formed by the above method is formed as a part of the wiring, the size can be made smaller than that of the conventional capacitor, and since it has a structure embedded in the substrate, it has a thickness direction. Since it can be reduced, for example, it can be applied to an inner layer capacitor in a multilayer circuit board. As a result, it contributes to the reduction in size and weight of the product.
[0023]
Furthermore, when a flexible substrate is applied as a base material, a flexible circuit substrate having a capacitor can be formed, and further light weight, downsizing, and flexible mounting can be achieved. As a result, it contributes to the reduction in size and weight of the product.
[Brief description of the drawings]
FIG. 1 is a manufacturing process diagram of a film capacitor according to an embodiment of the present invention.
FIG. 2 is a manufacturing process diagram of a film capacitor according to another embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Insulating base material 2 Recessed part 3 Circuit wiring pattern 4 Conductive layer 5 of recessed part inner periphery Dielectric layer 6 Opposing conductor layer 7 formed on the dielectric layer Insulating base material 8 Through hole 9 Circuit wiring pattern 10 In through hole Circumferential conductor layer 11 Dielectric layer 12 Opposing conductor layer formed on the dielectric layer

Claims (4)

絶縁性基材の所定の箇所に凹部あるいは貫通孔を設け、該凹部あるいは貫通孔内周に導体層を設け、前記導体層上に電着手段で誘電体層を設け、この誘電体層上に対向電極を設けると共に、前記導体層および誘電体層表面を粗化することによりコンデンサの対向面積を大きく構成した膜状コンデンサ。A recess or a through hole is provided at a predetermined location of the insulating base material, a conductor layer is provided on the inner periphery of the recess or the through hole, and a dielectric layer is provided on the conductor layer by electrodeposition means. A film capacitor in which a counter electrode is provided and a surface area of the capacitor is increased by roughening the surfaces of the conductor layer and the dielectric layer. 絶縁性基材の所定の箇所に凹部あるいは貫通孔を形成し、、該凹部あるいは貫通孔内周に導体層を形成し、この導体層上に電着手段で誘電体層を形成し、前記誘電体層上にコンデンサにおける対向電極である導体層を形成すると共に、前記導体層および誘電体層表面を粗化することによりコンデンサの対向面積を大きく形成した膜状コンデンサの製造法。A recess or a through hole is formed at a predetermined location of the insulating substrate, a conductor layer is formed on the inner periphery of the recess or the through hole, a dielectric layer is formed on the conductor layer by electrodeposition means, and the dielectric A manufacturing method of a film capacitor in which a conductor layer which is a counter electrode in a capacitor is formed on a body layer, and the opposing area of the capacitor is increased by roughening the surfaces of the conductor layer and the dielectric layer. 前記電着手法の条件を変えることにより静電容量を任意に設定した請求項2の膜状コンデンサの製造法。The method for manufacturing a film capacitor according to claim 2, wherein the capacitance is arbitrarily set by changing the conditions of the electrodeposition technique. 前記請求項のいずれかにより構成された膜状コンデンサを一体に形成した回路基板。A circuit board on which a film-like capacitor constituted by any one of the preceding claims is integrally formed.
JP2002029100A 2002-02-06 2002-02-06 Membrane capacitor and manufacturing method thereof Expired - Fee Related JP3854517B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002029100A JP3854517B2 (en) 2002-02-06 2002-02-06 Membrane capacitor and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002029100A JP3854517B2 (en) 2002-02-06 2002-02-06 Membrane capacitor and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2003234236A JP2003234236A (en) 2003-08-22
JP3854517B2 true JP3854517B2 (en) 2006-12-06

Family

ID=27773562

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002029100A Expired - Fee Related JP3854517B2 (en) 2002-02-06 2002-02-06 Membrane capacitor and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP3854517B2 (en)

Also Published As

Publication number Publication date
JP2003234236A (en) 2003-08-22

Similar Documents

Publication Publication Date Title
US9999134B2 (en) Self-decap cavity fabrication process and structure
KR101084250B1 (en) Electronic Components Embedded Printed Circuit Board and Method of Manufacturing the Same
TW200601926A (en) Printed circuit board and manufacturing method thereof
JP2004522304A (en) Method of forming a printed circuit board and printed circuit board formed by this method
KR20150008771A (en) Printed Circuit Board Having Embedded Electronic Device And Manufacturing Method Thereof
US8604346B2 (en) Flex-rigid wiring board and method for manufacturing the same
JPH08125342A (en) Flexible multilayered wiring board and its manufacture
US10772220B2 (en) Dummy core restrict resin process and structure
CN105210462A (en) Method for manufacturing component-embedded substrate, and component-embedded substrate
US20190104615A1 (en) Printed wiring board and method for manufacturing the same
JP2004064052A (en) Noise shielding type laminated substrate and its manufacturing method
US20080251493A1 (en) Method for manufacturing printed wiring board with built-in capacitor
US8083954B2 (en) Method for fabricating component-embedded printed circuit board
JP3854517B2 (en) Membrane capacitor and manufacturing method thereof
KR101946989B1 (en) The printed circuit board and the method for manufacturing the same
JP2008311544A (en) Method for manufacturing compound multilayer printed-wiring board
US20110048777A1 (en) Component-Embedded Printed Circuit Board
KR100653247B1 (en) Printed circuit board having embedded electric components and fabricating method therefore
KR20190012997A (en) Double Side Embedded Manufacturing Method
JP4385729B2 (en) Capacitor element built-in multilayer circuit board and manufacturing method thereof
JP2004039908A (en) Circuit board and its manufacturing method
KR101555142B1 (en) Integrated chip manufacturing method FPCB
JP4252227B2 (en) Manufacturing method of double-sided flexible circuit board
JPH0548246A (en) Manufacture of flexible printed circuit board
JP2023042086A (en) Electronic device and method for manufacturing the same

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20051220

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060110

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060217

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20060905

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20060908

R150 Certificate of patent or registration of utility model

Ref document number: 3854517

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100915

Year of fee payment: 4

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100915

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110915

Year of fee payment: 5

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110915

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120915

Year of fee payment: 6

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120915

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130915

Year of fee payment: 7

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees