JP3838809B2 - Serial data transfer device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a serial data transfer apparatus that serially transfers data between a master device and a slave device.
[0002]
[Prior art]
For example, data is exchanged between a microcontroller and its peripheral devices using 8-bit (1 byte) data as one unit. The serial data transfer device is, for example, IIC (I²  As represented by C) -bus (Inter-IC Control bus) (hereinafter simply referred to as IIC bus), serial communication is performed between a master device that exchanges data in units of 8-bit data and a plurality of slave devices. The data is transferred to the network.
[0003]
In the serial data transfer apparatus to which the above-described IIC bus is applied, for example, data is transferred between a controlling master device such as a microcontroller and a plurality of controlled slave devices such as peripheral devices. A serial data line (SDA) and a serial clock line (SCL) for transferring a clock signal holding data are connected to each other by two bidirectional serial lines connected to a power source by a pull-up resistor. .
[0004]
Here, the serial data line basically changes during a period in which the serial clock line is at a low level. If the serial data line changes from the high level to the low level while the serial clock line is at the high level, it means that it is a start signal (START) instructing the start of data transfer, and if it changes from the low level to the high level. , It means a stop signal (STOP) for instructing the end of data transfer.
[0005]
The master device first outputs a 1-bit start signal on the serial data line. Subsequently, it consists of a 7-bit unique address that is uniquely assigned to each slave device in advance, and a 1-bit data control signal for instructing data write to the slave device or data read from the slave device. 8-bit parallel data is sequentially serially output from the MSB (Most Significant Bit) side on the serial data line.
[0006]
Each slave device receives 8-bit parallel data output from the master device on the serial data line serially in synchronization with the clock signal supplied from the serial clock line, and assigns it in advance to itself. Compare with the unique address. Then, the slave device that matches its own unique address outputs a 1-bit acknowledge signal (acknowledgment signal) on the serial data line.
[0007]
After confirming the acknowledge signal output from the slave device on the serial data line, the master device sequentially outputs 8-bit parallel data to be transferred serially on the serial data line in the case of data write to the slave device. . The slave device that has output the acknowledge signal sequentially receives the 8-bit parallel data output from the master device on the serial data line serially, and then outputs the same 1-bit acknowledge signal.
[0008]
A predetermined number of bytes of data are transferred from the master device to the slave device as necessary. Thereafter, the master device outputs a 1-bit stop signal on the serial data line, and the slave device receives this stop signal and confirms the end of data transmission. Thereafter, in the same manner, the master device repeatedly outputs the desired unique address, sequentially designates the slave devices to which data is to be transferred next, and transfers the data.
[0009]
In a serial data transfer apparatus to which the IIC bus is applied, it is necessary to sequentially access a plurality of slave devices to which data is to be transferred. Therefore, even when transferring data including the same control signal for controlling a plurality of the same devices connected to the slave device such as start, stop, abort, etc., to a plurality of the same slave devices, There is a problem that a plurality of slave devices cannot be accessed simultaneously.
[0010]
To solve this problem, conventional serial data transfer devices cannot be controlled simultaneously by connecting control signals directly from the master device to devices connected to a plurality of slave devices, or cannot be controlled simultaneously. In such a case, the frequency of the clock signal supplied from the serial clock line is increased to transfer data to a plurality of slave devices, or to reduce the time difference for control.
[0011]
However, if the control signal is directly connected to the device connected to the slave device from the master device, the number of lines increases in addition to the serial data line and serial clock line, and the merit of serial data transfer decreases. Even if the frequency of the clock signal is increased, since the same data is repeatedly transferred to each slave device, a longer time is required as the number of slave devices increases, and there is a problem that waste increases.
[0012]
[Problems to be solved by the invention]
An object of the present invention is to provide a serial data transfer apparatus capable of simultaneously transferring the same data from a master device to a plurality of slave devices in view of the problems based on the conventional technology.
[0013]
[Means for Solving the Problems]
  To achieve the above object, the present invention provides a serial data line for transferring data and a serial clock line for transferring a clock signal holding the data.ConnectedWith at least one master device,With multiple slave devicesAnd logic means,
  In the normal operation mode, a unique address designating one of the slave devices is transferred from one of the master devices via the serial data line, and the slave device having the unique address is transferred from the first terminal to the serial data. An acknowledge signal is output to the line,
In the local mode, a common shared address is transferred from one of the master devices to a plurality of slave devices set in advance among the plurality of slave devices via the serial data line, and the slave having the shared address The device outputs an acknowledge signal from the second terminal different from the first terminal to the logic means, and the logic means takes the logic of the acknowledge signal output from the slave device having the shared address and outputs the serial data. Output to lineThe present invention provides a serial data transfer device characterized by the above.
Here, the logic means is preferably an OR gate having an input terminal connected to the second terminals of a plurality of slave devices having the shared address.
[0014]
  Further, the present invention is a slave device connected to at least one master device via a serial data line for transferring data and a serial clock line for transferring a clock signal holding the data,
Means for performing data communication with the master device via the serial data line;
Means for comparing address information transferred from the master device via the serial data line with a unique address unique to itself;
Means for comparing address information transferred from the master device via the serial data line with a common shared address with other slave devices;
Means for outputting an acknowledge signal from a first terminal when the address information transferred from the master device is recognized as the unique address;
Means for outputting an acknowledge signal from a second terminal different from the first terminal when the address information transferred from the master device is recognized as the shared address. provide.
  Here, in addition, according to the state of the select signal, the data transmitted from the master device is held in any one of the first and second registers,
  The output of the first register isThe slave deviceDirectly against the device connected toConnectionThe output of the second register via the I / O port,The slave deviceIt is preferable that it is connected bidirectionally to the device connected to.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a serial data transfer apparatus according to the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.
[0016]
FIG. 1 is a system configuration diagram of an embodiment of a serial data transfer apparatus according to the present invention. The serial data transfer apparatus 10 shown in the figure includes a master device (MASTER) 12, slave devices (Slave1 to 3) 14 and OR gate 16 to which the present invention is applied, a conventional slave device (Slave) 18, Up resistors 19, 20 and a serial data line SDA and a serial clock line SCL are provided.
[0017]
Here, the serial data line SDA is a line for transferring data (including a control signal), and the serial clock line SCL is a line for supplying a clock signal for holding data. 20 is connected to the power supply VDD. The master device 12 is a device that controls the slave device 14, and its SCL terminal and SDA terminal are connected to a serial clock line SCL and a serial data line, respectively.
[0018]
Subsequently, the slave device 14 is a device controlled by the master device 12, and its SCL terminal and SDA1 terminal are connected to the serial clock line SCL and serial data line SDA, respectively, and its SDA2 terminal is both This is input to the OR gate 16. The output of the OR gate 16 is an open drain or open collector output, and is connected to the serial data line SDA.
[0019]
Similarly, the slave device 18 is a device controlled by the master device 12, and its SCL terminal and SDA terminal are connected to the serial clock line SCL and the serial data line, respectively. The master device 12, the slave device 18, the pull-up resistors 19 and 20, the serial data line SDA, and the serial clock line SCL except for the slave device 14 and the OR gate 16 have a conventionally known configuration.
[0020]
In the serial data transfer device 10 of the present invention, data is transferred serially between the master device 12 and the plurality of slave devices 14 and 18 via the serial data line SDA and the serial clock line SCL. Although details will be described later, in addition to transferring data one-to-one between the master device 12 and the slave devices 14, 18, it is also possible to simultaneously transmit data from the master device 12 to a plurality of slave devices 14. is there.
[0021]
Next, FIG. 2 shows a schematic configuration diagram of an embodiment of a master device.
As conceptually shown in the figure, the master device 12 includes a microcontroller (CPU) 22 and an output buffer 24 comprising an open drain type N-type MOS transistor (hereinafter referred to as NMOS) for driving the serial clock line SCL, And an input / output buffer 26 made of an open drain type NMOS for driving the serial data line SDA.
[0022]
In the master device 12, the microcontroller 22 controls the overall operation according to a program designed in advance. The output buffer 24 outputs a clock signal on the serial clock line SCL, the input / output buffer 26 outputs data to be transferred on the serial data line SDA, or is output on the serial data line SDA. The data to be received is taken in via the input buffer 28.
[0023]
Next, FIG. 3 shows a block configuration diagram of an embodiment of a slave device.
The slave device 14 has a circuit configuration unique to the present invention. As shown in the figure, the slave device 14 includes a filter 30, a bus control circuit 32, an S / P (serial / parallel) conversion circuit 34, and a P / S ( A parallel / serial conversion circuit 36, output registers 38 (OUTREG0) and 40 (OUTREG1), an I / O (input / output) port 42, and an input / output (output unit) buffer 44 are provided.
[0024]
In the slave device 14, the serial clock signal SCL output on the serial clock line and the serial data signal SDA1 output on the serial data line are input to the filter 30 first. These signals SCL and SDA1 are noise-removed by the filter 30, and are output from the filter 30 as a serial clock input signal SCLIN and a serial data input signal SDAIN, respectively.
[0025]
The serial clock input signal SCLIN and serial data input signal SDAIN output from the filter 30 are input to the bus control circuit 32. In addition, the bus control circuit 32 includes a reset signal RSTL, a select signal SEL1H, unique address signals A0-2, shared address signals CA0-2, parallel data output from the S / P conversion circuit 34, and P / S Serial data output from the conversion circuit 36 is input.
[0026]
Here, the reset signal RSTL resets and initializes the slave device 14. For example, the slave device 14 is reset when it is at a low level. The select signal SEL1H is a signal that designates whether the parallel data (S / P conversion output) after S / P conversion is held in the output register 38 or 40. The parallel data after S / P conversion is, for example, select When the signal SEL1H is at high level, it is held in the output register 40.
[0027]
In the serial data transfer device 10 of the present invention, for example, 7-bit address information is transmitted from the master device 12 to the slave devices 14 and 18 in order to specify the desired slave devices 14 and 18. The unique address signal A0-2 is a signal for setting a unique address unique to each slave device 14, and the shared address signal CA0-2 is a shared address common to a plurality of slave devices 14 set in advance. Is a signal for setting.
[0028]
The bus control circuit 32 controls the operation of the entire slave device 14. From the bus control circuit 32, in addition to serial data obtained by sequentially holding the serial data input signal SDAIN input from the filter 30 as the serial clock input signal SCLIN, the write clock signals WCLK0 and 1, the I / O control signal I / O OCONT, serial data output SDAOUT, and serial data output SDA2 are output.
[0029]
Here, the write clock signals WCLK0 and 1 hold the S / P converted parallel data output from the S / P conversion circuit 34 in the output registers 38 and 40, respectively, according to the state of the select signal SEL1H. This is a clock signal. For example, the write clock signal WCLK0 is output when the select signal SEL1H is at a low level, and the write clock signal WCLK1 is output when the select signal SEL1H is at a high level.
[0030]
In the serial data transfer apparatus 10 of the present invention, following the address information described above, a 1-bit data control signal that instructs data writing to the slave device or data reading from the slave device is transmitted. The I / O control signal I / OCONT is input of parallel data between the slave device 14 and a device connected to the slave device 14 (hereinafter referred to as a connection device) according to the state of the data control signal. This is a signal for switching the output direction.
[0031]
When the data control signal is at a low level, it means data write from the master device 12 to the slave devices 14 and 18, and data is transmitted from the master device 12 to the connection device via the slave devices 14 and 18. On the other hand, when the data control signal is at a high level, it means data read from the slave devices 14 and 18 to the master device 12, and data is received by the master device 12 from the connection device side via the slave devices 14 and 18.
[0032]
Next, FIG. 4 shows a block diagram of an embodiment of the bus control circuit. The bus control circuit 32 includes a device address detection circuit 50, WCLK0 and 1 generation circuits 52 and 54, a start signal / stop signal detection circuit 56, a data control signal detection circuit 58, an SCL counter 60, and SDA1 and SDA2 controllers. 62 and 64, a serial data holding circuit 66, and a controller 68.
[0033]
First, the controller 68 controls the operation of the entire bus control circuit 32. Various control signals output from the controller 68 are the device address detection circuit 50, the WCLK0 and 1 generation circuits 52 and 54, the data control signal detection circuit 58, and the SCL counter 60 except for the start signal / stop signal detection circuit 56. , SDA1 and SDA2 controllers 62 and 64, and serial data holding circuit 66.
[0034]
Subsequently, the serial signal input signal SCLIN and the serial data input signal SDAIN are input to the start signal / stop signal detection circuit 56. The start signal / stop signal detection circuit 56 detects a start signal (START) instructing the start of data transfer and a stop signal (STOP) instructing the end of data transfer. The detection result by the start signal / stop signal detection circuit 56 is input to the controller 68.
[0035]
In the serial data transfer device 10 of the present invention, the serial data input signal SDAIN basically changes while the serial clock input signal SCLIN is at a low level. The start signal / stop signal detection circuit 56 detects the start signal by looking at the change of the serial data input signal SDAIN from the high level to the low level while the serial clock input signal SCLIN is at the high level, and detects the start signal from the low level to the high level. The stop signal is detected by looking at the change to.
[0036]
Subsequently, the device address detection circuit 50 includes a select signal SEL1H, unique address signals A0 to A2, shared address signals CA0 to CA2, and parallel data (S / P conversion output) supplied from the S / P conversion circuit 34. Is entered. The device address detection circuit 50 compares the S / P conversion output (address information) with the unique address signals A0 to A2 and the shared address signals CA0 to 2 preset for each slave device 14.
[0037]
The comparison result of the device address detection circuit 50 is input to the WCLK 0 and 1 generation circuits 52 and 54 in addition to the controller 68. The WCLK0, 1 generation circuits 52, 54 receive the comparison result from the device address detection circuit 50, and when the data write from the master device 12 to the slave device 14 is designated by the data control signal, the WCLK0, 1 generation circuit 52, 54 is set to the state of the select signal SEL1H. In response, the write clock signals WCLK0 and 1 are generated.
[0038]
Here, FIG. 5 shows a configuration circuit diagram of an embodiment of the device address detection circuit and the WCLK generation circuit. This figure corresponds to a portion surrounded by a dotted line of the bus control circuit 32 shown in FIG. 4. First, the device address detection circuit 50 has two comparators (CMP) 70 and 72. The WCLK0 generation circuit 52 includes an AND gate 74, and the WCLK1 generation circuit 54 includes an AND gate 76 and an OR gate 78.
[0039]
In the device address detection circuit 50, the shared address signals CA0 to CA6 and the S / P conversion outputs SPR0 to SPR6 are input to the comparator 70. Similarly, the unique address signals A0 to 6 and the S / P conversion output are input to the comparator 72. SPR0 to 6 are input. The comparators 70 and 72 compare both input signals, respectively. As a result, when a match is detected, the comparators 70 and 72 output a high level, and if they do not match, a low level is output.
[0040]
  Of the unique address signals A0-6 and shared address signals CA0-6, the unique address signals A0-2 and shared address signals CA0-2 are:3 and 4The signal shown in FIG. The unique address signals A 3 to 6 and the shared address signals CA 3 to 6 need to be fixed values of “0100” or “0111” in consideration of compatibility with the IIC bus standard, for example. The S / P conversion outputs SPR0 to SPR6 are data representing address information after S / P conversion.
[0041]
The comparison result of the comparator 70 is input to one terminal of the AND gates 74 and 76, and the select signal SEL1H is input to the other terminal of the AND gates 74 and 76. A write clock signal WCLK 0 is output from the AND gate 74, and the output of the AND gate 76 is input to one terminal of the OR gate 78. The comparison result of the comparator 72 is input to the other terminal of the OR gate 78, and the write clock signal WCLK 1 is output from the OR gate 78.
[0042]
That is, the write clock signal WCLK0 becomes high level when the shared address signals CA0-6 match the P / S conversion outputs SPR0-6 and the select signal SEL1H is at low level. On the other hand, in the write clock signal WCLK1, the unique address signals A0-6 and the S / P conversion outputs SPR0-6 match, or the shared address signals CA0-6 and the P / S conversion outputs SPR0-6 match, and When the select signal SEL1H is at a high level, the signal becomes a high level.
[0043]
Subsequently, the serial data input signal SDAIN is input to the data control signal detection circuit 58. The data control signal detection circuit 58 detects the data control signal and determines whether the data write is from the master device 12 to the slave devices 14, 18 or the data read from the slave devices 14, 18 to the master device 12. Judgment is made and an I / O control signal I / OCONT is generated. The data write / read identification result is also input to the controller 68.
[0044]
A serial clock input signal SCLIN and a serial data input signal SDAIN are input to the SCL counter 60. For data transmission / reception, for example, 8 bits (1 byte) is transferred as one unit. Therefore, the SCL counter 60 adjusts the data transmission and reception timing by counting the serial clock input signal SCLIN using the start signal as a reference. The count result by the SCL counter 60 is input to the controller 68.
[0045]
Similarly, the serial data holding circuit 66 also receives the serial clock input signal SCLIN and the serial data input signal SDAIN. The serial data holding circuit 66 sequentially holds the serial data input signal SDAIN in synchronization with the serial clock input signal SCLIN. The serial data held in the serial data holding circuit 66 is sequentially output to the S / P conversion circuit 34 as shown in FIG.
[0046]
Serial data (P / S conversion output) supplied from the P / S conversion circuit 36 is input to the SDA1 controller 62. The SDA1 controller 62 receives the P / S conversion output from the P / S conversion circuit 36 and outputs it to the input / output buffer 44 as a serial data output signal SDAOUT. The SDA2 controller 64 outputs an acknowledge signal under the control of the controller 68 when a shared address is designated.
[0047]
At the time of data writing, serial data is output from the bus control circuit 32 and input to the S / P conversion circuit 34. The S / P conversion circuit 34 converts the serial data supplied from the bus control circuit 32 into, for example, 8-bit parallel data. The parallel data after the S / P conversion is fed back to the bus control circuit 32 for comparison with the unique address signals A0-2 and the shared address signals CA0-2 in addition to the output registers 38, 40.
[0048]
Subsequently, the output registers 38 and 40 hold, for example, 8-bit parallel data output from the S / P conversion circuit 34 based on the write clock signals WCLK0 and 1 input from the bus control circuit 32, respectively. The parallel data held in the output register 38 is directly output to the connection device of the slave device 14, and the parallel data output from the output register 40 is input to the I / O port 42.
[0049]
The I / O port 42 and the connection device are connected bidirectionally. Therefore, the output register 40 is suitable for exchanging data between the slave device 14 and the connection device. On the other hand, the parallel data held in the output register 38 is directly output to the connection device. Therefore, the output register 38 is suitable for holding control signals for controlling the connection device such as start, stop, and abort, and can be used by directly connecting to the connection device.
[0050]
In addition to the parallel data, a reset signal RSTL and an I / O control signal I / OCONT from the bus control circuit 32 are input to the I / O port 42. The I / O port 42 outputs the parallel data supplied from the output register 40 to the connection device or the parallel data supplied from the connection device according to the state of the I / O control signal I / OCONT. Is output to a P / S conversion circuit 36 described below.
[0051]
As described above, the I / O port 42 and the connection device are bidirectionally connected by an 8-bit parallel bus. Parallel data supplied from the connection device at the time of data reading is output from the I / O port 42 to the P / S conversion circuit 36.
The P / S conversion circuit 36 converts 8-bit parallel data supplied from the I / O port 42 into serial data. The serial data output from the P / S conversion circuit 36 is input to the bus control circuit 32 described above.
[0052]
The bus control circuit 32 sequentially outputs the serial data supplied from the P / S conversion circuit 36 as a serial data output SDAOUT. The serial data output SDAOUT is input to the gate of the NMOS 48 via the inverter 46 of the input / output buffer 44. The source of the NMOS 48 of the input / output buffer 44 is connected to the ground, and its drain is output on the serial data line as the serial data signal SDA1.
[0053]
The serial data output SDAOUT supplied from the bus control circuit 32 is sequentially output from the input / output buffer 44 as the serial data signal SDA1. The acknowledge signal is output from the SDA1 terminal when a unique address is designated and only one slave device 14 is accessed, and when a shared address is designated and all slave devices 14 are accessed simultaneously. Is output from the SDA2 terminal.
[0054]
Next, a data format used in the serial data transfer apparatus 10 of the present invention will be described.
[0055]
In the present invention, the master device 12 is programmed to selectively output either a unique address or a shared address as address information following the start signal. In the following description, a mode in which one of the slave devices 14 or 18 is specified using a unique address is referred to as a normal processing mode, and a plurality of slave devices 14 set in advance using a shared address are simultaneously displayed. The designated mode is called local mode.
[0056]
FIG. 6 is a conceptual diagram of an embodiment of a data format.
In the normal processing mode, first, the start signal (S) is output from the master device 12, and then the first byte data consisting of the unique address signal and the data control signal (R / W) is sequentially output serially. Is done. On the other hand, the acknowledge signal (A) is output from the slave device 14 or 18 in which the unique address matching the unique address signal is set.
[0057]
When write (W) is specified by the data control signal, data (DATA 0 to n) is transmitted from the master device 12 to the slave device 14 or 18 in which the unique address matching the unique address signal is set. Sent. The corresponding slave device 14 or 18 sequentially receives the data transmitted from the master device 12, serially, for example, receives 8-bit (1 byte) data, and then outputs an acknowledge signal (A).
[0058]
On the other hand, when read (R) is designated, data (DATA 0 to n) is transmitted from the corresponding slave devices 14 and 18 to the master device 12. The master device sequentially receives the 8-bit data from the slave device 14 or 18 serially. After transmitting 8-bit data, the slave devices 14 and 18 output an acknowledge signal (A). Finally, a stop signal (E) is output from the master device 12.
[0059]
In contrast, in the local mode, first, when the select signal SEL1H is at a high level, that is, when data is written to the output register 40, the start signal (S) is output from the master device 12, and the shared address signal The first byte data consisting of the data control signal (W) instructing data writing from the master device 12 to the slave devices 14 and 18 is output. The subsequent data format is the same as in the normal processing mode.
[0060]
When the select signal SEL1H is at a low level, that is, when data is written to the output register 38, the first byte from the master device 12 to the slave devices 14 and 18 is the same as when the select signal SEL1H is at a high level. Data is then output, and then only 1 byte of data (DATA0) is transmitted. Thereafter, an acknowledge signal (A) is output from the slave devices 14 and 18, and a stop signal (E) is output from the master device 12.
[0061]
  next,FIG.The operation of the serial data transfer apparatus of the present invention will be described with reference to the flowchart shown in FIG.
[0062]
As shown in step S1 of the flowchart, first, the reset signal RSTL is set to low level, and the serial data transfer device 10 is initialized. After the initialization, the process proceeds to step S2, and the slave devices 14 and 18 detect that the start signal (START) is output from the master device 12. When the start signal is not detected (N), the slave devices 14 and 18 repeatedly perform detection until the start signal is detected (Y).
[0063]
When the start signal is detected (Y), all the slave devices 14 and 18 receive the first byte data consisting of the address information and the data control signal from the master device 12. As shown in step S3, each of the slave devices 14 and 18 compares the received address information with a preset unique address by the timing control of the SCL counter 60 shown in FIG. Detect whether it has been.
[0064]
As a result, the slave device 14 or 18 whose address information matches its own unique address (Y) enters the normal processing mode shown in step S4, and the SDA terminal of the corresponding slave device 14 or SDA1 of the slave device 18 A low level acknowledge signal is output from the pin. Thereafter, data is exchanged between the master device 12 and the slave device 14 or 18 in accordance with the IIC bus standard in accordance with the data format shown in FIG.
[0065]
On the other hand, if the address information from the master device 12 does not match the own unique address (N), the process proceeds to step S5. Each slave device 14 compares the address information with a preset shared address and detects whether the address information matches the shared address.
As a result, if the address information is a shared address (Y), the process proceeds to the next step S6, and if it is not a shared address (N), the process returns to step S2.
[0066]
In this embodiment, all slave devices 14 (Slave1 to 3) are designated by the shared address, and the local mode is entered. As shown in step S6, a low level acknowledge signal is output from the SDA2 terminal of all the slave devices 14 and is input to the OR gate 16 shown in FIG. 1, and the low level acknowledge signal is output from the OR gate 16 onto the serial data line SDA. A signal is output. The master device 12 receives this and confirms that it has entered the local mode.
[0067]
Subsequently, the process proceeds to step S7, and the data control signal (R / W) is detected by the timing control of the SCL counter 60 shown in FIG. In the local mode, all slave devices 14 are accessed simultaneously, but the master device 12 cannot receive (read) data from all the slave devices 14 at the same time. In (N), it is determined that the operation is illegal, and the process returns to step S2.
[0068]
On the other hand, if it is data write (W) (Y), the process proceeds to the next step S8. In step S8, it is determined whether the second byte data is held in the output register 38 or the output register 40 in accordance with the state of the select signal SEL1H. When the second byte data is held in the output register 38, the process proceeds to step S13, and when held in the output register 40, the process proceeds to step S9.
[0069]
Here, when the second byte data is held in the output register 40 (Y), serial data is sequentially fetched, and in step S9, 8-bit (1 byte) data is obtained under the control of the SCL counter 60 shown in FIG. Detect if received. At this time, if there is no 8-bit data input (N), there is no subsequent data, and transmission is complete, so the process proceeds to step S12. If there is an 8-bit data input (Y), the process proceeds to the next step S10.
[0070]
In step S10, a low level acknowledge signal is output from the SDA2 terminals of all the slave devices 14, and a low level acknowledge signal is output on the serial data line SDA by the OR gate 16 shown in FIG. The master device 12 detects the acknowledge signal on the serial data line SDA, confirms that all the slave devices 14 have received the second byte data, and transmits the next data.
[0071]
On the other hand, as shown in step S11, all slave devices 14 output parallel data after P / S conversion by the P / S conversion circuit 34 by the write clock WCLK1 generated by the bus control circuit 32 shown in FIG. It is held in the register 40.
[0072]
In step S12, all slave devices 14 detect a stop signal. When the stop signal is detected by the slave device 14 (Y), the transmission of data from the master device 12 to the slave device 14 ends. On the other hand, when the stop signal is not detected (N), the data transmitted from the master device 12 to the slave device 14 is a plurality of bytes, so the process returns to step S9 to repeatedly receive the next 8-bit data.
[0073]
On the other hand, in the case where the second byte data is held in the output register 38 (N) in step S8, the operation is the same as the case where it is held in the output register 40. That is, data is exchanged according to steps S13 to S16 corresponding to steps S9 to S12. In this embodiment, since the data of the control signal to be transmitted is 1 byte, if no stop signal is detected in step S16 (N), the process returns to step S2 and is repeated.
[0074]
The serial data transfer apparatus of the present invention is basically as described above.
Note that the number of master devices 12 may be one or more, and the number of slave devices 14 may be any number as long as there are two or more. Further, since the serial data transfer device of the present invention conforms to the IIC bus standard in the normal processing mode, the slave device to which the present invention is applied and the slave device of the conventional configuration coexist as shown in the above embodiment. Can be used.
[0075]
In the above embodiment, taking account of compatibility with the IIC bus standard, the polarity of each signal, the number of bits of data to be transferred, a specific circuit configuration, and the like are illustrated, but compatibility with the IIC bus standard is illustrated. If not necessary, the present invention is not limited to the above specific examples.
The serial data transfer device according to the present invention has been described in detail above. However, the present invention is not limited to the above-described embodiments, and various improvements and modifications may be made without departing from the spirit of the present invention. It is.
[0076]
【The invention's effect】
As described above in detail, the serial data transfer device of the present invention transmits address information corresponding to the unique address from the master device to the slave device, and has a unique address that matches the master device and the address information. Sends and receives data to and from the device on a one-to-one basis, sends address information corresponding to the shared address, and sends data to multiple slave devices set in advance from the master device To do.
Therefore, according to the serial data transfer apparatus of the present invention, when it is desired to transfer the same data between the master device and a plurality of slave devices set in advance, this can be realized by a single data transfer. For example, in the past, the same data was sequentially transmitted to seven slave devices. However, in the present invention, only one transmission is required, and the transmission time for six transmissions can be reduced. Further, according to the present invention, by providing a register that is directly output to the connection device, a control signal such as start, stop, and abort is simultaneously transmitted to a plurality of preset slave devices, and a plurality of connections are simultaneously performed. The device can be controlled. For example, according to the present invention, a plurality of RAMs (random access memories) designated in advance are simultaneously cleared, or a parameter is set in advance in a register such as a VTR (video tape recorder) and is started simultaneously. It can be applied to any system that requires such control.
[Brief description of the drawings]
FIG. 1 is a block diagram of an embodiment of a serial data transfer apparatus according to the present invention.
FIG. 2 is a schematic configuration diagram of an embodiment of a master device.
FIG. 3 is a block diagram of an embodiment of a slave device.
FIG. 4 is a block diagram of an embodiment of a bus control circuit.
FIG. 5 is a configuration circuit diagram of an embodiment of a device address detection circuit and a WCLK generation circuit.
FIG. 6 is a conceptual diagram of an embodiment of a data format.
FIG. 7 is a flowchart of an embodiment showing the operation of the serial data transfer apparatus of the present invention.
[Explanation of symbols]
10 Serial data transfer device
12 Master device
14,18 Slave device
16,78 OR gate
19, 20 Pull-up resistor
22 Microcontroller
24 Output buffer
26, 44 I / O buffer
28 Input buffer
30 filters
32 Bus control circuit
34 S / P conversion circuit
36 P / S conversion circuit
38, 40 output register
42 I / O port
46 Inverter
48 N-type MOS transistor
50 Device address detection circuit
52 WCLK0 generation circuit
54 WCLK1 Generation Circuit
56 Start signal / stop signal detection circuit
58 Data control signal detection circuit
60 SCL counter
62 SDA1 controller
64 SDA2 controller
66 Serial data holding circuit
68 controller
70,72 Comparator
74,76 AND gate
SDA serial data line
SCL serial clock line

Claims (4)

A serial data line for transferring data, at least one master device connected via a serial clock line for transferring a clock signal holding the data , a plurality of slave devices, and logic means ,
In the normal operation mode, a unique address designating one of the slave devices is transferred from one of the master devices via the serial data line, and the slave device having the unique address is transferred from the first terminal to the serial data. An acknowledge signal is output to the line,
In the local mode, a common shared address is transferred from one of the master devices to a plurality of slave devices set in advance among the plurality of slave devices via the serial data line, and the slave having the shared address The device outputs an acknowledge signal from the second terminal different from the first terminal to the logic means, and the logic means takes the logic of the acknowledge signal output from the slave device having the shared address and outputs the serial data. A serial data transfer device that outputs to a line .   2. The serial data transfer apparatus according to claim 1, wherein the logic means is an OR gate having an input terminal connected to the second terminal of a plurality of slave devices having the shared address.   A slave device connected to at least one master device via a serial data line for transferring data and a serial clock line for transferring a clock signal holding the data,
  Means for performing data communication with the master device via the serial data line;
  Means for comparing address information transferred from the master device via the serial data line with a unique address unique to itself;
  Means for comparing address information transferred from the master device via the serial data line with a common shared address with other slave devices;
  Means for outputting an acknowledge signal from the first terminal when the address information transferred from the master device is recognized as the unique address;
  A slave device comprising: means for outputting an acknowledge signal from a second terminal different from the first terminal when the address information transferred from the master device is recognized as the shared address. Furthermore, according to the state of the select signal, it has first and second registers that hold the data transmitted from the master device,
The output of the first register is connected directly to the device connected to the slave device, the output of the second register via the I / O ports, the device connected to the slave device The slave device according to claim 3 , wherein the slave device is connected in both directions.

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