JP3821676B2 - CCD output reset signal clamp circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to processing of a CCD signal, and in particular, amplifies a CCD output signal, clamps a reset signal, extracts only a signal component that changes with respect to the light level, and outputs it to a CDS circuit (Correlated Double Sampling circuit) in the next stage. The present invention relates to a CCD output reset signal clamping circuit for outputting.
[0002]
[Prior art]
In a satellite remote sensing device or the like, a reduction in size and weight is required, and the optical system cannot be enlarged. For this reason, a sufficient amount of light cannot be obtained, and the signal must be amplified and used. In principle, a reset signal is superimposed on all CCD outputs, so that the larger the amplification factor, the more the signal is amplified and the input range of the next stage CDS circuit is exceeded. From such a background, a reset clamp circuit is indispensable particularly for a circuit using a minute signal of CCD output.
[0003]
[Problems to be solved by the invention]
An object of the present invention is to provide a CCD output reset signal clamping circuit that does not exceed the input range of the CDS circuit and can prevent deterioration of linearity due to saturation of the output of the CDS circuit.
[0004]
[Means for Solving the Problems]
A CCD output reset signal clamp circuit according to the present invention includes a first signal amplifying means for amplifying an input signal from the CCD, and a limiter means for adjusting the level of the reset signal of the CCD among the output signals of the first signal amplifying means by a bias resistor. And a second signal amplifying means for amplifying the output signal of the first signal amplifying means including the level-adjusted reset signal, and a reset for clamping only the reset signal of the output signal of the second signal amplifying means and outputting only the signal component And clamping means.
[0005]
Further, the first signal amplifying means, the limiter means, and the second signal amplifying means are constituted by a balanced amplifier.
[0006]
Further, the reset clamp means is constituted by an inverter that removes an oscillator synchronized with a reset signal in reverse phase.
[0007]
Moreover, CCD output reset signal clamping circuit of the present invention is characterized in that the repetition period of the CCD of the reset signal is valid also for the case with the above velocity 10M Hz.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a CCD output reset signal clamp circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing output waveforms in each component of the CCD output reset signal clamp circuit, and FIG. It is a concrete circuit block diagram.
[0010]
Referring to FIG. 1, the CCD output reset signal clamp circuit according to the present embodiment amplifies an input signal from the CCD, and among the output signals of the first signal amplifier 1, the CCD reset signal is received. A limiter unit 2 for adjusting the level by the bias resistor 3, a second signal amplifier unit 4 for amplifying the output signal of the first signal amplifier unit 1 including the level-adjusted reset signal, and an output signal of the second signal amplifier unit 4 The reset signal is clamped by a reset clamp pulse 6 and includes a reset clamp unit 5 that outputs only a signal component.
[0011]
Next, the operation of the CCD output reset signal clamp circuit of this embodiment will be described with reference to FIGS.
[0012]
First, a signal inputted from the CCD (→ 1: □ in FIG. 2) is amplified by the first signal amplifying unit 1 (amplified signal → 2: ▽ in FIG. 2). At this point, the reset signal is amplified, and the input range of the CDS circuit is exceeded.
[0013]
Next, the level range of the reset signal is adjusted by the bias resistor 3 of the limiter unit 2. However, due to the level loss due to the limiter unit 2, the loss is taken into consideration, the second signal amplification unit 4 in the next stage further amplifies, and the output signal of the second signal amplification unit 4 is reset clamped by the reset clamp unit 5. Then, the data is output to the CDS circuit in the next stage (→ 3 in FIG. 2: ◇). Only signal components can be extracted by reset clamping.
[0014]
FIG. 2 shows an output waveform in each component of each CCD output reset signal clamp circuit. As shown in FIG. 2, one period of the signal waveform is about 0.1 μsec, indicating that what was conventionally 2 to 3M samples easily reaches 10M samples. As for the use environment, sufficient normal operation was confirmed at -10 ° C to + 40 ° C.
[0015]
FIG. 3 is a specific circuit configuration diagram of the present embodiment. The first signal amplifying unit 1, the limiter unit 2, and the second signal amplifying unit 4 are constituted by balanced amplifiers, and the reset clamp unit 5 Is constituted by an inverter that removes the reset clamp pulse 6 synchronized with the reset signal in reverse phase.
[0016]
【The invention's effect】
In the normal CCD signal processing, the CCD output signal is amplified, and then only a signal component that changes with respect to the light level is taken out by the CDS circuit and A / D converted.
[0017]
If there is a harmful reset signal, amplification of the signal may exceed the input range of the CDS circuit.
[0018]
According to the present invention, the input range of the CDS circuit is not exceeded, and there is an effect of preventing deterioration of linearity due to saturation of the CDS output of the circuit. Further, since it is possible to amplify early in the previous stage, the S / N ratio has an advantageous effect.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a CCD output reset signal clamp circuit according to an embodiment of the present invention.
2 is a diagram showing output waveforms in respective components of the CCD output reset signal clamp circuit of FIG. 1. FIG.
FIG. 3 is a circuit configuration diagram of a CCD output reset signal clamp circuit showing an embodiment of the present invention.
[Explanation of symbols]
1 First signal amplifier
2 Limiter section
3 Bias resistor
4 Second signal amplifier
5 Reset clamp
6 Reset clamp pulse

Claims (4)

First signal amplifying means for amplifying an input signal from the CCD;
Limiter means for adjusting the level of the reset signal of the CCD with a bias resistor among the output signals of the first signal amplifying means;
Second signal amplification means for amplifying an output signal of the first signal amplification means including the level-adjusted reset signal;
A reset clamp means for clamping a reset signal of the output signal of the second signal amplifying means and outputting only a signal component other than the reset signal.  2. The CCD output reset signal clamp circuit according to claim 1, wherein the first signal amplifying means, the limiter means, and the second signal amplifying means are constituted by balanced amplifiers.  2. The CCD output reset signal clamp circuit according to claim 1, wherein the reset clamp means comprises an inverter for removing an oscillator synchronized with the reset signal in reverse phase. CCD output reset signal clamping circuit according to claim 1, wherein the repetition period of the CCD of the reset signal, characterized in that it is also effective for the case with the above velocity 10M Hz.

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