JP3818435B2 - Synchronous rectifier circuit - Google Patents

Synchronous rectifier circuit Download PDF

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Publication number
JP3818435B2
JP3818435B2 JP2001309422A JP2001309422A JP3818435B2 JP 3818435 B2 JP3818435 B2 JP 3818435B2 JP 2001309422 A JP2001309422 A JP 2001309422A JP 2001309422 A JP2001309422 A JP 2001309422A JP 3818435 B2 JP3818435 B2 JP 3818435B2
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Japan
Prior art keywords
mosfet
capacitor
voltage
diode
circuit
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JP2001309422A
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Japanese (ja)
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JP2003116279A (en
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征輝 五十嵐
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Fuji Electric Co Ltd
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Fuji Electric Device Technology Co Ltd
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Description

【0001】
【発明の属する技術分野】
この発明は、低電圧出力の同期整流回路の改良、特に効率を向上させることが可能な同期整流回路に関する。
【0002】
【従来の技術】
図3に同期整流回路の第1の従来例を示す。
【0003】
これは、米国特許第5,528,482号として公知のもので、トランス1の1次巻線N1には金属酸化物半導体型電界効果トランジスタ(MOSFET)Q1が、トランス1の2次巻線N2にはMOSFETQ2,Q3の直列回路が、MOSFETQ2,Q3にはそれぞれ並列にダイオードD1,D2が、さらにMOSFETQ2には並列にリアクトルL1とコンデンサCoとの直列回路がそれぞれ接続されている。
【0004】
この回路は、MOSFETQ1がオンしているときには、トランス1の1次巻線N1には実線矢印の向きに電圧V1が、2次巻線N2には同じく実線矢印の向きに電圧V2が印加される。また、リアクトルL1に流れていた電流iLは、コンデンサCo→ダイオードD2→トランス2次巻線N2を介して流れる。このとき、MOSFETQ3のゲート・ソース間には2次巻線電圧V2が印加され、MOSFETQ3がオンする。MOSFETQ2のゲート・ソース間はダイオードD2とMOSFETQ3がオンしていることにより、零電圧となりオフ状態となる。
【0005】
次に、MOSFETQ1がオフしているときには、トランス1の1次巻線N1には点線矢印の向きに電圧V1が、2次巻線N2には同じく点線矢印の向きに電圧V2が印加される。また、リアクトルL1に流れていた電流iLは、コンデンサCo→ダイオードD1を介して流れる。このとき、MOSFETQ2のゲート・ソース間には2次巻線電圧V2が印加され、MOSFETQ2がオンする。MOSFETQ3のゲート・ソース間はトランス2次電圧V2が逆バイアス方向に印加され、オフ状態となる。
【0006】
ダイオードは、PN接合のしきい値電圧があり0.5〜1V程度の順電圧であるが、MOSFETはユニポーラデバイスでしきい値電圧がなくオン抵抗素子であるため、オン電圧を0.1Vにも低減できる。例えば、3V出力の電源においては、1Vの順電圧は1V/(3V+1V)で25%の効率低減となるが、これを0.1Vに低減できれば0.1V/(3V+0.1V)で3%の効率低減となり、装置の高効率化が達成できる。
【0007】
図4に同期整流回路の第2の従来例を示す。
【0008】
これは、特開平08−223906号として公知のもので、図3との相違はトランス1に3次巻線N3を設け、MOSFETQ2,Q3のゲートを3次巻線で駆動する点にある。また、MOSFETQ2のゲートには抵抗R1とコンデンサC1のフィルタ回路とダイオードD3を、MOSFETQ3のゲートには抵抗R2とコンデンサC2のフィルタ回路とダイオードD4を、それぞれ接続して構成される。
【0009】
図4の回路で、MOSFETQ1がオンしているときには、トランス1の1次巻線N1には実線矢印の向きに電圧V1が、3次巻線N3には同じく実線矢印の向きに電圧V3が印加される。また、リアクトルL1に流れていた電流iLは、コンデンサCo→ダイオードD2→トランス2次巻線N2を介して流れる。このとき、MOSFETQ3のゲート・ソース間には3次巻線電圧V3が印加され、MOSFETQ3がオンする。MOSFETQ2のゲート・ソース間はダイオードD3がオンしていることにより、零電圧となりオフ状態となる。
【0010】
次に、MOSFETQ1がオフしているときには、トランス1の1次巻線N1には点線矢印の向きに電圧V1が、3次巻線N3には同じく点線矢印の向きに電圧V3が印加される。また、リアクトルL1に流れていた電流iLは、コンデンサCo→ダイオードD1を介して流れる。このとき、MOSFETQ2のゲート・ソース間には3次巻線電圧V3が印加され、MOSFETQ2がオンする。MOSFETQ3のゲート・ソース間はダイオードD4がオンしていることによりオフ状態となる。
【0011】
【発明が解決しようとする課題】
現在、CPU(中央処理装置)の動作電圧は1.5V〜2.5Vと低下してきており、これに伴ってCPUに電力を供給する電源の出力電圧も1.5V〜2.5Vと低圧になっている。一方、電力用のMOSFETのゲート電圧には5〜10Vの電圧が必要である。これに対し、図3に示す回路ではトランス2次電圧が2〜5Vと低く、そのため、MOSFETを充分に駆動できないという問題がある。
【0012】
一方、図4に示す回路ではトランスに3次巻線が必要で、トランスが大型化するという問題がある。つまり、これらの装置に使用されるトランスは一般に、巻線にプリント板を使用したプレーナトランスが使用されるため、3次巻線を設けることはトランスの大型化につながり、高価になるという訳である。
【0013】
したがって、この発明の課題は、小型かつ安価に高効率化を実現することにある。
【0014】
【課題を解決するための手段】
このような課題を解決するため、請求項1の発明では、同期整流回路の整流素子としてオン抵抗素子としてのMOSFETを用い、MOSFETのドレインとソース間には第1ダイオードと第1コンデンサとを直列に接続した第1の直列回路を、MOSFETのドレインと第1コンデンサ間には第2ダイオードと第2コンデンサとを直列に接続した第2の直列回路を、MOSFETのソースと第2コンデンサ間には第3ダイオードと第3コンデンサとの直列回路をそれぞれ接続し、MOSFETに印加される電圧にて第3コンデンサを倍圧充電することにより、第3コンデンサに充電される電圧でMOSFETを駆動可能にしたことを特徴とする。
【0015】
上記請求項1の発明では、前記第1,第2の直列回路を組として複数組用いてMOSFETに印加される電圧を複数倍に昇圧し、MOSFETの駆動電力とすることができ、(請求項2の発明)、または、前記第3コンデンサと並列にP型MOSFETとN型MOSFETの直列回路と第1,第2抵抗の直列回路とをそれぞれ接続するとともに、第1,第2抵抗の直列接続点をP型MOSFET,N型MOSFETの各ゲートに、また、P型MOSFET,N型MOSFETの各ゲートとMOSFETのドレイン間をダイオードを介してそれぞれ接続し、MOSFETの電圧状態によりMOSFETのゲートにP型またはN型MOSFETのいずれかを接続して充,放電することができる(請求項3の発明)。
【0016】
すなわち、MOSFETQ4のドレイン・ソース間に印加される電圧は、ダイオードD6とコンデンサC3との第1直列回路のコンデンサC3に充電される。MOSFETQ4のドレイン・ソース間の電圧が零になると、ダイオードD7とコンデンサC4との第2直列回路により、コンデンサC3に充電された電圧がコンデンサC4に移される。次に、MOSFETQ4のドレイン・ソース間に電圧が印加されると、コンデンサC5にはMOSFETQ4の電圧とコンデンサC4の電圧とが加わって充電される。この電圧をMOSFETQ4の駆動電力として利用することにより、低電圧出力の整流回路においてもMOSFETを充分駆動できるようにする。
【0017】
【発明の実施の形態】
図1はこの発明の実施の形態を示す回路図である。
【0018】
図示のように、MOSFETQ4とダイオードD5の並列回路にはダイオードD6とコンデンサC3との直列回路が、コンデンサC3とMOSFETQ4のドレイン間にはダイオードD7とコンデンサC4との直列回路が、コンデンサC4とMOSFETQ4のソース間にはダイオードD8とコンデンサC5との直列回路が、コンデンサC5にはMOSFETQ5とQ6との直列回路および抵抗R3とR4との直列回路がそれぞれ接続され、さらに、MOSFETQ5とQ6との接続点にはMOSFETQ4のゲートが、抵抗R3とR4との接続点にはMOSFETQ5とQ6の各ゲートがそれぞれ接続され、また、MOSFETQ5とQ6の各ゲートとMOSFETQ4のドレイン間にはダイオードD9が接続されて構成されている。
【0019】
図1の回路において、MOSFETQ4に電圧VQ4が印加された場合、ダイオードD6を介してコンデンサC3が電圧VQ4に充電される。MOSFETQ4の電圧VQ4が零になると、ダイオードD7,MOSFETQ4を介してコンデンサC4がコンデンサC3の電圧で充電される。次に、MOSFETQ4に電圧VQ4が印加されると、コンデンサC4とMOSFETQ4のVQ4電圧がダイオードD8を介してコンデンサC5に充電される。したがって、コンデンサC5の電圧は電圧VQ4の倍電圧となる。
【0020】
また、ダイオードD5がオンするとダイオードD9が導通し、MOSFETQ5,Q6のゲートはともに負電位となるが、MOSFETQ5はP型MOSFETであるためオンし、MOSFETQ6はN型MOSFETであるためオフする。その結果、MOSFETQ4のゲートにはMOSFETQ5を介してコンデンサC5の電圧が印加され、Q4がオンする。
【0021】
MOSFETQ4に電圧が印加されるとダイオードD9がオフし、MOSFETQ5のソース・ゲート間にはコンデンサC5の電圧を抵抗R3とR4で分圧した電圧が印加され、MOSFETQ6のゲート・ソース間にもコンデンサC5の電圧を抵抗R3とR4で分圧した電圧が印加される。すると、MOSFETQ5はP型MOSFETであるためオフし、MOSFETQ6はN型MOSFETであるためオンする。その結果、MOSFETQ4のゲートはMOSFETQ6を介して放電し、Q4がオフする。
【0022】
このように、図1の駆動回路では、ダイオードD5がオンするとMOSFETQ4がオンし、ダイオードD5がオフするとMOSFETQ4がオフするので、MOSFETをダイオード(整流素子)と同等に用いることができる。
【0023】
図2に上記のような駆動回路2,3をフォワードコンバータに適用した場合の構成例を示す。
【0024】
図示のように、トランス1の1次巻線には直列にMOSFETQ1が、トランス1の2次巻線にはMOSFETQ2とQ3との直列回路が、MOSFETQ2,Q3にはそれぞれ並列にダイオードD1と駆動回路2,ダイオードD2と駆動回路3が、MOSFETQ2には並列にリアクトルL1とコンデンサCoとの直列回路がそれぞれ接続されている。
【0025】
図2の回路でも、ダイオードがオンするとMOSFETがオンし、ダイオードがオフするとMOSFETがオフするため、MOSFETをダイオードと同じように使用することができる。また、出力電圧が1.5V〜2.5Vと低圧でトランス2次電圧が2〜5Vと低い場合でも、MOSFET駆動電圧は倍電圧に昇圧されるため4〜10Vと高い電圧で駆動することが可能である。さらに、図1のダイオードD6とコンデンサC3との直列回路、ダイオードD7とコンデンサC4との直列回路を複数個設けることで、複数倍に昇圧することもできる。
【0026】
【発明の効果】
この発明によれば、トランス2次電圧が2〜5Vと低い場合でも、倍電圧の4〜10Vの駆動電圧でMOSFETを駆動できるため、オン電圧を充分小さくでき、発生損失を低減し得ると言う利点がある。
【0027】
また、トランスに3次巻線を巻く必要がないので、装置の小型化を実現することができる。さらに、駆動回路を集積化すればダイオードと同じように2端子素子として使用でき、回路間の配線の簡素化、組み立て工数の低減化、装置の低価格化などが可能となる。
【図面の簡単な説明】
【図1】この発明の実施の形態を示す回路図である。
【図2】この発明のフォワードコンバータへの適用例を示す構成図である。
【図3】第1の従来例を示す回路図である。
【図4】第2の従来例を示す回路図である。
【符号の説明】
1…トランス、2,3…駆動回路、Q1〜Q6…金属酸化物半導体型電界効果トランジスタ(MOSFET)、D1〜D9…ダイオード、L1…リアクトル、R1〜R4…抵抗、Co〜C5…コンデンサ。
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an improvement in a low-voltage output synchronous rectifier circuit, and more particularly to a synchronous rectifier circuit capable of improving efficiency.
[0002]
[Prior art]
FIG. 3 shows a first conventional example of a synchronous rectifier circuit.
[0003]
This is known as US Pat. No. 5,528,482, and a metal oxide semiconductor field effect transistor (MOSFET) Q1 is connected to the primary winding N1 of the transformer 1 and the secondary winding N2 of the transformer 1. Are connected in series to MOSFETs Q2 and Q3, diodes D1 and D2 are connected in parallel to MOSFETs Q2 and Q3, respectively, and a series circuit of a reactor L1 and a capacitor Co is connected in parallel to MOSFET Q2.
[0004]
In this circuit, when MOSFET Q1 is on, voltage V1 is applied to primary winding N1 of transformer 1 in the direction of the solid line arrow, and voltage V2 is applied to secondary winding N2 in the direction of the solid line arrow. . In addition, the current i L that has flowed through the reactor L1 flows through the capacitor Co → the diode D2 → the transformer secondary winding N2. At this time, the secondary winding voltage V2 is applied between the gate and source of the MOSFET Q3, and the MOSFET Q3 is turned on. Since the diode D2 and the MOSFET Q3 are turned on between the gate and the source of the MOSFET Q2, the voltage becomes zero and the circuit is turned off.
[0005]
Next, when MOSFET Q1 is OFF, voltage V1 is applied to primary winding N1 of transformer 1 in the direction of the dotted arrow, and voltage V2 is applied to secondary winding N2 in the direction of the dotted arrow. In addition, the current i L that has flowed through the reactor L1 flows through the capacitor Co → the diode D1. At this time, the secondary winding voltage V2 is applied between the gate and source of the MOSFET Q2, and the MOSFET Q2 is turned on. A transformer secondary voltage V2 is applied in the reverse bias direction between the gate and source of the MOSFET Q3, and the MOSFET Q3 is turned off.
[0006]
The diode has a PN junction threshold voltage and is a forward voltage of about 0.5 to 1 V. However, since the MOSFET is a unipolar device and has no threshold voltage and is an on-resistance element, the on-voltage is set to 0.1 V. Can also be reduced. For example, in a power supply of 3V output, the forward voltage of 1V is reduced by 25% at 1V / (3V + 1V), but if this can be reduced to 0.1V, 3% at 0.1V / (3V + 0.1V) The efficiency is reduced and the efficiency of the apparatus can be increased.
[0007]
FIG. 4 shows a second conventional example of a synchronous rectifier circuit.
[0008]
This is known as Japanese Patent Application Laid-Open No. 08-223906. The difference from FIG. 3 is that the transformer 1 is provided with a tertiary winding N3 and the gates of the MOSFETs Q2 and Q3 are driven by the tertiary winding. The MOSFET Q2 has a gate connected to a resistor R1 and a capacitor C1 filter circuit and a diode D3, and the MOSFET Q3 has a gate connected to a resistor R2 and a capacitor C2 filter circuit and a diode D4.
[0009]
In the circuit of FIG. 4, when MOSFET Q1 is on, voltage V1 is applied to primary winding N1 of transformer 1 in the direction of the solid line arrow, and voltage V3 is applied to tertiary winding N3 in the direction of the solid line arrow. Is done. In addition, the current i L that has flowed through the reactor L1 flows through the capacitor Co → the diode D2 → the transformer secondary winding N2. At this time, the tertiary winding voltage V3 is applied between the gate and source of the MOSFET Q3, and the MOSFET Q3 is turned on. Since the diode D3 is turned on between the gate and the source of the MOSFET Q2, the voltage becomes zero and the device is turned off.
[0010]
Next, when MOSFET Q1 is off, voltage V1 is applied to primary winding N1 of transformer 1 in the direction of the dotted arrow, and voltage V3 is applied to tertiary winding N3 in the direction of the dotted arrow. In addition, the current i L that has flowed through the reactor L1 flows through the capacitor Co → the diode D1. At this time, the tertiary winding voltage V3 is applied between the gate and source of the MOSFET Q2, and the MOSFET Q2 is turned on. The gate and the source of the MOSFET Q3 are turned off when the diode D4 is turned on.
[0011]
[Problems to be solved by the invention]
At present, the operating voltage of the CPU (central processing unit) has been lowered to 1.5V to 2.5V, and accordingly, the output voltage of the power source that supplies power to the CPU is also lowered to 1.5V to 2.5V. It has become. On the other hand, a voltage of 5 to 10 V is required for the gate voltage of the power MOSFET. On the other hand, the circuit shown in FIG. 3 has a problem that the transformer secondary voltage is as low as 2 to 5 V, so that the MOSFET cannot be driven sufficiently.
[0012]
On the other hand, the circuit shown in FIG. 4 requires a tertiary winding in the transformer, which increases the size of the transformer. In other words, the transformer used in these devices is generally a planar transformer using a printed board as the winding, so providing a tertiary winding leads to an increase in size of the transformer and is expensive. is there.
[0013]
Accordingly, an object of the present invention is to realize high efficiency in a small size and at a low cost.
[0014]
[Means for Solving the Problems]
In order to solve such a problem, in the invention of claim 1, a MOSFET as an on-resistance element is used as a rectifying element of a synchronous rectifier circuit, and a first diode and a first capacitor are connected in series between the drain and source of the MOSFET. A second series circuit in which a second diode and a second capacitor are connected in series between the drain of the MOSFET and the first capacitor is connected between the source of the MOSFET and the second capacitor. A series circuit of a third diode and a third capacitor is connected to each other, and the third capacitor is double-charged with a voltage applied to the MOSFET, so that the MOSFET can be driven with the voltage charged to the third capacitor. It is characterized by that.
[0015]
In the first aspect of the present invention, the voltage applied to the MOSFET can be boosted multiple times by using a plurality of the first and second series circuits as a set to obtain the driving power of the MOSFET. 2), or a series circuit of a P-type MOSFET and an N-type MOSFET and a series circuit of first and second resistors, respectively, in parallel with the third capacitor, and a series connection of first and second resistors. The points are connected to the gates of the P-type MOSFET and N-type MOSFET, and the gates of the P-type MOSFET and N-type MOSFET and the drain of the MOSFET are connected via a diode. Either type or N-type MOSFET can be connected and charged and discharged (invention of claim 3).
[0016]
That is, the voltage applied between the drain and source of the MOSFET Q4 is charged in the capacitor C3 of the first series circuit of the diode D6 and the capacitor C3. When the voltage between the drain and source of MOSFET Q4 becomes zero, the voltage charged in capacitor C3 is transferred to capacitor C4 by the second series circuit of diode D7 and capacitor C4. Next, when a voltage is applied between the drain and source of the MOSFET Q4, the capacitor C5 is charged with the voltage of the MOSFET Q4 and the voltage of the capacitor C4. By using this voltage as the driving power for the MOSFET Q4, the MOSFET can be sufficiently driven even in a rectifier circuit with a low voltage output.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a circuit diagram showing an embodiment of the present invention.
[0018]
As shown, a series circuit of a diode D6 and a capacitor C3 is provided in a parallel circuit of the MOSFET Q4 and the diode D5, and a series circuit of a diode D7 and a capacitor C4 is provided between the drains of the capacitor C3 and the MOSFET Q4. A series circuit of a diode D8 and a capacitor C5 is connected between the sources. A series circuit of MOSFETs Q5 and Q6 and a series circuit of resistors R3 and R4 are connected to the capacitor C5. Further, a connection point between the MOSFETs Q5 and Q6 is connected. Is configured such that the gate of the MOSFET Q4 is connected to each other, the gates of the MOSFETs Q5 and Q6 are connected to the connection point between the resistors R3 and R4, and the diode D9 is connected between the gates of the MOSFETs Q5 and Q6 and the drain of the MOSFET Q4. ing.
[0019]
In the circuit of FIG. 1, when the voltage V Q4 is applied to the MOSFET Q4, the capacitor C3 is charged to the voltage V Q4 via the diode D6. When the voltage V Q4 of the MOSFET Q4 becomes zero, the capacitor C4 is charged with the voltage of the capacitor C3 via the diode D7 and the MOSFET Q4. Next, when the voltage V Q4 is applied to the MOSFET Q4, the capacitor C4 and the V Q4 voltage of the MOSFET Q4 are charged to the capacitor C5 via the diode D8. Therefore, the voltage of the capacitor C5 is a double voltage of the voltage VQ4 .
[0020]
When the diode D5 is turned on, the diode D9 is turned on, and the gates of the MOSFETs Q5 and Q6 both have a negative potential. However , the MOSFET Q5 is turned on because it is a P-type MOSFET, and the MOSFET Q6 is turned off because it is an N-type MOSFET. As a result, the voltage of the capacitor C5 is applied to the gate of the MOSFET Q4 via the MOSFET Q5, and the Q4 is turned on.
[0021]
When a voltage is applied to the MOSFET Q4, the diode D9 is turned off, a voltage obtained by dividing the voltage of the capacitor C5 by the resistors R3 and R4 is applied between the source and gate of the MOSFET Q5, and the capacitor C5 is also connected between the gate and source of the MOSFET Q6. Is divided by resistors R3 and R4. Then, the MOSFET Q5 is turned off because it is a P-type MOSFET, and the MOSFET Q6 is turned on because it is an N-type MOSFET. As a result, the gate of MOSFET Q4 is discharged via MOSFET Q6, and Q4 is turned off.
[0022]
Thus, in the drive circuit of FIG. 1, MOSFET Q4 is turned on when diode D5 is turned on, and MOSFET Q4 is turned off when diode D5 is turned off, so that the MOSFET can be used in the same manner as a diode (rectifier element).
[0023]
FIG. 2 shows a configuration example when the drive circuits 2 and 3 as described above are applied to a forward converter.
[0024]
As shown, a MOSFET Q1 is connected in series to the primary winding of the transformer 1, a series circuit of MOSFETs Q2 and Q3 is connected to the secondary winding of the transformer 1, and a diode D1 and a driving circuit are connected in parallel to the MOSFETs Q2 and Q3, respectively. 2, a diode D2 and a drive circuit 3, and a series circuit of a reactor L1 and a capacitor Co are connected in parallel to the MOSFET Q2.
[0025]
Also in the circuit of FIG. 2, the MOSFET is turned on when the diode is turned on, and the MOSFET is turned off when the diode is turned off. Therefore, the MOSFET can be used in the same manner as the diode. Even when the output voltage is as low as 1.5 to 2.5 V and the transformer secondary voltage is as low as 2 to 5 V, the MOSFET drive voltage is boosted to a double voltage, so that it can be driven at a high voltage of 4 to 10 V. Is possible. Further, by providing a plurality of series circuits of the diode D6 and the capacitor C3 and a series circuit of the diode D7 and the capacitor C4 in FIG.
[0026]
【The invention's effect】
According to the present invention, even when the transformer secondary voltage is as low as 2 to 5 V, the MOSFET can be driven with a drive voltage of 4 to 10 V, which is the double voltage, so that the on-voltage can be sufficiently reduced and the generated loss can be reduced. There are advantages.
[0027]
Further, since it is not necessary to wind a tertiary winding around the transformer, it is possible to reduce the size of the apparatus. Further, if the drive circuit is integrated, it can be used as a two-terminal element like a diode, and the wiring between the circuits can be simplified, the number of assembly steps can be reduced, and the cost of the apparatus can be reduced.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing an embodiment of the present invention.
FIG. 2 is a block diagram showing an application example of the present invention to a forward converter.
FIG. 3 is a circuit diagram showing a first conventional example.
FIG. 4 is a circuit diagram showing a second conventional example.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Transformer, 2, 3 ... Drive circuit, Q1-Q6 ... Metal oxide semiconductor type field effect transistor (MOSFET), D1-D9 ... Diode, L1 ... Reactor, R1-R4 ... Resistance, Co-C5 ... Capacitor.

Claims (3)

同期整流回路の整流素子としてオン抵抗素子としてのMOSFETを用い、MOSFETのドレインとソース間には第1ダイオードと第1コンデンサとを直列に接続した第1の直列回路を、MOSFETのドレインと第1コンデンサ間には第2ダイオードと第2コンデンサとを直列に接続した第2の直列回路を、MOSFETのソースと第2コンデンサ間には第3ダイオードと第3コンデンサとの直列回路をそれぞれ接続し、MOSFETに印加される電圧にて第3コンデンサを倍圧充電することにより、第3コンデンサに充電される電圧でMOSFETを駆動可能にしたことを特徴とする同期整流回路。A MOSFET as an on-resistance element is used as a rectifier of the synchronous rectifier circuit, and a first series circuit in which a first diode and a first capacitor are connected in series between the drain and source of the MOSFET is connected to the drain of the MOSFET and the first A second series circuit in which a second diode and a second capacitor are connected in series is connected between the capacitors, and a series circuit of a third diode and a third capacitor is connected between the source of the MOSFET and the second capacitor, respectively. A synchronous rectifier circuit characterized in that a MOSFET can be driven by a voltage charged in a third capacitor by double-charging the third capacitor with a voltage applied to the MOSFET. 前記第1,第2の直列回路を組として複数組用いてMOSFETに印加される電圧を複数倍に昇圧し、MOSFETの駆動電力とすることを特徴とする請求項1に記載の同期整流回路。2. The synchronous rectifier circuit according to claim 1, wherein a plurality of sets of the first and second series circuits are used to boost a voltage applied to the MOSFET by a plurality of times to obtain driving power for the MOSFET. 前記第3コンデンサと並列にP型MOSFETとN型MOSFETの直列回路と第1,第2抵抗の直列回路とをそれぞれ接続するとともに、第1,第2抵抗の直列接続点をP型MOSFET,N型MOSFETの各ゲートに、また、P型MOSFET,N型MOSFETの各ゲートとMOSFETのドレイン間をダイオードを介してそれぞれ接続し、MOSFETの電圧状態によりMOSFETのゲートにP型またはN型MOSFETのいずれかを接続して充,放電することを特徴とする請求項1に記載の同期整流回路。A series circuit of a P-type MOSFET and an N-type MOSFET and a series circuit of first and second resistors are connected in parallel with the third capacitor, respectively, and the series connection point of the first and second resistors is connected to the P-type MOSFET, N The gates of the P-type MOSFETs and the gates of the P-type MOSFETs and N-type MOSFETs and the drains of the MOSFETs are respectively connected via diodes. 2. The synchronous rectifier circuit according to claim 1, wherein the two are connected to charge and discharge.
JP2001309422A 2001-10-05 2001-10-05 Synchronous rectifier circuit Expired - Fee Related JP3818435B2 (en)

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JP4926100B2 (en) * 2008-03-21 2012-05-09 三菱電機株式会社 Rectifier
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