JP3817447B2 - Memory circuit block - Google Patents

Description

[0001]
[Technical field to which the invention belongs]
The present invention relates to a memory circuit block and a memory method for writing data by current driving. In particular, the present invention relates to a memory circuit block and a memory method that share one current path for data writing of a plurality of memory cells by connecting bit lines to which memory cells to which data is to be written belong.
[0002]
[Prior art]
For a magnetic random access storage device, FIG. 7 shows a side view of a conventional memory cell.
[0003]
FIG. 7 shows a conventional 1T (1Transistor) 1MTJ (1 Magnetic Tunnel Junction) type memory cell 700 used for a 1 Kbit MRAM chip and a 512 bit MRAM chip.
[0004]
The MTJ element 728 has a pinned magnetic layer 726 that is a ferromagnetic layer whose magnetization direction is fixed, a tunnel barrier 724 that is an insulating layer through which a tunnel current passes, and a magnetization direction that depends on the magnetization direction from the outside. A data non-volatile memory element composed of at least three thin films including a free ferromagnetic layer 722 that is a changing ferromagnetic layer (however, the positions of the free ferromagnetic layer 722 and the pinned magnetic layer 726 are reversed). It may be)
[0005]
A bit line 744 electrically connected to the MTJ element 728 is used as a line for a read operation and a write operation. The MTJ element 728 and the diffusion region n of the drain (D) of the MOSFET 718 are connected via a first wiring structure 717 composed of MX, V2, M2, V1, M1, and CA in the drawing. MX, M1, and M2 are metal wire layers, and V1, V2, and CA are holes in which a hole (via hole) is formed in the insulating layer, and the body is embedded in the hole. The gate of the MOSFET 718 is a read word line 720, and when a voltage is applied to the read word line 720 during a read operation, the MOSFET 718 is turned on. As a result, a current path from the bit line 744 to the ground 731 is formed via the MTJ element 728.
[0006]
The resistance of the MTJ element 728 is determined by the magnetization direction of the free ferromagnetic layer 722 with respect to the magnetization direction of the pinned magnetic layer 726, and is determined by the value of the read current flowing through the resistance of the MTJ element 728, or its resistance and current. The data stored in the MTJ element 728 is read according to the voltage value. For example, if the magnetization direction of the free ferromagnetic layer 722 is the same as the magnetization direction of the pinned magnetic layer 726, it is “0”, and if it is opposite, it is “1”.
[0007]
A cell called a twin cell is known for such a typical 1T1MTJ type cell.
[0008]
FIG. 8 is a diagram showing a conventionally known 2T2MTJ (2Transistor 2Magnetic Tunnel Junction) type memory cell, a so-called twin cell 800. As shown in FIG. This is an MRAM memory cell using two MTJ elements and two transistors, and the principle of one memory circuit is the same as in FIG. 7, so the same components as those in FIG. The description is omitted. Note that “′” is attached to the reference numerals of the constituent elements of adjacent memory circuits to distinguish the memory circuits. A feature of this type of memory cell is that there is a number of bit lines corresponding to the storage circuit for one cell.
[0009]
In this type of memory cell, for example, a write current path is configured in a loop shape, and a current is flown in an opposite direction to adjacent memory circuits in the cell to write data opposite to each other. Moreover, the magnitude of noise can be suppressed thereby. That is, it has a double driving capability at substantially the same current value. At the time of reading, data opposite to each other is taken out from each storage circuit as a differential signal in each of the T bit line (true bit line) and the C bit line (complement bit line), so that the read signal is 1T1MTJ cell. This makes it possible to read noise-resistant. However, the current path does not need to be configured as a loop, and writing can be performed if current flows through the T-bit line 744 and the C-bit line 744 'in the opposite directions.
[0010]
FIG. 9 is a block diagram of the storage block of the MRAM using this twin cell. In this write circuit, when a drive current IWL flows through a write word line 716 corresponding to a row and a current flows through both bit lines corresponding to a column, a magnetic field generated in a memory cell at the intersection. Data is written depending on the direction of the.
Here, logical data “0” and “1” are written separately depending on the direction of the current flowing through the bit line.
[0011]
In FIG. 9, since the bit lines 744 and 744 'connected to the write current drive circuit 910 on the right side of the drawing are connected in a loop, the current direction of the T bit line 744 and the C bit line The direction of the current 744 ′ is opposite to the cell 800.
[0012]
In this configuration, for example, as shown in the figure, when a current flows in a direction from the T bit line 744 to the C bit line 744 ′, “1” is written, and in the opposite case (the left side in the figure). Can be written as “0”.
[0013]
[Problems to be solved by the invention]
However, in the configuration as shown in FIG. 9, for example, when data is simultaneously written to a plurality of data bits belonging to the same column address, it is necessary to pass a current for each bit line, so that the current required for writing increases. There is a problem.
[0014]
For example, in a 1 Kbit MRAM, it is known that the current required to flow through the bit line in order to obtain a desired magnetic field and perform stable writing is about 10 mA.
[0015]
Therefore, when simultaneously writing a plurality of bits of data, if a driving circuit is prepared according to each bit of data as in a conventional semiconductor memory device, n times as much current is required to write n bits of data. . For example, if the word length is 64 bits, the current required for writing exceeds 600 mA.
[0016]
This value is quite large, and since this value is an average current value, the peak current is several times that and the temporal change in current is large. Further, this causes generation of noise due to inrush current and an increase in load on the power supply circuit.
[0017]
[Means for Solving the Problems]
A memory circuit block according to the present invention includes a plurality of bit line pairs including a first bit line and a second bit line, and a plurality of information for storing information according to the direction of current flowing in the bit line pairs. A plurality of memory cells, at least one current driving source connected to at least one of the bit line pair, and passing currents in opposite directions to the first bit line and the second bit line, and the bit line It includes at least one switch circuit for connecting the pair and the bit line pair, and a control circuit for controlling the connection state of the switch circuit in accordance with information stored in the memory cell.
[0018]
In the memory circuit block according to the present invention, the bit line pairs may be connected in series, and the current path of the bit lines may be configured in a loop.
[0019]
The memory circuit block according to the present invention may be connected in series with a current path connecting the end of the first bit line and the second bit line in the bit line pair as a unit.
[0020]
The storage circuit block according to the present invention may store information in an MTJ (Magnetic Tunnel Junction) element.
[0021]
The memory cell may have a so-called twin cell configuration including two MTJs per bit.
[0022]
The storage method according to the present invention is connected to at least one of a plurality of bit line pairs including a first bit line and a second bit line, and the first bit line and the second bit line are connected. By means of a memory circuit block comprising at least one current drive source for flowing currents in opposite directions to the bit line, a switch circuit for connecting the bit line pair and a switch circuit control circuit for controlling the switch circuit, the bit circuit A method of storing information for a plurality of storage cells in which information is stored according to the direction of current flowing in a line pair, comprising: selecting a storage cell; and storing information in the selected storage cell And controlling the connection state of the switch circuit in response, the switch circuit connecting the bit line pair and the bit line pair, and a current drive source, Current driving source so that a current flows in the opposite direction to the connection has been first bit line and second bit line comprises flowing a current.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments relating to a circuit and method for reducing drive current in a magnetic random access memory (MRAM) that generates a magnetic field by an electric current and writes information according to the direction of the magnetic field will be described.
[0024]
In this embodiment, for example, when a memory array such as an MRAM having a long word length of 8 bits, 16 bits,... Is a circuit for reducing data and a method for storing data in an MRAM.
[0025]
It is an object of the present invention to share a single current path for data writing of a plurality of memory cells by connecting in series the bit lines to which the memory cells to which data is to be written belong. However, since it is necessary to write arbitrary data for each cell, the connection method is controlled by the data to be written.
[0026]
FIG. 1 is a configuration diagram of a storage block 10 showing an embodiment of the present invention. FIG. 1 shows an example of how bit lines are connected in series and an arrangement of switches for switching the connection.
[0027]
In FIG. 1, the 0th bit line pair, the (K-1) th bit line pair, and the Kth bit line pair as viewed from the write current drive circuit 12 are connected via the switch unit 20b. Bit line pair connection 18 and the final stage of the (n-1) th bit line pair.
[0028]
Since the connection state in the middle is the same, the switch portions 20a and 20c for connecting the pair of the C bit line 14 and the T bit line 15 are shown while omitting the middle.
[0029]
In FIG. 1, numbers are assigned from the 0th. Further, FIG. 1 clearly shows only bit lines belonging to the same column address corresponding to data bits to which data is simultaneously written, a part of memory cells, and a circuit related to writing.
[0030]
In the memory block 10, a write current driving circuit 12 and one end of a pair of a C bit line (Complement) 14 and a T bit line (True) 15 are connected. The T bit line 15 and the C bit line 14 are complementary to each other in current direction.
[0031]
The other end of the pair of the C bit line 14 and the T bit line 15 is connected to the C bit line 14 and the T bit line 15 through a switch.
[0032]
In the (n-1) th final stage through the connection part 18 of the bit line pair (pair), the end is connected to the C bit line 14 and the T bit line 15.
[0033]
The storage block 10 is configured such that current flows back to and from the write current drive circuit 12 by connecting the n−1th C bit line 14 and the T bit line 15 at the end. .
[0034]
Of course, the current source may be reinforced by providing a second current driving circuit without connecting the terminal end of the (n-1) th bit line pair.
[0035]
With this configuration, the operation of the storage block 10 in FIG. 1 will be described.
In FIG. 1, it is assumed that 1 is written in the selected memory cell when a current flows through the T bit line 15 downward in the figure.
The switch is placed on the lower side of the stored array between even numbered bit line pairs and one higher numbered bit line pair, and odd numbered bit line pairs and It is assumed that it is arranged above the storage cell array between the bit line pair numbered by one more.
[0036]
A circuit for driving a current for writing, that is, a write current driving circuit 12 is outside the bit line pair having the number 0 and is set to 0 in the selected storage cell on the bit line having the number 0. Depending on whether or not 1 is written, a signal line for sending out current is determined, and current is sucked in from the other line.
[0037]
With this arrangement, the current sent from the write current driving circuit flows from the top to the bottom for the even-numbered bit line pairs and from the bottom to the top for the odd-numbered bit line pairs. The current sucked into the write current drive circuit 12 is reversed.
[0038]
FIG. 2 is a diagram showing the bit / line pair connection unit 18 in the storage block 10 of FIG. The K-1th bit line pair and the Kth bit line pair are connected via the switch unit 20b.
In FIG. 2, the k-1 th C bit line 14 is replaced by a C bit line 14-1, the k th C bit line 14; Line C-bit line 15-2 , K−1 th T bit line 15 to T bit line 15 −1, k th T bit line 15 Line to T bit line 14-2 This is described with reference to the above.
[0039]
Of the word lines 26, 16, and 28, data is written into the memory cells 22 and 24 where the current flowing through the word line 16 and the current flowing through the bit line pair intersect.
[0040]
Assume that 0 is written to the selected storage cell 22 on the bit line having the even number k and 1 is written to the selected storage cell 24 on the bit line having the number k-1.
[0041]
In this case, the selected memory cell on the bit line with even number k 22 C bit line of the bit line pair to which 15-2 T-bit line with current flowing down 14-2 Therefore, it is necessary to pass a current sent from the write current drive circuit (write current drive circuit 12 in FIG. 1) through this C bit line.
[0042]
On the other hand, if it is on the bit line having the number k-1, the selected memory cell 24 Since it is necessary to pass an upward current to the C bit line 14-1 and a downward current to the T bit line 15-1 of the bit line pair to which the C bit line 14-1 belongs, the C bit line 14-1 Also write current drive circuit 12 The current sent out from flows.
[0043]
Accordingly, the switch 20b between the k-1th bit line pair and the kth bit line pair is connected to the C bit line 14-1 (BLCK-1) and the C bit line. 15-2 (BLCk) and T bit line 15-1 (BLTk-1) and T bit line 14-2 (BLTk) is connected.
[0044]
Since there are only four combinations of data to be written in the memory cell 22 and the memory cell 24, when considering the other three cases in the same way, when writing different data to the memory cell 22 and the memory cell 24, the T bit line It can be seen that when the same data is written by connecting the C-bit lines and the C-bit lines, the T-bit line and the C-bit line may be connected.
[0045]
The above is the case of a switch between a bit line pair having an odd number and a bit line pair having a higher number, but a bit line pair having an even number and a bit having a higher number than that. It can be seen that the same control can be applied to the switch between the line pair.
[0046]
FIG. 3 is a configuration diagram of a memory circuit block 30 according to another embodiment of the present invention.
In the storage block 30 in FIG. 3, the pair of C bit line 14 and T bit line 15 is configured as a unit of a loop having terminal ends connected.
In FIG. 3, the 0th bit line pair, the (K-1) th bit line pair, and the Kth bit line pair as viewed from the write current drive circuit 12 are connected via the switch unit 36c. Bit line pair connection 40 and the (n-1) th last stage are described. A switch part 36b or 36d for connecting the pair of the C bit line 14 and the T bit line 15 with the middle omitted is also shown.
[0047]
In FIG. 3, as in FIG. 1, numbers are assigned from the 0th. Also in FIG. 3, only the bit line belonging to the same column address corresponding to the data bit to which data is simultaneously written, a part of the memory cell, and a circuit related to writing are clearly shown in FIG.
[0048]
One end of the write current drive circuit 12 and the 0th C-bit line 14 or T-bit line 15 are connected in a switchable state by the switch unit 36a. The other end of the write current driving circuit 12 and the (n-1) th C bit line 14 or T bit line 15 are connected in a state that can be switched by the switch unit 36e.
[0049]
For the 1st to (n-1) th C bit line 14 and T bit line 15 pairs, the C bit line 14 and T bit line 15 pairs are switched between each other, with the loop connecting the terminations as a unit. Connected through.
[0050]
The bit line pair at the final stage is also connected to the switch unit 36d, but the connection state in the middle is repeated and is omitted as in FIG.
[0051]
With this configuration, the operation of the storage block 30 in FIG. 3 will be described.
Assuming that a current flows through the word line 16, data is written at the intersection of the word line and the bit line pair through which the current flows.
[0052]
Since the T side and the C side are connected at the lower end of the bit line pair, when the current flows from the T bit line 15 and the current flows from the C bit line 14, 1 is selected in the selected memory cell. Written, and vice versa, 0 is written.
[0053]
Here, the switch unit 36c between the bit line pair having the number k-1 and the bit line pair having the number k is called a switch SWk, and the write current driving circuit and the bit line pair having the number 0 are connected to each other. The switch unit 36a between them is referred to as SW0, and the switch unit 36d between the bit line pair having the number n-1 and the write current drive circuit 12 is referred to as SWn.
[0054]
It is assumed that the write current drive circuit 12 sends out current from the lower terminal and sucks current from the upper terminal when writing any data.
Under which the setting is made, the switch unit 36a (SW0) is to be tilted depending on whether 0 or 1 is written in the selected memory cell on the bit line having the number 0.
[0055]
The switch 36c (SWk) controls the data to be written to the selected memory cell on the bit line having the number k-1 and the selected memory cell on the bit line having the number k. It depends on the data to be written.
[0056]
In addition, the switch unit 36e (SWn) is defeated depending on whether 0 or 1 is written in the selected memory cell on the bit line having the number n. Thus, each switch is controlled by the data to be written.
[0057]
FIG. 4 is a diagram showing a bit line pair connection unit 40 that indicates connection with the K-1th bit line pair and the Kth bit line pair in the storage block 30 of FIG.
[0058]
In FIG. 4, the k-1 th C bit line 14 is a C bit line 14-1, the k th C bit line 14 is a C bit line 14-2, and the k-1 th T bit line. Reference numeral 15 denotes a T bit line 15-1, and a kth T bit line 15 is indicated as a T bit line 15-2.
[0059]
Consider the case where 0 is written to the selected memory cell on the bit line having the number k and 1 is written to the selected memory cell on the bit line having the number k-1.
[0060]
Since 0 is written to the selected storage cell on the bit line having the number k, current flows from the C bit line 14-2 in the bit line pair having the number k, and the T bit line 15- Current must flow out of 2.
[0061]
Since the current flows from the bit line pair with the smaller number, the C bit line 14-2 (BLCk) is set to the T bit line 15-1 (BLTk-1) or C bit in the switch section 36c (SWk). • It must be connected to line 14-1 (BLCk-1).
[0062]
On the other hand, since 1 is written to the selected memory cell on the bit line having the number k-1, current flows from the bit line on the T side in the bit line pair having the number k-1. Current must flow out on the C-side bit line.
[0063]
From the above, the switch unit 36c (SWk) connects the C bit line 14-1 (BLCk-1) and the C bit line 14-2 (BLCk), and the T bit line 15-1 (BLTk-1) Neither T-bit line 15-2 (BLTk) nor C-bit line 14-2 (BLCk) is connected.
[0064]
FIG. 5 is an example of a specific circuit diagram of the switch units 20a, 20b, and 20c in FIG.
In FIG. 1, the way of connecting the switches depends on whether the same data is written in different memory cells or different data is written. Therefore, the switch control circuit can be configured by using a coincidence circuit (EXNOR) or an anti-coincidence circuit (EXOR) that receives adjacent data bits.
[0065]
The specific circuit of the switch shown in FIG. 5 includes a switch circuit control circuit 505 including an exclusive OR circuit 510 and a negation circuit 520, and a switch circuit 525 including MOSFETs 530 to 560.
[0066]
Hereinafter, the switch of FIG. 5 is assumed to be the switch unit 20b in FIGS. 1 and 2, and the same reference numerals as those of the bit lines shown in FIG. 2 are assumed to be the same.
[0067]
The switch unit 20b is connected to the 2-input exclusive OR circuit of the (k-1) th data input 500 and the kth data input 502, and the negation circuit 520 connected to the output of the exclusive OR circuit and inverting the output, An NMOSFET 540 that connects the C bit lines 14-1 and 14-2, an NMOSFET 550 that connects the T bit lines 15-1 and 15-2, and a negation circuit 520 using the output of the exclusive OR circuit 510 as a gate input The NMOSFET 530 connecting the C bit line 14-1 and the T bit line 15-2 and the NMOSFET 560 connecting the T bit line 15-1 and the C bit line 14-2. .
[0068]
When the data input 500 and the data input 502 match, the output of the exclusive OR circuit is L, and therefore the output of the negation circuit 520 is H. Therefore, in this case, the C bit line 14-1 and the T bit line 15-2 are connected, and the C bit line 14-2 and the T bit line 15-1 are connected.
[0069]
As a result, the C bit lines 14-1 and 14-2 in FIG. 1 have the same current direction.
[0070]
Thus, the switch circuit control circuit 505 can control the connection state of the bit lines depending on the data to be written.
[0071]
Since there are only four combinations of data to be written in the memory cell 22 and the memory cell 24, when considering the other three cases in the same way, when writing different data to the memory cell 22 and the memory cell 24, T bit It can be seen that when the same data is written by connecting the lines and the C bit lines, the T bit line and the C bit line may be connected.
[0072]
This is the case for a switch between a bit line pair with an odd number and a bit line pair with a number greater than 1, but with a bit line pair with an even number and a number greater than one. The same control may be applied to a switch between a pair of bit lines.
[0073]
In the integrated circuit, the switch is actually composed of a MOS transistor or the like. Further, the other bit line pair connection units are not limited to the switch circuit unit 20b, and a circuit example for realizing the switch unit 20a and the switch unit 20c can be realized by the one shown in FIG.
[0074]
FIG. 6 is an example of a specific circuit diagram of the switch units 36b, 36c, and 36d in FIG. In FIG. 2, it is determined by the combination of data to be written in the selected memory cell belonging to the bit line pair on both sides of the switch, and the 2-bit data is decoded.
[0075]
The specific circuit of the switch unit shown in FIG. 6 includes a switch circuit control circuit 603 including negation circuits 604 and 606 and AND circuits 608 to 614, and a switch circuit 625 including MOSFETs 630 to 660. Yes.
[0076]
Hereinafter, the switch in FIG. 6 is assumed to be the switch unit 36c in FIGS. 3 and 4, and the same reference numerals as those of the bit lines shown in FIG. 4 are assumed to be the same.
[0077]
The switch unit 36c receives the k-1th data input 600 and the kth data input 602 as inputs, and negates circuits 604 and 606 that invert these inputs, and the data inputs 600 and 602 or negation circuits 604 and 606, respectively. AND circuits 608 to 614 having any two of the inverted input signals as inputs, and the C bit line 14-1 and the T bit line 15-2 using the output of the AND circuit 608 as gate inputs. NMOSFET 630 to be connected, NMOSFET 640 to connect C bit line 14-1 and C bit line 14-2 with the output of AND circuit 610 as the gate input, and T bit with the output of AND circuit 612 as the gate input NMOSFET 650 connecting line 15-1 and T-bit line 15-2; Configured to output the AND circuit 614 in the NMOSFET660 connecting the T bit lines 15-1 and C bit line 14-2 as a gate input.
[0078]
This switch section functions as a data decoder, and the outputs of the negation circuits 604 and 606 are connected to decoders for other data (not shown).
[0079]
The operation of the switch unit 36c will be described. When both the data inputs 600 and 602 are L, the output of the AND circuit 614 is H and the NMOSFET 660 is turned on. When both are H, the output of the AND circuit 608 is H and the NMOSFET 630 is Turn on.
[0080]
On the other hand, when the data input 600 is H and the data input 602 is L, the AND circuit 610 is H and the NMOSFET 640 is turned on. In the opposite case, the output of the AND circuit 612 is H and the NMOSFET 650 is turned on. Is turned on. In this way, the bit line pair connection is determined by the combination of the data.
[0081]
In the integrated circuit, the switch is actually composed of a MOS transistor or the like.
[0082]
Further, a circuit example for realizing each circuit of the switch units 36b and 36d as well as the switch unit 36c may be as shown in FIG.
[0083]
As described above, in the embodiment in which bit line pairs are connected in series, in the case of a memory device having an n-bit configuration in which writing is performed by current drive, the write current can be reduced to 1 / n. .
[0084]
Although the present invention has been specifically described based on the embodiments, the present invention is not limited to these specific examples. For example, even a single serial connection can have various changes in the connection method. Also, various selections and modifications can be made as to how many bit-line pairs are connected in series.
[0085]
For example, the number of bit line pairs connected in series is the maximum current value allowed for writing as a whole storage device, the resistance value of the bit line pair and the switch, the required writing speed, the configuration of the storage cell array, etc. Can be determined by. Further, in the case of a storage device having a 1-word / 64-bit configuration, a 16-bit bit line can be directly connected and four bit line drive circuits for writing can be provided.
[0086]
In the above figure, a twin cell having MTJ as a storage element is described as an example. However, the storage circuit block and the storage method of the present invention have such a twin cell and a plurality of storage elements. The memory cell is not limited. In short, one memory cell has two or more write bit lines and can be applied to any current-driven cell as long as each current can be controlled.
Accordingly, in particular, in interpreting the scope of claims, it is needless to say that the invention described in all claims should not be construed as limited to twin cells.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a storage block 10 according to the present invention.
FIG. 2 is a diagram showing a bit line pair connection unit 18;
FIG. 3 is a configuration diagram of a storage block 30 which is another embodiment of the storage block according to the present invention.
4 is a diagram illustrating a bit line pair connection unit 40. FIG.
FIG. 5 is a specific circuit diagram of a switch circuit.
FIG. 6 is a specific circuit diagram of a switch circuit.
FIG. 7 is a side view of a conventional memory cell.
FIG. 8 is a circuit configuration diagram of a conventional twin cell.
FIG. 9 is a configuration diagram of a storage block of a conventional twin cell.
[Explanation of symbols]
10 storage blocks
12 Write current drive circuit
14, 15 bit line
16 word lines
18-bit line pair connection
20a, 20b, 20c Switch part
22, 24 memory cells
26, 28 word lines
30 storage blocks
36a, 36b, 36c, 36d, 36e Switch part
40 bit line pair connection
500, 502 Data input
505 Control circuit for switch circuit
525 Switch circuit
530-560 MOSFET switch
600, 602 Data input
603 Control circuit for switch circuit
625 switch circuit
630-660 MOSFET switch
700 memory cells
713 Second wiring structure
716 Write word line
717 First wiring structure
718, 718 'switching element (MOSFET)
720 Read word line
722 Free ferromagnetic layer
724 Tunnel Barrier
726 Fixed magnetic layer
728, 728 ′ storage element (MTJ element)
730 Insulation area
744, 744 'bit line
800 twin cells
910 Write current drive circuit

Claims (2)

Multiple word lines,
  N bit line pairs arranged in a direction orthogonal to the plurality of word lines, each consisting of a C bit line and a T bit line, the bit lines of two adjacent bit line pairs Are arranged in the order of a C bit line, a T bit line, a C bit line, and a T bit line, and the C of the (n-1) th bit line pair among the n bit line pairs. The n bit line pairs, wherein only the lower ends of the bit line and the T bit line are connected to each other;
  An MTJ (magnetic tunnel junction) element disposed at each of intersections of the plurality of word lines and the n bit line pairs with the C bit line and the T bit line, An MTJ element at the intersection of a line and the C bit line of one bit line pair, and an intersection of the one word line and the T bit line of the one bit line pair The MTJ element constitutes one memory cell, and the MTJ element,
  A write current driving circuit connected to the upper ends of the C bit line and the T bit line of the 0th bit line pair, which is the first bit line pair among the n bit line pairs, When writing data 0 to a selected storage cell consisting of an MTJ element on the C bit line of the 0th bit line pair and an MTJ element on the T bit line of the 0th bit line pair, Send current to the C bit line and receive current from the T bit line, and send current to the T bit line and write current from the C bit line when writing data 1 to the selected storage cell. Receiving the write current drive circuit; and
  Of the n bit line pairs, the lower end of the 0th and even numbered bit line pairs excluding the (n-1) th bit line pair, and the next bit line pair of the bit line pair First switch means provided between the lower ends;
  Second switch means respectively connected between an upper end of an odd-numbered bit line pair of the n bit line pairs and an upper end of a next bit line pair of the bit line pair;
  When the first switch means and the second switch means write different data to two adjacent memory cells on one selected word line, one of the two storage cells Connecting a T bit line to a T bit line of the other storage cell of the two storage cells, and a C bit line of the one storage cell and a C bit line of the other storage cell; Connect
  The first switch means and the second switch means may write the same data to the two memory cells adjacent to each other on the selected one word line when the one of the two memory cells is written. Connecting the T bit line of the memory cell and the C bit line of the other memory cell, and connecting the C bit line of the one memory cell and the T bit line of the other memory cell. A memory circuit block characterized by the above. The MTJ element is characterized in that it comprises a layer of ferromagnetic material in which a magnetization direction according to the direction of the magnetic field generated by current flowing through the bit line is determined, stored according to claim 1 Circuit block.

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