JP3814488B2 - Negative booster circuit and nonvolatile semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a negative booster circuit that generates a boosted voltage of a negative voltage from a power supply voltage, and more particularly to a negative booster circuit incorporated in a booster power supply circuit of a nonvolatile semiconductor memory device and the nonvolatile semiconductor memory device.
[0002]
[Prior art]
Flash memory or EEPROM, which is a non-volatile semiconductor memory device, boosts the power supply voltage and generates negative voltage on-chip for a single power supply, and supplies an internal voltage necessary for writing, erasing, etc. A generation circuit is built-in. The internal voltage generation circuit is required to be highly efficient as the power supply voltage in the semiconductor integrated circuit is reduced and the power is saved.
As a conventional example of the negative booster circuit, for example, JP-A-11-265593 is cited.
[0003]
FIG. 15 shows a configuration example of a conventional negative booster circuit, and FIG. 16 shows an input clock waveform of the negative booster circuit.
In FIG. 15, M1 to M5 are N-type MOS transistors, and C1 to C4 are boost capacitors. The N-type MOS transistors M1 to M5 are diode-connected, the back gate is connected to the drain, and they are connected in series. The source of the N-type MOS transistor M1, which is one end of this transistor row, is connected to the ground potential VSS, and the drain of the N-type MOS transistor M5, which is the other end of the transistor row, is connected to the negative voltage output end. One end of the boost capacitor C1 is connected to the drain of the N-type MOS transistor M1, and the boost clock CLK1 is input to the other end. One end of the boost capacitor C2 is connected to the drain of the N-type MOS transistor M2, and the boost clock CLK2 is input to the other end. Similarly, one end of the booster capacitor C3 is connected to the drain of the N-type MOS transistor M3, the other end of the booster clock CLK1 is input, and the other end of the booster capacitor C4 is connected to the drain of the N-type MOS transistor M4. The boost clock CLK2 is input to the end.
[0004]
The operation of the conventional negative booster circuit configured as described above will be described below.
As shown in FIG. 16, boosted clocks CLK1 and CLK2 having opposite phases are input to the input terminal, and adjacent boosting capacitors are driven by clocks having opposite phases. For example, focusing on one N-type MOS transistor M2, when the boost clock CLK1 is L and the boost clock CLK2 is H, the node N2 is at a higher potential than the node N1, and the diode-connected N-type MOS transistor M2 is forward biased. As a result, a current flows in the direction from the boost capacitor C2 to the boost capacitor C1, charge is transferred between the boost capacitor C1 and the boost capacitor C2, and the drain potential of the N-type MOS transistor M2 is lowered. On the other hand, when the boost clock CLK1 is H and the boost clock CLK2 is L, the node N2 is at a lower potential than the node N1, and the diode-connected N-type MOS transistor M2 is reverse-biased, so that no current flows, Delivery is not performed. By repeating this charge transfer operation, the potential of the node N2 is lowered. In other words, in the conventional negative booster circuit, the operation as described above is performed in each of the N-type MOS transistors M1 to M5. As a result, a potential lower than the ground potential VSS, that is, a negative voltage is output from the output terminal VBB.
[0005]
[Problems to be solved by the invention]
However, in the conventional negative booster circuit, as shown in FIG. 17, the N-type MOS transistors M1 to M5 form an N-well on a P-type substrate, and further form a P-well therein, It is formed on a triple well structure on which the transistor Mi is formed. With this structure, the back gate and drain of the N-type MOS transistor can be connected.
[0006]
However, in this triple well structure, the parasitic NPN bipolar transistor Qi shown in FIG. 17 is included. When the base P well and the emitter N type diffusion layer are forward biased, the power supply of the collector N well is supplied. Current flows from the voltage VDD. This raises the potential of each of the nodes N1 to N4 and the output voltage VBB, and has the problem that the efficiency of the negative booster circuit decreases.
The present invention has been made to solve the above problems, and an object thereof is to provide a negative booster circuit with improved boosting efficiency.
[0007]
[Means for Solving the Problems]
In order to solve this problem, a negative booster circuit according to a first aspect of the present invention is a negative booster circuit including two booster cells formed of a plurality of booster cell columns connected in series. The boosting cell includes one or a plurality of N-type MOS transistors and one or a plurality of boosting capacitors, and a boosting clock is input to one end of the boosting capacitor, and the boosting cells in the facing boosting cell row face each other. A reverse phase boosting clock is input, and the back gate terminal of at least one N-type MOS transistor in the boosting cell is connected to the output terminal of the boosting cell one stage after the boosting cell in the facing boosting cell row. Is.
[0008]
The negative booster circuit according to claim 2 of the present invention is the negative booster circuit according to claim 1, wherein the last stage cell of the booster cell row is a diode connection in which a gate and a drain are connected, and a source is connected to the negative booster circuit. The first N-type MOS transistor is connected to the input terminal of the final stage cell, the drain is the output terminal of the negative booster circuit, and the diode is connected to the gate and the drain, and the source is the input terminal of the final stage cell. A second N-type MOS transistor having a back gate connected to the drain, a boost capacitor having one end connected to the drain of the second N-type MOS transistor and the other end serving as an input end of the boost clock. And the drain of the second N-type MOS transistor is used as a back bias output terminal, and the N-type MOS transistor in the boosting cell in the previous stage of the boosting cell row facing the second N-type MOS transistor Connect the back bias output to Kkugeto terminal, connects to the back bias output of the final stage cells of the boosting cell row facing the back gate of the first N-type MOS transistor.
[0009]
According to claim 3 of the present invention, in the negative booster circuit according to claim 1 or 2, the booster cell includes one N-type MOS transistor and one booster capacitor. The N-type MOS transistor has a diode connection in which the gate and the drain are connected, the source is the input terminal of the boosting cell, the drain is the output terminal of the boosting cell, the back gate is the back bias input terminal, One end is connected to the drain of the N-type MOS transistor, and the other end is used as an input end of a boost clock.
[0010]
A negative booster circuit according to a fourth aspect of the present invention is the negative booster circuit according to the first or second aspect, wherein the booster cell includes a first N-type MOS transistor and a second N-type MOS transistor. A first booster capacitor and a second booster capacitor; the first N-type MOS transistor has a source as an input terminal of the booster cell and a drain as an output terminal of the booster cell; The second N-type MOS transistor has one end of its current path connected to the drain of the first N-type MOS transistor, the other end of the current path connected to the gate of the first N-type MOS transistor, The gate of the second N-type MOS transistor is connected to the source of the first N-type MOS transistor, and one end of the first boost capacitor is connected to the drain of the first N-type MOS transistor. The other end of the second boosting capacitor is connected to the gate of the first N-type MOS transistor, and the other end is connected to the second boosting clock input end. It is a thing.
[0011]
A negative booster circuit according to a fifth aspect of the present invention is the negative booster circuit according to the fourth aspect, wherein the first booster clock input terminal is connected to the input terminal of the first booster cell of the booster cell string. A boost clock having a phase opposite to that of the input boost clock is input.
[0012]
A negative booster circuit according to a sixth aspect of the present invention is the negative booster circuit according to the fourth or fifth aspect, wherein the second boost clock input terminal of the boost cell is connected to a bootstrap circuit. The boosted clock boosted in this way is input.
[0013]
A negative booster circuit according to a seventh aspect of the present invention is the negative booster circuit according to any one of the first to sixth aspects, wherein the negative booster circuit generates a detection voltage determined based on a reference voltage. The voltage detection circuit outputs a boost clock control signal for controlling the boost clock as compared with the negative voltage output from the negative boost circuit.
[0014]
The negative booster circuit according to an eighth aspect of the present invention is the negative booster circuit according to the seventh aspect, wherein the voltage detection circuit includes a current mirror circuit connected to a power supply potential, a source connected to a ground potential, and a drain. Is connected to the current input terminal of the current mirror circuit, a second N-type MOS transistor having a gate and a drain connected to the gate of the first N-type MOS transistor, and one end A transistor string comprising one or a plurality of diode-connected N-type MOS transistors connected in series, connected to the negative voltage output terminal of the negative booster circuit, the other end connected to the source of the second N-type MOS transistor. The first input terminal is connected to the drain of the second N-type MOS transistor, the reference voltage is input to the second input terminal, and the boost clock is input. And a comparator or differential amplifier circuit outputs a control signal, said first N-type MOS transistor, said second N-type MOS transistor, and the transistor size of the transistor array is intended both identical.
[0015]
The negative booster circuit according to claim 9 of the present invention is the negative booster circuit according to claim 7, wherein the voltage detection circuit includes a current mirror circuit connected to a power supply potential, a source connected to a ground potential, and a drain. Is connected to the current input terminal of the current mirror circuit, a second N-type MOS transistor having a gate and a drain connected to the gate of the first N-type MOS transistor, and one end A transistor string comprising one or a plurality of diode-connected N-type MOS transistors connected in series, connected to the negative voltage output terminal of the negative booster circuit, the other end connected to the source of the second N-type MOS transistor. One current path is connected to the drain of one of the N-type MOS transistors constituting the transistor array, and the other current path is connected Level conversion of one or a plurality of third N-type MOS transistors connected to the negative voltage output terminal of the negative booster circuit and a voltage selection signal for selecting the detection voltage is performed, and the third N-type MOS transistor is converted. One or a plurality of level shift circuits to be output to the gate of the transistor, a first input terminal is connected to the drain of the second N-type MOS transistor, a reference voltage is input to the second input terminal, and the booster A comparator or a differential amplifier circuit for outputting a clock control signal, wherein the first N-type MOS transistor, the second N-type MOS transistor, and the transistor row have the same transistor size, and the negative booster The voltage value at the negative voltage output terminal of the circuit is switched by the voltage selection signal.
[0016]
According to a tenth aspect of the present invention, there is provided a semiconductor integrated circuit including the negative booster circuit according to any one of the seventh to eighth aspects, wherein the semiconductor integrated circuit is referred to above. A negative voltage input from the negative booster circuit is controlled by a voltage, and a regulator circuit that outputs a negative voltage having a predetermined voltage value is provided.
[0017]
In addition, a semiconductor integrated circuit according to an eleventh aspect of the present invention is a semiconductor integrated circuit including the negative booster circuit according to the ninth aspect, and the semiconductor integrated circuit is configured by the reference voltage and the voltage selection signal. A regulator circuit that controls a predetermined voltage value input from the negative booster circuit and outputs a negative voltage having a higher potential than the voltage value is provided.
[0018]
A non-volatile semiconductor memory device according to claim 12 of the present invention is a non-volatile semiconductor memory device including a negative booster circuit, and the negative booster circuit is any one of claims 6 to 9. The negative booster circuit described is used.
[0019]
A nonvolatile semiconductor memory device according to claim 13 of the present invention is a nonvolatile semiconductor memory device including a negative booster circuit, and the semiconductor according to claim 10 or 11 is used as the negative booster circuit. An integrated circuit is used.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
(Embodiment 1)
1 is a circuit diagram of a negative booster circuit according to a first embodiment of the present invention.
In FIG. 1, 11-14, 21-24 are boosting cells, 15 and 25 are final stage cells, M11-M16, M21-M26 are N-type MOS transistors, and C11-C15, C21-C25 are boosting capacitors. It is.
[0021]
The boosting cells 11 to 14 and 21 to 24 include diode-connected N-type MOS transistors M11 to M15 and M21 to M26 in which gates and drains are connected, and boosting capacitors C11 to C15 and C21 to C26. One end is connected to the drain of the N-type MOS transistor, the source of the N-type MOS transistor is the input end of the boosting cell, the back gate is the back bias input end, the drain is the output end of the boosting cell, and the other end of the boosting capacitor is the boosting clock. Input end.
[0022]
The booster cells 11 to 14 and the last stage cell 15 are connected in series to form one booster cell column, and the input terminal of the booster cell 11 which is the input terminal of the booster cell column is connected to the ground potential VSS. The output terminal of the last stage cell 15 which is the output terminal of the booster cell string is connected to the negative voltage output terminal. Similarly, the booster cells 21 to 24 and the last stage cell 25 are connected in series to form the other booster cell column, and the input terminal of the booster cell 21 which is the input terminal of the booster cell column is set to the ground potential VSS. Connect the output terminal of the last stage cell 25, which is the output terminal of the booster cell string, to the negative voltage output terminal.
[0023]
Then, the boosting clock CLK1 is input to the boosting clock input terminals of the boosting cells 11 and 13 and the last stage cell 15 corresponding to the odd-numbered stages of one boosting cell column, and the boosting cells 12 and 14 corresponding to the even-numbered stages are input. The boost clock CLK2 is input to the boost clock input terminal. The boosting clock CLK2 is input to the boosting clock input terminals of the boosting cells 21 and 23 corresponding to the odd-numbered stages of the other boosting cell column and the final-stage cell 25, and the boosting cells 22 and 24 corresponding to the even-numbered stages are input. The boost clock CLK1 is input to the boost clock input terminal. That is, the two boost cell arrays operate with boost clocks having opposite phases.
[0024]
The back bias input terminal is connected to the output terminal of the boosting cell in the next stage of the boosting cell array facing the back bias input terminal. For example, the back bias input terminal of the boosting cell 12 is connected to the output terminal of the boosting cell 23.
[0025]
The final stage cell 15 includes an N-type MOS transistor M15 having a gate and drain connected, a back gate and a drain connected, a diode-connected N-type MOS transistor M16 having a gate and a drain connected, and a boost capacitor C15. The input terminal of the final stage cell 15 is connected to the source of the N-type MOS transistor M15 and the source of the N-type MOS transistor M16, one end of the boost capacitor C15 is connected to the drain of the N-type MOS transistor M15, and the other end The boosting clock input terminal of the final stage cell 15 is used, the drain of the N-type MOS transistor M16 is the output terminal of the final stage cell 15, the back gate of the N-type MOS transistor M16 is the back bias input terminal of the final stage cell 15, and the N-type The drain of the MOS transistor M15 is used as a back bias output terminal. The back bias input terminal of the last stage cell 15 is connected to the back bias output terminal of the last stage cell 25 of the boosting cell row facing. Note that the configuration of the final stage cell 25 is the same as the configuration of the final stage cell 15, and thus the description thereof is omitted.
[0026]
The operation of the negative booster circuit configured as described above will be described.
FIG. 2 is a diagram showing the waveform of the boosting clock of the negative booster circuit according to the first embodiment of the present invention. FIG. 3 is a diagram of the negative booster circuit showing the voltage waveform of each node focusing on one booster cell. It is a voltage waveform diagram.
[0027]
The negative booster circuit according to the first embodiment operates in accordance with the boost clocks CLK1 and CLK2 that are in the opposite phases shown in FIG. 2, and as shown in FIG. 3, the negative booster circuit is connected to the input terminal (thin line) of the booster cell. Since the output end (bold line) is driven by the boost clocks CLK1 and CLK2, in the section D2 of FIG. 2, if the input end of the boost cell is on the high potential side, the output end is on the low potential side. In section D1, if the input side of the booster cell is on the low potential side, its output terminal is on the high potential side. At this time, due to the action of the diode-connected N-type MOS transistor in the booster cell, the charge is moved only during the section D1, and the potential of the output terminal is lowered. By performing this operation in the booster cells of each stage, a negative voltage VBB proportional to the number of stages of the negative booster circuit is output to the negative voltage output terminal. This operation is the same as that of the conventional negative booster circuit. However, in the negative booster circuit according to the first embodiment, the booster cell at the next stage of the booster cell row facing the back bias input terminal of one booster cell row. As shown in FIG. 3, the back gate of the N-type MOS transistor is always at a lower potential than the drain and source (dotted line), as shown in FIG. Activation is prevented.
[0028]
As described above, according to the negative booster circuit of the first embodiment, the booster cell array is composed of two pairs of booster cell columns, operates with booster clocks having opposite phases, and the back gate of the N-type MOS transistor in the booster cell. Is connected to the output of the next stage of the boosting cell array facing each other, the loss of charge due to the operation of the parasitic bipolar transistor can be suppressed, and the boosting efficiency can be improved.
[0029]
(Embodiment 2)
4 is a circuit diagram of a negative booster circuit according to the second embodiment of the present invention, FIG. 5 is a diagram showing a waveform of a boost clock input to the negative booster circuit, and FIG. 6 is a voltage waveform diagram of the negative booster circuit. It is.
[0030]
In FIG. 4, reference numerals 31 to 34 and 41 to 44 denote boosting cells, 35 and 45 denote final stage cells, M31 to M36 and M51 to M56 denote first N-type MOS transistors, and M41 to M44 and M61 to M64 denote first cells. 2 are N-type MOS transistors, and C31 to C35 and C51 to C55 are first boost capacitors, and C41 to C44 and C61 to C64 are second boost capacitors.
[0031]
Each boosting cell includes two N-type MOS transistors and two boosting capacitors. For example, the boosting cell 31 connects the source of the N-type MOS transistor M31, which is the first N-type MOS transistor, to the input terminal of the boosting cell. The drain is connected to the output terminal of the booster cell 31, one end of the current path of the N-type MOS transistor M41, which is the second N-type MOS transistor, is connected to the output terminal of the booster cell 31, and the other end of the current path is connected. The gate of the N-type MOS transistor M31 is connected, the gate of the N-type MOS transistor M41 is connected to the input terminal of the booster cell 31, and one end of the booster capacitor C31 that is the first booster capacitor is the output terminal of the booster cell 31. And the other end of the boosting capacitor C41, which is the second boosting capacitor, is connected to the gate of the N-type MOS transistor M31. Continue to the other end as a second boosting clock input, connected to the back gate of the N-type MOS transistor M31 and the N-type MOS transistor M41 to each other and a back bias input of the booster cell 31. Since the other boosting cells have the same configuration as the boosting cell 31 described above, description thereof is omitted.
[0032]
The boosting cells 31 to 34 and the final stage cell 35 are connected in series to form one boosting cell column, and the boosting clock CLK2 is input to the input terminal of the boosting cell 31 which is the input terminal of the boosting cell column. Is connected to the negative voltage output terminal. Similarly, the boosting cells 41 to 44 and the last stage cell 45 are connected in series to form the other boosting cell column, and the input terminal of the boosting cell 41 which is the input terminal of the boosting cell string is connected to the input terminal of the boosting clock CLK1. The output terminal of the last stage cell 45, which is the output terminal of the booster cell string, is connected to the negative voltage output terminal.
[0033]
Further, the boost clock CLK1 is input to the first boost clock input terminal which is one end of the first boost capacitors C31, C33, C35 in the odd-numbered boost cells 31, 33, 35 of one boost cell row, The boost clock CLK3 is input to the second boost clock input terminal, which is one end of the second boost capacitors C41, C43, and is one end of the first boost capacitors C32, C34 in the even-numbered boost cells 32, 34. The boost clock CLK2 is input to the first boost clock input terminal, and the boost clock CLK4 is input to the second boost clock input terminal which is one end of the second boost capacitors C42 and C44. Further, the boosting clock CLK2 is input to the first boosting clock input terminal which is one end of the first boosting capacitors C51, C53, C55 in the odd-numbered boosting cells 41, 43, 45 of the other boosting cell column. The boosting clock CLK4 is input to the second boosting clock input terminal, which is one end of the second boosting capacitors C61 and C63, and at one end of the first boosting capacitors C52 and C54 in the boosting cells 42 and 44 in the even-numbered stages. A boost clock CLK1 is input to a certain first boost clock input terminal, and a boost clock CLK3 is input to a second boost clock input terminal which is one end of the second boost capacitors C62 and C64. That is, the two boost cell arrays operate with boost clocks having opposite phases.
[0034]
The back bias input terminal is connected to the output of the boosting cell in the next stage of the boosting cell row facing, for example, the back bias input terminal of the boosting cell 32 is connected to the output terminal of the boosting cell 43.
[0035]
Each final stage cell 35, 45 has the same configuration as the final stage cell of the negative booster circuit of the first embodiment described above. For example, the final stage cell 35 connects the gate and the drain, and connects the back gate and the drain. It comprises a connected N-type MOS transistor M35, a diode-connected N-type MOS transistor M36 whose gate and drain are connected, and a boosting capacitor C35. The input terminal of the final stage cell 35 has the source of the N-type MOS transistor M35, N Connected to the source of the MOS transistor M36, one end of the boost capacitor C35 is connected to the drain of the N-type MOS transistor M35, the other end is used as the boost clock input terminal of the final stage cell 35, and the drain of the N-type MOS transistor M36 is connected The output terminal of the last stage cell 35 is used, and the back gate of the N-type MOS transistor M36 is used as the last stage cell 35. And Kkubaiasu input, and a drain of the N-type MOS transistor M35 and the back bias output. The back bias input terminal of the final stage cell 35 is connected to the back bias output terminal of the final stage cell 45 of the facing booster cell row. The configuration of the final stage cell 45 is the same as the configuration of the final stage cell 35, and thus the description thereof is omitted.
[0036]
The operation of the negative booster circuit configured as described above will be described.
The negative booster circuit according to the second embodiment operates in accordance with the four-phase boost clocks CLK1, CLK2, CLK3, and CLK4 shown in FIG. 5, and, as shown in FIG. 6, the input terminal (thin line) of the boost cell. Since the output terminal (thick line) is driven by the boosting clock CLK1 and the boosting clock CLK2 which are in opposite phase to each other, if the input terminal of the boosting cell is on the high potential side in the sections D6 to D8 in FIG. The output terminal of the booster cell is on the high potential side if the input terminal of the booster cell is on the low potential side in the sections D2 to D4. At this time, in the section D3, the gate potential of the first N-type MOS transistor rises (dash-and-dash line) due to the action of the second N-type MOS transistor and the second boosting capacitor, and the first N-type MOS transistor is turned on. When the state is reached and the charge is transferred, the potential at the output terminal of the booster cell is lowered. This operation is performed in the booster cells of each stage, and a negative voltage VBB proportional to the number of stages of the negative booster circuit is output to the negative voltage output terminal.
[0037]
As described above, according to the negative booster circuit according to the second embodiment, two booster cell columns having two N-type MOS transistors and two booster capacitors are paired, and are boosted in opposite phases. Since it operates with a clock and the back gate of the N-type MOS transistor in the boosting cell is connected to the output of the next stage of the boosting cell row facing, the back gate of the N-type MOS transistor is connected to the drain, source as shown in FIG. Since the potential is always lower (dotted line) and the activation of the parasitic bipolar transistor is prevented, in addition to the effect of the first embodiment, the drop of the output voltage by the threshold voltage Vt in each booster cell can be canceled. Therefore, a lower negative voltage VBB can be obtained with the same number of boosting stages.
[0038]
(Embodiment 3)
FIG. 7 is a circuit diagram of a negative booster circuit according to the third embodiment of the present invention, and FIG. 8 is a diagram showing a waveform of a boost clock input to the negative booster circuit.
7, the same reference numerals as those in FIG. 4 denote the same or corresponding parts. Reference numerals 36 and 46 denote bootstrap circuits, and the boost clocks CLK3 and CLK4 are supplied to the boost capacitors via the bootstrap circuit 36 and the bootstrap circuit 46, respectively. For example, the bootstrap circuit 36 includes a second boosting clock input terminal that is one end of the second boosting capacitors C41 and C43 in the odd-numbered boosting cells 31 and 33 in one boosting cell column, and the other boosting cell. It is connected to a second boost clock input terminal which is one end of the second boost capacitors C62 and C64 in the boost cells 42 and 44 in the even-numbered stages of the column. Note that the configuration of the bootstrap circuit 46 is the same as the configuration of the bootstrap circuit 36, and thus description thereof is omitted.
[0039]
The operation of the negative booster circuit configured as described above will be described.
As shown in FIG. 8, the boost clock CLK3 and the boost clock CLK3 ′ obtained by boosting the boost clock CLK4 are supplied to the boost capacitor, so that the gate voltage of the N-type MOS transistor at the time of charge transfer in each boost cell is As a result, the current capability of the transistor is increased, and as a result, the current supply capability of the negative booster circuit as a whole is improved.
[0040]
As described above, according to the negative booster circuit according to the third embodiment, since the booster clock is supplied to the booster capacitor via the bootstrap circuits 36 and 46, the current supply of the negative voltage output in the low voltage operation of the power supply voltage VDD is performed. Can compensate for the decline in capacity. That is, the low voltage operation of the negative booster circuit can be enabled.
[0041]
(Embodiment 4)
FIG. 9 is a block diagram of a negative booster circuit according to a fourth embodiment of the present invention, and FIG. 10 is a circuit diagram showing a specific example of a voltage detection circuit included in the negative booster circuit.
In FIG. 9, 51 is a negative booster circuit, 52 is a negative voltage charge pump circuit, 53 is a booster clock circuit, 54 is a voltage detection circuit, and 55 is a reference voltage generation circuit.
[0042]
The negative booster circuit 51 includes a booster clock circuit 53, a negative voltage charge pump circuit 52, and a voltage detection circuit 54. The booster clock circuit 53 outputs a booster clock to the negative voltage charge pump circuit 52, and a negative voltage charge pump. 52 outputs a negative voltage VBB. The voltage detection circuit 54 receives the negative voltage VBB and the reference voltage Vref, and outputs a boost clock control signal CCP to the boost clock circuit 53. The reference voltage generation circuit 55 outputs a reference voltage Vref. Here, the negative voltage charge pump circuit 52 uses any of the configurations of the negative booster circuits described in the first to third embodiments.
[0043]
In FIG. 10, 60 is a comparator or differential amplifier circuit, MP1 and MP2 are P-type MOS transistors, and MN1, MN2, and MN21 to MN2n are N-type MOS transistors.
[0044]
The P-type MOS transistor MP1 has a source connected to the power supply potential VDD, a gate connected to the drain, the P-type MOS transistor MP2 has a source connected to the power supply potential VDD, and a gate connected to the drain of the P-type MOS transistor MP1. A current mirror circuit is formed by the P-type MOS transistor MP1 and the P-type MOS transistor MP2.
[0045]
The N-type MOS transistor MN1 has a source connected to the ground potential VSS and a drain connected to the drain of the P-type MOS transistor MP1, and the diode-connected N-type MOS transistors MN2, MN21 to MN2n are connected in series. The drain of the N-type MOS transistor MN2 is connected to the gate of the N-type MOS transistor MN1 and the drain of the P-type MOS transistor MP2, and the source of the N-type MOS transistor MN2n is connected to the negative voltage output VBB of the negative booster circuit 51. Yes. Here, the N-type MOS transistor MN1 and the N-type MOS transistors MN21 to MN2n are composed of transistors having the same size as the N-type MOS transistor MN2. The comparator 60 has a first input terminal connected to the drain of the N-type MOS transistor MN2, a reference voltage Vref input to the second input terminal, and a boost clock control signal CCP.
[0046]
The operation of the negative booster circuit configured as described above will be described.
The voltage detection circuit 54 detects whether the voltage of the negative voltage VBB is equal to or lower than a predetermined detection voltage determined based on the reference voltage Vref, and outputs a boost clock control signal CCP as a result to the boost clock circuit 53. According to the boost clock control signal CCP, the boost clock circuit 53 continues to output the boost clock when the negative voltage VBB is equal to or higher than a predetermined detection voltage value, and when the negative voltage VBB is equal to or lower than the predetermined detection voltage value, Is stopped, the operation of the negative voltage charge pump circuit 52 is stopped, and the voltage of the negative voltage VBB is limited. By this operation, the negative voltage VBB of the negative booster circuit 51 is maintained at a predetermined voltage value.
[0047]
In the voltage detection circuit 54 of FIG. 10, the P-type MOS transistor MP1 and the P-type MOS transistor MP2 form a current mirror circuit, and this current mirror circuit includes the current of the N-type MOS transistor MN1 and the current of the N-type MOS transistor MN2. Therefore, the gate-source voltages of the N-type MOS transistor MN1 and the N-type MOS transistor MN2 are equal to each other. Since the N-type MOS transistor MN1 and the N-type transistor NM2 have their gates connected to each other, the source potential of the N-type MOS transistor MN2 is equal to the source potential of the N-type MOS transistor MN1, that is, the ground potential VSS. Since the N-type MOS transistor MN2 and the N-type MOS transistors MN21 to MN2n are diode-connected N-type MOS transistors of the same size, the gate-source voltages of the N-type MOS transistors MN21 to MN2n are N-type MOS transistors. Equal to transistor MN2. Therefore, VBB = −nv, that is, v = −VBB / n holds for the drain potential v of the N-type MOS transistor MN2. This potential and the reference voltage Vref are compared by the comparator 60, and the boosted clock control signal CCP is output. As a result, the negative booster circuit 51 is controlled so that Vref = −VBB / n, and finally the negative voltage VBB becomes VBB = −nVref.
[0048]
As described above, according to the negative booster circuit 51 according to the fourth embodiment, the voltage detection circuit 54 detects the voltage level of the negative voltage VBB with high accuracy based on the reference voltage Vref and inputs it to the load charge pump circuit 52. By controlling the boosted clock, the voltage of the negative voltage VBB can be accurately limited, so that a predetermined negative voltage output can be obtained. Further, by controlling the voltage of the negative voltage VBB, it is possible to prevent a voltage exceeding the element breakdown voltage from being output and to protect the circuit element.
[0049]
(Embodiment 5)
FIG. 11 is a block diagram of a negative booster circuit according to a fifth embodiment of the present invention, and FIG. 12 is a circuit diagram showing a specific example of a voltage detection circuit included in the negative booster circuit.
11, the same reference numerals as those in FIG. 9 denote the same or corresponding parts. Reference numeral 56 denotes a voltage detection circuit, which is different from FIG. 9 in that a voltage selection signal CVBB is input.
[0050]
12, the same reference numerals as those in FIG. 10 denote the same or corresponding parts. 61 and 62 are level shift circuits, and MN31 and MN32 are N-type MOS transistors. The N-type MOS transistor MN31 has a source and a back gate connected to the negative voltage VBB, a drain connected to the drain of the N-type MOS transistor MN2n, and the level shift circuit 61 receives the voltage selection signal CVBB1 and the negative voltage VBB as inputs. The output is applied to the gate of the N-type MOS transistor MN31. Similarly, the N-type MOS transistor MN32 has a source and a back gate connected to the negative voltage VBB, a drain connected to the drain of the N-type MOS transistor MN2 (n−1), and the level shift circuit 62 receives the voltage selection signal CVBB2. And the negative voltage VBB are input, and the output is given to the gate of the N-type MOS transistor MN32.
[0051]
The operation of the negative booster circuit configured as described above will be described. As in the fourth embodiment described above, the negative booster circuit 51 outputs and stops the booster clock according to the booster clock control signal CCP output from the voltage detection circuit 56, and the negative voltage charge pump circuit 52 The stop of the operation is controlled, and the negative voltage VBB maintained at a predetermined voltage value is output. Here, differences from the above-described fourth embodiment will be described.
[0052]
The voltage detection circuit 56 in the fifth embodiment has a plurality of types of detection voltages determined based on the reference voltage Vref, and selects one of the detection voltages according to the voltage selection signal CVBB, and the voltage of the negative voltage VBB is selected. It is detected whether the detected voltage value is equal to or lower than the detected voltage value, and the result is output to the boost clock circuit 53 as the boost clock control signal CCP. Thereby, the negative booster circuit 51 can output a negative voltage selected according to the voltage selection signal CVBB from a plurality of types of voltage values.
In the voltage detection circuit 56 shown in FIG. 12, the description of the same configuration as the operation of FIG. 10 described above is omitted.
[0053]
Level shift circuits 61 and 62 receive voltage selection signals CVBB1 and CVBB2, respectively, and output a voltage obtained by level conversion of negative voltage VBB to LOW level. The N-type MOS transistors MN31 and MN32 function as switches between the drains of the N-type MOS transistors MN2n and MN2 (n-1) and the negative voltage VBB, respectively, and are controlled by the outputs of the level shift circuits 61 and 62. Yes. For example, when CVBB1 = "L" (LOW level) and CVBB2 = "H" (HIGH level), the outputs of the level shift circuits 61 and 62 are VBB and VDD, respectively, and the N-type MOS transistor MN31 is in the OFF state. The type MOS transistor MN32 is turned on. At this time, the drain potential of the N-type MOS transistor MN2 (n-1) becomes VBB, the N-type MOS transistors MN2n and MN2 (n-1) are turned off, and the N-type MOS transistors MN21 to MN2n connected in series Since the actual number of stages is n-2, the negative voltage output VBB of the negative booster circuit 51 is VBB =-(n-2) Vref. Further, when CVBB1 = "L" and CVBB2 = "L", the outputs of the level shift circuits 61 and 62 are the negative voltage VBB, the N-type MOS transistors MN31 and MN32 are turned off, and the negative voltage VBB is VBB. = −nVref. In this way, the voltage value of the negative voltage VBB can be selected by the voltage selection signal CVBB.
[0054]
Note that the circuit for realizing the voltage detection circuit 56 shown in FIG. 12 is merely an example.
As described above, according to the negative booster circuit according to the fifth embodiment, the voltage value of the negative voltage VBB can be changed by the voltage selection signal CVBB. Therefore, in the nonvolatile semiconductor memory device, it is necessary in different operation modes such as erasing and writing. Even when different voltage values are different, it can be easily supplied from one negative voltage circuit.
Note that the negative voltage VBB can be changed or adjusted by changing the reference voltage Vref output from the reference voltage generation circuit 55.
[0055]
(Embodiment 6)
FIG. 13 is a block diagram of a semiconductor integrated circuit diagram according to the sixth embodiment of the present invention.
[0056]
13, the same reference numerals as those in FIG. 11 denote the same or corresponding parts. A regulator circuit 57 is provided between the output of the negative booster circuit 51 and the negative voltage output terminal, and the reference voltage Vref and the voltage selection signal CVBB are input to the regulator circuit 57.
[0057]
The operation of the semiconductor integrated circuit configured as described above will be described.
Negative booster circuit 51 outputs a constant output voltage VBBP in accordance with voltage selection signal CVBB. The regulator circuit 57 stably outputs a constant voltage higher than the input negative voltage VBBP and selected according to the voltage selection signal CVBB as the negative voltage VBB. The voltage selection signal CVBB is input to both the voltage detection circuit 56 and the regulator circuit 57. The detection voltage of the voltage detection circuit 56 and the output voltage VBB of the regulator circuit 57 are whatever the state of the voltage selection signal CVBB. The detection voltage of the voltage detection circuit 56 is set lower than the output voltage VBB of the regulator circuit 57, and the voltage difference is set smaller. As a result, it is possible to output a stable negative voltage VBB from which voltage fluctuations of the output voltage VBBP of the negative booster circuit 51 are removed. Further, since the voltage difference between the output voltage VBBP of the negative booster circuit 51 and the output VBB of the regulator circuit 57 is small, the power loss due to the series transistor in the regulator circuit 57 can be suppressed low.
[0058]
As described above, according to the semiconductor integrated circuit according to the sixth embodiment, the regulator circuit 57 can obtain a stable negative voltage VBB with a small voltage fluctuation, and the negative booster circuit in any output voltage VBBP based on the voltage selection signal CVBB. Since the difference between the output voltage 51 and the output voltage of the regulator circuit 57 can be kept small, power loss in the regulator circuit 57 can be suppressed.
[0059]
In the sixth embodiment, the case where the reference voltage Vref and the voltage selection signal CVBB are input to the regulator circuit 57 is described as an example. However, the voltage selection signal CVBB is not input to the regulator circuit 57. In accordance with the reference voltage Vref, the output voltage VBB output from the regulator circuit 57 is set to be higher than the voltage value of VBBP and the voltage difference is reduced.
[0060]
(Embodiment 7)
FIG. 14 is a block diagram of a nonvolatile semiconductor memory device according to Embodiment 7 of the present invention.
In FIG. 14, 70 is a nonvolatile memory cell array, 71 is a row decoder, 72 is a bit line control circuit, 73 is a column decoder, 74 is an address buffer, 75 is a data buffer, 76 is an internal power supply circuit, and 77 is a negative voltage generation circuit. It is.
[0061]
The bit line control circuit 72 includes a sense amplifier circuit, a column gate, and a write control circuit. The bit line control circuit 72 reads data from and writes data to the nonvolatile memory cell array 70. The control gate and select gate of the nonvolatile memory cell array 70 are controlled.
[0062]
The bit control circuit 72 is connected to the data buffer 75 and the column decoder 73, and the address buffer 74 transmits an address signal to the row decoder 71 and the column decoder 73. An internal power supply circuit 76 having a negative voltage generation circuit 77 supplies a positive boosted voltage VPP generated at the time of writing / erasing of the nonvolatile memory cell array 70 to the row decoder 71, the bit line control circuit 72, and the column decoder 73, The negative boosted voltage VBB output from the negative voltage generating circuit 77 is supplied to the row decoder 71. Here, the negative voltage generation circuit 77 includes the negative booster circuit 51 described in the second to sixth embodiments.
[0063]
The operation of the nonvolatile semiconductor memory device configured as described above will be described.
First, in the negative voltage generation circuit 77, when the negative booster circuit 51 shown in the fourth or fifth embodiment is used, the negative booster circuit 51 in the fourth and fifth embodiments has improved boosting efficiency. In the nonvolatile semiconductor memory device, power consumption during writing / erasing can be reduced. Further, since the negative booster circuit 51 has improved boosting efficiency, the circuit scale can be reduced, and the area of the nonvolatile semiconductor memory device can be reduced.
[0064]
In addition, when the negative booster circuit 51 described in the sixth embodiment is used for the negative voltage generation circuit 77, the negative booster circuit 51 in the sixth embodiment has a stable negative voltage with small voltage fluctuations in addition to the above effects. Since the voltage VBB is obtained, the accuracy of threshold control of the nonvolatile memory cell 70 can be improved, which is effective in a multi-value nonvolatile semiconductor memory device.
[0065]
Further, when the negative booster circuit described in the third embodiment is used for the negative voltage generation circuit 77, the negative booster circuit in the third embodiment can generate a negative voltage at a low voltage. The low-voltage operation of the nonvolatile semiconductor memory device can be enabled.
[0066]
Thus, according to the nonvolatile semiconductor memory device according to the seventh embodiment, a high-accuracy negative voltage having an appropriate voltage value can be stably supplied, and the memory cell in the nonvolatile semiconductor memory device can be programmed / erased. The threshold voltage control can be made highly accurate.
[0067]
【The invention's effect】
As described above, according to the negative booster circuit of the first aspect of the present invention, there is provided a negative booster circuit including two booster cells each made up of a plurality of booster cell columns connected in series. Includes one or a plurality of N-type MOS transistors and one or a plurality of boost capacitors, and a boost clock is input to one end of the boost capacitor, and the boost cells of the boost cell array facing each other are in opposite phases to each other. And the back gate terminal of at least one N-type MOS transistor in the booster cell is connected to the output terminal of the booster cell in the next stage from the booster cell of the booster cell row facing. Therefore, the back gate potential of each N-type MOS transistor is always set lower than the drain and source potentials, preventing forward bias between the drain and the back gate. It is possible to improve the boosting efficiency for suppressing a decrease in boosting efficiency due to the operation of the bipolar transistor.
[0068]
According to a negative booster circuit as set forth in claim 2 of the present invention, in the negative booster circuit as set forth in claim 1, the last stage cell of the booster cell row is a diode connection in which a gate and a drain are connected, and a source is connected. The first N-type MOS transistor is connected to the input terminal of the final stage cell and the drain is the output terminal of the negative booster circuit, and the diode is connected to the gate and the drain, and the source is the input of the final stage cell. A second N-type MOS transistor having a back gate connected to the drain and a booster capacitor having one end connected to the drain of the second N-type MOS transistor and the other end serving as an input end of the boost clock And the drain of the second N-type MOS transistor as a back bias output terminal, and the N-type MOS transistor in the boosting cell in the previous stage of the boosting cell row facing each other. The back bias output terminal is connected to the back gate terminal of the first N-type MOS transistor, and the back gate of the first N-type MOS transistor is connected to the back bias output terminal of the last stage cell of the boosting cell row. The back gate potential of the N-type MOS transistor is always set lower than the drain and source potentials, prevents forward biasing between the drain and the back gate, and suppresses a decrease in boosting efficiency due to the operation of the parasitic bipolar transistor, thereby boosting the voltage. Efficiency can be improved.
[0069]
According to a negative booster circuit according to claim 3 of the present invention, in the negative booster circuit according to claim 1 or 2, the booster cell includes one N-type MOS transistor, one boost capacitor, The N-type MOS transistor has a diode connection in which a gate and a drain are connected, a source as an input terminal of the boosting cell, a drain as an output terminal of the boosting cell, and a back gate as a back bias input terminal. Since one end of the capacitor is connected to the drain of the N-type MOS transistor and the other end is used as the input end of the boosting clock, a decrease in boosting efficiency due to the operation of the parasitic bipolar transistor can be suppressed, and the boosting efficiency can be improved. A booster circuit can be provided.
[0070]
According to a negative booster circuit of a fourth aspect of the present invention, in the negative booster circuit of the first or second aspect, the booster cell includes a first N-type MOS transistor and a second N-type MOS transistor. A first booster capacitor and a second booster capacitor. The first N-type MOS transistor has a source as an input terminal of the booster cell and a drain as an output terminal of the booster cell. The second N-type MOS transistor has one end of the current path connected to the drain of the first N-type MOS transistor, and the other end connected to the gate of the first N-type MOS transistor. The gate of the second N-type MOS transistor is connected to the source of the first N-type MOS transistor, and one end of the first booster capacitor is connected to the drain of the first N-type MOS transistor. The other end of the second boost capacitor is connected to the gate of the first N-type MOS transistor, and the other end is connected to the second boost clock input. Since it is an end, a lower negative voltage VBB can be obtained.
[0071]
According to a negative booster circuit of a fifth aspect of the present invention, in the negative booster circuit according to the fourth aspect of the present invention, the first boost clock input is provided at the input terminal of the first booster cell in the booster cell row. Since the boost clock having the opposite phase to that of the boost clock input to the terminal is input, the two boost cell arrays forming a pair can be operated with the boost clocks having opposite phases.
[0072]
According to a negative booster circuit of a sixth aspect of the present invention, in the negative booster circuit of the first or second aspect, the booster cell includes one N-type MOS transistor, one booster capacitor, The N-type MOS transistor has a diode connection in which a gate and a drain are connected, a source as an input terminal of the boosting cell, a drain as an output terminal of the boosting cell, and a back gate as a back bias input terminal. Since one end of the capacitor is connected to the drain of the N-type MOS transistor and the other end is used as the input end of the boost clock, the low voltage operation of the negative boost circuit can be enabled.
[0073]
According to a negative booster circuit of a seventh aspect of the present invention, in the negative booster circuit according to any one of the first to sixth aspects, the negative booster circuit is detected based on a reference voltage. Since a voltage detection circuit for obtaining a voltage and outputting a boost clock control signal for controlling the boost clock compared with the negative voltage output from the negative boost circuit is provided, the output voltage from the negative boost circuit By controlling the output voltage, a predetermined output voltage can be obtained, and by controlling the output voltage, it is possible to prevent a voltage exceeding the element breakdown voltage from being output.
[0074]
Further, according to a negative booster circuit according to an eighth aspect of the present invention, in the negative booster circuit according to the seventh aspect, the voltage detection circuit includes a current mirror circuit connected to a power supply potential and a source connected to a ground potential. A first N-type MOS transistor having a drain connected to a current input terminal of the current mirror circuit; a second N-type MOS transistor having a gate and a drain connected to the gate of the first N-type MOS transistor; One end is connected to the negative voltage output terminal of the negative booster circuit, the other end is connected to the source of the second N-type MOS transistor, and one or a plurality of diode-connected N-type MOS transistors are connected in series. The transistor array and the first input terminal are connected to the drain of the second N-type MOS transistor, the reference voltage is input to the second input terminal, and the booster A comparator or a differential amplifier circuit for outputting a lock control signal is provided, and the transistor sizes of the first N-type MOS transistor, the second N-type MOS transistor, and the transistor array are all the same. Therefore, highly accurate voltage detection based on the reference voltage is possible, and the voltage level of the negative voltage output from the negative booster circuit can be accurately controlled.
[0075]
According to a negative booster circuit of a ninth aspect of the present invention, in the negative booster circuit according to the seventh aspect of the present invention, the voltage detection circuit includes a current mirror circuit connected to a power supply potential and a source connected to a ground potential. A first N-type MOS transistor having a drain connected to a current input terminal of the current mirror circuit; a second N-type MOS transistor having a gate and a drain connected to the gate of the first N-type MOS transistor; One end is connected to the negative voltage output terminal of the negative booster circuit, the other end is connected to the source of the second N-type MOS transistor, and one or a plurality of diode-connected N-type MOS transistors are connected in series. One current path is connected to the drain of the transistor string and one of the N-type MOS transistors constituting the transistor string, and the other current One or a plurality of third N-type MOS transistors having a path connected to the negative voltage output terminal of the negative booster circuit, and level conversion of a voltage selection signal for selecting the detection voltage are performed, and the third N-type is performed. One or a plurality of level shift circuits that output to the gate of the MOS transistor, a first input terminal is connected to the drain of the second N-type MOS transistor, and a reference voltage is input to the second input terminal, A comparator or a differential amplifier circuit that outputs the boost clock control signal, and the transistor sizes of the first N-type MOS transistor, the second N-type MOS transistor, and the transistor row are all the same, Since the voltage value at the negative voltage output terminal of the negative booster circuit is switched by the voltage selection signal, it can be operated in different operation modes such as erasing and writing. For if the necessary voltage value There are different it can also be easily supplied from one of the negative voltage circuit.
[0076]
Further, according to a semiconductor integrated circuit according to claim 10 of the present invention, a semiconductor integrated circuit comprising the negative booster circuit according to any one of claims 7 to 8, wherein the semiconductor integrated circuit comprises: Since the negative voltage input from the negative booster circuit is controlled by the reference voltage and a regulator circuit that outputs a negative voltage of a predetermined voltage value is provided, the boosted voltage of the negative booster circuit is output from the regulator circuit. By controlling so that the potential difference from the voltage is always reduced, power loss in the regulator circuit can be reduced, and power efficiency can be improved.
[0077]
In addition, a semiconductor integrated circuit according to an eleventh aspect of the present invention is a semiconductor integrated circuit including the negative booster circuit according to the ninth aspect, and the semiconductor integrated circuit is configured by the reference voltage and the voltage selection signal. Since a regulator circuit that controls a predetermined voltage value input from the negative booster circuit and outputs a negative voltage higher than the voltage value is provided, the regulator is regulated to a higher potential than the output terminal of the negative booster circuit. By outputting the negative voltage, it is possible to obtain a stable and highly accurate negative voltage with a small voltage fluctuation, and to perform highly accurate control such as writing and erasing in the nonvolatile semiconductor memory device.
[0078]
According to a nonvolatile semiconductor memory device of a twelfth aspect of the present invention, there is provided a nonvolatile semiconductor memory device including a negative booster circuit, wherein the negative booster circuit is any one of the sixth to ninth aspects. Thus, the threshold voltage control of the memory cell at the time of writing / erasing can be performed with high accuracy and high power efficiency.
[0079]
The nonvolatile semiconductor memory device according to claim 13 of the present invention is a nonvolatile semiconductor memory device including a negative booster circuit, wherein the negative booster circuit is described in claim 10 or claim 11. Therefore, the threshold voltage control of the memory cell at the time of writing / erasing can be performed with high accuracy and high power efficiency.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a negative booster circuit according to a first embodiment of the present invention.
FIG. 2 is a diagram showing a waveform of a boost clock of the negative boost circuit according to the first embodiment of the present invention.
FIG. 3 is a voltage waveform diagram of the negative booster circuit according to the first embodiment of the present invention.
FIG. 4 is a circuit diagram of a negative booster circuit according to a second embodiment of the present invention.
FIG. 5 is a diagram showing a waveform of a boost clock of a negative booster circuit according to a second embodiment of the present invention.
FIG. 6 is a voltage waveform diagram of the negative booster circuit according to the second embodiment of the present invention.
FIG. 7 is a circuit diagram of a negative booster circuit according to a third embodiment of the present invention.
FIG. 8 is a diagram showing a waveform of a boost clock of a negative boost circuit according to a third embodiment of the present invention.
FIG. 9 is a block diagram of a negative booster circuit according to a fourth embodiment of the present invention.
FIG. 10 is a detailed circuit diagram of a voltage detection unit according to a fourth embodiment of the present invention.
FIG. 11 is a block diagram of a negative booster circuit according to a fifth embodiment of the present invention.
FIG. 12 is a detailed circuit diagram of a voltage detection unit according to a fifth embodiment of the present invention.
FIG. 13 is a block diagram of a semiconductor integrated circuit diagram according to a sixth embodiment of the present invention.
FIG. 14 is a block diagram of a nonvolatile semiconductor memory device in a seventh embodiment of the present invention.
FIG. 15 is a circuit diagram of a conventional negative booster circuit.
FIG. 16 is a diagram showing a waveform of a boosting clock in a conventional negative boosting circuit.
FIG. 17 is a cross-sectional structure diagram of an N-type MOS transistor in a conventional negative booster circuit.
[Explanation of symbols]
11-14, 21-24 Booster cell
31-34, 41-44 Booster cell
15, 25, 35, 45 Final cell
36, 46 Bootstrap circuit
51 Negative booster circuit
52 Negative Voltage Charge Pump Circuit
53 Boost clock circuit
54 Voltage detection circuit
55 Reference voltage generator
56 Voltage detection circuit
57 Negative Voltage Regulator Circuit
60 Comparator or differential amplifier circuit
61 Level shift circuit
70 memory cell array
71 row decoder
72 bit line control circuit
73 Column decoder
74 Address buffer
75 Data buffer
76 Internal power supply circuit
77 Negative voltage generator

Claims (13)

A negative booster circuit comprising two parallel booster cells composed of a plurality of booster cell columns connected in series,
The boosting cell includes one or a plurality of N-type MOS transistors and one or a plurality of boosting capacitors.
A boost clock is input to one end of the boost capacitor,
The boosting cells in the boosting cell row facing each other are input with boosting clocks having opposite phases to each other,
A back gate terminal of at least one N-type MOS transistor in the booster cell is connected to an output terminal of the booster cell in a stage one stage after the booster cell of the booster cell row facing;
A negative booster circuit. The negative booster circuit according to claim 1,
The last stage cell of the boost cell row is
A first N-type MOS transistor having a diode connected by connecting a gate and a drain, a source connected to the input terminal of the final cell, and a drain output terminal of the negative booster circuit;
A second N-type MOS transistor having a source connected to the input terminal of the final stage cell and a back gate connected to the drain in a diode connection in which the gate and the drain are connected;
A boosting capacitor having one end connected to the drain of the second N-type MOS transistor and the other end serving as an input end of the boosting clock;
The drain of the second N-type MOS transistor is used as a back bias output terminal, and the back bias output terminal is connected to the back gate terminal of the N-type MOS transistor in the boosting cell in the previous stage of the boosting cell line facing the drain. The back gate of the first N-type MOS transistor is connected to the back bias output terminal of the last stage cell of the boost cell array facing the back gate.
A negative booster circuit. In the negative booster circuit according to claim 1 or 2,
The boosting cell includes one N-type MOS transistor and one boosting capacitor,
The N-type MOS transistor has a diode connection in which a gate and a drain are connected, a source as an input terminal of the boosting cell, a drain as an output terminal of the boosting cell, a back gate as a back bias input terminal, and one end of the boosting capacitor. Is connected to the drain of the N-type MOS transistor, and the other end is used as the input terminal of the boost clock.
A negative booster circuit. In the negative booster circuit according to claim 1 or 2,
The boosting cell includes a first N-type MOS transistor, a second N-type MOS transistor, a first boosting capacitor, and a second boosting capacitor,
The first N-type MOS transistor has a source as an input terminal of the boosting cell, a drain as an output terminal of the boosting cell, and the second N-type MOS transistor has one end of its current path as the first end. The drain of the N-type MOS transistor is connected, the other end of the current path is connected to the gate of the first N-type MOS transistor, and the gate of the second N-type MOS transistor is connected to the first N-type MOS transistor. The first booster capacitor is connected at one end thereof to the drain of the first N-type MOS transistor, the other end is used as a first booster clock input terminal, and the second booster capacitor is , One end of which is connected to the gate of the first N-type MOS transistor, and the other end is a second boosted clock input end.
A negative booster circuit. The negative booster circuit according to claim 4, wherein
A boost clock having a phase opposite to that of the boost clock input to the first boost clock input terminal is input to an input terminal of the first boost cell in the boost cell row.
A negative booster circuit. In the negative booster circuit according to claim 4 or 5,
The boosted clock boosted via the bootstrap circuit is input to the second boosted clock input terminal of the booster cell.
A negative booster circuit. The negative booster circuit according to any one of claims 1 to 6,
The negative booster circuit obtains a detection voltage determined based on a reference voltage, and compares the negative voltage output from the negative booster circuit with a voltage detection circuit that outputs a boost clock control signal for controlling the boost clock. Prepared,
A negative booster circuit. The negative booster circuit according to claim 7, wherein
The voltage detection circuit is
A current mirror circuit connected to the power supply potential;
A first N-type MOS transistor having a source connected to a ground potential and a drain connected to a current input terminal of the current mirror circuit;
A second N-type MOS transistor having a gate and a drain connected to the gate of the first N-type MOS transistor;
One end is connected to the negative voltage output terminal of the negative booster circuit, the other end is connected to the source of the second N-type MOS transistor, and one or a plurality of diode-connected N-type MOS transistors are connected in series. A transistor array;
A first input terminal connected to the drain of the second N-type MOS transistor, a reference voltage input to the second input terminal, and a comparator or differential amplifier circuit that outputs the boost clock control signal; Prepared,
The transistor sizes of the first N-type MOS transistor, the second N-type MOS transistor, and the transistor array are all the same.
A negative booster circuit. The negative booster circuit according to claim 7, wherein
The voltage detection circuit is
A current mirror circuit connected to the power supply potential;
A first N-type MOS transistor having a source connected to a ground potential and a drain connected to a current input terminal of the current mirror circuit;
A second N-type MOS transistor having a gate and a drain connected to the gate of the first N-type MOS transistor;
One end is connected to the negative voltage output terminal of the negative booster circuit, the other end is connected to the source of the second N-type MOS transistor, and one or a plurality of diode-connected N-type MOS transistors are connected in series. A transistor array;
One or a plurality of second current paths are connected to the drain of one of the N-type MOS transistors constituting the transistor array, and the other current path is connected to the negative voltage output terminal of the negative booster circuit. 3 N-type MOS transistors;
One or a plurality of level shift circuits for performing level conversion of a voltage selection signal for selecting the detection voltage and outputting to the gate of the third N-type MOS transistor;
A first input terminal connected to the drain of the second N-type MOS transistor; a reference voltage input to the second input terminal; and a comparator or differential amplifier circuit for outputting the boosted clock control signal. ,
The first N-type MOS transistor, the second N-type MOS transistor, and the transistor row have the same transistor size, and the voltage value at the negative voltage output terminal of the negative booster circuit is switched by the voltage selection signal. ,
A negative booster circuit. A semiconductor integrated circuit comprising the negative booster circuit according to any one of claims 7 to 8,
The semiconductor integrated circuit includes a regulator circuit that controls a negative voltage input from the negative booster circuit by the reference voltage and outputs a negative voltage having a predetermined voltage value.
A semiconductor integrated circuit. A semiconductor integrated circuit comprising the negative booster circuit according to claim 9,
The semiconductor integrated circuit includes a regulator circuit that controls a predetermined voltage value input from the negative booster circuit according to the reference voltage and the voltage selection signal, and outputs a negative voltage higher than the voltage value.
A semiconductor integrated circuit. A non-volatile semiconductor memory device including a negative booster circuit, wherein the negative booster circuit according to claim 6 is used as the negative booster circuit. . A nonvolatile semiconductor memory device comprising a negative booster circuit, wherein the semiconductor integrated circuit according to claim 10 or 11 is used as the negative booster circuit.

Images