JP3810424B2 - PWM motor drive device - Google Patents

Description

  The present invention relates to a PWM motor driving apparatus that drives a brushless DC motor such as a VTR capstan motor while controlling the number of rotations by a PWM method.

A configuration example of the output stage of the motor drive device is shown in FIG. In the figure, T _UU , T _VU , T _WU , T _UL , T _VL , and T _WL are NPN type power transistors. L _U , L _V , and L _W are U-phase, V-phase, and W-phase coils of the motor, respectively, and are Y-connected. Transistor T _UU, T _VU, the collector of T _WU are applied drive voltage V _M of the motor is, the emitter of the transistor T _UL, T _VL, T _WL is connected to the ground. The coil L _U collector and the motor of the U-phase of the emitter and the transistor T _UL transistor T _UU, and the collector of the emitter and the transistor T _VL of the transistor T _VU is the coil L _V of the V-phase of the motor, the transistor T _WU The emitter and the collector of the transistor T _WL are connected to the W phase coil L _W of the motor, respectively.

For example, as indicated by an arrow Y ₁ in FIG. 9, when the current flows from the coil L _U of the motor of the U-phase to the coil L _V of the V-phase, makes ON the upper output transistor T _UU and lower output transistor T _VL However, in the PWM drive system, one or both of these transistors are switched ON / OFF. The amount of electric power supplied to the motor, that is, the rotational speed of the motor is controlled by the ON / OFF duty ratio.

  In the conventional PWM motor driving device, the U-phase voltage (voltage at point PU), the V-phase voltage (voltage at point PV), and the W-phase voltage (voltage at point PW) so that the upper output transistor is not saturated. ), The base current value of the upper output transistor is controlled, and the U-phase voltage, V-phase voltage, and W-phase voltage are controlled so that the lower output transistor is not saturated. The base current of the lower output transistor is controlled according to the lowest voltage among them.

  Patent Document 1 discloses a motor drive device that employs another saturation prevention method. In the motor drive circuit of Patent Document 1, the first saturation prevention circuit compares the voltage corresponding to the lowest voltage at any one of the midpoints of each phase with the first reference value, and controls the PMW comparator according to the result. As a result, the amplitude of the power supply voltage supplied to each phase is changed. In this way, saturation of the entire output transistor is prevented. Similarly, the second saturation prevention circuit compares the voltage corresponding to the lowest voltage at any one of the midpoints of the respective phases with the second reference value lower than the first reference value, and the torque command value according to the result. To change. In this way, saturation of the entire output transistor is prevented in two stages.

JP-A-8-019284 (3rd page, 4th page, FIG. 1 and FIG. 2)

Here, for example, when the upper output transistor T _UU is switched from ON to OFF, the reverse voltage of the coil L _U causes a diode D parasitic on the lower output transistor T _UL as shown by an arrow Y ₂ in FIG. Current flows, and the voltage of the U phase becomes lower than the ground level by the voltage drop of the diode D. Originally, the phase of the coil driven by the lower output transistor of the U phase, V phase, and W phase Although the voltage should be the lowest, the voltage of the coil phase not driven by the other lower output transistor will be lower.

  For this reason, in the conventional PWM motor driving apparatus, when switching the ON / OFF of the upper output transistor, the base current of the lower output transistor is controlled by the voltage of the phase of the coil driven by the upper output transistor. Therefore, saturation of the lower output transistor could not be detected. Similarly, when the ON / OFF state of the lower output transistor is switched, the saturation of the upper output transistor cannot be detected. As a result, it has been difficult to improve the rotation characteristics of the motor.

  In the method employed in Patent Document 1, the motor drive voltage is changed by the first saturation prevention circuit, and the torque command value is lowered by the second saturation prevention circuit. Therefore, when the output transistor is viewed as a whole, the saturation prevention has a certain effect, but it is not a saturation prevention measure for the output transistor that is particularly likely to be saturated. It was difficult to improve. Furthermore, it has been difficult to employ a method in which the output transistor is switching-controlled by the PWM method according to the torque command.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a PWM motor driving apparatus that improves the rotational characteristics of a motor by preventing saturation of an output transistor.

In order to achieve the above object, in the present invention, in order to drive each phase of the motor with a pulse, an upper output transistor connected between the high voltage side of the driving power supply and each of the phases, and each of the driving power supply In a PWM motor driving device that includes a lower output transistor connected to a phase and controls the amount of electric power supplied to the motor by a PWM method, the upper output transistor and the lower output transistor according to a signal indicating the rotational position of the motor Means for supplying a signal for turning on / off the side output transistor, and during a period in which the signal for turning on the side output transistor is supplied, by controlling the duty ratio in accordance with the torque control signal in a PWM manner, The control means for controlling the amount of power supplied to each phase and the control current to the upper output transistor are set to the maximum of the voltages of each phase of the motor. Based on a high voltage and a signal corresponding to the torque control signal, a first saturation prevention means for controlling the upper output transistor not to be saturated, and a signal for turning the lower output transistor ON / OFF Detection means for detecting the voltage of the phase driven by the lower output transistor for each phase, and the control current to the lower output transistor according to the lowest voltage detected by the detection means and the torque control signal And a second saturation prevention means for controlling the lower output transistor so as not to saturate .

  With this configuration, control is performed so that the output transistor of the driven phase among the plurality of phases of the motor is not saturated.

Further, in the present invention, since each phase of the motor is driven with a pulse, the upper output transistor connected between the high voltage side of the driving power source and each phase is connected between each phase of the driving power source. In the PWM motor driving apparatus that includes the lower output transistor and controls the amount of power supplied to the motor by the PWM method, the upper output transistor and the lower output transistor are turned on / off according to a signal indicating the rotation position of the motor. Power supplied to each phase from the drive power source by controlling the duty ratio according to the torque control signal in a PWM manner during the period during which the signal for turning on the upper output transistor is supplied and the means for supplying the signal to turn off A control means for controlling the amount, and an upper output transistor based on a signal for turning ON / OFF the upper output transistor. First detection means for detecting the voltage of the phase being moved for each phase, and the control current to the upper output transistor according to the highest voltage detected by the first detection means and the torque control signal The first saturation prevention means for controlling the upper output transistor so as not to saturate, and the voltage of the phase driven by the signal for turning on / off the lower output transistor for each phase. The lower output is obtained by setting the control current to the second detection means to be detected and the lower output transistor to a magnitude corresponding to the lowest voltage detected by the second detection means and the torque control signal. Second saturation prevention means for controlling the transistor not to be saturated .

  With this configuration, the output transistors on the upper and lower sides of the driven phase among the plurality of phases of the motor are accurately controlled so as not to be saturated.

  As described above, according to the PWM motor driving device of the present invention, since the base current of the output transistor is controlled according to the voltage of the driven phase among the plurality of phases of the motor, the saturation of the output transistor is suppressed. This can prevent the rotation characteristics of the motor.

  Further, according to the PWM motor driving device of the present invention, the phase driven by the upper output transistor and the lower output transistor among the plurality of phases of the motor is detected, and the upper and lower sides of the detected phase are detected. Since the base current of the output transistor is controlled, saturation of the output transistor can be reliably prevented, and the rotation characteristics of the motor can be further improved.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of a PWM motor driving apparatus according to an embodiment of the present invention. Hall signals H1, H2, and H3 respectively output from Hall elements HU, HV, and HW attached to the periphery of the rotor, which is a rotating portion of the motor, are amplified by the Hall amplifier 1 to become signals A1, A2, and A3. Thereafter, it is input to the three-phase synthesis circuit 2. The three hall signals H1, H2, and H3 indicate the rotational position of the motor.

The reference voltage V _REF is input to the inverting input terminal (−) of the control amplifier 4, while the torque control signal T _CTL that is a voltage signal is input to the non-inverting input terminal (+). The control amplifier 4 outputs a current I _CTL corresponding to the voltage difference between the voltage input to the inverting input terminal (−) and the voltage input to the non-inverting input terminal (+). Specifically, the current I _CTL output from the control amplifier 4 increases as the voltage of the torque control signal T _CTL becomes higher than the reference voltage V _REF . The current supply circuit 5 supplies a current corresponding to the current I _CTL output from the control amplifier 4 to the resistor 6, the upper saturation prevention circuit 9, and the lower saturation prevention circuit 10.

The torque control signal T _CTL is a signal output from a circuit (not shown) that detects the number of rotations of the motor and compares the detected number of rotations with the set number of rotations. The lower the rotation speed is, the higher the rotation speed is. The higher the rotation speed is, the lower the rotation speed is. Therefore, the current I _CTL output from the control amplifier 4 is a signal corresponding to an error between the actual rotational speed of the motor and the set rotational speed.

The current corresponding to the current I _CTL output from the control amplifier 4 is converted into a voltage by the resistor 6 and input to the non-inverting input terminal (+) of the PWM comparator 7, while the inverting input terminal (+) A high-frequency triangular wave output from the triangular wave generating circuit 8 is input to-).

From the above, the PWM comparator 7 outputs a high-frequency binary signal (hereinafter referred to as “PWM signal”) S _PWM . The high-level duty ratio for one cycle of the PWM signal S _PWM is the torque control signal. increases as the voltage value of the T _CTL is high, becomes smaller as the voltage value of the signal is low. The PWM signal S _PWM is input to the three-phase synthesis circuit 2.

The output amplifier 3 includes NPN-type power transistors T _UU , T _VU , T _WU , T _UL , T _VL , and T _WL . The motor drive voltage V _M is applied to the collectors of the upper output transistors T _UU , T _VU , T _WU , and the emitters of the lower output transistors T _UL , T _VL , T _WL are connected to the ground. The emitter of the upper output transistor _{TUU and} the collector of the lower output transistor _TUL are the U phase coil L _U of the motor, and the emitter of the upper output transistor T _{VU and} the collector of the lower output transistor T _VL are the V phase of the motor. the coil L _V of a collector of the upper output transistor T _WU of the emitter and the lower output transistor T _WL is the coil L _W of the W phase of the motor, are respectively connected.

  As shown in FIG. 3, sinusoidal Hall signals H1, H2, and H3, which are output from the Hall elements HU, HV, and HW and are shifted in phase by 120 ° from each other, have phases of 30 by the Hall amplifier 1, respectively. After being advanced, it is amplified to become signals A1, A2, and A3.

  The internal configuration of the three-phase synthesis circuit 2 is shown in FIG. As shown in FIG. 3, the logarithmic conversion circuit 21 extracts the positive portions of the signals A1, A2, and A3, and obtains the switching signals B1, B2, and B3, and the negative values of the signals A1, A2, and A3, respectively. Switching signals B4, B5, and B6 obtained by extracting the portions are generated.

The configuration of the three differential circuit 22 is shown in FIG. PNP transistors 2201 and 2202 constitute a current mirror circuit. A current I _UO output from an upper saturation prevention circuit 9 described later flows through the collector of the transistor 2201 on the input side. On the other hand, the collector of the NPN transistor 2203 is connected to the collector of the transistor 2202 on the output side.

  NPN transistors 2203 and 2204 constitute a current mirror circuit. As described above, the collector of the transistor 2202 is connected to the collector of the transistor 2203. The collector of the transistor 2204 is connected to the emitters of NPN transistors 2205, 2206, and 2207.

NPN transistors 2208 and 2209 constitute a current mirror circuit. A current _ILO output from the lower saturation prevention circuit 10 described later flows through the collector of the transistor 2208 on the input side. On the other hand, the collector of the output side transistor 2209 is connected to the collector of a PNP transistor 2210.

  PNP transistors 2210 and 2211 form a current mirror circuit. As described above, the collector of the transistor 2209 is connected to the collector of the transistor 2210 on the input side. To the collector of the output-side transistor 2211, the emitters of PNP transistors 2212, 2213, and 2214 are connected.

  The base of the transistor 2205 has a switching signal B1, the base of the transistor 2206 has a switching signal B2, the base of the transistor 2207 has a switching signal B3, the base of the transistor 2212 has a switching signal B4, and the base of the transistor 2213 has The switching signal B5 is input to the base of the transistor 2214, and the switching signal B6 is input thereto.

Then, currents I 1, I 2, I 3, I 4, I 5, and I 6 flowing through the collectors of the transistors 2205, 2212, 2206, 2213, 2207, and 2214 are output from the three differential circuit 22. The currents I1, I2, I3, I4, I5, and I6 output from the three differential circuit 22 are amplified by the preamplifier 23 to become currents UU, UL, VU, VL, WU, and WL, and then output amplifiers to be described later Three output transistors T _UU , T _UL , T _VU , T _VL , T _WU , T _WL are input to the bases.

Of the current output from the three differential circuit 22, currents I1, I3, and I5 related to the current input to the base of the upper output transistor are input to the preamplifier 23 via the switches 24, 25, and 26, respectively. . Each switch 24, 25 and 26 is adapted to OFF when ON, a low level when the PWM signal S _PWM is high. Therefore, ON / OFF of the upper output transistor of the output amplifier 3 is switched at the same frequency and the same duty ratio as the PWM signal S _PWM .

With the above configuration, the driven coil is switched at an appropriate timing according to the rotational position of the motor, and the motor rotates. As the high-level duty ratio for one cycle of the PWM signal S _PWM increases, the time during which the upper output transistor of the output amplifier 3 is turned on increases, so that the amount of power supplied to the coil (in other words, the coil drive current) ) Increases and the motor load is constant, the motor speed increases.

When the current I _UO output from the upper saturation prevention circuit 9 increases, the current flowing through the base of the upper output transistor increases, and when the current I _LO output from the lower saturation prevention circuit 10 increases, The current flowing through the base of the side output transistor increases.

The internal configuration of the upper saturation prevention circuit 9 is shown in FIG. NPN transistors 901 and 902 constitute a current mirror circuit. The emitters of the transistors 901 and 902 are grounded via resistors 903 and 904, respectively. A current I _CTL output from the control amplifier 4 is input to the collector of the transistor 901 on the input side. A collector of a diode-connected PNP transistor 905 is connected to the collector of the transistor 902 on the output side.

The emitter of transistor 905 is connected to the driving voltage V _M of the motor through two resistors 909 and 910 connected in series. A constant current I _CC1 flows out from the connection point between the two resistors 909 and 910. The bases of the PNP transistors 906, 907, and 908 are commonly connected to the base of the transistor 905.

Connection point between the collector of the emitter and the low side output transistor T _UL of the upper output transistor T _UU emitter of the transistor 906 in the output amplifier 3 through a resistor 911 (hereinafter, referred to as "output point of the U-phase") in PU The emitter of the transistor 907 is a connection point between the emitter of the upper output transistor T _{VU and} the collector of the lower output transistor T _VL in the output amplifier 3 through the resistor 912 (hereinafter referred to as “V-phase output point”) PV. The emitter of the transistor 908 is connected through a resistor 913 to a connection point between the emitter of the upper output transistor T _{WU and} the collector of the lower output transistor T _WL in the output amplifier 3 (hereinafter referred to as “W-phase output point”). Each is connected to a PW.

  NPN transistors 914 and 915 form a current mirror circuit with the transistor 914 as an input side and the transistor 915 as an output side. The emitter of the transistor 914 is grounded via a resistor 916, and the collectors of the transistors 906, 907, and 908 are connected in common to the collector. The emitter of the transistor 915 is grounded via a resistor 917, and its collector is connected to the collector of an NPN transistor 918.

The NPN transistors 918 and 919 form a current mirror circuit with the transistor 918 as an input side and the transistor 919 as an output side. The emitters of the transistors 918 and 919 are grounded through resistors 920 and 921, respectively. A constant current output from the constant current source 922 is supplied to the collector of the transistor 918 via the resistor 923. Then, the current I _UO flowing through the collector of the transistor 919 is output from the upper saturation prevention circuit 9. Note that an external capacitor (not shown) for phase compensation is connected to a connection point between the constant current source 922 and the resistor 923.

Due to the configuration of the upper saturation prevention circuit 9, the voltage at the highest voltage among the U-phase output point PU, the V-phase output point PV, and the W-phase output point PW is the upper set voltage (specifically, the transistor The base current of the upper output transistor of the output amplifier 3 is feedback-controlled so as to be equal to the emitter voltage 905). Thereby, it is possible to prevent the upper output transistors T _UU , T _VU and T _WU from being saturated.

The emitter voltage V _E of the transistor 905 is V _E = V _M −I _CC1 · R1−I _CTL · (R1 + R2), assuming that the resistance values of the resistors 909 and 910 are R1 and R2, respectively.
Thus, the output current I _CTL of the control amplifier 4 changes. Thus, the base current of the upper output transistor is controlled according to the rotation state of the motor, and the controllability of the motor rotation speed is improved.

The internal configuration of the lower saturation prevention circuit 10 is shown in FIG. The emitters of the PNP transistors 1001 and 1002 are connected to a constant current source 1003 in common. The emitter of a PNP transistor 1004 is connected to the base of the transistor 1001. The base of the transistor 1004 is grounded via a resistor 1005. A constant current I _CC2 output from the constant current source 1006 and a current I _CTL output from the control amplifier 4 flow into the connection point between the transistor 1004 and the resistor 1005.

The emitters of PNP transistors 1007, 1008, and 1009 are connected to the base of the transistor 1002. The collectors of the transistors 1002, 1007, 1008, and 1009 are grounded. Three voltages V _UL , V _VL , and V _WL output from the lower phase detection circuit 11 to be described later are input to the bases of the transistors 1007, 1008, and 1009 via resistors 1010, 1011, and 1012, respectively.

  The collector of the transistor 1001 is connected to the collector of the NPN transistor 1013. The NPN transistors 1013 and 1014 form a current mirror circuit with the transistor 1013 as an input side and the transistor 1014 as an output side. The emitters of the transistors 1013 and 1014 are grounded via resistors 1015 and 1016, respectively.

The PNP transistors 1017, 1018 and 1019 constitute a current mirror circuit. The emitters of the input-side transistor 1017 and the output-side transistor 1018 are connected to the power supply voltage V _CC via resistors 1020 and 1021, respectively. The collector of the input-side transistor 1017 is connected to the collector of the transistor 1014 via the resistor 1022. Then, the current I _LO flowing through the collector of the transistor 1018 is output from the lower saturation prevention circuit 10. An external capacitor (not shown) for phase compensation is connected to a connection point between the collector of the transistor 1014 and the resistor 1022.

  With the configuration of the lower saturation prevention circuit 10, the lowest voltage among the three voltages output from the lower phase detection circuit 11 becomes equal to the lower set voltage (specifically, the base voltage of the transistor 1004). In addition, the base current of the lower output transistor is feedback controlled.

Note that the base voltage V _B of the transistor 1004 is V _B = (I _CTL + I _CC2 ) · R, where R is the resistance value of the resistor 1005, and changes depending on the output current I _CTL of the control amplifier 4. Thereby, the base current of the lower output transistor is controlled according to the rotation state of the motor, and the controllability of the rotation speed of the motor is improved.

The lower phase detection circuit 11 includes a first circuit 111, a second circuit 112, and a third circuit 113, as shown in FIG. The first circuit 111 will be described. The NPN-type transistor 1101 has its base via a resistor 1102 is grounded, the emitter is grounded, the collector is connected to a driving voltage V _M of the motor via the two resistors 1103 and 1104 connected in series Has been. A signal corresponding to the switching signal B4 generated by the three-phase synthesis circuit 2 is input to a connection point between the base of the transistor 1101 and the resistor 1102. The PNP-type transistor 1105, to the connection point between the base resistors 1102 and 1103, the driving voltage V _M of the emitter motor is connected to the output point PU of U-phase collector through a resistor 1106.

Note that the second circuit 112 and the third circuit 113 have the same configuration as that of the first circuit 111, and thus description thereof is omitted. However, in the second circuit 112 and the third circuit 113, signals corresponding to the switching signals B5 and B6 generated by the three-phase synthesis circuit 2 are input to the connection point between the base of the transistor 1101 and the resistor 1102, respectively. The collectors of the transistors 1105 are connected to the V-phase output point PV and the W-phase output point PW via the resistor 1106, respectively. Further, the voltages V _UL , V _VL , and V _{WL at} the three connection points of the transistor 1105 and the resistor 1106 in the first circuit 111, the second circuit 112, and the third circuit 113 are detected in the lower phase. Output from the circuit 11.

With this configuration of the lower phase detection circuit 11, when the switching signal B4 is at a low level, in the first circuit 111, the transistor 1101 is OFF, so the transistor 1105 is OFF and the U-phase output point PU the voltage of the output, whereas, in the second circuit 112 and the third circuit 113, the transistor 1101 is oN, the transistor 1105 is oN, the output is substantially a voltage equal to the driving voltage V _M of the motor The

Similarly, when the switching signal B5 is at the low level, the voltage of the V-phase output point PV is output from the second circuit 112, but the motor from the first circuit 111 and the third circuit 113 is output. A voltage substantially equal to the drive voltage V _M is output. When the switching signal B6 is at the low level, the third circuit 113 outputs the voltage at the W-phase output point PW, but the first circuit 111 and the second circuit 112 drive the motor. substantially equal voltage is output to the V _M.

In summary, when the switching signals B4, B5, and B6 are at a low level, the U-phase coil L _U , the V-phase coil L _V , and the W-phase coil are respectively output by the lower output transistors T _UL , T _VL , and T _WL . Since the coil L _W is being driven, the voltage at the output point of the phase in which the coil is driven by the lower output transistor is always lower than the other two voltages from the lower phase detection circuit 11. Will be output in the state.

  Based on the operation contents of the lower saturation prevention circuit 10 and the lower phase detection circuit 11 described above, the base current of the lower output transistor is controlled based on the voltage at the output point of the phase in which the coil is driven by the lower output transistor. Will be. Therefore, unlike the conventional case, the base current of the lower output transistor is not controlled based on the voltage at the output point of the phase where the coil is not driven by the lower output transistor, and saturation of the lower output transistor is prevented. Thus, the rotational characteristics of the motor can be improved.

  When switching the ON / OFF of the lower output transistor of the output amplifier 3, a signal output from the upper phase detection circuit 12 configured as shown in FIG. 8 is input to the upper saturation prevention circuit 9. Just keep it.

The upper phase detection circuit 12 includes a first circuit 121, a second circuit 122, and a third circuit 123. The first circuit 121 will be described. The PNP-type transistor 1201 has its base connected to the driving voltage V _M of the motor through the resistor 1202, the emitter is connected to a driving voltage V _M of the motor, the collector of the two in series connected resistors Grounded through 1203 and 1204.

  A signal corresponding to the switching signal B1 generated by the three-phase synthesis circuit 2 is input to a connection point between the base of the transistor 1201 and the resistor 1202. The NPN transistor 1205 has a base connected to a connection point between the resistors 1203 and 1204, an emitter grounded, and a collector connected to the U-phase output point PU via the resistor 1206.

Note that the second circuit 122 and the third circuit 123 have the same configuration as that of the first circuit 121, and thus description thereof is omitted. However, in the second circuit 121 and the third circuit 123, signals corresponding to the switching signals B2 and B3 generated by the three-phase synthesis circuit 2 are input to the connection point between the base of the transistor 1201 and the resistor 1202, respectively. The collectors of the transistors 1205 are connected to the V-phase output point PV and the W-phase output point PW via the resistor 1206, respectively. Further, voltages V _UU , V _VU , and V _{WU at} three connection points of the transistor 1205 and the resistor 1206 in the first circuit 121, the second circuit 122, and the third circuit 123 are the upper saturation prevention circuit. 9 is input.

  With this configuration of the upper phase detection circuit 12, the base current of the upper output transistor is controlled based on the voltage at the output point of the phase in which the coil is driven by the upper output transistor, thereby preventing saturation of the upper output transistor. can do.

  In addition, when switching ON / OFF of both the output transistors of the upper side and the lower side of the output amplifier, both the lower phase detection circuit 11 and the upper phase detection circuit 12 may be provided.

1 is a block diagram of a PWM motor driving apparatus according to an embodiment of the present invention. It is a figure which shows the internal structure of a three-phase synthetic | combination circuit. It is a timing chart of each signal. It is a circuit diagram of a three differential circuit. It is a circuit diagram of an upper side saturation prevention circuit. It is a circuit diagram of a lower side saturation prevention circuit. It is a circuit diagram of a lower side phase detection circuit. It is a circuit diagram of an upper phase detection circuit. It is a circuit diagram of the output stage of a motor drive device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Hall amplifier 2 Three-phase synthetic circuit 3 Output amplifier 4 Control amplifier 5 Current supply circuit 6 Resistance 7 PWM comparator 8 Triangle wave generation circuit 9 Upper saturation prevention circuit 10 Lower saturation prevention circuit 11 Lower phase detection circuit 12 Upper phase detection circuit

Claims (2)

In order to drive each phase of the motor with pulses, an upper output transistor connected between the high voltage side of the drive power supply and each phase, and a lower output transistor connected between the respective phases of the drive power supply In a PWM motor drive device that controls the amount of power supplied to the motor by the PWM method,
Means for supplying a signal for turning on and off the upper output transistor and the lower output transistor in response to a signal indicating a rotational position of the motor;
Control means for controlling the amount of power supplied from the drive power source to each phase by controlling the duty ratio in a PWM manner according to the torque control signal during a period in which the signal for turning on the upper output transistor is supplied.
A control current to the upper output transistor is controlled so as not to saturate by setting the control current to the highest voltage among the voltages of each phase of the motor and the torque control signal. Anti-saturation means,
Detecting means for detecting, for each phase, a voltage of a phase driven by the lower output transistor based on a signal for turning ON / OFF the lower output transistor;
A second saturation for controlling the lower output transistor not to be saturated by setting the control current to the lower output transistor to a level corresponding to the lowest voltage detected by the detecting means and the torque control signal. PWM motor drive apparatus characterized by and a prevention means.
In order to drive each phase of the motor with pulses, an upper output transistor connected between the high voltage side of the drive power supply and each phase, and a lower output transistor connected between the respective phases of the drive power supply In a PWM motor drive device that controls the amount of power supplied to the motor by the PWM method,
Means for supplying a signal for turning on and off the upper output transistor and the lower output transistor in response to a signal indicating a rotational position of the motor ;
Control means for controlling the amount of power supplied from the drive power source to each phase by controlling the duty ratio in a PWM manner according to the torque control signal during a period in which the signal for turning on the upper output transistor is supplied.
First detection means for detecting, for each phase, a voltage of a phase driven by the upper output transistor based on a signal for turning on / off the upper output transistor;
A control current to the upper output transistor is set to a magnitude corresponding to the highest voltage detected by the first detection means and the torque control signal, thereby controlling the upper output transistor so as not to be saturated. Anti-saturation means,
Second detection means for detecting, for each phase, a voltage of a phase driven by a signal for turning on and off the lower output transistor;
A control current to the lower output transistor is controlled so as not to saturate by setting the control current to the lower output transistor to a magnitude corresponding to the lowest voltage detected by the second detection means and the torque control signal. A PWM motor drive device comprising two saturation prevention means .

Images