JP3809242B2 - Image data transfer device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image data transfer device, and more particularly to a data transfer device for writing and reading image data in a background image of a karaoke device, a game machine, or the like.
[0002]
[Prior art]
On the screen of a karaoke device or a game machine, moving images and images are displayed constantly changing as the music progresses and the game develops.
The image data displayed on the screen is written from the processing system to the image memory, and then read from the image memory and displayed on the screen of the display device.
In personal computers and desktop computers where the image displayed on the screen is an important component, the image memory has a one-to-one correspondence with the bitmap of the screen, and a large-capacity image memory is used. Reading is performed.
[0003]
Such a high-performance image memory that requires a certain price is incorporated in the price of a personal computer or the like from the beginning of the design.
On the other hand, in karaoke devices and game machines, other functions such as important sound source circuits are assigned as high performance as possible. As a low price.
Karaoke devices, game machines, and the like use a general-purpose two-line image memory that is supplied as a standard product in the market, and satisfy the display function while reducing costs.
[0004]
A conventional image data transfer apparatus will be described with reference to FIG.
The operation time ROM 4 instructs the central processing unit CPU 6 on a preparation time for handling data. For example, 3.6406 ns is set as an address hold time or an address setup time.
The bus width ROM 5 instructs the CPU 6 on the bus width of handling data. For example, 16 bits is set as the data bus width.
[0005]
The operating time ROM4 of 3.6406 ns and the bus width ROM5 of 16 bits are fixedly set and are determined when the semiconductor circuit is created.
Now, the image data processed by the separate circuit is input to the CPU 6 of the central processing unit and sent to the writing circuit 7 every 16 bits of data.
[0006]
The write circuit 7 alternately writes 16-bit data to the line 3 a or the line 3 b in the line memory 3 in accordance with an instruction from the CPU 6.
The line memory 3 is composed of independent lines 3a and 3b, and the lines 3a and 3b have the same configuration as a pair.
The line 3a and the line 3b are each composed of, for example, a (512w) × 16 bit bus semiconductor memory.
The read circuit 8 alternately reads 16-bit data from the line 3 a or the line 3 b in the line memory 3 in accordance with an instruction from the CPU 6.
[0007]
The 16-bit data read alternately from the line 3a or the line 3b is sent to the liquid crystal panel or CRT of the display device 1 and displayed.
The overall operation of the conventional line memory 3 for an image having a two-line structure will be described with reference to FIG.
The screen of the display device 1 such as a karaoke device or a game machine is composed of 263 × 263 pixels in the horizontal and vertical directions, taking the roughest display as an example.
[0008]
The screen is displayed with 263 to 526 scanning lines 2 laid out sequentially from top to bottom in 1/60 seconds.
When displaying a screen image of a background image of a karaoke device or a changing image of a game machine, a line memory 3 for each scanning line 2 at a speed of (1/60) · (1/263 to 1/526) seconds. Display data is written in, read out and displayed.
[0009]
After writing to the line memory 3 every 16 bits and writing all, 16 bits of the display data are read from the beginning and displayed.
Usually, two popular and low-cost line memories 3 are provided in parallel, and continuous display is possible while switching between writing and reading to shorten the waiting time.
[0010]
In the timing chart of FIG. 3, the basic clock a is (1 / 15.625) · 1,000,000 hz with an “H” and “L” time of 7.2812 ns, and an address hold time t1 and an address setup time t2. The read data latch up time t3 is the same 3.6406 ns.
Thereafter, the 0th 16-bit data is written, 12-bit data is written to the line 3a in the line memory 3 with 1.5 pulses of the basic clock a, and simultaneously read from the other line 3b.
[0011]
When this operation is repeated, the first 16-bit data is written to the line 3b in the line memory 3 at the next basic clock a1.5 pulse and simultaneously read from the other line 3a.
Accordingly, 32-bit data is written at the time of 3 pulses T1 of the basic clock a, and is simultaneously read from the other line 3a.
[0012]
The number of bits allocated to one scanning line 2 varies depending on the quality of the image, but in the case of normal image data, the data width to be written in the line memory 2 is conventionally a 16-bit bus. The operation speed was 21 MHZ.
This operating speed is limited to the AC specification standard of the popular and low-cost line memory 3, and when the movement of the background image and the change of the game screen are maximized, the image data transfer becomes full, the temperature change and voltage There was a case where an operation error of the line memory 3 was caused by the fluctuation.
[0013]
[Problems to be solved by the invention]
There is a limit to game development and screen display, and when screens to be displayed are sent one after another from the processing system, if the rise of the pulse is delayed due to fluctuations in temperature and power supply voltage, the image may flow and watch. It ’s stupid.
Even if the popular and low-cost line memory 3 operates at a speed where the operation standard is full or the AC spec standard is barely limited, the temperature of the environment in which the karaoke apparatus or the game machine is installed is the present invention. It is an object of the present invention to provide a screen data transfer device that operates stably and operates normally when writing to and reading from a line memory without being affected by changes and power supply voltage fluctuations.
According to the present invention, the data bus written to the line memory is expanded from 16 bits to 32 bits to increase the data transfer speed.
[0014]
[Means for Solving the Problems]
The present invention provides a pair of line memories, a writing circuit that selectively writes image data to one of the line memories, and an image data that is read and displayed alternatively from one of the line memories in synchronization with the writing operation. A screen data transfer device comprising: a read circuit to be sent to the device; and a central processing unit for instructing the write circuit and the read circuit of a predetermined initial operation time and a predetermined image data bus width.
An operation time setting circuit configured to increase the storage capacity of the pair of line memories, set an initial operation time longer than a predetermined initial operation time, and send it to the central processing unit, and longer than a predetermined image data bus width A bus width setting circuit for setting the bus width of the image data and sending it to the central processing unit;
The central processing unit instructs the write circuit and the read circuit on the set initial operation time and the set bus width.
For the input image data, the writing circuit writes the image data to the one of the line memories and the reading circuit reads the image data from the one of the line memories according to the instructed initial operation time and the instructed bus width. Read data.
The amount of image data transferred in a certain time is increased, and the time for transferring a certain amount of image data is shortened.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
With reference to FIG. 1, a screen data transfer apparatus according to the present invention will be described.
The operation time setting circuit 12 can set an initial operation time and a longer initial operation time of each circuit determined by the hardware environment constituting the system.
The initial operation time indicates a preparation time for data handling, and corresponds to a pulse rise time, and the set initial operation time is sent to the central processing unit CPU6.
[0016]
In a predetermined hardware environment, the initial operation time at the time of image data transfer is, for example, an address hold time or an address setup time, and the initial operation time is 1/4 hour of the clock of FIGS. If so, the operation time setting circuit 12 can set a longer initial operation time of 7.2812 ns.
[0017]
The bus width setting circuit 13 can set the bus width of image data and the bus width of longer image data determined in the hardware environment constituting the system. Here, the set bus width of the image data is sent to the central processing unit CPU &.
For example, if the bus width is 16 bits in a predetermined hardware environment, the long pulse width can be set by the bus width setting circuit 13 to double the 32-bit bus width.
[0018]
Image data is sent to the CPU 6 from another processing system, and this image data is sent to the writing circuit 7 in units of a bus width of 32 bits.
The CPU 6 sends the 32-bit bus width information and the initial operation time 3.6426 ns or longer 7.2812 ns information as control signals to the writing circuit 7 and the reading circuit 7.
[0019]
The line memory 3 is composed of independent lines 10 and 11, and the lines 10 and 11 have the same configuration that makes a pair.
The line 10 and the line 11 are each composed of, for example, a (256w × 8 bits) × 4 32-bit bus semiconductor memory.
The semiconductor memories 10 and 11 have double the capacity compared to the conventional ones, but have a simple configuration as an element, and are products of almost the same standard and the same price system as a (512 w) × 16 bit bus semiconductor.
[0020]
The writing circuit 7 selectively sends image data to either the line 10 or the line 11 in units of a bus width of 32 bits and writes it to the selected position.
The selection of the write circuit 7 is performed alternately and changed from the line 10 to the line 11 and from the line 11 to the line 10.
[0021]
In accordance with an instruction from the CPU 6, the read circuit 8 selectively reads image data from either the line 10 or the line 11 in units of a bus width of 32 bits.
The selection of the readout circuit 8 is performed alternately and changed from the line 11 to the line 10 and from the line 10 to the line 11.
32-bit image data is alternately read from the line 11 or the line 10 in the line memory 3.
The 32-bit image data read alternately from the line 10 or the line 11 is sent to the liquid crystal panel or CRT of the display device 1 and displayed.
[0022]
First, the first operation will be described with reference to the timing chart of FIG.
In the timing chart of FIG. 2, the upper part shows the conventional operation timing before changing the initial operation time and the bus width, and the lower part shows the comparison of the operation timing of the present application after changing the bus width with the same initial operation time. ing.
In this case, the operation time setting circuit 12 sets the initial operation time as it is, for example, 3.6406 ns of 1/4 clock determined in the configuration environment of Hardoue to which the image data transfer device is mounted.
[0023]
On the other hand, the bus width setting circuit 13 changes the bus width from 16 bits to 32 bits and sets it.
The basic clock a is (1 / 15.625) · 1,000,000 hz with a pulse “H” and “L” time of 7.2812 ns, respectively, and an initial operation time of an address hold time t1 and an address setup time t2. The read data latch up time t3 is the same 3.6406 ns.
[0024]
After 3.6406 ns × 3, the 0th 32-bit data is written to the line 10 of the line memory 3 by the writing circuit 7 in units of 32 bits (32-bit transfer with 1.5 pulses of the basic clock a). .
At the same time, the conventional bus width is 16 bits, so only 16 bits are transferred.
Here, if image data has already been written to the line 11 in the line memory 3, 32-bit unit image data is read from the other line 11 by the read circuit 8 simultaneously with the writing to the line 10.
[0025]
When this operation is repeated, the first 32-bit data is written to the line 11 of the line memory 3 in the next 1.5 pulses of the basic clock a, and at the same time, the 32-bit data written from the other line 10 in the previous operation. Is read out.
Conventionally, only 16 bits × 2 = 32 bits of data are transferred from the line memory 3 in the time of 3 pulses T1 of the basic clock a. However, in the present invention, 32 bits × 2 = 62 which is doubled in the time of 3 pulses T1. Bit data is transferred from the line memory 3 to the display device 1.
[0026]
Next, the second operation will be described according to the timing chart of FIG.
In the timing chart of FIG. 3, the upper part shows the conventional operation timing before changing the initial operation time and the bus width, and the lower part shows the operation timing of the present application after both the initial operation time and the bus width are increased. ing.
In this case, the operation time setting circuit 12 sets the initial operation time longer from 3.6406 ns as follows.
[0027]
Further, the bus width setting circuit 13 also changes the bus width from 16 bits to 32 bits and sets it.
The basic clock a has “H” and “L” times of pulses of 7.2812 ns, respectively. However, the time setting circuit 12 sets the address hold time t1 of the initial operation time to 5.000 ns and the address setup time t2 to 10.00 ns. At 625 ns, the read data latch up time t3 is set to 15.625 ns.
[0028]
During one pulse (15.625 ns) after (5.000 / 10.625 + 15.625) ns, the 0th 32-bit data is written to the line 10 of the line memory 3 by the write circuit 7 in units of 32 bits (basic 32 bits are transferred in the time of 3 pulses T1 of clock a)
Again, if image data has already been written to the line 11 in the line memory 3, 32-bit unit image data is read from the other line 11 by the read circuit 8 simultaneously with the writing to the line 10.
[0029]
Conventionally, 16 bits × 2 = 32 bits are transferred at the same time. However, since the bus width is 16 bits, the preparation for the initial operation is performed twice, so that there is little time margin in the standard. In this second operation, the initial operation time is longer than twice, so even if the amount of transferred data is the same as in the past, there is a margin of time according to the standard, and stable data is not affected by fluctuations in temperature and power supply voltage. Transfer can be realized.
[0030]
Since the bus is changed from 16 bits to 32 bits, the amount of data to be written in a certain time is doubled even at the same speed.
Since the bus has been changed from 16 bits to 32 bits, if the amount of data to be transferred is the same, the time required for all writing is halved, so that there is a margin in the standard.
[0031]
Even when switching the background screen of a karaoke device or a high-speed screen of a game machine, it will follow sufficiently, the screen will not be disturbed, the image will not flow even if the temperature of the installation environment changes or the power supply voltage changes, A stable image can always be seen.
[Brief description of the drawings]
FIG. 1 is a block diagram of an image data transfer apparatus according to the present invention.
FIG. 2 is a timing waveform for explaining an operation of the image data transfer apparatus according to the present invention.
FIG. 3 is a timing waveform illustrating another operation of the image data transfer apparatus of the present invention.
FIG. 4 is a diagram showing the concept of a general image data screen and a line memory.
FIG. 5 is a block diagram of a conventional image data transfer apparatus.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Display apparatus 2 Scan line 3 Line memory 6 CPU
7 Writing circuit 8 Reading circuit 10, 11 Line 12 Operation time setting circuit 13 Bus width setting circuit

Claims (1)

A pair of line memories, a writing circuit that alternatively writes image data to one of the line memories, and a read that selectively reads image data from either one of the line memories in synchronization with the writing operation and sends it to the display device In a screen data transfer device comprising: a circuit; and a central processing unit that instructs a predetermined initial operation time and a bus width of predetermined image data to the writing circuit and the reading circuit,
Increasing the storage capacity of the pair of line memories;
An operation time setting circuit that sets an initial operation time longer than the predetermined initial operation time and sends it to the central processing unit;
A bus width setting circuit for setting the bus width of the image data longer than the bus width of the predetermined image data and sending it to the central processing unit;
The central processing unit instructs the write circuit and the read circuit on the set initial operation time and the set bus width,
For the input image data, the writing circuit writes the image data into the one of the line memories and the reading circuit of the one of the line memories according to the instructed initial operation time and the instructed bus width. Read image data from
An image data transfer device characterized in that the amount of image data transferred in a certain time is increased and the time for transferring a certain amount of image data is shortened.

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