JP3808670B2 - Semiconductor integrated circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a clock synchronous semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit equipped with a DLL (Delay Locked Loop) circuit that synchronizes an internal clock signal used in an internal circuit with an external clock signal.
[0002]
[Prior art]
As a clock synchronous semiconductor integrated circuit, SDRAM (Synchronous DRAM), DDR-SDRAM (Double Data Rate-Synchronous DRAM), and the like are known. In this type of semiconductor integrated circuit, an internal circuit is operated in synchronization with a clock signal supplied from the outside to input / output data. Generally, a semiconductor integrated circuit includes a plurality of data output terminals. Each output data output from these output terminals has a skew due to the wiring length of the signal lines depending on the circuit layout on the chip. The skew increases relatively as the clock frequency increases. Recently, SDRAMs and DDR-SDRAMs whose operating frequency exceeds 100 MHz have been developed, and the above skew cannot be ignored.
[0003]
In order to reduce such a skew, a semiconductor integrated circuit equipped with a DLL circuit has been developed. The DLL circuit is a circuit that adjusts a predetermined phase of an internal clock signal used in an internal circuit with respect to an external reference clock signal. For example, a basic configuration is disclosed in JP-A-10-112182. Yes.
Further, a DLL circuit including a rough delay circuit having a coarse delay time adjustment unit and a fine delay circuit having a fine delay time adjustment unit has been proposed. In this type of DLL circuit, the accuracy of phase adjustment can be improved, and at the same time, fluctuation (jitter) of the internal clock signal can be reduced.
[0004]
FIG. 63 shows an example of a semiconductor integrated circuit equipped with the DLL circuit proposed by the present applicant. Note that the circuit shown in FIG. 63 is not yet known.
This semiconductor integrated circuit includes an input buffer 1 that outputs an externally taken clock signal CLK as an internal clock signal ICLK, a delayed clock generator 2 that generates an internal clock signal ICLK2 that is delayed from the internal clock signal ICLK for a predetermined time, and a memory The output buffer 3 that outputs the data signal DATA read from the cell or the like as the output data signal DOUT in synchronization with the internal clock signal ICLK2 and the delay clock generator 2 are controlled, and the phase of the internal clock signal ICLK2 is changed to the phase of the clock signal CLK. And a start signal generator 5 that generates a start signal START that synchronizes the operations of the delay clock generation unit 2 and the phase control unit 4.
[0005]
The delay clock generation unit 2 includes a rough variable delay circuit 6 and a fine variable delay circuit 7.
The rough variable delay circuit 6 is configured by cascading a plurality of delay stages (not shown) having a long delay time, and roughly adjusting the delay time according to the number of delay stages connected. Under the control of the rough delay control circuit 13, the rough variable delay circuit 6 increases (shifts up) or decreases (shifts down) the number of delay stages connected.
[0006]
The fine variable delay circuit 7 is configured by cascading a plurality of delay stages (not shown) having a short delay time, and is a circuit for finely adjusting the delay time according to the number of connections of these delay stages. . Under the control of the fine delay control circuit 15, the fine variable delay circuit 7 increases (shifts up) or decreases (shifts down) the number of delay stages connected. The maximum delay time of the fine variable delay circuit 7 is slightly larger than the delay time of one delay stage of the rough variable delay circuit 6.
[0007]
The phase controller 4 includes frequency dividers 8 and 9, a dummy output buffer 10 equivalent to the output buffer 3, a dummy input buffer 11 equivalent to the input buffer 1, a rough phase comparator 12, and a rough delay control circuit 13. A fine phase comparator 14, a fine delay control circuit 15, a stage number setting circuit 16, a stage number detection circuit 17, and a DLL control circuit 18.
[0008]
The frequency divider 8 divides the frequency of the internal clock signal ICLK to generate the internal clock signal / CLK1, and outputs it to the rough phase comparator 12 and the fine phase comparator 14. Here, “/” of the clock signal / CLK1 indicates that the logic is inverted with respect to the clock signal CLK.
The frequency divider 9 divides the frequency of the internal clock signal ICLK2 to generate the internal clock signal ICLK3 and outputs it to the dummy output buffer 10. The frequency dividing ratio of the frequency dividers 8 and 9 is, for example, ¼. By dividing the clock signals ICLK and ICLK2, phase comparison at high frequency is facilitated and power consumption is reduced.
[0009]
The signal output from the dummy output buffer 10 is supplied to the dummy input buffer 11 and output to the rough phase comparator 12 and the fine phase comparator 14 as the internal clock signal DICLK.
The stage number setting circuit 16 has a delay circuit equivalent to one of the delay stages of the rough delay control circuit 6 and a delay circuit equivalent to the fine variable delay circuit 7. The stage number setting circuit 16 always monitors how many stages of the delay stage of the fine variable delay circuit 7 corresponds to the delay time of one stage of the rough variable delay circuit 6, and uses the stage number as a maximum stage number signal J2 for fine delay. This is output to the control circuit 15 and the stage number detection circuit 17. The maximum stage number signal J2 varies depending on the operating voltage of the semiconductor integrated circuit and the ambient temperature.
[0010]
The stage number detection circuit 17 receives the stage number signal J1 and the maximum stage number signal J2 that are the number of stages used by the fine variable delay circuit 7, and when the stage number signal J1 becomes the maximum stage number signal J2, and the stage number signal J1 is the minimum value. Each has a function of outputting an overflow signal OF and an underflow signal UF.
The DLL control circuit 18 receives the phase matching signal SJTR from the rough phase comparator 12, receives the overflow signal OF and the underflow signal UF from the stage number detection circuit 17, and outputs the selection signals S1, S2, the increase signal UP, and the decrease signal DOWN. is doing. The DLL control circuit 18 activates the selection signal S1 when the phase match signal JSTR is inactivated, deactivates the selection signal S2, and deactivates the selection signal S1 when the phase match signal JSTR is activated. Has a function to activate S2. Further, the DLL control circuit 18 outputs a shift-up signal UP to the rough phase comparator 12 when receiving the overflow signal OF and operates underflow signal UF when the fine phase comparator 14 is in operation. , And has a function of outputting a downshift signal DOWN to the rough phase comparator 12.
[0011]
The rough phase comparator 12 is a circuit that receives the activation of the selection signal S1, compares the phases of the internal clock signal / CLK1 and the internal clock signal DICLK, and outputs the comparison result to the rough delay control circuit 13. The rough phase comparator 12 has a function of activating the phase matching signal SJTR when the phases of the internal clock signal DICLK and the internal clock signal / CLK1 match, and the rough variable delay circuit 6 when receiving the upshift signal UP. , A function to shift down the rough variable delay circuit 6 when receiving the downshift signal DOWN, and a reset signal MIN and a set signal MAX when the rough variable delay circuit 6 is shifted up and down, respectively. And a function of outputting.
[0012]
The rough delay control circuit 13 has a function of adjusting the delay time by shifting up and down the rough variable delay circuit 6 based on the comparison result of the rough phase comparator 12. That is, when the phase of the internal clock signal DICLK is advanced with respect to the phase of the internal clock signal / CLK1, the rough delay control circuit 13 increases the number of delay stages connected by 1 to increase the phase of the internal clock signal DICLK. Is delayed with respect to the phase of the internal clock signal / CLK1, the number of delay stages connected is reduced by one.
[0013]
The fine phase comparator 14 is a circuit that receives the activation of the control signal S2, compares the phases of the internal clock signal DICLK and the internal clock signal / CLK1, and outputs the comparison result to the fine delay control circuit 15.
The fine delay control circuit 15 has a function of shifting the fine variable delay circuit 7 up and down and adjusting the delay time based on the comparison result in the fine phase comparator 14. That is, when the phase of the internal clock signal DICLK is advanced with respect to the phase of the internal clock signal / CLK1, the fine delay control circuit 15 increases the number of delay stage connections by one, and the phase of the internal clock signal DICLK. Is delayed with respect to the phase of the internal clock signal / CLK1, the number of delay stages connected is reduced by one. The fine delay control circuit 15 has a function of minimizing the number of delay stages connected to the fine variable delay circuit 7 when receiving the reset signal MIN, and the fine variable delay circuit 7 when receiving the set signal MAX. The number of delay stages connected to the maximum stage number signal J2 and the function of outputting the current number of delay stages of the fine variable delay circuit 7 as the stage number signal J1 are provided.
[0014]
The start signal generator 5 receives the internal clock signal ICLK and outputs a start signal STT. This circuit activates the start signal STT in synchronization with the falling edge of the internal clock signal ICLK when the reset signal / RESET is released. The delay clock generator 2 and the frequency dividers 8 and 9 start to operate in response to activation of the start signal STT.
FIG. 64 is a flowchart showing control of phase adjustment performed by each circuit. The phase adjustment control is started by releasing the reset signal / RESET.
[0015]
First, in step S1, initialization is performed. The stage number setting circuit 16 shown in FIG. 63 obtains how many stages of the fine variable delay circuit 7 the delay time of one delay stage of the rough variable delay circuit 6 corresponds to, and outputs it as the maximum stage number signal J2. . Further, the phase control unit 4 is initialized, and the number of connections of the delay stages of the rough variable delay circuit 6 and the fine variable delay circuit 7 is set to an initial value. The DLL control circuit activates the selection signal S1 and deactivates the selection signal S2.
[0016]
Next, initial adjustment of the rough variable delay circuit 6 is performed in steps S2 to S5.
In step S2, the phase control unit 4 sets the frequency division ratio of the frequency dividers 8 and 9 to 1/4. The frequency divider 8 receives the internal clock signal ICLK and outputs the divided internal clock signal / CLK1. The frequency divider 9 receives the internal clock signal ICLK2 and outputs the divided internal clock signal ICLK3.
[0017]
In step S3, the rough phase comparator 12 compares the phases of the internal clock signal / CLK1 and the internal clock signal DICLK, and outputs the comparison result to the rough delay control circuit 13. At this time, the fine phase comparator 14 is deactivated in response to the deactivation of the selection signal S2.
In step S4, the rough phase comparator 12 activates the phase matching signal SJTR when the phases of the two signals compared by the rough phase comparator 12 match. The DLL control circuit 18 receives the phase match signal SJTR, deactivates the selection signal S1, and activates the selection signal S2. Thereafter, the control proceeds to step S6. If the phases of the two signals compared by the rough phase comparator 12 do not match, the control moves to step S5.
[0018]
In step S5, the rough delay control circuit 13 shifts up or down the rough variable delay circuit 6 according to the comparison result of the rough phase comparator 12, and adjusts the delay time. Thereafter, the control again proceeds to step S3.
Next, in steps S6 to S15, phase adjustment using the rough variable delay circuit 6 and the fine variable delay circuit 7 is performed.
[0019]
First, in step S 6, the fine phase comparator 14 compares the phases of the internal clock signal / CLK 1 and the internal clock signal DICLK and outputs the comparison result to the fine delay control circuit 15. At this time, the rough variable delay circuit 6 is deactivated in response to the deactivation of the selection signal S1.
[0020]
In step S7, when the phases of the two signals compared by the fine phase comparator 14 coincide with each other, the control shifts again to step S6. When the phase of internal clock signal DICLK is ahead of the phase of internal clock signal / CLK1, control proceeds to step S8. When the phase of internal clock signal DICLK is delayed from the phase of internal clock signal / CLK1, control proceeds to step S12.
[0021]
In step S8, the stage number detection circuit 17 compares the stage number signal J1 with the maximum stage number signal J2. When the stage number signal J1 is equal to the maximum stage number signal J2, it is determined that the carry processing is necessary, and the control shifts to step S10. When the stage number signal J1 is smaller than the maximum stage number signal J2, it is determined that the carry-up process is unnecessary, and the control shifts to step S9.
[0022]
In step S9, the fine delay control circuit 15 shifts up the fine variable delay circuit 7 by one stage and delays the phase of the internal clock signal ICLK2.
In step S10, the stage number detection circuit 17 outputs an overflow signal OF. The DLL control circuit 18 receives the overflow signal OF and outputs the upshift signal UP. The rough phase comparator 12 receives the upshift signal UP, shifts up the rough variable delay circuit 6 by one stage, and outputs a reset signal MIN.
[0023]
In step S11, the fine delay control circuit 15 receives the reset signal MIN and sets the number of connections of the delay stages of the fine variable delay circuit 7 to the minimum.
After executing Steps S9 and S11, the control returns to Step S6 again.
On the other hand, in step S12, the stage number detection circuit 17 checks whether or not the stage number signal J1 is the minimum value. When the stage number signal J1 is the minimum value, it is determined that the carry-down process is necessary, and the control shifts to step S14. If the stage number signal J1 is not the minimum value, it is determined that the carry-down process is unnecessary, and the control shifts to step S13.
[0024]
In step S13, the fine delay control circuit 15 shifts down the fine variable delay circuit 7 by one stage and advances the phase of the internal clock signal ICLK2.
In step S14, the stage number detection circuit 17 outputs an underflow signal UF. The DLL control circuit 18 receives the underflow signal UF and outputs a downshift signal DOWN. The rough phase comparator 12 receives the downshift signal DOWN, shifts down the rough variable delay circuit 6 by one stage, and outputs a set signal MAX.
[0025]
In step S15, the fine delay control circuit 15 receives the set signal MAX and sets the number of delay stage connections of the fine variable delay circuit 7 to the maximum.
After executing Steps S13 and S15, the control returns to Step S6 again.
Then, the phase adjustment is repeatedly performed for each delay time of the delay stage of the fine variable delay circuit 7. That is, the phase control unit 4 performs rough phase adjustment by the rough delay control circuit 13 and then performs fine phase adjustment by the fine delay control circuit 15. Then, the phase of the internal clock signal DICLK is matched with the phase of the internal clock signal / CLK1.
[0026]
FIG. 65 shows the timing of main signals at the time of phase adjustment. FIG. 65 shows a state in which phase adjustment is performed and the phases of the internal clock signal / CLK1 and the internal clock signal DICLK match.
The start signal STT is activated in synchronization with the fall of the internal clock signal ICLK after the reset signal / RESET is released and becomes L level (FIG. 65 (a)). The internal clock signal ICLK is output delayed by the delay time T1 of the input buffer 1 shown in FIG. 51 from the rising edge of the clock signal CLK (FIG. 65 (b)). The internal clock signal ICLK is divided by a quarter by the frequency divider 8 and output as an internal clock signal / CLK1 delayed by a delay time T2 of the frequency divider 8 (FIG. 65 (c)). The internal clock signal ICLK2 is output with a delay of the delay time T3 of the delay clock generator 2 from the rising edge of the internal clock signal ICLK (FIG. 65 (d)). The internal clock signal ICLK2 is divided by a quarter by the frequency divider 9, and is output as the internal clock signal ICLK3 delayed by the delay time T2 of the frequency divider 9 (FIG. 65 (e)). The delay times T2 of the frequency dividers 8 and 9 are the same. For this reason, the delay of the internal clock signal ICLK3 with respect to the internal clock signal / CLK1 becomes equal to the delay time T3 of the delay clock generation unit 2 (FIG. 65 (f)). The internal clock signal ICLK3 is output as the internal clock signal DICLK after a delay time T4 between the dummy output buffer 10 and the dummy input buffer 11 (FIG. 65 (g)). The delay time T4 is equal to the sum of the delay times of the input buffer 1 and the output buffer 3.
[0027]
Therefore, in a state where the phases of the internal clock signal / CLK1 and the internal clock signal DICLK coincide with each other, the half cycle of the internal clock signal / CLK1 (= two cycles of the clock signal CLK) is equal to the delay time T3 of the delay clock generator 2. This is the same as the sum of the delay time T4 of the input buffer 1 and the output buffer 3 (FIG. 65 (h)). The total time T3 + T4 is the same as the time when the output data signal DOUT is output after the clock signal CLK is supplied. As a result, the phase of the output data signal DOUT output from the output buffer 3 matches the phase of the clock signal CLK (FIG. 65 (i)).
[0028]
[Problems to be solved by the invention]
By the way, when the DLL control circuit 18 determines “with carry” and “with carry” in steps S8 and S12 of the flowchart shown in FIG. 64, the phase control unit 4 performs steps S10, S11 and Steps S14 and S15 are executed. At this time, for example, if the internal clock signal ICLK changes during the processing of steps S10 and S11, the delay stage may not be controlled correctly, and the timing of the internal clock signal ICLK2 may be greatly shifted. For this reason, the processes in steps S10 and S11 and the processes in steps S14 and S15 must be performed continuously while the internal clock signal ICLK is at a high level or at a low level. In other words, at the time of carry-up and carry-down, the shift operation of the rough variable delay circuit 6 and the set / reset operation of the fine variable delay circuit 7 are continued while the internal clock signal ICLK is at a high level or at a low level. It is necessary to do it.
[0029]
However, as the frequency of the clock signal CLK increases, the timing margin necessary for such control decreases. In particular, control is becoming difficult in a semiconductor integrated circuit in which the frequency of the clock signal CLK exceeds 100 MHz.
[0030]
In the above-described semiconductor integrated circuit, the stage number setting circuit 16 determines how many stages of the fine variable delay circuit 7 the delay time of one stage of the rough variable delay circuit 6 corresponds to. Since the stage number setting circuit 16 is composed of a circuit equivalent to the delay stage of the rough variable delay circuit 6, it has an error with respect to the delay time of one stage of the actual delay variable delay circuit 6. . Due to this error, jitter may occur in the internal clock signal ICLK2.
[0031]
Further, in the above-described semiconductor integrated circuit, the rough phase comparator 12 and the fine phase comparator 14 compare the clock signals divided by the frequency dividers 8 and 9. However, when a low-frequency clock signal is supplied to the semiconductor integrated circuit, a large number of delay stages of the rough variable delay circuit 6 are required, which increases the circuit scale. When the frequency dividing ratio of the frequency dividers 8 and 9 is lowered to reduce the number of delay stages, the operation of the rough phase comparator 12 and the fine phase comparator 14 is performed when the clock signal CLK having a high frequency is supplied. It becomes unstable. In addition, the frequency of phase comparison increases and power consumption increases.
[0032]
On the other hand, a delay circuit in which a plurality of delay stages having variable delay times are connected in cascade (4 stages (or 8 stages)) and two adjacent clock signals among the clock signals output from each delay stage are received, and an internal clock signal is received. An interpolating circuit that generates a phase comparison circuit, a phase comparison circuit that compares the phase of the internal clock signal with the phase of the external clock signal, and a control circuit that controls the delay circuit and the interpolation circuit based on the comparison result of the phase comparison circuit A phase adjustment circuit is proposed.
[0033]
In this phase adjustment circuit, each delay circuit adjusts the delay time of each delay stage according to the frequency of the external clock signal, and outputs a clock signal whose phase is shifted by 90 degrees (or 45 degrees). The interpolation circuit receives two adjacent clock signals and generates a clock signal having a phase between the clock signals. Then, the phase comparison circuit and the control circuit control the delay circuit and the interpolation circuit so that the phase of the internal clock signal matches the phase of the external clock signal.
[0034]
However, this type of phase adjustment circuit has a problem that the phase can be adjusted only for one period of the external clock signal. In particular, when a high-frequency external clock signal is supplied to the semiconductor integrated circuit, the phase adjustment range becomes narrow. In addition, the delay stage is provided with extra elements such as a CR time constant circuit so that the delay time can be adjusted, and the layout size is large.
[0035]
An object of the present invention is to provide a semiconductor integrated circuit that can always perform phase comparison correctly without depending on the frequency of a clock signal.
Another object of the present invention is to prevent the occurrence of jitter in the internal clock signal during phase adjustment.
Another object of the present invention is to reduce the number of phase comparisons and reduce the time required for phase comparison.
[0036]
Another object of the present invention is to reduce the layout size of the delay stage by using a delay stage having a fixed delay time.
Another object of the present invention is to reduce power consumption of a circuit necessary for phase comparison.
[0037]
[Means for Solving the Problems]
FIG. 1 is a block diagram showing the basic principle of a semiconductor integrated circuit according to any one of claims 1 to 5.
[0038]
In the semiconductor integrated circuit according to the first aspect, the reference clock signal supplied to the delay circuit 21 is sequentially transmitted to the cascaded delay stages 21a and 21b having a predetermined delay time. A delayed clock signal is output from each of the delay stages 21a and 21b. The delayed clock signal is not fed back to the preceding delay stage. The switch circuit 22 selects one of the clock signals output from the odd-numbered delay stage 21a in the delay circuit 21 as the first clock signal. The switch circuit 22 selects one of the clock signals output from the even-numbered delay stage 21b adjacent to the delay stage 21a that outputs the first clock signal as the second clock signal. The interpolation circuit 24 generates an internal clock signal having a phase having a transition edge between the transition edge of the first clock signal and the transition edge of the second clock signal in accordance with the ratio information supplied from the control circuit 25. The phase comparison circuit 26 compares the phases of the reference clock signal and the internal clock signal. The control circuit 25 controls the switch circuit 22 based on the comparison result of the phase comparison circuit 26, and switches the delay stage 21a (or 21b) selected by the switch circuit 22.
[0039]
For example, the phase of the first clock signal is advanced from the phase of the second clock signal, and the phase comparison circuit 26 indicates that the phase of the internal clock signal is advanced relative to the phase of the reference clock signal. When shown, the control circuit 25 controls the switch circuit 22 so that the clock signal output from the delay stage 21a (odd-numbered stage) on the downstream side from the present is output as the first clock signal. Similarly, the phase of the first clock signal is ahead of the phase of the second clock signal, and as a result of comparison by the phase comparison circuit 26, the phase of the internal clock signal is delayed from the phase of the reference clock signal. , The control circuit 25 controls the switch circuit 22 so that the clock signal output from the delay stage 21b (even-numbered stage) on the preceding stage from the present is output as the second clock signal. Further, it is confirmed that the phase of the first clock signal is delayed from the phase of the second clock signal, and that the phase of the internal clock signal is advanced relative to the phase of the reference clock signal as a result of the comparison by the phase comparison circuit 26. When shown, the control circuit 25 controls the switch circuit 22 so that the clock signal output from the delay stage 21b (even-numbered stage) on the rear stage side from the present is output as the second clock signal. Similarly, the phase of the first clock signal is delayed from the phase of the second clock signal, and the phase comparison circuit 26 compares the phase of the internal clock signal with respect to the phase of the reference clock signal. , The control circuit 25 controls the switch circuit 22 so that the clock signal output from the delay stage 21a (odd-numbered stage) on the upstream side from the present is output as the first clock signal.
[0040]
Further, the control circuit 25 gives ratio information to the interpolation circuit 24 based on the comparison result of the phase comparison circuit 26 so that the phase of the internal clock signal matches the phase of the reference clock signal, and the phase of the internal clock signal. Make fine adjustments.
Note that the control circuit 25 may perform control of the switch circuit 22 and control of the interpolation circuit 24 separately or simultaneously. Control by the control circuit 25 is performed until the phase of the internal clock signal matches the phase of the reference clock signal.
[0041]
In this semiconductor integrated circuit, the number of connections of the delay stages 21a and 21b is determined according to the maximum value (determined at the time of design) of the phase shift between the reference clock signal and the internal clock signal. For this reason, the phase comparison between the internal clock signal and the reference clock signal can always be performed correctly, and the phases of both signals can always be matched.
Since the delay circuit 21 is configured by cascading delay stages 21a and 21b whose delay times are fixed to a predetermined value, there is no need to add an extra element for adjusting the delay time to the delay stage. The layout size of the delay stage can be reduced. As a result, the chip size can be reduced.
[0042]
Since the phase of the internal clock signal is finely adjusted using the interpolation circuit 24, the minimum unit of fine adjustment can be reduced. That is, phase adjustment is reliably performed even in a semiconductor integrated circuit to which a high-frequency reference clock signal is supplied.
According to another aspect of the semiconductor integrated circuit of the present invention, the control circuit 25 controls the switch circuit 22 at the start of the phase comparison, and roughly adjusts the phase of the internal clock signal according to the comparison result of the phase comparison circuit 26. The control circuit 25 gives ratio information to the interpolation circuit 24 according to the comparison result of the phase comparison circuit 26 after the phase difference between the internal clock signal and the reference clock signal becomes equal to or less than the delay time of the delay stages 21a and 21b. Fine-tune the phase of the internal clock signal. By performing the phase adjustment of the internal clock signal separately for the coarse adjustment and the fine adjustment, the phases of the internal clock signal and the reference clock signal can be quickly matched with a small number of phase comparisons.
[0043]
According to another aspect of the semiconductor integrated circuit of the present invention, the control circuit 25 outputs the count value of the binary counter 27 as the ratio information. When the binary counter 27 increases, the interpolation circuit 24 changes the phase of the internal clock signal from the first clock signal side to the second clock signal side. The phase of the internal clock signal is delayed as the binary counter 27 increases when the phase of the first clock signal is ahead of the phase of the second clock signal. The phase of the internal clock signal advances as the binary counter 27 increases when the phase of the first clock signal is delayed from the phase of the second clock signal. Further, the interpolation circuit 24 changes the phase of the internal clock signal from the second clock signal side to the first clock signal side when the binary counter 27 is decreased. The phase of the internal clock signal advances with the decrease of the binary counter 27 when the phase of the first clock signal is ahead of the phase of the second clock signal. The phase of the internal clock signal is delayed as the binary counter 27 decreases when the phase of the first clock signal is delayed from the phase of the second clock signal. For this reason, for example, when the counter value of the binary counter 27 is at the maximum value, the counter value may be decreased both when the phase of the internal clock signal is advanced and when it is delayed, and the counter value is reset to the minimum value. There is no need. Therefore, the binary counter 27 can be controlled easily and smoothly. As a result, the timing margin for the operation of the control circuit 25 can be increased. As a result, it is possible to prevent jitter from occurring in the internal clock signal.
[0044]
According to another aspect of the semiconductor integrated circuit of the present invention, after the phase difference between the internal clock signal and the reference clock signal becomes equal to or less than the delay time of the delay stages 21a and 21b by rough adjustment, the control circuit 25 further The operation of increasing or decreasing the value of the upper 2 bits is sequentially performed toward the lower side of the binary counter 27 to roughly adjust the phase of the internal clock signal. For this reason, the number of phase comparisons in coarse adjustment can be reduced.
[0045]
In the semiconductor integrated circuit according to the fifth aspect, since the control circuit 25 deactivates at least one of the delay stages 25a and 25b on the rear stage side that is not used, the power consumption can be reduced.
[0046]
DETAILED DESCRIPTION OF THE INVENTION
A semiconductor integrated circuit according to a first embodiment of the present invention will be described below with reference to the drawings. This embodiment corresponds to claims 1 to 5.
This semiconductor integrated circuit is formed as a DDR-SDRAM, for example, on a silicon substrate using a CMOS process technology. The DDR-SDRAM has a memory core part and a peripheral circuit part, like a general semiconductor memory. In the memory core portion, a memory cell array having a plurality of memory cells, a sense amplifier, and the like are formed. The DDR-SDRAM has a function of outputting a data signal read from a memory cell in synchronization with a rising edge of a complementary clock signal supplied from the outside.
[0047]
FIG. 2 shows the clock control unit 30 in the DDR-SDRAM.
The clock control unit 30 includes a start signal generator 32, clock buffers 34a and 34b, a delay clock generation unit 36, interpolation circuits 38 and 40, buffers 42 and 44, a phase comparison unit 46, a rough / fine control unit 48, and a rough control unit. 50 and a fine control unit 52.
[0048]
The start signal generator 32 receives the deactivation of the reset signal / RESET generated in the chip when the power is turned on or when the self-refresh mode is released, and sets the start signal STT to the H level at a predetermined timing. Circuit.
The clock buffers 34a and 34b are configured by a current mirror type differential amplifier circuit. The clock buffers 34a and 34b receive the clock signals CLK and / CLK and output internal clock signals CLK-K and / CLK-K, respectively. The clock signals CLK and / CLK correspond to the reference clock signal. The notation “/” of the clock signal / CLK indicates that the logic is opposite to that of the clock signal CLK.
[0049]
The delay clock generation unit 36 includes internal clock signals CLK-K, / CLK-K, control signals A1, B1, C1, D1, A2, B2, C2, D2 (hereinafter abbreviated as control signals A1-D1, A2-D2). In some cases, the internal clock signals ACLK, / ACLK, BCLK, and / BCLK are output in response to the start signal STT. The internal clock signals ACLK and / ACLK correspond to the first clock signal, and the internal clock signals BCLK and / BCLK correspond to the second clock signal.
[0050]
The interpolation circuit 38 receives the internal clock signals ACLK and BCLK and the counter signals CNT3, CNT2, CNT1, and CNT0 (hereinafter sometimes abbreviated as counter signals CNT3-CNT0) and has a phase between the internal clock signals ACLK and BCLK. The internal clock signal ABCLK is output. Interpolation circuit 40 receives internal clock signals / ACLK, / BCLK and counter signals CNT3-CNT0, and outputs internal clock signal / ABCLK having a phase between internal clock signals / ACLK and / BCLK. The interpolation circuit is generally also called an interpolator.
[0051]
The buffers 42 and 44 are circuits that adjust the signal waveforms of the internal clock signals ABCLK and / ABCLK output from the interpolation circuits 38 and 40, respectively, and output them as the internal clock signals CLKI and / CLKI. Internal clock signals CLKI and / CLKI are supplied to an output buffer (not shown) and used for output control of data signals.
The phase comparator 46 receives the start signal STT and the internal clock signals CLK-K and CLKI, compares the phases of the internal clock signals CLK-K and CLKI, and outputs a comparison result signal COMP and a timing signal TIM.
[0052]
The rough / fine control unit 48 includes a comparison result signal COMP, a timing signal TIM, a maximum signal MAX, a minimum signal MIN from the fine control unit 52, a rough shift order signal RSO, a rough shift direction signal RSD, and a start signal from the rough control unit 50. In response to STT, a rough enable signal REN, a fine enable signal FEN, and a rough lock on signal RLON are output.
[0053]
The rough control unit 50 receives a rough enable signal REN, a rough lock on signal RLON, a maximum signal MAX, a minimum signal MIN, and a start signal STT, and receives a rough shift direction signal RSD, a rough shift order signal RSO, and control signals A1-D1, A2 -D2 is output.
The fine control unit 52 receives the comparison result signal COMP, the fine enable signal FEN, the rough shift order signal RSO, and the start signal STT, and outputs the maximum signal MAX, the minimum signal MIN, and the counter signals CNT3-CNT0. Hereinafter, the value of the counter signals CNT3-CNT0 may be referred to as a counter value.
[0054]
The rough / fine control unit 48, the rough control unit 50, and the fine control unit 52 correspond to a control circuit.
FIG. 3 shows details of the delay clock generator 36.
The delay clock generation unit 36 includes a delay circuit 54, a delay stage activation circuit 56, a first switch circuit 58, a first shift register 60, a second switch circuit 62, and a second shift register 64. The first switch circuit 58 and the second switch circuit 62 correspond to the switch circuit 22 shown in FIG.
[0055]
The delay circuit 54 includes a plurality of delay stages D01, D11, D02, D12, D03,. The first delay stage D01 receives the internal clock signals CLK-K and / CLK-K and the enable signal EN01, and outputs the internal clock signals CLK01 and / CLK01. The next delay stage D02 receives the internal clock signals CLK01 and / CLK01 and the enable signal EN11, and outputs the internal clock signals CLK11 and / CLK11. Similarly, each delay stage D02, D12,... Receives the internal clock signal and enable signal output from the previous stage, and outputs the delayed internal clock signal to the next stage. The delayed internal clock signal is not fed back to the preceding delay stage.
[0056]
The delay stage activation circuit 56 receives enable signals E01, E02, E03,... From the first shift register 60 and receives enable signals E11, E12,. Enable signals EN01, EN11, EN02, EN12, ... are output.
The first switch circuit 58 includes internal clock signals CLK01, / CLK01, CLK02, / CLK02, CLK03, / CLK03,... Output from the odd-numbered delay stages D01, D02, D03,. Are selected according to the selection signals P01, P02, P03,... And output as internal clock signals ACLK, / ACLK.
[0057]
The first shift register 60 receives the control signals A1-D1 and the start signal STT, and outputs enable signals E01, E02, E03,... And selection signals P01, P02, P03,.
The second switch circuit 62 selects any one of the internal clock signals CLK11, / CLK11, CLK12, / CLK12,... Output from the even-numbered delay stages D11, D12,. Are selected according to the signals P11, P12,... And output as internal clock signals BCLK, / BCLK.
[0058]
The second shift register 64 receives the control signal A2-D2 and the start signal STT, and outputs enable signals E11, E12,... And selection signals P11, P12,.
As will be described later, the first switch circuit 58 and the second switch circuit 62 select internal clock signals output from the delay stages adjacent to each other. That is, when the first switch circuit 58 selects the internal clock signals CLK02 and / CLK02 from the delay stage D02 as the internal clock signals ACLK and / ACLK, the second switch circuit 62 receives the internal clock signals from the delay stage D11. The clock signals CLK11, / CLK11 or the internal clock signals CLK12, / CLK12 from the delay stage D12 are selected as the internal clock signals BCLK, / BCLK.
[0059]
FIG. 4 shows details of each delay stage D01, D11,...
The delay stages D01, D11,... Include an inverter 48a, two-input NOR gates 48b and 48c, and CR time constant circuits 48d and 48e. The CR time constant circuits 48d and 48e include, for example, a MOS capacitor CAP1 and a diffused resistor R1 in which the source and drain of an nMOS transistor (hereinafter referred to as nMOS) are connected to the ground line VSS. The delay stages D01, D11,... Are connected to a low-voltage power line (not shown) independent of other circuits. Therefore, the power consumption of the delay stages D01, D11,... Is small, and the output waveform is gentler than when the power supply line VDD is connected. Further, the delay time of the delay stages D01, D11,... Does not fluctuate due to the influence of other circuits. The delay time of each delay stage D01, D11,... Is determined to be a predetermined time depending on the CR time constant circuits 48d and 48e. In this embodiment, the delay stages D01, D11,... Use the same diffused resistor R1 and the same MOS capacitor CAP1, and their delay times are all the same. An input signal IN and an enable signal EN01 are supplied to the input of the NOR gate 48b via the inverter 48a. The output of the NOR gate 48a is connected to the CR time constant circuit 48d. An input signal / IN and an enable signal EN are supplied to the input of the NOR gate 48c via the inverter 48a. The output of the NOR gate 48b is connected to the CR time constant circuit 48e. Output signals / OUT and OUT are output from the CR time constant circuits 48d and 48e. The delay stages D01, D11,... Are activated when the enable signals EN01, EN11,... Are at the H level, and the received clock signals are delayed by a predetermined time and output. For example, in the first delay stage D01, the internal clock signals CLK-K and / CLK-K are supplied as the input signals IN and / IN, the enable signal EN01 is supplied as the enable signal EN, and the output signals / OUT and OUT are internal. Clock signals / CLK01 and CLK01 are output.
[0060]
FIG. 5 shows a main part of the first shift register 60.
The first shift register 60 includes a plurality of control circuits 66 for controlling odd-numbered delay stages D01, D02, D03,... Of the delay circuit 54 shown in FIG. Each control circuit 66 includes a two-input NOR gate 66a, a two-input NAND gate 66b, an inverter 66c, and nMOSs 66d, 66e, 66f, and 66g. The input of the NOR gate 66a is connected to the output of the NAND gate 66b and the output of the inverter 66c included in the adjacent control circuit 66 on the preceding stage (right side in the figure). A selection signal P01 (or P02, P03,...) Is output from the output of the NOR gate 66a. The input of the NAND gate 66b is supplied with the start signal STT and the output of the inverter 66c. The output of the NAND gate 66b is connected to the input of the inverter 66c, the input of the NOR gate 66a, the drain of the nMOS 66d, and the gate of the nMOS 66g provided in the adjacent control circuit on the rear side (left side in the figure). The output of the inverter 66c is connected to the input of the NAND gate 66b, the drain of the nMOS 66f, the gate of the nMOS 66e included in the adjacent front-stage control circuit 66, and the input of the NOR gate 66a included in the adjacent rear-stage control circuit 66. Yes. The output of the inverter 66c is output as an enable signal E01 (or E02, E03,...). The nMOSs 66d and 66e are connected in series, and the source of the nMOS 66e is connected to the ground line VSS. The nMOSs 66f and 66g are connected in series, and the source of the nMOS 66g is connected to the ground line VSS. The gate of the nMOS 66e is connected to the output of the inverter 66c included in the adjacent control circuit 66 on the subsequent stage side. The output of the NAND gate 66b included in the adjacent control circuit 66 on the previous stage side is connected to the gate of the nMOS 66g.
[0061]
Control signals A1 and C1 or control signals B1 and D1 are connected to the gates of the nMOSs 66d and 66f, respectively. That is, control signals A1 and C1 and control signals B1 and D1 are alternately supplied to adjacent control circuits 66.
The operation of the first shift register 60 will be described together with a rough initial adjustment flowchart (step S6 in FIG. 31) described later.
[0062]
FIG. 6 shows a main part of the second shift register 64.
The second shift register 64 is composed of the same circuit as the first shift register 60 shown in FIG. The second shift register 64 includes a plurality of control circuits 66 for controlling even-numbered delay stages D11, D12,... Of the delay circuit 54 shown in FIG. A selection signal P11 (or P12, P13,...) Is output from the NOR gate 66a of each control circuit 66. An enable signal EN11 (or EN12, EN13,...) Is output from the inverter 66c of the control circuit 66. Control signals A 2 and C 2 or control signals B 2 and D 2 are alternately supplied to the gates of the nMOSs 66 d and 66 f of the control circuit 66.
[0063]
The operation of the second shift register 64 will be described together with a rough initial adjustment flowchart (step S6 in FIG. 31) described later.
FIG. 7 shows the main part of the first switch circuit 58.
The first switch circuit 58 includes a switch unit 68 that outputs an internal clock signal ACLK and a switch unit 70 that outputs an internal clock signal / ACLK. Each of the switch sections 68 and 70 includes a pMOS transistor (hereinafter referred to as pMOS) and a CMOS switch 72a in which the source and drain of the nMOS are connected to each other, and an inverter 72b connected to the pMOS in the CMOS switch 72a. The switch 72 is configured. Selection signals P01, P02, P03... Are supplied to the control terminals of the switches 72 of the switch unit 68, respectively. Internal clock signals CLK01, CLK02, CLK03,... Are supplied to input terminals of the switches 72 of the switch unit 68, respectively. The output terminals of the switches 72 of the switch unit 68 are connected to each other and output as the internal clock signal ACLK. Similarly, selection signals P01, P02, P03... Are supplied to the control terminals of the switches 72 of the switch unit 70, respectively. Internal clock signals / CLK01, / CLK02, / CLK03,... Are supplied to the input terminals of the switches 72 of the switch unit 70, respectively. The output terminals of the switches 72 of the switch unit 68 are connected to each other and output as an internal clock signal / ACLK.
[0064]
The first switch circuit 58 generates internal clock signals CLK01, / CLK01, CLK02, / CLK02, which are output from the odd delay stages D01, D02, D03,... According to the selection signals P01, P02, P03. This circuit outputs any one of CLK03, / CLK03, etc. as internal clock signals ACLK, / ACLK.
FIG. 8 shows a main part of the second switch circuit 62.
[0065]
The second switch circuit 62 has the same circuit configuration as the first switch circuit 58. The second switch circuit 62 generates internal clock signals CLK11, / CLK11, CLK12, / CLK12 output from the even-numbered delay stages D11, D12, D13,... According to the selection signals P11, P12, P13. This circuit outputs any one of CLK13, / CLK13... As internal clock signals BCLK, / BCLK.
[0066]
FIG. 9 shows the main part of the delay stage activation circuit 56.
The delay stage activation circuit 56 is configured by arranging two-input NOR gates 56a, 56b, 56c,... In parallel. The NOR gate 56a receives enable signals E01 and E11 and outputs an enable signal EN12. The NOR gate 56b receives enable signals E11 and E02 and outputs an enable signal EN03. Similarly, the inputs of the other NOR gates 56c, 56d,... Are enabled signals E02, E03,... From the first shift register 60 and the enable signals E12, E13,. Are sequentially supplied, and enable signals EN13, EN04,... Are output from the NOR gates 56c, 56d,.
[0067]
FIG. 10 shows details of the interpolation circuits 38 and 40 and the buffers 42 and 44. The interpolation circuits 38 and 40 and the buffers 42 and 44 are the same circuit, and signals used in the interpolation circuit 40 and the buffer 44 are indicated by parentheses in the figure.
The interpolation circuit 38 includes switch circuits 74a, 74b, 74c, and 74d that receive the internal clock signal ACLK, switch circuits 76a, 76b, 76c, and 76d that receive the internal clock signal BCLK, four inverters 78, and resistors R2 and R3. It has. Each switch circuit includes a clocked inverter and an inverter connected to the pMOS of the clocked inverter. Counter signals CNT0, CNT1, CNT2, and CNT3 are supplied to the control terminals of the switch circuits 74a, 74b, 74c, and 74d through an inverter 78, respectively. Counter signals CNT0, CNT1, CNT2, and CNT3 are supplied to the control terminals of the switch circuits 76a, 76b, 76c, and 76d, respectively. The numbers described in each switch circuit indicate the ratio of the gate width of the clocked inverter. That is, the on-resistances of the clocked inverters of the switch circuits 74a, 74b, 74c, and 74d are successively halved. Similarly, the ON resistances of the clocked inverters of the switch circuits 76a, 76b, 76c, and 76d are successively halved. In other words, a variable resistor that changes in accordance with the weighting of the counter signals CNT3-CNT0 is formed by the four switch circuits 74a, 74b, 74c, 74d (or 76a, 76b, 76c, 76d). Currents according to the weights of the counter signals CNT3 to CNT0 flow through the resistors R2 and R3 in accordance with changes in the internal clock signals ACLK and BCLK, respectively. Then, an internal clock signal ABCLK having a phase having a transition edge between the transition edge of the internal clock signal ACLK and the transition edge of the internal clock signal BCLK is generated at a node between the resistors R2 and R3.
[0068]
Buffer 42 has resistors R4 and R5 connected in series and both ends connected to power supply line VDD and ground line VSS, a differential amplifier circuit 80a receiving the voltage between resistors R4 and R5 and internal clock signal ABCLK, And an inverter 80b for shaping an output waveform from the differential amplifier circuit 80a and outputting it as an internal clock signal CLKI.
[0069]
FIG. 11 shows the input waveforms of the internal clock signals ACLK and BCLK supplied to the interpolation circuit 38 and the output waveform of the internal clock signal ABCLK output from the interpolation circuit 38. Here, in order for the interpolation circuit 38 to operate normally, the internal clock signals ACLK and BCLK require a period T1 that overlaps each other. In this embodiment, the gentle signals output from the delay stages D01, D11, D02, D12,... Are selected via the switches 72 of the first and second switch circuits 58 and 62 shown in FIG. The internal clock signals ACLK and BCLK having the overlapping period T1 are generated.
[0070]
For example, when the counter value is “zero”, only the switch circuits 74a, 74b, 74c, and 74d to which the internal clock signal ACLK shown in FIG. 10 is supplied operate, and the switch circuits 76a and 76b to which the internal clock BCLK is supplied. , 76c and 76d do not operate. For this reason, the internal clock signal ABCLK has substantially the same phase as the internal clock signal ACLK (FIG. 11 (a)). When the counter value is “8” in decimal, among the switch circuits to which the internal clock signal ACLK is supplied, the switch circuits 74a, 74b and 74c operate, and among the switch circuits to which the internal clock BCLK is supplied, the switch circuit Only 76d operates. Therefore, the internal clock signal ABCLK has a phase substantially in the middle of the internal clock signals ACLK and BCLK. (FIG. 11 (b)). Similarly, the phase of the internal clock signal ABCLK is changed to 16 ways by changing the counter value.
[0071]
FIG. 12 shows details of the phase comparison unit 46.
The phase comparison unit 46 includes a first frequency divider 82, a second frequency divider 84, a dummy output buffer 86, a dummy input buffer 88, and a phase comparison circuit 90.
The first frequency dividing circuit 82 receives the internal clock signal CLK-K and the start signal STT, and outputs a reference clock signal REFCLK obtained by frequency division to the phase comparison circuit 90. The second frequency divider 84 receives the internal clock signal CLKI and the start signal STT, and outputs a clock signal obtained by dividing the frequency. The clock signal divided by the second frequency dividing circuit 84 is transmitted to the dummy output buffer 86 and the dummy input buffer 88 and output to the phase comparison circuit 90 as the internal clock signal DICLK.
[0072]
The phase comparison circuit 90 is a circuit that compares the phases of the reference clock signal REFCLK and the internal clock signal DICLK and outputs a comparison result signal COMP and a timing signal TIM.
FIG. 13 shows a first frequency dividing circuit 82 and a second frequency dividing circuit 84.
The first frequency divider 82 and the second frequency divider 84 are configured by connecting two frequency dividers 92 in series, and are circuits that divide the frequency of the clock signal by a quarter.
[0073]
The first frequency dividing circuit 82 receives the internal clock signal CLK-K at the input terminal IN of the preceding frequency divider 92 and outputs the reference clock signal REFCLK from the output terminal OUT of the subsequent frequency divider 92. The output terminal OUT of the first-stage frequency divider 92 is connected to the input terminal IN of the second-stage frequency divider 92. The start signal STT is supplied to the control terminal STT1 and the control terminal STT2 of the subsequent divider 92, and the control terminal STT2 of the previous divider 92 and the control terminal STT1 of the subsequent divider 92 are Power supply line VDD is connected.
[0074]
The second frequency dividing circuit 84 receives the internal clock signal CLKI at the input terminal IN of the previous frequency divider 92 and outputs the internal clock signal DICLK from the output terminal OUT of the subsequent frequency divider 92. The output terminal OUT of the first-stage frequency divider 92 is connected to the input terminal IN of the second-stage frequency divider 92. The start signal STT is supplied to the control terminal STT1 of each frequency divider 92, and the power supply line VDD is connected to the control terminal STT2.
[0075]
FIG. 14 shows details of the frequency divider 92.
The frequency divider 92 transmits the state of the first latch circuit to the second latch 98 in synchronization with the rising edge of the clock signal supplied from the input terminal and the first latch 94 composed of the three-input NAND gates 92a and 92b. A second latch 96 comprising a four-input NAND gate 92c and a two-input NAND gate 92d, three-input NAND gates 92e and 92f, and a second latch 96 in synchronization with the fall of the clock signal supplied from the input terminal. The two-input NAND gates 92g and 92h that transmit the state of the signal to the first latch 94, the inverter 92i that supplies the NAND gates 92g and 92h with the inverted logic of the clock signal, and the series that controls the output of the divided clock signal PMOS 92j and nMOS 92k, 92l connected to each other, an output latch 98 comprising two-input NAND gates 92m, 92n, and inverters 92o, 92p And an output circuit 100 consisting of 92q.
[0076]
The output (node N2) of the NAND gate 92a is connected to the inputs of the NAND gates 92b and 92c. The output (node N3) of the NAND gate 92b is connected to the inputs of the NAND gates 92a and 92d and the gate of the nMOS 92k. The output (node N0) of the NAND gate 92c is connected to the input of the NAND gate 92e and the gate of the pMOS 92j. The output (node N1) of the NAND gate 92d is connected to the input of the NAND gate 92f. The output of the NAND gate 92e (node N7) is connected to the inputs of the NAND gates 92f and 92g. The output (node N8) of the NAND gate 92f is connected to the inputs of the NAND gates 92e and 92h. The output (node N5) of the NAND gate 92g is connected to the input of the NAND gate 92b. The output (node N6) of the NAND gate 92h is connected to the input of the NAND gate 92a. An output (node N4) of the inverter 92i is connected to inputs of NAND gates 92g and 92h. The output of the NAND gate 92m is connected to the input of the NAND gate 92n. The output of the NAND gate 92n is connected to the input of the NAND gate 92m and the drains of the transistors 92j and 92k. The output of the NAND gate 92n is output as an output signal OUT via the inverters 92o and 92p and as an output signal / OUT via the inverter 92q.
[0077]
The input terminal IN is connected to the gates of NAND gates 92c and 92d, an inverter 92i, and an nMOS 92l. The control terminal STT1 is connected to NAND gates 92b, 92c, 92e, and 92m. The control terminal STT2 is connected to NAND gates 92a, 92c, 92f, and 92n. The sources of the transistors 92j and 92l are connected to the power supply line VDD and the ground line VSS, respectively.
[0078]
15 and 16 show a basic operation of the frequency divider 92. FIG.
FIG. 15 shows the operation when the control terminal STT2 is fixed at the H level.
In the initial state, NAND gate 92d and inverter 92i shown in FIG. 14 are activated, and a clock signal supplied from input terminal IN is transmitted to nodes N1 and N4. When the H level is supplied to the control terminal STT1, the NAND gates 92d and 92f are activated, and the node N1 becomes the L level in synchronization with the rising edge of the clock signal. Due to the L level of the node N1, the node N8 becomes the H level and the node N7 becomes the L level (FIG. 15 (a)).
[0079]
The NAND gate 92h is activated by the H level of the node N8, and the node N6 becomes L level in synchronization with the fall of the clock signal. Due to the L level of the node N6, the node N2 becomes the H level and the node N3 becomes the L level (FIG. 15 (b)).
The NAND gate 92c is activated by the H level of the node N2, and the node N0 becomes L level in synchronization with the rising edge of the clock signal. Due to the L level of the node N0, the node N7 becomes the H level and the node N8 becomes the L level (FIG. 15 (c)).
[0080]
Further, the transistor 92j is turned on by the L level of the node N0, and the node N9 becomes the H level. (FIG. 15 (d)).
The NAND gate 92g is activated by the H level of the node N7, and the node N5 becomes L level in synchronization with the fall of the clock signal. Due to the L level of the node N5, the node N3 becomes the H level and the node N2 becomes the L level (FIG. 15 (e)).
[0081]
Thereafter, the above-described operation is repeated, and a clock signal obtained by dividing the frequency of the supplied clock signal by half is generated at the node N9 which is an output node.
FIG. 16 shows the operation when the control terminal STT1 is fixed at the H level.
In the initial state, NAND gate 92d and inverter 92i shown in FIG. 14 are activated, and a clock signal supplied from input terminal IN is transmitted to nodes N4 and N6. When the H level is supplied to the control terminal STT2, the NAND gate 92c is activated, and the node N0 becomes L level in synchronization with the rising edge of the clock signal. Due to the L level of the node N0, the node N7 becomes the L level and the node N8 becomes the H level (FIG. 16 (a)).
[0082]
The NAND gate 92g is activated by the H level of the node N8, and the node N5 becomes L level in synchronization with the fall of the clock signal. Due to the L level of the node N5, the node N3 becomes the H level and the node N2 becomes the L level (FIG. 16 (b)). The transistor 92k is turned on by the H level of the node N3.
The NAND gate 92d is activated by the H level of the node N3, and the node N1 becomes L level in synchronization with the rising edge of the clock signal. Due to the L level of the node N1, the node N8 becomes the H level and the node N7 becomes the L level (FIG. 16 (c)).
[0083]
Further, the transistor 92l is turned on in synchronization with the rising edge of the clock signal, and the node N9 becomes L level (FIG. 16 (d)).
The NAND gate 92h is activated by the H level of the node N8, and the node N6 becomes L level in synchronization with the fall of the clock signal. Due to the L level of the node N6, the node N2 becomes the H level and the node N3 becomes the L level (FIG. 16 (e)).
[0084]
Thereafter, the above-described operation is repeated, and a clock signal obtained by dividing the frequency of the supplied clock signal by half is generated at the node N9 which is an output node.
As described above, by controlling the control signal STT1, a divided signal starting from the rising edge is generated, and by controlling the control signal STT2, a divided signal starting from the falling edge is generated.
[0085]
FIG. 17 shows details of the phase comparison circuit 90.
The phase comparison circuit 90 includes a pulse generation circuit 102, flip-flops 104 and 106, and a timing generation circuit 108.
The pulse generation circuit 102 includes a 2-input NAND gate 102a that receives the internal clock signal DICLK and the reference clock signal REFCLK, a delay circuit 102b connected to the output of the NAND gate 102a, an output of the NAND gate 102a, and an output of the delay circuit 102b. And a two-input NOR gate 102c. The delay circuit 102b is configured by connecting a MOS capacitor between three inverters. The pulse generation circuit 102 is a circuit that generates an H pulse when both the internal clock signal DICLK and the reference clock signal REFCLK become H level.
[0086]
The flip-flop 104 is configured by mutually feeding back the outputs of the two-input NAND gates 104a and 104b. An internal clock signal DICLK and a reference clock signal REFCLK are supplied to inputs of the NAND gates 104a and 104b. The flip-flop 104 is a circuit that changes the output of the clock signal DICLK, REFCLK that rises earlier to L level.
[0087]
The flip-flop 106 includes two-input NAND gates 106a and 106b whose outputs are fed back to each other, and two-input NAND gates 106c and 106d connected to the inputs of the NAND gates 106a and 106b. The output of the pulse generation circuit 102 is connected to one input of the NAND gates 106c and 106d. The other inputs of the NAND gates 106c and 106d are connected to the outputs of the NAND gates 104a and 104b, respectively. The comparison result signal COMP is output from the output of the NAND gate 106b. The flip-flop 106 sets the comparison result signal COMP to the H level when the phase of the internal clock signal DICLK is ahead of the phase of the reference clock signal REFCLK, and the phase of the internal clock signal DICLK is behind the phase of the reference clock signal REFCLK. Sometimes the comparison result signal COMP is set to L level.
[0088]
The timing generation circuit 108 includes a delay circuit 108a composed of a NAND gate and an inverter, a two-input NAND gate 108b receiving the reference clock signal REFCLK and the delay circuit 108a, and an inverter 108c connected in series to the output of the NAND gate 108b. , 108d. A timing signal TIM is output from the output of the inverter 108d. The timing generation circuit 108 is a circuit that generates a timing signal TIM that rises with a delay of the delay time of the delay circuit 108 from the rise of the reference clock signal REFCLK.
[0089]
FIG. 18 shows details of the rough / fine control unit 48.
The rough / fine control unit 48 includes a NAND gate and an inverter, a combinational circuit 110 that activates the rough enable signal REN or the fine enable signal FEN, a shift direction holding circuit 112 that holds information of the rough shift direction signal RSD, an EOR A circuit 114 and a lock-on generation circuit 116 that outputs a rough lock-on signal RLON are provided.
[0090]
The combinational circuit 110 is a circuit that activates the rough enable signal REN or the fine enable signal FEN in accordance with the control state diagram shown in FIG. For example, the combinational circuit 110 activates the fine enable signal FEN in synchronization with the timing signal TIM when the rough lock on signal RLON is at the L level. The combinational circuit 110 activates the rough enable signal REN in synchronization with the timing signal TIM when the rough lock on signal RLON, the rough shift order signal RSO, the maximum signal MAX, and the comparison result signal COMP are all at the H level.
[0091]
The shift direction holding circuit 112 holds CMOS switches 112a and 112b in which the pMOS and nMOS sources and drains are connected to each other and latches 112c and 112d in which the inputs and outputs of the two inverters are connected to each other in series. And an inverter 112e for controlling the CMOS switches 112a and 112b. The CMOS switches 112a and 112b are controlled by a timing signal TIM. The shift direction holding circuit 112 is a circuit that takes in and holds the rough shift direction signal RSD in synchronization with the rising edge of the timing signal TIM.
[0092]
The EOR circuit 114 is a circuit that compares the current rough shift direction signal RSD and the state of the rough shift direction signal RSD one clock before output from the shift direction holding circuit 112.
The lock-on generation circuit 116 is connected to a flip-flop obtained by feeding back the outputs of the two 2-input NOR gates 116a and 116b, an inverter train 116c connected to the input of the NOR gate 116b, and an output of the NOR gate 116b. And an inverter row 116d. The output of the EOR circuit 114 is connected to the input of the NOR gate 116a, and the start signal STT is supplied to the input of the inverter row 116c via two inverters. A rough lock on signal RLON is output from the output of the inverter train 116d.
[0093]
FIG. 20 shows details of the rough control unit 50.
The rough control unit 50 includes a rough control 118, a rough shift latch 120, a shift direction latch 122, and a register selection switch 124. The rough control 118 receives the rough lock on signal RLON, the rough shift order signal RSO, the rough enable signal REN, the comparison result signal COMP, the maximum signal MAX, and the minimum signal MIN, and performs the shift operation of the first and second shift registers 60 and 64. The shift notification signal SINF for generating the H pulse and the control signals A, B, C, and D of the original signals for shift control of the first and second shift registers 60 and 64 are output.
[0094]
The rough shift latch 120 receives the start signal STT and the shift notification signal SINF, and outputs a rough shift order signal RSO.
The shift direction latch 122 receives the start signal STT and the control signals A, B, C, and D, and outputs a rough shift direction signal RSD.
The register selection switch 124 outputs the control signals A, B, C, and D as the control signals A1, B1, C1, and D1 or the control signals A2, B2, C2, and D2 according to the level of the rough shift order signal RSO. .
[0095]
FIG. 21 shows details of the rough control 118.
The rough control 118 includes a combinational circuit 126 composed of NAND gates and inverters, a frequency dividing circuit 128, a control circuit 130 that generates control signals A, B, C, and D, and control signals A, B, C, and D. And a four-input OR circuit 132 that generates a shift notification signal SINF in response to any one of the H levels.
[0096]
The combination circuit 126 is a circuit that activates the advance signal FW or the delay signal BW in accordance with the control state diagram shown in FIG. For example, the combinational circuit 126 activates the advance signal FW when both the rough lock on signal RLON and the comparison result signal COMP are at L level. The combinational circuit 126 activates the delay signal BW when the rough lock on signal RLON, the rough shift order signal RSO, the maximum signal MAX, and the comparison result signal COMP are all at the H level. The combinational circuit 126 deactivates both the advance signal FW and the delay signal BW when the rough lock on signal RLON and the rough shift order signal RSO are at the H level, the maximum signal MAX, and the minimum signal MIN are at the L level.
[0097]
The frequency divider circuit 128 is configured by cascading two stages of flip-flop circuits in which eight 2-input NAND gates are combined. The frequency dividing circuit 128 is a circuit that divides the frequency of the rough enable signal REN by half and alternately outputs a pulse signal of the same H period as the rough enable signal REN to the node N10 and the node N11.
The control circuit 130 includes AND circuits 130a, 130b, 130c, and 130d in which two-input NAND gates and three inverters are connected in cascade. The AND circuit 130a receives the pulse signal of the node N10 and the delay signal BW and outputs a control signal D. The AND circuit 130b receives the pulse signal of the node N11 and the delay signal BW, and outputs a control signal C. The AND circuit 130c receives the pulse signal of the node N10 and the advance signal FW, and outputs a control signal B. The AND circuit 130d receives the pulse signal of the node N11 and the advance signal FW, and outputs a control signal A.
[0098]
FIG. 23 shows an outline of the operation timing of the rough control 118.
First, the case where the rough enable signal REN is held at the L level will be described.
The frequency dividing circuit 128 of the rough control 118 shown in FIG. 21 receives the L level of the rough enable signal REN and sets the nodes N10 and N11 to the L level (FIG. 23 (a)). The control circuit 130 receives the nodes N10 and N11 at the L level and sets the control signals A, B, C, and D to the L level (FIG. 23 (b)). That is, when the rough enable signal REN is at the L level, the control signals A, B, C, and D are at the L level regardless of the levels of the advance signal FW and the delay signal BW.
[0099]
Next, a case where the rough enable signal REN generates a clock pulse will be described.
The frequency dividing circuit 128 alternately outputs a clock signal obtained by dividing the rough enable signal REN by half to the nodes N10 and N11 (FIG. 23 (c)). The control circuit 130 outputs H pulse control signals A, B, C, and D according to the clock signals of the nodes N10 and N11 and the levels of the advance signal FW and the delay signal BW from the combinational circuit 126. That is, the control circuit 130 sets the control signal A to the H level in synchronization with the clock signal of the node N11 and the synchronization signal to the clock signal of the node N10 when the advance signal FW is at the H level and the delay signal BW is at the L level. The control signal B is set to the H level (FIG. 23 (d)). The control circuit 130 sets the control signal C to H level in synchronization with the clock signal of the node N11 and the control signal in synchronization with the clock signal of the node N10 when the advance signal FW is L level and the delay signal BW is H level. D is set to the H level (FIG. 23 (e)).
[0100]
The OR circuit 132 receives the H level of the control signals A, B, C, and D and sets the shift notification signal SINF to the H level (FIG. 23 (f)).
FIG. 24 shows details of the rough shift latch 120.
Rough shift latch 120 includes CMOS switches 120a and 120b in which pMOS and nMOS sources and drains are connected to each other, and latches 120c and 120d in which inverters and inputs and outputs of two-input NAND gates are connected to each other in series. A connected holding unit, an inverter 120e for controlling the CMOS switches 120a and 120b, an inverter 120f for feeding back the output of the holding unit to an input, and an inverter row 120g for controlling a 2-input NAND gate are provided. A rough shift order signal RSO is output from the output of the holding unit. The CMOS switches 120a and 120b are controlled by a shift notification signal SINF. A start signal STT is supplied to the input of the inverter train 120g. The rough shift latch 120 is a circuit that alternately changes the rough shift order signal RSO to the H level and the L level in synchronization with the rising edge of the shift notification signal SINF.
[0101]
FIG. 25 shows details of the shift direction latch 122.
The shift direction latch 122 includes a flip-flop circuit that feeds back the outputs of the two-input NAND gates 122a and 122b, and two-input NOR gates 122c and 122d connected to the respective inputs of the flip-flop circuit. ing. Control signals C and D are supplied to the input of the NOR gate 122c. Control signals A and B are supplied to the input of the NOR gate 122d. A rough shift direction signal RSD is output from the output of the NOR gate 122b. The shift direction latch 122 sets the rough shift direction signal RSD to L level when the control signals C and D become H level, and sets the rough shift direction signal RSD to H level when the control signals A and B become H level. It is a circuit to make.
[0102]
FIG. 26 shows details of the register selection switch 124.
The register selection switch 124 includes eight AND circuits each including a two-input NAND gate and an inverter, and an inverter. The register selection switch 124 outputs control signals A, B, C, and D as control signals A1, B1, C1, and D1 when the rough shift order signal RSO is at the H level, and controls when the rough shift order signal RSO is at the L level. This circuit outputs signals A, B, C, and D as control signals A2, B2, C2, and D2.
[0103]
FIG. 27 shows the fine control unit 52.
The fine control unit 52 includes a fine control 134, a binary counter 136, and a maximum / minimum detector 138.
The fine control 134 receives the rough shift order signal RSO, the comparison result signal COMP, and the fine enable signal FEN, and outputs a count up signal UP and a count down signal DOWN.
[0104]
The binary counter 136 increases the built-in counter when it receives the count-up signal UP, and decreases the built-in counter when it receives the count-down signal DOWN. The binary counter 136 is configured as a 4-bit counter, and outputs the value of each bit as count signals CNT3-CNT0. Here, the count signal CNT3 corresponds to the upper bits.
[0105]
The maximum / minimum detector 138 outputs a maximum signal MAX when the counter value reaches the maximum (all bits are at the H level), and outputs a minimum signal MIN when the counter value reaches the minimum (zero). It is.
FIG. 28 shows details of the fine control 134.
The fine control 134 includes a combinational circuit composed of a NAND gate and an inverter. The fine control 134 is a circuit that outputs a count-up signal UP and a count-down signal DOWN in accordance with the control state diagram shown in FIG. For example, the count up signal UP and the count down signal DOWN are both deactivated when the fine enable signal FEN is at L level. The count up signal UP is when the fine enable signal FEN, the rough shift order signal RSO, and the comparison result signal COMP are at the H level, and when the fine enable signal FEN is at the H level, the rough shift order signal RSO, and the comparison result signal COMP is at the L level. Activated. The countdown signal DOWN is when the fine enable signal FEN and the rough shift order signal RSO are H level and the comparison result signal COMP is L level, and when the fine enable signal FEN and the comparison result signal COMP are H level and the rough shift order signal RSO is L level. Sometimes activated.
[0106]
In the semiconductor integrated circuit described above, the phase of the internal clock signal CLKI is adjusted as described below.
FIG. 30 is a flowchart showing the phase adjustment control performed by each circuit described above. The phase adjustment control is started by releasing the reset signal / RESET. After the initial setting (FIG. 31), rough initial adjustment (FIG. 31), fine initial adjustment (FIGS. 32 and 33), and rough / fine adjustment (FIG. 34). , 35) are sequentially performed. Rough initial adjustment and fine initial adjustment correspond to coarse adjustment, and rough / fine adjustment corresponds to fine adjustment.
[0107]
(A) Initial setting (FIG. 31)
First, in step S1, the first and second shift registers 60 and 64, the rough / fine control unit 48, and the rough control unit of the delay clock generation unit 36 to which the start signal STT is supplied as shown in FIGS. 50 rough shift latches 120, the binary counter 136 of the fine control unit 52, and the first and second frequency dividing circuits 82 and 84 of the phase comparison unit 46 are initialized.
[0108]
FIG. 36 shows the operation of the start signal generator 32.
After receiving the inactivation of the reset signal / RESET, the start signal generator 32 sets the start signal STT to the H level in synchronization with the falling edge of the internal clock signal CLK-K. For this reason, at the start of phase comparison, the delay clock generation unit 36, the phase comparison unit 46, and the like start operation in synchronization with each other, and phase comparison is always started from a predetermined state. Further, for example, in the first frequency dividing circuit 82, the H level period of the internal clock signal CLK-K is masked by the start signal STT, preventing a hazard and preventing malfunction at the start of phase comparison. .
[0109]
The deactivation of the reset signal / RESET is performed in response to a DLL start signal, a DLL reset release signal, a power-on completion detection signal, etc. from a mode register built in the semiconductor integrated circuit.
The first shift register 60 (FIG. 5) and the second shift register (FIG. 6) are activated in response to the H level of the start signal STT, and control signals A1, B1, C1, D1 and control signals A2, B2, respectively. , C2, D2 can be accepted. The binary counter 136 (FIG. 27) of the fine control unit 52 receives the H level of the start signal STT and sets the counter to the central value C (3: 0) = (1,0,0,0).
[0110]
The rough / fine control unit 48 (FIG. 18) sets the rough lock on signal RLON to L level by initialization. The rough shift latch 120 sets the rough shift order signal RSO to L level by initialization.
The first and second frequency dividers 82 and 84 (FIG. 13) activate each frequency divider 92 in response to the H level of the start signal STT.
[0111]
FIG. 37 shows the timing of each clock signal in the phase comparator 46.
After receiving the internal clock signal CLK-K, the first frequency dividing circuit 82 starts outputting the reference clock signal REFCLK with five clocks. The second frequency divider 84 receives the internal clock signal CLKI and outputs a signal divided by 3 clocks. FIG. 37 shows a case where the delay time setting in the delay clock generator 36 is minimum. The signal output from the second frequency dividing circuit 84 is supplied to the dummy output buffer 86 and the dummy input buffer 88, and the internal clock signal DICLK delayed by the delay time T5 is generated. Then, the phases of the reference clock signal REFCLK and the internal clock signal DICLK are compared.
[0112]
By performing the operations of the first and second frequency dividers 82 and 84 in synchronization with the start signal STT, the phase adjustment is always started with a predetermined phase difference.
Next, in step S2, the delay stage is initialized. The delay clock generation unit 36 shown in FIG. 2 generates internal clock signals BCLK and / BCLK using, for example, internal clock signals CLK13 and / CLK13 output from the delay stage D13, and outputs the internal clock signals from the delay stage D03. The internal clock signals ACLK and / ACLK are generated using the clock signals CLK03 and / CLK03. The initial setting of the delay stage is performed in accordance with the initial value (L level) of the rough shift order signal RSO. Here, the L level of the rough shift order signal RSO indicates that the phase of the internal clock signal ACLK is slower than the phase of the internal clock signal BCLK. Although not specifically shown as a circuit, the initial setting of the delay stage may be performed by controlling the control signals A1-D1 and A2-D2, and an initial circuit is provided to force the first and second shifts. The values of the registers 60 and 62 may be set.
[0113]
(B) Rough initial setting (FIG. 31)
First, in step S3, the phase comparison circuit 90 shown in FIG. 12 compares the phases of the reference clock signal REFCLK and the internal clock signal DICLK. When the phase of internal clock signal DICLK is ahead of the phase of reference clock signal REFCLK, comparison result signal COMP is set to the H level. Thereafter, the internal clock signal DICLK is controlled to be delayed by the H level of the comparison result signal COMP. When the phase of the internal clock signal DICLK is delayed from the phase of the reference clock signal REFCLK, the comparison result signal COMP is set to the L level. Thereafter, the control of advancing the phase of the internal clock signal DICLK is performed according to the L level of the comparison result signal COMP.
[0114]
In step S4, the rough / fine control unit 48 shown in FIG. 18 uses the EOR circuit 114 to determine the information (previous shift direction) held in the shift direction holding circuit 112 and the current shift direction. Compare for a match.
In step S5, when the comparison results in the shift direction match (the shift direction is the same), the control proceeds to step S6. If the comparison result is inconsistent (shift direction is changed), it is determined that the phase of the internal clock signal DICLK has approached the phase of the reference clock signal REFCLK, and the rough initial adjustment is completed, so the control shifts to step S9. Since the determination of the completion of rough initial adjustment is easily performed by a simple latch circuit (shift direction holding circuit 112), the circuit scale is reduced.
[0115]
The EOR circuit 114 of the rough / fine control unit 48 outputs an H level when the comparison result does not match. Since correct comparison cannot be performed immediately after the start of phase adjustment, the control is forcibly shifted to step S6.
In step S6, the rough control 118 shown in FIG. 21 performs control to switch the delay stage. The delay stage is controlled according to the control state diagram shown in FIG. 22 and the timing diagram shown in FIG. During rough initial adjustment, the rough lock on signal RLON is at L level. Therefore, the rough control 118 sets the advance signal FW to the H level and the control signals A and B to the H level when the comparison result signal COMP is at the L level. The rough control 118 sets the delay signal BW to H level and the control signals C and D to H level when the comparison result signal COMP is at H level.
[0116]
The shift register selection circuit 124 shown in FIG. 26 outputs the control signals A, B, C, and D as the control signals A1, B1, C2, and D2 when the rough shift order signal RSO is at the L level, and the rough shift order signal RSO is When the signal is at the H level, control signals A, B, C, and D are output as control signals A2, B2, C1, and D1.
FIG. 38A shows an outline of switching control of these signals when the phase of the internal clock signal ACLK is ahead of the phase of the internal clock signal BCLK.
[0117]
As a result of the phase comparison, when the comparison result signal COMP becomes H level, the internal clock signal ACLK is changed to ACLK ′ and the phase is advanced. That is, the advance signal BW is set to H level, the control signals C and D are set to H level, and the control signals C1 and D1 are set to H level according to the H level of the rough shift order signal RSO.
The first shift register 60 shown in FIG. 5 receives the control signals C1 and D1, sets the selection signal P03 to L level, sets the selection signal P04 to H level, and sets the enable signal E03 to L level. That is, the output node of the inverter 66c of the control circuit 66 outputting the selection signal P03 is forcibly changed to L level by the H level of the control signal D1, and the enable signal E03 is changed from H level to L level. Due to this L level, the output of the NAND gate 66b becomes H level, the selection signal P03 becomes L level, and the output (selection signal P04) of the NOR gate 66a of the adjacent control circuit 66 (left side in the figure) becomes H level. .
[0118]
In response to the L level of the enable signal E03, the delay stage activation circuit 56 shown in FIG. 9 changes the enable signal EN04 from the L level to the H level. The first switch circuit 58 shown in FIG. 7 is switched by the H level of the selection signal P04, and a new internal clock signal ACLK ′ is generated using the output of the delay stage D04.
Here, when the phase is delayed, the activation of the even-numbered selection signal (P04, etc.) is performed when the control signal D1 becomes H level. Similarly, the activation of the odd-numbered selection signal (P03, etc.) is performed when the control signal C1 becomes H level.
[0119]
On the other hand, when the comparison result signal COMP becomes L level as a result of the phase comparison, the internal clock signal BCLK is changed to BCLK ′ and the phase is delayed. That is, the advance signal FW is set to H level, the control signals A and B are set to H level, and the control signals A2 and B2 are set to H level by the H level of the rough shift order signal RSO.
The second shift register 64 shown in FIG. 6 receives the control signals A2 and B2, sets the selection signal P13 to L level, sets the selection signal P12 to H level, and sets the enable signal E12 to H level. That is, according to the H level of the control signal A2, the output node of the NAND gate 66b of the control circuit 66 outputting the selection signal P12 is forcibly changed to the L level, and the selection signal P12 is changed from the L level to the H level. When the output of the inverter 66c changes to the H level, the enable signal E12 changes from the L level to the H level, and the output (selection signal P13) of the NOR gate 66a of the adjacent control circuit 66 (left side in the figure) changes to the L level. .
[0120]
The delay stage activation circuit 56 shown in FIG. 9 changes the enable signal EN13 from the H level to the L level according to the H level of the enable signal E12. In response to the L level of the enable signal EN13, the delay stage D13 is deactivated. The second switch circuit 62 shown in FIG. 8 is switched by the H level of the selection signal P12, and a new internal clock signal BCLK ′ is generated using the output of the delay stage D12.
[0121]
Here, when the phase is advanced, the activation of the even-numbered selection signal (P12 or the like) is performed when the control signal A2 becomes H level. Similarly, the activation of the odd-numbered selection signal (P13 or the like) is performed when the control signal B2 becomes H level.
FIG. 38B shows an outline of switching control of these signals when the phase of the internal clock signal ACLK is delayed from the phase of the internal clock signal BCLK at the time of rough initial adjustment.
[0122]
After the above initial setting, as shown in FIG. 38A, the internal clock signals BCLK and ACLK are generated using the outputs of the delay stages D11 and D02, respectively.
As a result of the phase comparison, when the comparison result signal COMP becomes H level, control for changing the internal clock signal BCLK to BCLK ′ is performed. That is, the advance signal BW is set to the H level, the control signals C and D are set to the H level, and the control signals C2 and D2 are set to the H level according to the L level of the rough shift order signal RSO. Similarly to the description of FIG. 38A described above, the second shift register 64 operates, the second switch circuit 62 is switched, and a new internal clock signal BCLK ′ is generated using the output of the delay stage D13. Is done.
[0123]
On the other hand, when the comparison result signal COMP becomes L level as a result of the phase comparison, control for changing the internal clock signal ACLK to ACLK ′ is performed. That is, the advance signal FW is set to H level, the control signals A and B are set to H level, and the control signals A1 and B1 are set to H level by the L level of the rough shift order signal RSO. Similarly to the description of FIG. 38A described above, the first shift register 60 operates, the first switch circuit 58 is switched, and a new internal clock signal ACLK ′ is generated using the output of the delay stage D02. Is done.
[0124]
When the shift direction is reversed by switching the delay stage, the shift direction latch 122 shown in FIG. 25 inverts the level of the rough shift direction signal RSD.
FIG. 39 shows changes in the internal clock signal CLKI due to switching between the internal clock signals ACLK and BCLK. 39A shows the case where the initial value of the binary counter 136 is set to “8” in the center employed in the present embodiment. FIG. 39B shows the case where the initial value of the binary counter 136 is shifted from the center. The case of 4 ″ is shown.
[0125]
The interpolation circuits 38 and 40 shown in FIG. 10 output the internal clock signal ACLK as the internal clock signal CLKI when the counter value is minimum (zero), and when the counter value is maximum (decimal number 15), The internal clock signal BCLK is output as the internal clock signal CLKI. Therefore, as the counter value increases, the phase of the internal clock signal CLKI always changes from the odd delay stages D01, D02, D03 toward the even delay stages D11, D12. Therefore, when the counter value is set to the center value, as shown in FIG. 39A, the phase of the internal clock signal CLKI changes evenly when the delay stage is switched. For this reason, in fine initial adjustment after rough initial adjustment, the range of phase adjustment by the interpolation circuits 38 and 40 is set within a predetermined range, and the number of phase comparisons can be reduced. On the other hand, when the counter value is shifted from the central value, as shown in FIG. 39B, the position of the internal clock signal CLKI does not change evenly when the delay stage is switched. For this reason, the number of phase comparisons increases in fine initial adjustment.
[0126]
In step S7, the rough shift latch 120 shown in FIG. 24 receives the shift notification signal SINF output from the rough control 118, inverts the rough shift order signal RSO, and the phases of the internal clock signals ACLK and BCLK are reversed. Is communicated to each circuit.
[0127]
In step S8, the shift direction holding circuit 112 of the rough / fine control unit 48 shown in FIG. 18 holds the current value of the rough shift direction signal RSD. Thereafter, the control again proceeds to step S3.
On the other hand, in step S9, the shift direction holding circuit 112 of the rough / fine control unit 48 holds the current value of the rough shift direction signal RSD.
[0128]
Next, in step S10, the lock-on generation circuit 116 of the rough / fine control unit 48 receives the H level output from the EOR circuit 114 and sets the rough lock-on signal RLON to the H level.
The rough initial adjustment is thus completed, and then fine initial adjustment is performed.
(C) Fine initial adjustment (FIGS. 32 and 33)
First, in step S12, control is divided according to the level of the rough shift order signal RSO. If the rough shift order signal RSO is at the H level, the control proceeds to step S13. If the rough shift order signal RSO is at the L level, the control proceeds to step S22. That is, steps S13 to S21 are fine initial adjustment performed when the phase of the internal clock signal ACLK is ahead of the internal clock signal BCLK. Steps S22 to S30 are fine initial adjustments performed when the phase of the internal clock signal ACLK is delayed from the internal clock signal BCLK.
[0129]
In step S13, the phase comparison circuit 90 shown in FIG. 12 compares the phases of the internal clock signal DICLK and the reference clock signal REFCLK. When the phase of the internal clock signal DICLK is delayed from the phase of the reference clock signal REFCLK, the control proceeds to step S14 in order to advance the phase of the internal clock signal DICLK. If the phase of the internal clock signal DICLK is ahead of the phase of the reference clock signal REFCLK, the control shifts to step S15 in order to delay the phase of the internal clock signal DICLK.
[0130]
In step S14, the values of the upper 2 bits CNT3 and CNT2 of the binary counter are set to “−1”, and the count value is set to “4” in decimal.
In step S15, the upper two bits CNT3 and CNT2 of the binary counter are incremented by "+1", and the count value is decremented by "12".
Similarly, in steps S16 to S18 and steps S19 to S21, the value of the next upper 2 bits of the binary counter is set to “−1” or “+1” according to the phase comparison result.
[0131]
On the other hand, in step S22, the phase comparison circuit 90 shown in FIG. 12 compares the phases of the internal clock signal DICLK and the reference clock signal REFCLK. When the phase of the internal clock signal DICLK is delayed from the phase of the reference clock signal REFCLK, the control proceeds to step S23 in order to advance the phase of the internal clock signal DICLK. When the phase of the internal clock signal DICLK is ahead of the phase of the reference clock signal REFCLK, the control shifts to step S24 in order to delay the phase of the internal clock signal DICLK.
[0132]
In step S23, the upper two bits CNT3 and CNT2 of the binary counter are incremented by "+1", and the count value is decremented by "12".
In step S24, the values of the upper 2 bits CNT3 and CNT2 of the binary counter are set to “−1”, and the count value is set to “4” in decimal.
Similarly, in steps S25 to S27 and steps S28 to S30, the value of the next upper 2 bits of the binary counter is “+1” or “−1” according to the phase comparison result.
[0133]
FIG. 40A shows an outline of fine initial adjustment when the phase of the internal clock signal ACLK is advanced earlier than the phase of the internal clock signal BCLK. The count value of the binary counter 136 is determined sequentially from the upper bits according to the comparison result in the phase comparison circuit 90. Then, the phase of the internal clock signal CLKI changes according to the counter value.
[0134]
FIG. 40B shows an outline of fine initial adjustment when the phase of the internal clock signal ACLK is delayed from the phase of the internal clock signal BCLK. The count value of the binary counter 136 is sequentially determined from the upper bits in accordance with the comparison result in the phase comparison circuit 90, as in FIG. Then, the phase of the internal clock signal CLKI changes according to the counter value.
[0135]
In this way, since the phase of the internal clock signal ABCLK is changed rapidly, the number of phase comparisons in the fine initial adjustment is minimized. Further, the phase adjustment is performed earlier than in the case where the fine adjustment is performed immediately after the rough initial adjustment.
After executing Steps S20 and S21 or Steps S29 and S30, the control shifts to rough / fine adjustment.
[0136]
(C) Rough / Fine adjustment (FIGS. 34 and 35)
First, in step S32, the level of the rough shift order signal RSO is compared. If the rough shift order signal RSO is at the H level, the control proceeds to step S33. If the rough shift order signal RSO is at the L level, the control proceeds to step S44. That is, steps S33 to S43 are a control flow of rough / fine adjustment performed when the phase of the internal clock signal ACLK is ahead of the internal clock signal BCLK. Steps S44 to S55 are a control flow of rough / fine adjustment performed when the phase of the internal clock signal ACLK is delayed from the internal clock signal BCLK.
[0137]
In step S33, the phase comparison circuit 90 shown in FIG. 12 compares the phases of the internal clock signal DICLK and the reference clock signal REFCLK. When the phase of the internal clock signal DICLK is delayed from the phase of the reference clock signal REFCLK, the control proceeds to step S34 in order to advance the phase of the internal clock signal DICLK. If the phase of the internal clock signal DICLK is ahead of the phase of the reference clock signal REFCLK, the control shifts to step S35 in order to delay the phase of the internal clock signal DICLK.
[0138]
In step S34, the rough / fine control unit 48 shown in FIG. 18 monitors the level of the minimum signal MIN. When the minimum signal MIN is at the L level, the rough / fine control unit 48 determines that the binary counter 136 does not fall down even if the phase of the internal clock signal DICLK is advanced. Then, as shown in the control state diagram (A) of FIG. 19, the rough / fine control unit 48 activates the fine enable signal FEN, and the control proceeds to step S36. The rough / fine control unit 48 determines that when the phase of the internal clock signal DICLK is advanced when the minimum signal MIN is at the H level, the binary counter 136 is lowered. Then, as shown in the control state diagram (D) of FIG. 19, the rough / fine control unit 48 activates the rough enable signal REN and shifts the control to step S37.
[0139]
In step S36, the fine control 134 shown in FIG. 28 receives the fine enable signal FEN and activates the countdown signal DOWN as shown in the control state diagram (A) of FIG. The binary counter 136 receives the countdown signal DOWN, decrements the counter value “−1”, and outputs it as counter signals CNT3 to CNT0. The interpolation circuits 38 and 40 shown in FIG. 10 advance the phases of the internal clock signals CLKI and / CLKI in accordance with the counter signals CNT3-CNT0.
[0140]
In the rough / fine adjustment, by shifting the 4-bit counter value one by one, the phase adjustment can be performed accurately with respect to a phase shift due to a temperature variation or the like.
In step S37, the rough control 118 shown in FIG. 21 receives the rough enable signal REN, activates the advance signal FW as shown in the control state diagram (D) of FIG. 22, and controls the control signals A, B and The shift notification signal SINF is activated (FIGS. 23 (c) (d) (g)). The shift register selection circuit 124 shown in FIG. 26 receives the control signals A and B and activates the control signals A2 and B2. The second shift register 64 shown in FIG. 3 receives selection signals P11, P12,... And enable signals E11, E12,. Shift one. The second switch circuit 62 receives the newly activated selection signal (for example, P11), and shifts the even-numbered delay stage to be selected to the previous stage (for example, D11). Then, the delay circuit 54 outputs internal clock signals BCLK and / BCLK whose phases are advanced from those of the internal clock signals ACLK and / ACLK. The delay stage activation circuit 56 deactivates an enable signal (for example, E12) supplied to an even-numbered delay stage (for example, D12), and reduces power consumed by the delay circuit.
[0141]
Here, the switching of the delay stage is performed when the count value of the binary counter 136 is the minimum value (zero). For this reason, as shown in FIG. 39A, the phase of the internal clock signal CLKI does not change by switching the delay stage. In other words, jitter does not occur in the internal clock signal CLKI due to switching of the delay stage.
In step S38, the rough shift latch 120 shown in FIG. 24 receives the shift notification signal SINF and inverts the level of the rough shift order signal RSO.
[0142]
In step S39, the fine control 134 shown in FIG. 27 activates the count-up signal UP. In response to the count-up signal UP, the binary counter 136 increases the counter value by one.
In the rough / fine adjustment, the phase adjustment unit of the internal clock signal CLKI is one unit of the binary counter 136 even if the delay stage is switched. For this reason, even when the phase comparison result momentarily deviates due to the generation of noise, the phase of the internal clock signal CLKI does not change following it. That is, it is not easily affected by noise.
[0143]
On the other hand, in step S35, the rough / fine control unit 48 shown in FIG. 18 monitors the level of the maximum signal MAX. The rough / fine control unit 48 determines that the binary counter 136 is not incremented even if the phase of the internal clock signal DICLK is delayed when the maximum signal MAX is at the L level. Then, as shown in the control state diagram (A) of FIG. 19, the rough / fine control unit 48 activates the fine enable signal FEN and shifts the control to step S40. The rough / fine control unit 48 determines that the binary counter 136 is incremented when the phase of the internal clock signal DICLK is delayed when the maximum signal MAX is at the H level. Then, as shown in the control state diagram (C) of FIG. 19, the rough / fine control unit 48 activates the rough enable signal REN and shifts the control to step S41.
[0144]
In step S40, the fine control 134 shown in FIG. 28 receives the fine enable signal FEN and activates the count-up signal UP as shown in the control state diagram (B) of FIG. In response to the count-up signal UP, the binary counter 136 increments the counter value by “+1” and outputs it as counter signals CNT3-CNT0. The interpolation circuits 38 and 40 shown in FIG. 10 delay the phases of the internal clock signals CLKI and / CLKI according to the counter signals CNT3-CNT0.
[0145]
In step S41, the rough control 118 shown in FIG. 21 receives the rough enable signal REN, activates the delay signal BW as shown in the control state diagram (C) of FIG. 22, and controls the control signals C, D and The shift notification signal SINF is activated (FIGS. 23 (e) (f)). The shift register selection circuit 124 shown in FIG. 26 receives the control signals C and D and activates the control signals C1 and D1. The first shift register 60 shown in FIG. 3 receives the control signals C1, D1, and activates selection signals P01, P02,... And enable signals E01, E02,. Shift one. The first switch circuit 58 receives the newly activated selection signal (for example, P03) and shifts the odd-numbered delay stage to be selected to the next stage (for example, D03). Then, the delay circuit 54 outputs internal clock signals ACLK and / ACLK that are later in phase than the internal clock signals BCLK and / BCLK.
[0146]
Here, switching of the delay stage is performed when the count value of the binary counter 136 is the maximum value (decimal number “16”). For this reason, as shown in FIG. 39A, the phase of the internal clock signal CLKI does not change by switching the delay stage. That is, as in step S37, no jitter occurs in the internal clock signal CLKI by switching the delay stage.
[0147]
In step S42, the same control as in step S38 described above is performed, and the level of the rough shift order signal RSO is inverted.
In step S43, the fine control 134 shown in FIG. 27 activates the countdown signal DOWN. The binary counter 136 receives the countdown signal DOWN and decrements the counter value by one.
[0148]
After executing Steps S36, S39, S40, and S43, the control returns to Step S32.
On the other hand, in steps S44 to S54, the control for advancing the phase of the internal clock signal DICLK and the control for delaying are performed in reverse to the above-described steps S33 to S43. First, in step S44, the phase comparison circuit 90 shown in FIG. 12 compares the phases of the internal clock signal DICLK and the reference clock signal REFCLK. If the phase of the internal clock signal DICLK is ahead of the phase of the reference clock signal REFCLK, control proceeds to step S45 in order to advance the phase of the internal clock signal DICLK. When the phase of the internal clock signal DICLK is delayed from the phase of the reference clock signal REFCLK, the control shifts to step S46 in order to delay the phase of the internal clock signal DICLK.
[0149]
In step S45, the rough / fine control unit 48 shown in FIG. 18 monitors the level of the maximum signal MAX. The rough / fine control unit 48 determines that the binary counter 136 is not incremented even if the phase of the internal clock signal DICLK is advanced when the maximum signal MAX is at the L level. Then, as shown in the control state diagram (F) of FIG. 19, the rough / fine control unit 48 activates the fine enable signal FEN, and the control proceeds to step S47. The rough / fine control unit 48 determines that the binary counter 136 is incremented when the phase of the internal clock signal DICLK is delayed when the maximum signal MAX is at the H level. Then, as shown in the control state diagram (G) of FIG. 19, the rough / fine control unit 48 activates the rough enable signal REN and shifts the control to step S48.
[0150]
In step S47, the same control as in step S40 described above is performed, and the count value of the binary counter 136 is incremented by "+1".
In step S48, the rough control 118 shown in FIG. 21 receives the rough enable signal REN and activates the advance signal FW as shown in the control state diagram (G) of FIG. The shift notification signal SINF is activated (FIGS. 23 (c) (d) (g)). The shift register selection circuit 124 shown in FIG. 26 receives the control signals A and B and activates the control signals A1 and B1. 3 receives selection signals P01, P02,... And enable signals E01, E02,. Shift one. The first switch circuit 58 receives the newly activated selection signal (for example, P01) and shifts the odd-numbered delay stage to be selected to the previous stage side (for example, D01). Then, the delay circuit 54 outputs internal clock signals ACLK and / BCLK that are advanced in phase from the internal clock signals BCLK and / BCLK. The delay stage activation circuit 56 deactivates an enable signal (for example, E02) supplied to an odd-numbered delay stage (for example, D02), and reduces power consumed by the delay circuit.
[0151]
In step S49, the same control as in step S38 described above is performed, and the level of the rough shift order signal RSO is inverted.
In step S50, the same control as in step S43 described above is performed, and the count value of the binary counter 136 is "-1".
On the other hand, in step S46, the rough / fine control unit 48 shown in FIG. 18 monitors the level of the minimum signal MIN. When the minimum signal MIN is at the L level, the rough / fine control unit 48 determines that the binary counter 136 is not lowered even if the phase of the internal clock signal DICLK is delayed. Then, as shown in the control state diagram (F) of FIG. 19, the rough / fine control unit 48 activates the fine enable signal FEN, and the control proceeds to step S51. The rough / fine control unit 48 determines that when the phase of the internal clock signal DICLK is delayed when the minimum signal MIN is at the H level, the binary counter 136 is lowered. Then, as shown in the control state diagram (J) of FIG. 19, the rough / fine control unit 48 activates the rough enable signal REN and shifts the control to step S52.
[0152]
In step S51, the same control as in step S36 described above is performed, and the count value of the binary counter 136 is set to "-1."
In step S52, the rough control 118 shown in FIG. 21 receives the rough enable signal REN and activates the delay signal BW as shown in the control state diagram (J) of FIG. The shift notification signal SINF is activated (FIGS. 23 (e) (f)). The shift register selection circuit 124 shown in FIG. 26 receives the control signals C and D and activates the control signals C2 and D2. The second shift register 64 shown in FIG. 3 receives selection signals P11, P12,... And enable signals E11, E12,. Shift one. The second switch circuit 62 receives the newly activated selection signal (for example, P13) and shifts the even-numbered delay stage to be selected to the next stage side (for example, D13). Then, the delay circuit 54 outputs internal clock signals BCLK and / BCLK that are later in phase than the internal clock signals ACLK and / ACLK.
[0153]
In step S53, the same control as in step S38 described above is performed, and the level of the rough shift order signal RSO is inverted.
In step S54, the same control as in step S39 described above is performed, and the count value of the binary counter 136 is incremented by "+1".
After executing Steps S47, S50, S51, and S54, the control proceeds to Step S55.
[0154]
In step S55, the level of the rough shift order signal RSO is compared. When the rough shift order signal RSO is at the L level, the control again proceeds to step S44. If the rough shift order signal RSO is at the H level, the control proceeds to step S33.
As described above, steps S32 to S55 are repeatedly executed to perform rough / fine adjustment. Then, the phase of the internal clock signal CLKI is matched with the phase of the clock signal CLK.
[0155]
In the semiconductor integrated circuit configured as described above, the phase adjustment is performed in three stages of rough initial adjustment, fine initial adjustment (coarse adjustment), and rough / fine adjustment (fine adjustment), so that the internal clock signal DICLK And the reference clock signal REFCLK can be matched quickly with a small number of phase comparisons.
Since the delay circuit 54 is configured by cascading delay stages D01, D11,... With the delay time fixed to a predetermined value, the delay circuit 54 can be configured simply. Generally, the delay stages D01, D11,... Are often composed of a CR time constant circuit having a large layout size. In the present invention, by fixing the delay times of the delay stages D01, D11,..., Unnecessary elements are not required and the layout size is reduced. As a result, the chip size can be reduced.
[0156]
Since the phase is finely adjusted using the interpolation circuits 38 and 40, the minimum unit of the fine adjustment can be reduced according to the system of the interpolation circuits 38 and 40. That is, phase adjustment can be reliably performed even in a semiconductor integrated circuit to which high frequency clock signals CLK and / CLK are supplied.
Since the delay stage activation circuit 56 inactivates unused delay stages, the power consumption can be reduced.
[0157]
Since independent power lines are connected to the delay stages D01, D11,..., It is possible to prevent the delay times of the delay stages D01, D11,. . In addition, since the independent power supply line has a low voltage, the power consumption of the delay stages D01, D11,... Can be reduced, and its output waveform is made more gradual than when the power supply line VDD is connected. be able to.
[0158]
Since the period T1 overlapping the internal clock signals ACLK and BCLK is provided, the interpolation circuit 38 can be operated normally and reliably.
The start signal STT is activated in synchronization with the falling edge of the internal clock signal CLK-K. Therefore, when the phase comparison is started, the operations of the delay clock generation unit 36, the phase comparison unit 46, and the like can be started in synchronization with each other, and the phase comparison can always be started from a predetermined state. Further, it is possible to prevent the H level period of the internal clock signal CLK-K or the like from being masked by the start signal STT and causing a hazard, thereby preventing a malfunction at the start of the phase comparison.
[0159]
Using the first and second frequency dividers 82 and 84, the internal clock signal DICLK and the reference clock signal REFCLK frequency-divided by a quarter were compared in phase. Therefore, even when high-frequency clock signals CLK and / CLK are supplied, the phase comparison circuit 90 can be reliably operated. Further, since the frequency of phase comparison is reduced, power consumption can be reduced. Furthermore, the power consumption can be further reduced by further reducing the frequency of phase comparison after the end of steps S20 and S21 in FIG. 32, or after a predetermined number of clocks after the rough lock on signal RLON becomes H level. it can.
[0160]
At the start of the phase comparison, the first frequency dividing circuit 82 and the second frequency dividing circuit 84 are operated in synchronization with the start signal STT, and the internal clock signal and the reference clock signal REFCLK frequency-divided after a predetermined number of clocks are output. Therefore, when the frequencies of the clock signals CLK and / CLK are in a specific range, the maximum value of the phase shift between the internal clock signal and the reference clock signal REFCLK supplied to the phase comparison circuit 90 is reduced at the start of phase comparison. can do. As a result, the number of phase comparisons in coarse adjustment can be reduced. In general, a semiconductor integrated circuit has a range of operating frequency determined by a product, and therefore, a sufficient effect can be obtained by applying the present invention.
[0161]
Since the determination of the completion of the rough initial adjustment is made by a simple latch circuit (shift direction holding circuit 112), the circuit scale can be reduced.
In the rough initial adjustment, the counter value of the binary counter 136 is set to the center value, so that the phase of the internal clock signal CLKI can be changed evenly when the delay stage is switched. For this reason, in the fine initial adjustment after the rough initial adjustment, the range of phase adjustment by the interpolation circuits 38 and 40 is set within a predetermined range, and the number of phase comparisons can be minimized.
[0162]
In the fine initial adjustment, the phase of the internal clock signal ABCLK is changed rapidly, so that the number of phase comparisons in the fine initial adjustment can be minimized. In addition, phase adjustment can be performed faster than when fine adjustment is performed immediately after rough initial adjustment.
In rough / fine adjustment, when the counter value increases, the phase of the internal clock signal CLKI is always directed from the odd delay stages D01, D02,... To the even delay stages D11, D12,. When the counter value decreases, the phase of the internal clock signal CLKI always changes from the odd delay stages D01, D02, ... to the even delay stages D11, D12, ... I let you. Therefore, it is not necessary to reset or set the counter value even when the counter value becomes maximum or minimum, and it is only necessary to switch the delay stage delay stage D01 D11,. For this reason, as shown in FIG. 39A, the phase of the internal clock signal CLKI does not change by switching the delay stage. As a result, it is possible to prevent jitter from occurring in the internal clock signal due to switching of the delay stage.
[0163]
In rough / fine adjustment, control was performed to shift the 4-bit counter value one by one. For this reason, even when the phase comparison result deviates momentarily due to the generation of noise, it is possible to prevent the phase of the internal clock signal CLKI from changing following it. That is, it is not easily affected by noise.
In addition, phase adjustment can be performed accurately with respect to phase shift due to temperature fluctuation, voltage fluctuation, and the like. The phases of the internal clock signals ACLK and BCLK are equally divided into 16, and the internal clock signals ABCLK having 16 types of phases can be generated by the interpolation circuits 38 and 40.
[0164]
Next, a second embodiment of the semiconductor integrated circuit of the present invention will be described. This embodiment corresponds to claims 1 to 5. The same circuits as those described in the first embodiment are denoted by the same reference numerals, and detailed description of these circuits is omitted.
FIG. 41 shows the clock control unit 140 mounted on the DDR-SDRAM. The clock control unit 140 of this embodiment is different from the first embodiment in a phase comparison unit 141, a rough / fine control unit 142, and a rough control unit 144.
[0165]
The phase comparator 141 receives the internal clock signals CLKI and CLK-K and the start signal STT, and outputs a fine comparison result signal FCOMP, a rough phase comparison signal RCOMP, and a timing signal TIM. The rough / fine control unit 142 receives the rough comparison result signal COMP, the timing signal TIM, the maximum signal MAX, the minimum signal MIN, the rough shift order signal RSO, and the start signal STT, and receives the rough enable signal REN, the fine enable signal FEN, and the rough signal. The lock-on signal RLON is output. The rough control unit 144 receives the rough enable signal REN, the rough lock on signal RLON, the maximum signal MAX, the minimum signal MIN, and the start signal STT, and outputs the rough shift order signal RSO and the control signals A1-D1 and A2-D2. ing.
[0166]
FIG. 42 shows details of the phase comparison unit 141.
The phase comparator 141 includes the same first frequency divider 82, second frequency divider 84, dummy output buffer 86, and dummy input buffer 88 as those in the first embodiment, a fine phase comparator 148, and a rough phase comparator. 150. The fine phase comparison circuit 148 compares the phases of the reference clock signal REFCLK and the internal clock signal DICLK, and outputs a fine comparison result signal FCOMP. The rough phase comparison circuit 150 compares the phases of the reference clock signal REFCLK and the internal clock signal DICLK, and outputs a rough comparison result signal RCOMP and a timing signal TIM.
[0167]
FIG. 43 shows details of the fine phase comparison circuit 148.
The fine phase comparison circuit 148 is a circuit obtained by removing the timing generation circuit 108 from the phase comparison circuit 90 of the first embodiment. The fine phase comparison circuit 148 outputs the sampling signal SMPL from the output of the NOR gate 102c of the pulse generation circuit 102, and outputs the fine comparison result signal FCOMP from the output of the NAND gate 106b of the flip-flop 106.
[0168]
FIG. 44 shows details of the rough phase comparison circuit 150.
Rough phase comparison circuit 150 is connected to the inputs of flip-flop circuits 150a, 150b, 150c, and 150d, each of two input NAND gates, two-input AND circuit 150e, and flip-flop circuits 150c and 150d. It consists of input NAND gates 150f, 150g, 150h, and 150i, and a timing generation circuit 150j. The timing generation circuit 150j is a circuit in which the delay circuit 108a of the timing generation circuit 108 of the first embodiment is replaced with a CR time constant circuit 150k. The CR time constant circuit 150k has a delay time that is the same as or slightly larger than the delay times of the delay stages D01, D11, D02, D12,... Shown in FIG. The timing generation circuit 150j receives the internal clock signal DICLK and the reference clock signal REFCLK delayed by the CR time constant circuit 150k by the NAND gate 108b, and outputs the timing signal TIM.
[0169]
The reference clock signal REFCLK and the internal clock signal DICLK are supplied to the input of the flip-flop circuit 150a. Output nodes N21 and N22 of the flip-flop circuit 150a are connected to one input of NAND gates 150f and 150g, respectively. The input of the flip-flop circuit 150b is supplied with the reference clock signal REFCLK and the internal clock signal DICLK delayed by the CR time constant circuit 150k of the timing generation circuit 150j. The output nodes N23 and N24 of the flip-flop circuit 150b are respectively connected to one input of NAND gates 150h and 150i.
[0170]
A sampling signal SMPL is supplied to the other input of the NAND gates 150f to 150i. The flip-flop circuits 150c and 150d output comparison result signals CP5 and CP6 and comparison result signals CP7 and CP8, respectively. The AND circuit 150e receives the comparison result signals CP5 and CP8 and outputs a rough lock on signal RLON.
FIG. 45 shows the operation timing of the rough phase comparison circuit 150.
[0171]
When the phase of internal clock signal DICLK is ahead of the phase of reference clock signal REFCLK, flip-flop circuits 150a and 150b shown in FIG. 44 both operate in synchronization with internal clock signal DICLK. For this reason, substantially the same signal is output to the nodes N21 and N23 and the nodes N22 and N24 (FIG. 45 (a)). Here, since the internal clock signal DICLK is supplied to the input of the flip-flop circuit 150b via the CR time constant circuit 150k, the signal waveforms are slightly different. The flip-flop circuits 150c and 150d take in the signals of the nodes N21 to N24 in synchronization with the sampling signal SMPL and output them as comparison result signals CP5 to CP8, respectively (FIG. 45 (b)).
[0172]
When the difference between the phase of the internal clock signal DICLK and the phase of the reference clock signal REFCLK is smaller than the delay time of the CR time constant circuit 150k, the flip-flop circuit 150a operates in synchronization with the internal clock signal DICLK. The circuit 150b operates in synchronization with the reference clock signal REFCLK. For this reason, signals having opposite phases are output to the nodes N21 and N23 and the nodes N22 and N24 (FIG. 45 (c)). The flip-flop circuits 150c and 150d take in the signals of the nodes N21 to N24 in synchronization with the sampling signal SMPL and output them as comparison result signals CP5 to CP8, respectively (FIG. 45 (d)).
[0173]
When the phase of the internal clock signal DICLK is delayed from the phase of the reference clock signal REFCLK, the flip-flop circuits 150a and 150b both operate in synchronization with the reference clock signal REFCLK. Therefore, substantially the same signal is output to the nodes N21 and N23 and the nodes N22 and N24 (FIG. 45 (e)). The flip-flop circuits 150c and 150d take in the signals of the nodes N21 to N24 in synchronization with the sampling signal SMPL and output them as comparison result signals CP5 to CP8, respectively (FIG. 45 (f)).
[0174]
Further, the rough phase comparison circuit 150 has a phase in rough initial adjustment described later when the phase difference becomes smaller than the delay time of the CR time constant circuit 150k and the comparison result signals CP5 and CP8 both become H level. Judge that they match. Then, the rough lock on signal RLON is activated (FIG. 45 (g)). As described above, since the phase match determination at the time of rough initial adjustment is performed by the independent rough phase comparison circuit 150, the shift direction of the internal clock signal ACLK (or / BCLK) is changed unlike the first embodiment. No need to reverse. As a result, rough initial adjustment can be performed at high speed.
[0175]
FIG. 46 shows details of the rough / fine control unit 142. The rough / fine control unit 142 is the same circuit as the combinational circuit 110 of the rough / fine control unit 48 of the first embodiment.
FIG. 47 shows details of the rough control unit 144.
The rough control unit 144 includes a rough control 152, a rough shift latch 120, and a register selection switch 124. The rough shift latch 120 and the register selection switch 124 are the same circuit as in the first embodiment. In this embodiment, the shift direction latch 122 of the first embodiment is not mounted.
[0176]
FIG. 48 shows details of the rough control 152.
The rough control 152 includes a combinational circuit 154, a frequency dividing circuit 128, a control circuit 130, and an OR circuit 132. The frequency dividing circuit 128, the control circuit 130, and the OR circuit 132 are the same circuits as those in the first embodiment.
The combinational circuit 154 is different from the combinational circuit 126 of the first embodiment shown in FIG. 21 in the following points. That is, in the combinational circuit 126, the logic of the comparison result signal COMP is supplied to the 3-input NAND gate and the 2-input NAND gate preceding the NAND gate that outputs the advance signal FW and the delay signal BW. In the combinational circuit 154, the logic of the fine comparison result signal FCOMP is supplied to the 3-input NAND gate, and the comparison result signals CP5 and CP7 and the comparison result signals CP6 and CP8 are respectively supplied to the 2-input NAND gate via the AND circuit. Is supplied.
[0177]
FIG. 49 shows a control state diagram of the operation of the combinational circuit 154.
For example, the combinational circuit 154 activates the delay signal BW when the rough lock on signal RLON is at L level and the comparison result signals CP5 and CP7 are at H level, and the rough lock on signal RLON is at L level and the comparison result signal CP6, When CP8 is at H level, the advance signal FW is activated. The combinational circuit 154 activates the delay signal BW when the rough lock on signal RLON, the rough shift order signal RSO, the maximum signal MAX, and the fine comparison result signal FCOMP are all at the H level. The combination circuit 154 deactivates both the advance signal FW and the delay signal BW when the rough lock on signal RLON and the rough shift order signal RSO are at the H level, the maximum signal MAX, and the minimum signal are at the L level.
[0178]
In the semiconductor integrated circuit described above, the phase of the internal clock signal CLKI is adjusted as described below.
FIG. 50 is a flowchart showing control of phase adjustment performed by each circuit described above. The phase adjustment control is started by releasing the reset signal / RESET, and initial setting, rough initial adjustment, fine initial adjustment, and rough / fine adjustment are sequentially performed.
[0179]
Since the control flow of initial setting, fine initial adjustment, and rough / fine adjustment is the same as that of the first embodiment, description thereof is omitted.
In rough initial adjustment, in step S61, the rough phase comparison circuit 150 shown in FIG. 42 compares the phases of the reference clock signal REFCLK and the internal clock signal DICLK. When the phase of the internal clock signal DICLK is ahead of the phase of the reference clock signal REFCLK, the rough comparison result signal FCOMP is set to the H level. Thereafter, the internal clock signal DICLK is controlled to be delayed by the H level of the rough comparison result signal FCOMP. When the phase of the internal clock signal DICLK is delayed from the phase of the reference clock signal REFCLK, the rough comparison result signal FCOMP is set to the L level. Thereafter, control for advancing the internal clock signal DICLK is performed according to the L level of the rough comparison result signal FCOMP. Further, when the phase of the internal clock signal DICLK matches the phase of the reference clock signal REFCLK, the rough lock on signal RLON is set to the H level.
[0180]
If the rough lock on signal RLON is at H level in step S62, the control shifts to fine adjustment. If the rough lock on signal RLON is at the L level, the control proceeds to step S63.
In step S63, the rough control 152 shown in FIG. 48 performs control to switch delay stages. The delay stage is controlled in accordance with the control state diagram shown in FIG.
[0181]
The inversion of the rough shift order signal RSO in step S64 and the shift direction latch in step S65 are controlled in the same manner as in steps S7 and S8 of the first embodiment. Thereafter, the control again proceeds to step S61.
After the rough initial adjustment, fine initial adjustment and rough / fine adjustment are performed, and the phase of the internal clock signal CLKI is matched with the phase of the clock signal CLK.
[0182]
Also in the semiconductor integrated circuit of this embodiment, the same effects as those of the first embodiment described above can be obtained. Further, in this embodiment, the phase comparison circuit 146 includes the fine phase comparison circuit 148 and the rough phase comparison circuit 150, and the determination of phase matching in the rough initial adjustment and the determination of phase matching in the fine initial adjustment are separately performed. The control circuit was used. For this reason, rough initial adjustment can be performed efficiently and at high speed.
[0183]
Next, a third embodiment of the semiconductor integrated circuit of the present invention will be described. This embodiment corresponds to claims 1 to 5. The same circuits as those described in the first embodiment are denoted by the same reference numerals, and detailed description of these circuits is omitted.
In this embodiment, compared with the first embodiment, only the first frequency dividing circuit 156 is different, and the other configurations are the same. In addition, this embodiment can provide a remarkable effect when applied to a semiconductor integrated circuit that operates at a lower frequency than the first embodiment.
[0184]
FIG. 51 shows the first frequency dividing circuit 156.
The first frequency dividing circuit 156 includes two frequency dividers 92 that are the same as those in the first embodiment. In the previous-stage frequency divider 92, the internal clock signal CLK-K is supplied to the input terminal IN, the start signal STT is supplied to the control terminal STT1, and the power supply line VDD is connected to the control terminal STT2. Switches 156a, 156b, and 156c are connected to the input terminal IN and the control terminals STT1 and STT2 of the frequency divider 92 at the subsequent stage, respectively. The switch 156a is an element that connects one of the output terminals OUT and / OUT of the frequency divider 92 in the previous stage to the input terminal IN. The switch 156b is an element that supplies the H level of the power supply line VDD or the start signal STT to the control terminal STT1. The switch 156 is an element that supplies the H level of the power supply line VDD or the start signal STT to the control terminal STT2. Each switch 156a, 156b, 156c is formed of a CMOS switch. The switches 156a, 156b, and 156c are switched by setting a mode register that sets an operation mode of the semiconductor integrated circuit to a predetermined value.
[0185]
In the present embodiment, the output terminal / OUT of the previous frequency divider 92 is connected to the input terminal IN of the subsequent frequency divider 92, and the control terminal STT1 and the control terminal STT2 of the subsequent frequency divider 92 are The start signal STT and the H level of the power supply line VDD are supplied.
FIG. 52 shows the operation timing of the first frequency divider 156 and the second frequency divider 84 (FIG. 13) at the start of phase adjustment.
[0186]
In this embodiment, the reference clock REFCLK output from the first frequency divider 156 starts to be output in 4 clocks after receiving the internal clock signal CLKI. Therefore, the phase difference T6 between the internal clock signal DICLK and the reference clock REFCLK at the start of phase adjustment is smaller than the phase difference T7 when the reference clock REFCLK is output with 5 clocks. Therefore, when the operating frequency is low, the number of phase comparisons required for rough initial adjustment can be reduced by reducing the number of clocks until the output of the reference clock REFCLK is started. Further, by reducing the phase difference between the internal clock signal DICLK and the reference clock REFCLK at the start of phase adjustment (for example, T7 → T6), the number of delay stages activated in the delay circuit 54 shown in FIG. The power consumption can be reduced.
[0187]
In the first embodiment described above, the shift operations of the odd-numbered delay stages D01, D02,... And the even-numbered delay stages D11, D12,. The example performed by the shift registers 60 and 64 has been described. The present invention is not limited to such an embodiment. For example, as shown in FIG. 53, the shift operation of the delay stages D01, D11, D02, D12,... May be performed by one shift register 160.
[0188]
The shift register 160 includes the same control circuit 66 as the first shift register 60. In the shift register 160, one input of the NOR gate 66a is connected to the output of the NAND gate 66b of the adjacent control circuit 66 (left side in the figure), and the enable signals EN11, EN02,. This is different from the first shift register 60 in that it is output via the first shift register 60.
[0189]
Hereinafter, the operation of the shift register 160 will be briefly described. For example, in the initial state, it is assumed that the selection signals P02 and P12 are set to H level and the enable signal E03 and subsequent levels are set to L level. In this case, the internal clock signals ACLK and BCLK are generated from the outputs of the delay stages D02 and D12, respectively.
As a result of the phase comparison, when the phase needs to be delayed, the control signals C and D are activated. In response to the control signal C, the nMOS 66f of the control circuit 66 outputting the selection signal P12 is turned on, and the output of the inverter 66c is forcibly set to the L level. Due to the L level, the enable signal E03 and the selection signal P03 become H level, and the output of the NAND gate 66b becomes H level. The selection signal P02 becomes L level due to the H level of the NAND gate 66b. As a result, the phase of the internal clock signal ACLK is delayed as shown in FIG. The enable signals EN11, EN02,... Are directly supplied to the delay stages D11, D02,.
[0190]
On the other hand, when the phase needs to be advanced as a result of the phase comparison, the control signals A and B are activated. In response to the control signal B, the nMOS 66d of the control circuit 66 outputting the selection signal P02 is turned on, and the output of the NAND gate 66b is forcibly set to the L level. With this L level, the selection signal P11 becomes H level, and the output of the inverter 66c becomes H level. The enable signal E03 and the selection signal P12 become L level due to the H level of the inverter 66c. As a result, as shown in FIG. 38A, the phase of the internal clock signal BCLK is delayed.
[0191]
Since the control signal AD output from the rough control 118 shown in FIG. 20 can be directly supplied to the shift register 160, the register selection switch 124 (FIG. 26) of the first embodiment is not necessary. Further, since the enable signals EN11, EN02,... Of the shift register 160 can be directly supplied to the delay stages D11, D02,..., The delay stage activation circuit 56 (FIG. 9) is not necessary. .
[0192]
In the first embodiment described above, the example in which the delay stages D01, D11, D02, D12,... Are configured using the CR time constant circuits 48d and 48e as shown in FIG. The present invention is not limited to such an embodiment. Any delay stage may be used as long as it outputs a clock signal having a gentle waveform in order to operate the interpolation circuits 38 and 40 normally. Hereinafter, another configuration example of the delay stage will be shown.
[0193]
The delay stage 162 shown in FIG. 54 includes a differential amplifier circuit that receives input signals IN and / IN and generates output signals OUT and / OUT. The differential amplifier circuit includes a constant current source such as a current mirror circuit and an nMOS, and the enable signal EN is connected to the gate of the nMOS connected to the ground line VSS.
The delay stage 164 shown in FIG. 55 is configured by arranging two CR time constant circuits 164a in series.
[0194]
The delay stage 166 shown in FIG. 56 includes two OR circuits (negative logic AND circuits) 166a composed of CMOS and pMOSs 166b, 166c, nMOSs 166d, 166e connected to a power supply terminal (not shown) of the OR circuit 166a. And constant voltage sources 166f and 166g connected to the gates of the pMOSs 166b and 166c and the gates of the nMOSs 166d and 166e, respectively. Each of the transistors 166b to 166e acts as a resistor, and makes the output waveform of the OR circuit 166a gentle.
[0195]
In the first embodiment described above, as shown in FIG. 10, the interpolation circuit 38 is formed by using clocked inverters having different gate widths, and the phase ABCLK according to the weighting of the counter signals CNT3-CNT0 is generated. An example was given. The present invention is not limited to such an embodiment. Hereinafter, another configuration example of the interpolation circuit will be shown.
The interpolator 168 shown in FIG. 57 is connected in series to the constant current source 168a, four nMOSs 168b, 168c, 168d, 168e having different gate widths for extracting the current supplied from the constant current source 168a, and the source side of each transistor. The four nMOSs 168f are provided with two sets, and further, a differential amplifier 168i including two differential amplifiers 168g and 168h whose outputs are connected to each other is provided. The numbers described in the nMOSs 168b, 168c, 168d, and 168e indicate the ratio of the gate width. Counter signals CNT3-CNT0 are supplied to the gates of the nMOSs 168e, 168d, 168c, 168b, respectively. A constant voltage signal VC is supplied to the gate of the nMOS 168f. The nodes V1 and V2 connected to the constant current source 168a are connected to the gates of the nMOSs connected to the ground line VSS in the differential amplifier circuits 168g and 168h, respectively.
[0196]
The output of the differential amplifying unit 168i is connected to buffers 170a and 170b made of a differential amplifier circuit. Internal clock signals CLKI and / CLKI are output from the outputs of the buffers 170a and 170b.
In the interpolation circuit 168, the voltages at the nodes V1 and V2 change according to the weighting of the counter signals CNT3 to CNT0, and the amplification capabilities of the differential amplifier circuits 168g and 168h change, so that the internal clock signals ACLK and BCLK (or / An internal clock signal CLKI (or / CLKI) having a phase between ACLK and / BCLK) is generated.
[0197]
The interpolator 168 can be used in combination with the delay stage 162 shown in FIG. 54 to stably generate the internal clock signals CLKI and / CLKI having a constant duty ratio.
The interpolation circuit 172 shown in FIG. 58 includes two sets of four CMOS switches 170a, 172b, 172c, and 172d having different gate widths and outputs connected to each other. The numbers described in the CMOS switches 170a, 172b, 172c, and 172d indicate the ratio of the gate width. The CMOS switches 170a, 172b, 172c, and 172d supplied with the internal clock ACLK are controlled by counter signals CNT3-CNT0. The CMOS switches 170a, 172b, 172c, and 172d to which the internal clock BCLK is supplied are controlled by the inversion logic of the counter signals CNT3-CNT0 through the inverter. The internal clock signal ABCLK output from the interpolation circuit 172 is supplied to the buffer 42 (or 44).
[0198]
In the interpolation circuit 172, the CMOS switches 170a, 172b, 172c, and 172d act as variable resistors according to the weighting of the counter signals CNT3-CNT0, so that the internal clock signals ACLK, BCLK (or / ACLK, / BCLK) An internal clock signal ABCLK (or / ABCLK) having a phase at is generated. The internal clock signal ABCLK (or / ABCLK) is supplied to the buffer 42 (or 44) and output as the internal clock signal CLKI (or / CLKI).
[0199]
In the above-described first embodiment, the example in which the binary counter 136 is configured with 4 bits has been described. The present invention is not limited to such an embodiment. For example, the binary counter 136 may be configured with 6 bits or 8 bits in accordance with the phase adjustment accuracy of the interpolation circuits 38 and 40.
In the first embodiment described above, as shown in FIGS. 7 and 8, the first and second switch circuits 58 and 62 are constituted by the CMOS switch 72a, and the clock signal having a gentle waveform generated in the delay stage. An example in which is transmitted to the interpolation circuits 38 and 40 has been described. The present invention is not limited to such an embodiment. For example, as shown in FIG. 59, the switch circuit 174 may be configured by a clocked inverter 174a, and a clock signal having a gentle waveform may be generated by the switch circuit 174. In this case, as shown in FIG. 60, the delay stage 176 can be formed by a simple OR circuit or the like.
[0200]
In the first embodiment described above, the example applied to the DDR-SDRAM to which the complementary clock signals CLK and / CLK are supplied has been described. However, the present invention is not limited to such an embodiment. For example, the present invention may be applied to an SDRAM to which only the clock signal CLK is supplied. 61 and 62 show an SDRAM clock control unit 178 and a delayed clock generation unit 180 to which the present invention is applied.
[0201]
In FIG. 61, only the clock buffer 34a, the interpolation circuit 38, and the buffer 42 relating to the clock signal CLK are formed in the SDRAM. The delay clock generation unit 180 outputs only the internal clock signals ACLK and BCLK.
62, each delay stage D01, D11, D02, D12,... Of the delay circuit 182 outputs only the internal clock signals CLK01, CLK11, CLK02,. The first switch circuit 184 outputs any of the internal clock signals CLK01, CLK02,... As the internal clock signal ACLK. The second switch circuit 186 outputs any of the internal clock signals CLK11, CLK12,... As the internal clock signal BCLK.
[0202]
In the first embodiment described above, the example in which the present invention is applied to the DDR-SDRAM has been described. However, the present invention is not limited to such an embodiment. For example, the present invention may be applied to a semiconductor memory such as DRAM or SRAM. Furthermore, the present invention may be applied to a system LSI incorporating a DRAM memory core.
In the third embodiment described above, the first frequency dividing circuit 156 includes the switches 156a, 156b, and 156c formed by CMOS switches, and the switches 156a, 156b, and 156c are switched by setting the mode register to a predetermined value. An example to do was described. However, the present invention is not limited to such an embodiment. For example, the switch of the first frequency dividing circuit 156 may be composed of a fuse such as polysilicon, and the switch may be switched by blowing the fuse. In this case, the output timing of the reference clock REFCLK can be set in the manufacturing process of the semiconductor integrated circuit. In general, semiconductor integrated circuits are shipped with different product names for each operating frequency. Further, the frequency characteristics of the semiconductor integrated circuit vary to some extent depending on the position of the chip in the wafer and the manufacturing lot. Therefore, in the manufacturing process, the fuse is blown according to the operating frequency of the product, and the output timing of the reference clock REFCLK is set, so that the optimum output timing of the reference clock REFCLK is set according to each semiconductor integrated circuit be able to. As a result, the delay stage activation circuit 56 can be effectively operated to reduce power consumption.
[0203]
Further, an extraction portion such as a pad for controlling the switch may be formed on the chip. In this case, the product can be evaluated by using these pads as test terminals before shipping the product. When the product is shipped, by connecting the pad to the power supply line VDD or the ground line VSS with a bonding wire or the like, it is possible to obtain the same effect as when the switch is configured with a fuse. Further, by connecting the pad and the external terminal when the product is shipped, the output timing of the reference clock REFCLK can be set on the substrate in accordance with the clock frequency of the system in which the semiconductor integrated circuit is mounted.
[0204]
In the above description, as shown in FIG. 12, the dummy output buffer 86 and the dummy input buffer 88 have been used as dummy circuits. However, by using only the dummy input buffer 88, it is possible to match the timing of the clock signal CLK. Alternatively, by using only the dummy input buffer 88 and adding a delay circuit for the latch circuit to the reference clock signal REFCLK, an internal clock signal that is slower by the latch circuit can be generated from the clock signal CLK.
[0205]
In the above-described third embodiment, the example in which the first frequency dividing circuit 156 includes the switches 156a, 156b, and 156c has been described. However, the present invention is not limited to such an embodiment. For example, the second frequency dividing circuit 84 may be provided with a switch.
The invention described in the above embodiments is organized and the following items are disclosed.
[0206]
(1) In the semiconductor integrated circuit according to claim 2, when the phase of the reference clock signal and the internal clock signal is reversed, the control circuit determines that the comparison result is equal to or less than the delay time of the delay stage. A semiconductor integrated circuit.
In this semiconductor integrated circuit, the control circuit determines that the phase difference between the internal clock signal and the reference clock signal is equal to or less than the delay time of the delay stage based on the phase inversion between the internal clock signal and the reference clock signal. To do. Then, fine adjustment by the interpolation circuit is started. The determination of phase inversion can be easily performed with a simple circuit such as a latch, and the circuit scale can be reduced.
[0207]
(2) The semiconductor integrated circuit according to claim 3, wherein the control circuit sets the binary counter to a median value at the start of phase comparison.
In this semiconductor integrated circuit, the control circuit sets the binary counter to the median value at the start of the phase comparison. For this reason, when coarse adjustment of the phase is performed by the switch circuit, the phase of the internal clock signal can be changed uniformly according to the delay time of the delay stage. As a result, the number of phase comparisons can be minimized in the subsequent phase adjustment by the interpolation circuit.
[0208]
(3) In the semiconductor integrated circuit according to (3), the control circuit is configured such that the phase difference between the internal clock signal and the reference clock signal becomes equal to or less than a delay time of the delay stage by the coarse adjustment. A semiconductor integrated circuit, wherein the fine adjustment is performed by incrementing or decrementing a decimal counter by one.
In this semiconductor integrated circuit, after the phase difference between the internal clock signal and the reference clock signal becomes less than or equal to the delay time of the delay stage due to coarse adjustment, the control circuit increases or decreases the binary counter by 1 to increase the internal clock. Fine-tune the signal phase. For this reason, the phase adjustment of the internal clock signal is performed reliably and accurately.
[0209]
(4) In the semiconductor integrated circuit according to (4), the control circuit performs the operation of the binary counter up to the least significant 2 bits, and then increments or decrements the binary counter one by one. A semiconductor integrated circuit characterized by performing adjustment.
In this semiconductor integrated circuit, the control circuit performs the operation of the binary counter up to the least significant 2 bits, and after the phases of the internal clock signal and the reference clock signal substantially coincide, the binary counter is incremented or decremented by one. Finely adjust the phase of the internal clock signal. For this reason, it is possible to reliably and accurately adjust the phase of the internal clock signal with respect to the subsequent voltage fluctuation and temperature fluctuation.
[0210]
(5) In the semiconductor integrated circuit according to claim 3, when the control circuit has the binary counter attains a maximum value by the fine adjustment and further adjusts the phase of the internal clock signal in the same direction, the switch A semiconductor integrated circuit which controls a circuit and outputs the first clock signal from another delay stage adjacent to the delay stage which outputs the second clock signal.
[0211]
In this semiconductor integrated circuit, when the binary counter becomes the maximum value by fine adjustment, and when the phase of the internal clock signal is adjusted in the same direction, the control circuit controls the switch circuit to change the first clock signal to the first clock signal. Output from another delay stage adjacent to the delay stage that outputs the two clock signals. For this reason, when the phase of the first clock signal is ahead of the phase of the second clock signal, the phase of the first clock signal is delayed from the phase of the second clock signal by the switch circuit. When the phase of the first clock signal is delayed from the phase of the second clock signal, the phase of the first clock signal is advanced from the phase of the second clock signal by the switch circuit. The second clock signal does not change. When the binary counter has the maximum value, the phase of the internal clock signal is closest to the second clock signal regardless of the phase relationship between the first clock signal and the second clock signal. For this reason, the phase of the internal clock signal does not change greatly due to switching of the switch circuit. That is, it is possible to prevent jitter from occurring in the internal clock signal at the time of switching between coarse adjustment and fine adjustment.
[0212]
(6) In the semiconductor integrated circuit according to claim 3, when the control circuit sets the counter to the minimum value by the fine adjustment and further adjusts the phase of the internal clock signal in the same direction, A semiconductor integrated circuit that controls and outputs the second clock signal from another delay stage adjacent to the delay stage that outputs the first clock signal.
[0213]
In this semiconductor integrated circuit, when the binary counter is set to the minimum value by fine adjustment and the phase of the internal clock signal is adjusted in the same direction, the control circuit controls the switch circuit to change the second clock signal to the first value. Output from another delay stage adjacent to the delay stage that outputs the clock signal. For this reason, when the phase of the second clock signal is ahead of the phase of the first clock signal, the phase of the second clock signal is delayed from the phase of the first clock signal by the switch circuit. When the phase of the second clock signal is delayed from the phase of the first clock signal, the phase of the second clock signal is advanced from the phase of the first clock signal by the switch circuit. The first clock signal does not change. When the binary counter is at the minimum value, the phase of the internal clock signal is closest to the first clock signal regardless of the phase relationship between the first clock signal and the second clock signal. For this reason, the phase of the internal clock signal does not change due to switching of the switch circuit. That is, it is possible to prevent jitter from occurring in the internal clock signal at the time of switching between coarse adjustment and fine adjustment.
[0214]
(7) The semiconductor integrated circuit according to claim 1, wherein the delay time of each delay stage is the same regardless of the period of the reference clock signal.
In this semiconductor integrated circuit, the delay time of each delay stage is the same regardless of the period of the reference clock signal, so even when the frequency of the reference clock signal supplied to the delay circuit is changed, The delay time is held at a predetermined value. Therefore, the coarse adjustment and fine adjustment units do not vary depending on the frequency of the reference clock signal, and the coarse adjustment and fine adjustment can be reliably performed.
[0215]
(8) The semiconductor integrated circuit according to claim 2, wherein a part of each rising period and a part of each falling period of the first clock signal and the second clock signal supplied to the interpolation circuit are A semiconductor integrated circuit characterized by having an overlap.
In this semiconductor integrated circuit, a part of each rising period and a part of each falling period of the first clock signal and the second clock signal supplied to the interpolation circuit are overlapped with each other, so that the interpolation circuit operates reliably. Can be made.
[0216]
(9) The semiconductor integrated circuit according to claim 1, wherein an independent power supply voltage is supplied to the delay circuit.
In this semiconductor integrated circuit, since an independent power supply voltage is supplied to the delay circuit, it is possible to prevent the delay time of each delay stage of the delay circuit from fluctuating due to the influence of other circuits. . In addition, power consumption can be reduced by supplying a low voltage to the delay circuit.
[0217]
(10) The semiconductor integrated circuit according to claim 1, further comprising a start signal generator that activates a start signal in synchronization with the reference clock signal at the start of the phase comparison.
[0218]
This semiconductor integrated circuit includes a start signal generator that activates a start signal in synchronization with a reference clock signal at the start of phase comparison. For this reason, at the start of the phase comparison, the control circuits can be synchronized with each other, and the phase comparison can always be started from a predetermined state.
(11) The semiconductor integrated circuit according to (10), wherein the start signal generator activates the start signal in synchronization with a fall of the reference clock signal.
[0219]
In this semiconductor integrated circuit, the start signal generator activates the start signal in synchronization with the fall of the reference clock signal. Therefore, it is possible to prevent the H level period of the reference clock signal from being masked by the start signal and causing a hazard, and the delay circuit can be stably operated.
(12) The semiconductor integrated circuit according to claim 1, further comprising a frequency divider that divides the frequencies of the reference clock signal and the internal clock signal, and the phase comparison circuit includes the frequency dividers. A semiconductor integrated circuit, wherein the reference clock signal and the internal clock signal whose frequency are divided are supplied.
[0220]
This semiconductor integrated circuit includes a frequency divider that divides the frequencies of the reference clock signal and the internal clock signal. The phase comparison circuit is supplied with a reference clock signal and an internal clock signal whose frequency is divided through each frequency divider. Therefore, even when a high-frequency reference clock signal is supplied, the phase comparison circuit can be reliably operated. Further, since the frequency of phase comparison is reduced, power consumption can be reduced.
[0221]
(13) The semiconductor integrated circuit according to (12), further including a start signal generator that activates a start signal in synchronization with the reference clock signal at the start of the phase comparison. A semiconductor integrated circuit, which starts operating upon activation of a start signal and starts outputting the divided reference clock signal and internal clock signal after a predetermined number of clocks.
[0222]
This semiconductor integrated circuit includes a start signal generator that activates a start signal in synchronization with a reference clock signal at the start of phase comparison. Each frequency divider starts operation upon activation of the start signal, and starts outputting the divided reference clock signal and internal clock signal after a predetermined number of clocks. Therefore, when the reference clock signal has a specific frequency, the maximum value of the phase shift between the reference clock signal supplied to the phase comparison circuit and the internal clock signal can be reduced. As a result, the number of phase comparisons in coarse adjustment can be reduced. The number of delay stages of the delay circuit can be reduced.
[0223]
(14) The semiconductor integrated circuit according to (13), wherein the predetermined number of clocks can be set according to a frequency of a reference clock signal.
In this semiconductor integrated circuit, by setting the number of clocks from the activation of the start signal to the start of output of the divided reference clock signal and internal clock signal according to the frequency of the reference clock signal, The number of phase comparisons necessary for phase adjustment can be reduced.
[0224]
(15) The semiconductor integrated circuit according to (13), further comprising a mode register for setting the predetermined number of clocks.
This semiconductor integrated circuit includes a mode register for setting the number of wait clocks. For this reason, the number of wait clocks can be easily set according to the frequency of the reference clock signal by changing the mode register at the time of power-on or the like.
[0225]
(16) The semiconductor integrated circuit according to (13), further comprising a fuse for setting the predetermined number of clocks.
This semiconductor integrated circuit includes a fuse for setting a predetermined number of clocks. For this reason, in the manufacturing process, the predetermined number of clocks can be set easily and reliably by blowing the fuse according to the product specification (frequency).
[0226]
(17) The semiconductor integrated circuit according to (13), further comprising a control terminal for setting the predetermined number of clocks.
This semiconductor integrated circuit includes a control terminal for setting a predetermined number of clocks. For this reason, the product can be evaluated using these control terminals as test terminals. By connecting these control terminals to the power supply line VDD or the ground line VSS, a predetermined number of clocks can be set. By using these control terminals as external terminals, a predetermined number of clocks can be set on the substrate in accordance with the clock frequency of the system in which the semiconductor integrated circuit is mounted.
[0227]
【The invention's effect】
In the semiconductor integrated circuit according to the first aspect, the phase comparison between the internal clock signal and the reference clock signal can always be performed correctly, and the phases of both signals can always be matched regardless of the frequency of the reference clock signal.
By fixing the delay time of the delay stage to a predetermined value, unnecessary elements are not required and the layout size can be reduced. As a result, the chip size can be reduced.
[0228]
Since the phase of the internal clock signal is finely adjusted using the interpolation circuit, the minimum unit of fine adjustment can be reduced. That is, phase adjustment can be reliably performed even in a semiconductor integrated circuit to which a high-frequency reference clock signal is supplied.
According to another aspect of the semiconductor integrated circuit of the present invention, the phase of the internal clock signal is divided into coarse adjustment and fine adjustment so that the phases of the internal clock signal and the reference clock signal can be matched quickly with a small number of phase comparisons. Can do.
[0229]
In the semiconductor integrated circuit according to the third aspect, since it is not necessary to reset or set the counter value of the binary counter at the time of phase adjustment, the control of the binary counter can be performed easily and smoothly. As a result, the timing margin for the operation of the control circuit can be increased. As a result, it is possible to prevent jitter from occurring in the internal clock signal.
In the semiconductor integrated circuit of the fourth aspect, the number of phase comparisons in the coarse phase adjustment can be reduced.
In the semiconductor integrated circuit according to the fifth aspect, power consumption can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing the basic principle of the invention according to claims 1 to 5;
FIG. 2 is a block diagram showing a clock control unit in the first embodiment of the semiconductor integrated circuit of the present invention.
FIG. 3 is a block diagram illustrating a delay clock generation unit in FIG. 1;
4 is a circuit diagram showing the delay stage of FIG. 3;
FIG. 5 is a circuit diagram showing a first shift register of FIG. 3;
6 is a circuit diagram showing a second shift register of FIG. 3. FIG.
7 is a circuit diagram showing a first switch circuit of FIG. 3; FIG.
FIG. 8 is a circuit diagram showing a second switch circuit of FIG. 3;
FIG. 9 is a circuit diagram showing the delay stage activation circuit of FIG. 3;
10 is a circuit diagram showing the interpolation circuit and buffer of FIG. 2. FIG.
FIG. 11 is a timing chart showing an input waveform and an output waveform of the interpolation circuit.
12 is a block diagram showing a phase comparison unit in FIG. 2. FIG.
13 is a block diagram showing a first divider circuit and a second divider circuit of FIG.
14 is a circuit diagram showing the frequency divider of FIG.
FIG. 15 is a timing chart showing the basic operation of the frequency divider of FIG. 13;
16 is a timing chart showing the basic operation of the frequency divider of FIG.
17 is a circuit diagram showing the phase comparison circuit of FIG. 10;
FIG. 18 is a circuit diagram showing the rough / fine control unit of FIG. 1;
FIG. 19 is a control state diagram showing the operation of the combinational circuit of FIG. 18;
20 is a block diagram showing the rough control circuit of FIG. 1. FIG.
FIG. 21 is a circuit diagram showing rough control of FIG. 20;
22 is a control state diagram showing an operation of the combinational circuit of FIG. 21. FIG.
FIG. 23 is a timing chart showing an outline of the rough control operation of FIG. 20;
24 is a circuit diagram showing the rough shift latch of FIG. 20. FIG.
25 is a circuit diagram showing the shift direction latch of FIG. 20;
26 is a circuit diagram showing the register selection switch of FIG. 20;
FIG. 27 is a block diagram illustrating a fine control unit in FIG. 1;
28 is a circuit diagram showing the fine control of FIG. 27. FIG.
29 is a control state diagram showing the fine control operation of FIG. 27. FIG.
FIG. 30 is a flowchart showing phase adjustment control in the first embodiment;
FIG. 31 is a flowchart showing initial setting of phase adjustment and control of rough initial adjustment in the first embodiment.
FIG. 32 is a flowchart showing fine initial adjustment control in the first embodiment;
FIG. 33 is a flowchart showing fine initial adjustment control in the first embodiment;
FIG. 34 is a flowchart showing rough / fine adjustment control in the first embodiment;
FIG. 35 is a flowchart showing rough / fine adjustment control in the first embodiment;
FIG. 36 is a timing diagram showing the operation of the start signal generator of FIG. 1;
FIG. 37 is a timing chart showing states of clock signals in the phase comparison unit of FIG.
FIG. 38 is an explanatory diagram illustrating an overview of switching control of internal clock signals ACLK and BCLK during rough initial adjustment according to the first embodiment;
FIG. 39 is an explanatory diagram showing a change in the internal clock signal CLKI according to the initial value of the binary counter at the time of rough initial adjustment according to the first embodiment;
FIG. 40 is an explanatory diagram showing an outline of fine initial adjustment according to the first embodiment;
FIG. 41 is a block diagram showing a clock control unit in the second embodiment of the semiconductor integrated circuit of the present invention;
42 is a block diagram showing a phase comparison unit in FIG. 41. FIG.
43 is a circuit diagram showing the fine phase comparison circuit of FIG. 42. FIG.
44 is a circuit diagram showing the rough phase comparison circuit of FIG. 42. FIG.
FIG. 45 is a timing chart showing the operation of the rough phase comparison circuit in the second embodiment.
46 is a circuit diagram showing the rough / fine control unit of FIG. 41. FIG.
47 is a circuit diagram showing the rough control unit of FIG. 41. FIG.
48 is a circuit diagram showing the rough control of FIG. 47. FIG.
49 is a control state diagram showing the operation of the combinational circuit of FIG. 48. FIG.
FIG. 50 is a flowchart showing control of phase adjustment in the second embodiment.
FIG. 51 is a block diagram showing a first divider circuit in the third embodiment of the semiconductor integrated circuit according to the present invention;
FIG. 52 is a timing chart showing the operation of the first and second frequency dividers at the start of phase adjustment in the third embodiment.
FIG. 53 is a circuit diagram showing an example in which the first and second shift registers are combined into one;
FIG. 54 is a circuit diagram showing another example of a delay stage.
FIG. 55 is a circuit diagram showing another example of a delay stage.
FIG. 56 is a circuit diagram showing another example of a delay stage.
FIG. 57 is a circuit diagram showing another example of an interpolation circuit.
FIG. 58 is a circuit diagram showing another example of an interpolation circuit.
FIG. 59 is a circuit diagram showing another example of the first and second switch circuits.
FIG. 60 is a circuit diagram showing another example of a delay stage.
FIG. 61 is a block diagram showing an example in which the present invention is applied to SDRAM.
62 is a block diagram showing a delay clock generation unit in FIG. 61. FIG.
FIG. 63 is a block diagram showing a conventional semiconductor integrated circuit.
FIG. 64 is a flowchart showing control of phase adjustment of a conventional clock signal.
65 is a timing chart showing main signals at the time of phase adjustment in FIG. 64. FIG.
[Explanation of symbols]
30 Clock controller
32 Start signal generator
34a, 34b clock buffer
36 Delay clock generator
38, 40 Interpolation circuit
42, 44 buffers
46 Phase comparator
48 Rough / Fine Control
50 rough control section
52 Fine control unit
54 Delay circuit
56 Delay Stage Activation Circuit
58 First switch circuit
60 First shift register
62 Second switch circuit
64 Second shift register
82 First frequency divider
84 Second divider circuit
86 Dummy output buffer
88 Dummy input buffer
90 Phase comparison circuit
92 divider
118 rough control
120 rough shift latch
122 Shift direction latch
124 Register selection switch
134 Fine Control
136 Binary counter
138 Maximum and minimum detector
140 Clock controller
141 Phase comparison unit
142 Rough / Fine Control Unit
144 Rough control unit
148 Fine phase comparator
150 Rough Phase Comparison Circuit
152 rough control
156 First frequency divider
156a, 156b, 156c switch
A, B, C, D control signals
A1, B1, C1, D1, A2, B2, C2, D2 control signals
ABCLK, / ABCLK internal clock signal
ACLK, / ACLK, BCLK, / BCLK Internal clock signal
CNT3, CNT2, CNT1, CNT0 counter signal
CLK, / CLK clock signal
CLK-K, / CLK-K internal clock signal
COMP Comparison result signal
D01, D02, D03, D04 Delay stage
D11, D12, D13 Delay stage
DICLK Internal clock signal
FCOMP Fine comparison result signal
FEN Fine enable signal
MAX maximum signal
MIN Minimum signal
RCOMP Rough comparison result signal
REFCLK reference clock signal
REN Rough enable signal
/ RESET Reset signal
RLON Rough lock on signal
RSD Rough shift direction signal
RSO rough shift order signal
STT start signal
TIM timing signal

Claims (5)

A delay circuit having a predetermined delay time cascaded, receiving a reference clock signal and outputting a delayed clock signal from each of the delay stages; and
One of the clock signals output from the odd-numbered delay stages in the delay circuit is selected as the first clock signal, and the even-numbered delay adjacent to the delay stage that outputs the first clock signal A switch circuit that selects one of the clock signals output from the stage as a second clock signal;
An interpolation circuit for generating an internal clock signal having a phase having a transition edge between a transition edge of the first clock signal and a transition edge of the second clock signal according to ratio information;
A phase comparison circuit that compares the phase of the reference clock signal with the phase of the internal clock signal;
Based on the comparison result of the phase comparison circuit, the switching of the delay stage selected by the switch circuit is performed, and the ratio information is given to the interpolation circuit to match the phases of the reference clock and the internal clock signal. A semiconductor integrated circuit comprising a control circuit for performing control. The semiconductor integrated circuit according to claim 1,
The control circuit includes:
At the start of phase comparison, the switch circuit is controlled according to the comparison result of the phase comparison circuit, and the phase of the internal clock signal is roughly adjusted,
After the phase difference between the reference clock and the internal clock signal is equal to or less than the delay time of the delay stage, the ratio information is given to the interpolation circuit according to the comparison result of the phase comparison circuit, and the internal clock signal A semiconductor integrated circuit characterized by finely adjusting a phase. The semiconductor integrated circuit according to claim 2.
The control circuit outputs a count value of a binary counter as the ratio information,
The interpolation circuit changes the phase of the internal clock signal from the first clock signal side to the second clock signal side when the binary counter is increased, and when the binary counter is decreased, A semiconductor integrated circuit, wherein a phase is changed from the second clock signal side to the first clock signal side. The semiconductor integrated circuit according to claim 3.
After the phase difference between the reference clock and the internal clock signal becomes less than or equal to the delay time of the delay stage by the coarse adjustment, the control circuit determines the upper 2 bits of the binary counter according to the comparison result. A semiconductor integrated circuit characterized by sequentially performing an operation of increasing or decreasing the value toward the lower side. The semiconductor integrated circuit according to claim 1,
The semiconductor integrated circuit according to claim 1, wherein the control circuit deactivates at least one of the delay stages on the rear stage side that is not used.

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