JP5034938B2 - Phase comparator and measuring device - Google Patents

Description

  The present invention relates to a phase comparator that compares the phases of two signals and outputs a comparison result, and a measurement apparatus including the phase comparator.

  In a TDC (Time-to-Digital Converter) or DLL (Delay Locked Loop) circuit mounted on a semiconductor integrated circuit, a phase comparator that compares the phases of two signals and outputs a binary result is used. . This phase comparator does not measure the phase difference between the two signals, but determines whether the phase of the other signal (comparison signal) is advanced or delayed with one signal as a reference signal. As a result, for example, if the phase of the comparison signal is advanced compared to the reference signal, “1” is output as the comparison result, and if the phase of the comparison signal is delayed compared to the reference signal, “0” is output as the comparison result. Output.

FIG. 12 shows a configuration example of a conventional phase comparator (see, for example, Patent Document 1).
The comparison signal (for example, the input data signal) CMP is input to the NAND circuit 101 (NAND circuit) 101 and is also input to the NAND circuit 101 after being delayed by the delay circuit A102 and the inverter 103 by the delay time DW1. In addition, a reference signal (for example, a clock signal) REF is input to the NAND circuit 104, and is delayed by the delay time DW1 by the delay circuit A105 and the inverter 106 and input to the NAND circuit 104.

  The output Z1 of the NAND circuit 101 is input to the NAND circuit 107, and the output Z2 of the NAND circuit 104 is input to the NAND circuit 108. The NAND circuit 107 receives the output Q2 of the NAND circuit 108, and the NAND circuit 108 receives the output Q1 of the NAND circuit 107. That is, the NAND circuits 107 and 108 constitute a set / reset flip-flop (SR-FF).

  An output Q1 of the NAND circuit 107 is input to a D flip-flop (D-FF) 109. Further, the reference signal REF is input to the D-FF 109 after being delayed by the delay time DW1 by the delay circuit A105 and the inverter 106 and further delayed by the delay time DW2 by the delay circuit B110. Then, the output of the D-FF 109 is output as the output OUT of the phase comparator.

  In the phase comparator shown in FIG. 12, when the comparison signal CMP changes from the low level (“L”) to the high level (“H”), as shown in FIG. 13, the one-shot that becomes “L” only during the period DW1. A pulse is generated at the output Z1 of the NAND circuit 101 (time T51 to T53). Similarly, when the reference signal REF changes from “L” to “H”, a one-shot pulse that becomes “L” only during the period DW1 is generated at the output Z2 of the NAND circuit 104 (time T52 to T54).

  Since the outputs Z1 and Z2 of the NAND circuits 101 and 104 are both “L”, the outputs Q1 and Q2 of the NAND circuits 107 and 108 are both “H”. When one of the outputs Z1 and Z2 becomes “H”, only one of the outputs Q1 and Q2 becomes “L” (time T53, T54), and then both the outputs Z1 and Z2 become “H”. Thus, the phase comparison result is held. Specifically, when the output Z1 of the NAND circuit 101 first becomes “H”, the output Q1 of the NAND circuit 107 becomes “L”, and the outputs Q1 and Q2 are “L” and “H”, respectively. Stored as a phase comparison result. On the other hand, when the output Z2 of the NAND circuit 104 first becomes “H”, the output Q2 of the NAND circuit 108 becomes “L”, and the output Q1 and Q2 are “H” and “L”, respectively. Held as.

  Thereafter, when the reference signal REF changes from “H” to “L” (time T55), the output R1 changes from “L” to “H” after a delay time DW1 by the delay circuit A105 and the inverter 106 (time T56). ) Further, the delay circuit B110 delays the delay time DW2 and the output R2 changes from “L” to “H” (time T57). When the output R2 changes from “L” to “H”, the D-FF 109 holds the output Q1 of the NAND circuit 107, which is the phase comparison result, and outputs it as an output OUT (time T58).

JP 2003-243981 A

  A phase comparator that compares the phases of two signals and outputs the result as a binary value cannot perform phase comparison when the phase difference between the two signals is narrowed. This is called a dead zone, and a phase comparator usually has a dead zone with a certain width. Of course, the phase comparator has a response time, which accounts for the majority of the TDC timing. In particular, when the phase comparator operates near the dead zone, the response speed decreases. For example, in a phase comparator that compares the phases of positive edges whose signals change from “L” to “H”, the phase comparison result is cleared by a negative edge that changes from “H” to “L” depending on the circuit configuration. Some are.

The TDC is configured by using delay elements having different delay times τ _s and τ _f , and a phase difference between two signals is coded (for example, a thermometer) with a delay difference generated by the delay elements as a time resolution (τ _s −τ _f ). Code). The finer the measurement time resolution, the larger the dead zone of the phase comparator becomes an error factor. In addition, since the response time of the phase comparator is the most critical factor of the TDC timing, the phase comparator determines the upper limit of the speed performance of the TDC. Further, when the phase comparison result of the phase comparator is cleared at the negative edge, the duty ratio of the signal may determine the upper limit of the TDC speed.

  Therefore, in a TDC for measuring the phase difference of a high-frequency signal with high resolution, the phase comparator is required to have a narrow dead zone (high sensitivity), operate at high speed near the dead zone, and not depend on the signal duty ratio. The

  SR-FF and D-FF are phase comparators that compare the phases of two signals and output a binary result. SR-FF has a narrow dead zone (about 1 psec) and high phase comparison sensitivity. However, SR-FF has a drawback that the frequency limit depends on the duty ratio of the signal under measurement because the phase comparison result is cleared by the negative edge. The D-FF is classified into a circuit type constituted by NAND gates and a circuit type constituted by inverters and transfer gates. In the circuit system configured with NAND gates, the frequency limit depends on the duty ratio of the signal under measurement because the SR-FF is used in combination. On the other hand, in the circuit type composed of an inverter and a transfer gate, the negative edge of the signal under measurement does not act, so the frequency limit does not depend on the duty ratio of the signal under measurement but depends on the response speed of the phase comparator. Although it is excellent in terms, the dead zone is wide (about 8 psec).

As shown in FIG. 12, in order to prevent the phase comparison result from being cleared at the negative edge of the signal, there is a method of providing a hold circuit after the phase comparator. However, the one-shot pulse is used to hold the phase comparison result, the SR-FF has a sufficient pulse width that can be responded, and the one-shot pulse based on each signal becomes “L”. The phase comparison result needs to be cleared. Therefore, the delay time DW1 by the delay circuits A102 and 105 shown in FIG. 12 must be made sufficiently long, and the operation speed is lowered.

  Further, in order to output the phase comparison result to the outside or record it in an internal storage circuit such as a RAM, it is necessary to send a signal to the digital circuit. That is, as shown in FIG. 12, the phase comparison result needs to be held in the D-FF 109 or the like and transferred in clock synchronization.

  However, as shown in FIG. 14, when the phase difference (P11) between the comparison signal CMP and the reference signal REF is small and a metastable occurs, it takes time to determine the phase comparison result, and SR-FF The phase determination time due to becomes longer. Therefore, an accurate phase comparison result cannot be held unless the phase comparison result is determined between the negative edge of the reference signal REF (time T61) and the time T63 when the delay times DW1 and DW2 have elapsed. Further, as shown in FIG. 15, even if the delay time DW2 is too long, the phase comparison result is cleared before the time T74 when the delay times DW1 and DW2 have elapsed from the negative edge (time T71) of the reference signal REF. Therefore, an accurate phase comparison result cannot be held. Further, since the phase comparison result is held in the D-FF by the negative edge, the frequency limit capable of phase comparison depends on the duty ratio of the signal.

  It is an object of the present invention to provide a phase comparator that can reliably hold the phase comparison result of two signals and a measurement apparatus using the phase comparator.

  According to an aspect of the present invention, a comparison unit that compares phases of a first input signal and a second input signal and outputs a phase relationship thereof, and a phase comparison result output from the comparison unit as a third input signal A first holding unit that receives and outputs and determines whether or not the phase comparison result is determined based on the output of the comparison unit, and if it is determined that the phase comparison result is determined, the first control signal is A phase comparator is provided that includes a first signal generator for outputting. The first holding unit holds the third input signal while the first control signal is being output.

  Since the first signal generation unit outputs the first control signal and the first holding unit holds the phase comparison result when the phase comparison result in the comparison unit is confirmed, the first input signal and the second input signal It is possible to prevent the state from being held before the phase comparison result is determined, and to reliably hold the phase comparison result.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
A first embodiment of the present invention will be described.
FIG. 1 is a block diagram illustrating a configuration example of a phase comparator according to the first embodiment. The phase comparator according to the first embodiment includes a comparison unit 10, a hold signal generation unit 20, and a first hold circuit 30.

  The comparison unit 10 receives a comparison signal (for example, an input data signal) CMP and a reference signal (for example, a clock signal) REF. The comparison unit 10 compares the phases of the input comparison signal CMP and the reference signal REF, and outputs the phase comparison result as a binary value using the output signal S1.

The hold signal generator 20 receives the output signal S1 of the comparator 10, and generates and outputs a hold signal S3 based on the output signal S1. Specifically, the hold signal generation unit 20 determines whether or not the phase comparison result between the comparison signal CMP and the reference signal REF is determined based on the input signal S1, and determines that the phase comparison result is determined. If so, the hold signal S3 is output (asserted). The hold signal generation unit 20 processes the output signal S1 of the comparison unit 10, that is, the phase comparison result so as to match the first hold circuit 30, and outputs the result as the output signal S2.

  The first hold circuit 30 receives the output signal S <b> 2 and the hold signal S <b> 3 from the hold signal generation unit 20. The first hold circuit 30 holds (holds) the phase comparison result transmitted by the output signal S2 according to the hold signal S3, and outputs it as the output signal OUT. The first hold circuit 30 holds the value during the period in which the hold signal S3 is asserted and the period in which the output signal S2 is a predetermined value and outputs it as the output signal OUT, and the other period (the hold signal S3 is stopped) (Negated) and during the period when the output signal S2 is not a predetermined value), the output signal S2 is captured and output as the output signal OUT.

FIG. 2 is a diagram illustrating a circuit configuration example of the phase comparator illustrated in FIG. 1.
The comparison unit 10 includes two NAND circuits 11 and 12. The NAND circuit 11 receives the comparison signal CMP and the output QN of the NAND circuit 12. The NAND circuit 12 receives the reference signal REF and the output QP of the NAND circuit 11. That is, the NAND circuits 11 and 12 constitute an SR-FF. In this way, by using the SR-FF for the comparison unit 10 that performs the phase comparison between the comparison signal CMP and the reference signal REF, the dead zone of the comparison unit itself can be made very narrow, and a highly sensitive phase comparison is realized. can do. Note that the driving capability of the NAND circuits 11 and 12 may be adjusted in order to improve the phase comparison accuracy.

  The logical expression of the comparison unit 10 is shown below.

  That is, when both the comparison signal CMP and the reference signal REF are “L”, the outputs QP and QN of the comparison unit 10 are both “H”. When the comparison signal CMP and the reference signal REF both change from “L” to “H”, the output QP changes to “L” and the output QN maintains “H”. On the other hand, when the comparison signal CMP and the reference signal REF are both “L” and the reference signal REF changes to “H”, the output QN becomes “L” and the output QP maintains “H”.

  The hold signal generation unit 20 includes two inverters 21 and 22 and a negative OR operation circuit (NOR circuit) 23. The inverter 21 receives the output QP of the NAND circuit 11 in the comparison unit 10, and the inverter 22 receives the output QN of the NAND circuit 12 in the comparison unit 10. The NOR circuit 23 receives the outputs AP and AN of the inverters 21 and 22 and outputs the calculation result as a hold signal C.

  That is, when the comparison signal CMP and the reference signal REF are both “L”, the outputs AP and AN of the inverters 21 and 22 are both “L”, so that the hold signal C that is the output of the NOR circuit 23 is “H”. (Negate). When the comparison signal CMP and the reference signal REF are both in the “L” state, at least one of the comparison signal CMP and the reference signal REF becomes “H” and the phase comparison result in the comparison unit 10 is determined, the outputs AP and AN One becomes “H” and the hold signal C is asserted “L”.

  The first hold circuit 30 receives the input terminals AP and AN to which the outputs AP and AN of the inverters 21 and 22 in the hold signal generation unit 20 are input, respectively, and the output of the NOR circuit 23 (hold signal C). It has an input terminal C. The first hold circuit 30 has output terminals XP and XN, and an output from the output terminal XP is output as an output signal OUT of the phase comparator.

  A logical expression of the hold circuit 30 is shown below.

  That is, when the input to the input terminal C is “L”, the first hold circuit 30 enters the hold state and holds and outputs the previous value. The first hold circuit 30 is also in the hold state when the input to the input terminal C is “H” and the inputs to the input terminals AP and AN are both “L”. Hold and output. In other cases, that is, when the input to the input terminal C is “H” and one of the inputs to the input terminals AP and AN is “H”, the input terminal AP and AN are opened. An input is output from output terminals XP and XN.

FIG. 3 is a diagram illustrating a specific circuit configuration example of the hold circuit 30.
FIG. 3 shows, as an example, a pulsed latch type hold circuit that can write an input value even if the pulse widths of the input AP, AN and hold signal C are narrow.

  In FIG. 3, a hold signal C is supplied to the gates of N-channel transistors 31 and 32, and inputs AP and AN are supplied to the gates of N-channel transistors 33 and 34. The transistor 31 has a source connected to a reference potential (corresponding to “L” level) and a drain connected to the source of the transistor 33. Similarly, the transistor 32 has a source connected to the reference potential and a drain connected to the source of the transistor 34.

  The inverters 35 and 36 constitute a latch. The drain of the transistor 33 is connected to the connection point between the input terminal of the inverter 35 and the output terminal of the inverter 36, and the drain of the transistor 34 is connected to the connection point between the output terminal of the inverter 35 and the input terminal of the inverter 36. . The output of the inverter 35 is output as the output XP, and the output of the inverter 36 is output as the output XN. When the hold circuit 30 shown in FIG. 3 is used, the input AN must be an inversion of the input AP when the input value is captured.

  The input / output of the hold circuit 30 shown in FIG.

  By using the pulsed latch type hold circuit 30 as shown in FIG. 3, the input value can be written even if the pulse width of the input AP, AN or hold signal C is narrow as described above. A stable operation can be realized even with a high-frequency signal in which the pulse width of the hold signal C tends to be narrow. For example, even if the hold signal C having a sufficient pulse width is not output because the response speed of the comparison unit 10 is decreased by operating near the dead zone of the comparison unit 10 and the frequency of the signal to be measured is high, the input AP, AN can be written and held.

FIG. 4 is a diagram illustrating another circuit configuration example of the hold circuit 30.
FIG. 4 shows a general clock synchronous hold circuit using SR-FF as an example.

  In FIG. 4, the NAND circuit 71 receives the hold signal C and the input AP, and the NAND circuit 72 receives the hold signal C and the input AN. The NAND circuit 73 receives the output of the NAND circuit 71 and the output of the NAND circuit 74. Similarly, the NAND circuit 74 receives the output of the NAND circuit 72 and the output of the NAND circuit 73. That is, the NAND circuits 73 and 74 constitute an SR-FF, the output of the NAND circuit 73 is output as the output XP, and the output of the NAND circuit 74 is output as the output XN. When the hold circuit 30 shown in FIG. 4 is used, the input AN must be an inversion of the input AP at the time of holding.

  A logical expression of the hold circuit 30 shown in FIG.

Next, the operation of the phase comparator according to the first embodiment will be described.
FIG. 5 is a timing chart showing an operation example of the phase comparator according to the first embodiment.

  In the phase comparator according to the first embodiment, when the comparison signal CMP and the reference signal REF both change from “L” to “H” at time T11 as shown in FIG. The output QP changes from “H” to “L” by the phase comparison between the comparison signal CMP and the reference signal REF in the unit 10 (time T12).

  As a result, the output AP of the inverter 21 in the hold signal generation unit 20 changes from “L” to “H” at time T13. At this time, since the hold signal C is “H”, the outputs AP and AN of the inverters 21 and 22 are taken into the hold circuit 30. Further, the hold signal generation unit 20 determines that the phase comparison result in the comparison unit 10 is confirmed by the change of the output AP of the inverter 21 from “L” to “H”, and the delay by the NOR circuit 23 from time T13. The hold signal C is asserted to “L” at time T14 when the time has elapsed. As a result, the hold circuit 30 enters a hold state, and holds the input value at time T14, that is, the determined phase comparison result output as a binary value.

  Subsequently, when the comparison signal CMP changes from “H” to “L” at time T15, each signal changes as shown from time T16 to time T20. At this time, the outputs AP and AN of the inverters 21 and 22 also change. However, until the time T20, the hold signal C is maintained at “L”, so that the outputs AP and AN are not taken into the hold circuit 30. That is, in the period P1 from time T14 to time T20, the hold circuit 30 performs the holding operation based on the asserted hold signal C and continues to hold the value.

  Here, when the outputs AP and AN of the inverters 21 and 22 are both “L” at time T19, the hold signal C output from the hold signal generation unit 20 is changed from “L” to “H” at time T20. Change. Therefore, the hold circuit 30 does not perform the holding operation by the hold signal C, but performs the holding operation when the outputs AP and AN of the inverters 21 and 22 are both “L”, and maintains the hold state and holds the value. To do. When the reference signal REF changes from “L” to “H” at time T21, each signal changes as shown from time T21 to time T24, and one of the outputs AP and AN of the inverters 21 and 22 is “H”. Until time T23, the holding operation is performed because both the output AP and AN are “L”. That is, in the period P2 from time T19 to time T23, the hold circuit 30 continues to hold the input value because the inputs to the input terminals AP and AN are both “L”.

  Therefore, in the phase comparator according to the first embodiment, as shown in FIG. 5, the value is held by the hold signal C in the period P1, and the value is held by the function of the hold circuit 30 (hold by predetermined input) in the period P2. Is done. In addition, since the period P1 and the period P2 overlap by the delay time of the NOR circuit 23 in the hold signal generation unit 20, the phase comparison result by the comparison unit 10 can be reliably maintained. Further, as indicated by P3 in FIG. 5, the phase comparison result by the positive edge of the comparison signal CMP and the reference signal REF can be held without being cleared by the negative edge of the comparison signal CMP and the reference signal REF. Therefore, it does not depend on the duty ratio of the signal, the frequency limit capable of phase comparison can be increased, and phase comparison with high speed and high sensitivity can be realized.

According to the first embodiment, the comparison unit 10 performs phase comparison between the comparison signal CMP and the reference signal REF, and the hold signal generation unit 20 determines that the phase comparison result of the comparison unit 10 has been determined. A hold signal C for causing the hold circuit 30 to hold the result is asserted. Accordingly, it is possible to prevent the value from being held as the phase comparison result before the result of the phase comparison of the comparison unit 10 is fixed, and to reliably hold the determined phase comparison result.
Further, since the one-shot pulse as in the phase comparator shown in FIG. 12 is not used, the time restriction is eased and a high-speed and high-sensitivity phase comparison operation can be realized.

(Second Embodiment)
Next, a second embodiment of the present invention will be described.

The phase comparator according to the second embodiment is further provided with one hold circuit in addition to the phase comparator according to the first embodiment to generate a clock synchronization signal based on the hold signal and the clock signal. Hold control of the provided hold circuit is performed. In the second embodiment described below, it is assumed that the reference signal REF is a clock signal.

  FIG. 6 is a block diagram illustrating a configuration example of a phase comparator according to the second embodiment. In FIG. 6, the same components as those shown in FIG. 1 are denoted by the same reference numerals, and redundant description is omitted. The phase comparator according to the second embodiment includes a comparison unit 10, a hold signal generation unit 20, a first hold circuit 30, a clock synchronization signal generation unit 40, and a second hold circuit 50.

  The clock synchronization signal generator 40 receives the hold signal S3 from the reference signal REF and the hold signal generator 20. The clock synchronization signal generator 40 generates and outputs a clock synchronization signal S5 based on the reference signal REF and the hold signal S3. Specifically, the clock synchronization signal generation unit 40 detects that the phase comparison result is confirmed based on the input hold signal S3, detects the positive edge of the reference signal REF, and based on the detection result. Output a clock synchronization signal S5.

  The second hold circuit 50 receives the phase comparison result output from the first hold circuit 30 as the output signal S4 and the clock synchronization signal S5. The second hold circuit 50 takes in and holds the phase comparison result transmitted by the output signal S4 according to the clock synchronization signal S5, and outputs it as the output signal OUT.

  FIG. 7 is a diagram illustrating a circuit configuration example of the phase comparator illustrated in FIG. 6. In FIG. 7, components having the same functions as those shown in FIG. 2 are given the same reference numerals, and redundant descriptions are omitted. In FIG. 7, the hold signal is C1, and outputs from the output terminals XP and XN of the first hold circuit 30 are outputs XP1 and XN1.

  The clock synchronization signal generation unit 40 includes a NAND circuit 41, inverters 42 and 44, a D-FF 43, and a delay circuit 45. The NAND circuit 41 receives the hold signal C1 through the inverter 42 and the output CKP of the D-FF 43. The output of the NAND circuit 41 is output as the clock synchronization signal C2 via the inverter 44.

  The data input terminal of the D-FF 43 is fixed to “H”, and the reference signal REF is supplied to the clock input terminal. When the D-FF 43 detects the positive edge of the reference signal REF, the output CKP is fixed to “H”. The D-FF 43 is reset according to the clock synchronization signal C2 supplied via the delay circuit 45. The delay circuit 45 delays the clock synchronization signal C2 by a predetermined time and inverts and outputs it. The delay circuit 45 is configured by connecting, for example, an odd number of inverters in cascade.

  The second hold circuit 50 is configured in the same manner as the first hold circuit 30. The second hold circuit 50 has input terminals AP and AN to which the outputs XP1 and XN1 of the first hold circuit 30 are input, respectively, and an input to which the clock synchronization signal C2 output from the clock synchronization signal generation unit 40 is input. It has a terminal C. The second hold circuit 50 has output terminals XP and XN, and the output XP2 from the output terminal XP is output as the output signal OUT of the phase comparator.

  The second hold circuit 50 enters the hold state when the input to the input terminal C is “L”, holds and outputs the previous value, and when the input to the input terminal C is “H”. Then, an open state is entered, and inputs to the input terminals AP and AN are output from the output terminals XP and XN.

Next, the operation of the phase comparator according to the second embodiment will be described.
FIG. 8 is a timing chart showing an operation example of the phase comparator according to the second embodiment.

  In the phase comparator according to the second embodiment, when at least one of the comparison signal CMP and the reference signal REF changes to “H” from the state where both the comparison signal CMP and the reference signal REF are “L”, the first implementation The phase comparison result in the comparison unit 10 is held in the first hold circuit 30 in the same manner as in the embodiment.

  Here, as shown in FIG. 8, it is assumed that the reference signal REF changes to “H” at time T31 from the state where both the comparison signal CMP and the reference signal REF are “L”. As a result, the D-FF 43 in the clock synchronization signal generation unit 40 detects the positive edge of the reference signal REF, and its output CKP becomes “H” (time T32).

  Before the phase comparison result in the comparison unit 10 is confirmed, the output signal CLP of the inverter 42 is “L” because the hold signal C1 is “H”. Therefore, the clock synchronization signal C2 is “L”, and the second hold circuit 50 enters the hold state and holds the value.

  After that, when the phase comparison result in the comparison unit 10 is confirmed and the hold signal C1 becomes “L”, the phase comparison result is held in the first hold circuit 30 (time T33).

  Further, when the output CKP of the D-FF 43 is “H” and the hold signal C1 becomes “L” and the output CLP of the inverter 42 becomes “H”, the clock synchronization signal C2 becomes “H” (time) 34). As a result, the second hold circuit 50 is in an open state and takes in the outputs XP1 and XN1 of the first hold circuit 30 (that is, the phase comparison result determined in the holding comparison unit 10). Output as outputs XP2 and XN2. As shown at time T35, even when the reference signal REF changes to “L”, the output of the D-FF 43 is not changed at the negative edge of the reference signal REF, so that the output CKP maintains “H” and the clock synchronization signal C2 is maintained at “H”.

  The D-FF 43 is reset and the output CKP becomes “L” at time T36 when the delay time by the delay circuit 45 has elapsed since the clock synchronization signal C2 became “H”. As a result, at time T37, the clock synchronization signal C2 becomes “L”, and the second hold circuit 50 enters the hold state and holds the value.

  According to the second embodiment, the same effect as the phase comparator according to the first embodiment can be obtained, and the phase comparison result can be output to the outside or recorded in the internal storage circuit in synchronization with the reference signal REF. Can be.

Hereinafter, a measurement apparatus to which the phase comparator according to each embodiment described above is applied will be described. By using the phase comparator according to each of the above-described embodiments in a measuring apparatus, it is possible to realize a high-speed and high-sensitivity phase comparison operation and a stable operation even with a high-frequency signal.
FIG. 9 is a diagram illustrating a configuration example of a measurement apparatus configured using the phase comparator according to each of the above-described embodiments, and FIG. 9 illustrates a TDC as an example.

In FIG. 9, FC0 to FC7, FR0 to FR7, SC1 to SC7, SR1 to SR7 are variable delay elements. The delay times of the variable delay elements FC0 to FC7 and FR0 to FR7 are τ _f , and the delay times of the variable delay elements SC1 to FC7 and SR1 to FR7 are τ _s . here,
Delay time τ _f <delay time τ _s .

The variable delay elements FC0 to FC7 are cascaded to delay the comparison signal CMP. The output of the variable delay element FC0 is PD0. C and the output of the variable delay element FCi (i = 1 to 7) is PDi
+. C. The variable delay elements FR0 to FR7 are cascaded to delay the reference signal REF. The output of the variable delay element FR0 is PD0. R, and the output of the variable delay element FRi (i = 1 to 7) is PDi +. Let R be.

  Similarly, the variable delay elements SC1 to SC7 are cascaded to delay the comparison signal CMP. The output of the variable delay element SCi (i = 1 to 7) is connected to PDi−. C. The variable delay elements SR1 to SR7 are cascaded to delay the reference signal REF. The output of the variable delay element SRi (i = 1 to 7) is set to PDi−. Let R be.

  Reference numerals 90, 91A, 91B, ..., 97A, 97B denote phase comparators according to the above-described embodiments. The phase comparator 90 has PD0. C and PD0. R is input and the phase comparison result is output as Qf0. The phase comparator 91A includes PD1 +. C and PD1 +. R is input, the phase comparison result is output as Qf1 +, and the phase comparator 91B outputs PD1-. C and PD1-. R is input and the phase comparison result is output as Qf1-. Similarly, the phase comparator 97A includes PD7 +. C and PD7 +. R is input, and the phase comparison result is output as Qf7 +, and the phase comparator 97B outputs PD7−. C and PD7-. R is input, and the phase comparison result is output as Qf7−.

The TDC shown in FIG. 9 has a comparison signal CMP and a reference signal REF generated by outputs Qf0, Qf1 +, Qf1-,..., Qf7 +, Qf7− of the phase comparators 90, 91A, 91B,. Output phase difference with thermometer code.
10 and 11 show an output example of the TDC shown in FIG. When the thermometer code as shown in FIG. 10 is output, the comparison signal CMP is delayed by a time of 4 (τ _s −τ _f ) with respect to the reference signal REF. On the other hand, when the thermometer code as shown in FIG. 11 is output, the comparison signal CMP is advanced by 4 (τ _s −τ _f ) with respect to the reference signal REF.

The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.
Various aspects of the present invention will be described below as supplementary notes.

(Additional remark 1) The comparison part which compares the phase of the 1st input signal and the 2nd input signal, and outputs the phase relation of the 1st input signal and the 2nd input signal,
A first holding unit that receives and outputs a phase comparison result output from the comparison unit as a third input signal;
A first signal generation unit that determines whether or not a phase comparison result by the comparison unit is fixed based on an output of the comparison unit, and outputs a first control signal when it is determined that the phase comparison result is fixed And
The phase comparator according to claim 1, wherein the first holding unit holds the third input signal during a period in which the first control signal is output.
(Supplementary Note 2) When a phase comparison result between the first input signal and the second input signal is not fixed and a predetermined output is output from the comparison unit, the first holding unit is the third The phase comparator according to appendix 1, which holds an input signal.
(Supplementary note 3) The phase comparison according to supplementary note 2, wherein the first signal generation unit detects that the predetermined output is output from the comparison unit and stops the first control signal. vessel.
(Supplementary Note 4) The first signal generation unit detects that the phase comparison result has been determined by changing the output of the comparison unit from the predetermined output, and detects the first control signal after a predetermined time from the detection. The phase comparator according to appendix 2, wherein:
(Additional remark 5) The 2nd holding | maintenance part which receives and outputs the output of the said 1st holding | maintenance part as a 4th input signal,
A second signal generation unit that detects that the phase comparison result by the comparison unit is confirmed and stops the second control signal based on a reference clock;
5. The phase comparator according to claim 1, wherein the second holding unit holds the fourth input signal during a period in which the second control signal is output.
(Supplementary note 6) The phase comparator according to supplementary note 5, wherein the second signal generation unit outputs the second control signal after a predetermined time from stopping the second control signal.
(Supplementary note 7) The supplementary note 5 is characterized in that the second signal generation unit performs a logical operation on the first control signal and an edge detection signal of the reference clock, and outputs a calculation result as the second control signal. The phase comparator described.
(Appendix 8) The phase comparator according to any one of appendices 1 to 7,
A plurality of delay elements for delaying the comparison signal;
A plurality of delay elements for delaying the reference signal;
A set of the comparison signal and the reference signal, each having a different delay amount for each set, is input to each phase comparator, and the phase difference between the comparison signal and the reference signal is measured based on the output of the phase comparator. A measuring apparatus characterized by:

It is a figure which shows the structural example of the phase comparator which concerns on 1st Embodiment. It is a figure which shows the circuit structural example of the phase comparator which concerns on 1st Embodiment. It is a figure which shows the circuit structural example of a hold circuit. It is a figure which shows the other circuit structural example of a hold circuit. 6 is a timing chart illustrating an operation example of the phase comparator according to the first embodiment. It is a figure which shows the structural example of the phase comparator which concerns on 2nd Embodiment. It is a figure which shows the circuit structural example of the phase comparator which concerns on 2nd Embodiment. 10 is a timing chart illustrating an operation example of the phase comparator according to the second embodiment. It is a figure which shows the structural example of the measuring apparatus to which the phase comparator in this embodiment is applied. It is a figure which shows the example of an output by the measuring apparatus shown in FIG. It is a figure which shows the example of an output by the measuring apparatus shown in FIG. It is a figure which shows the structural example of the conventional phase comparator. 13 is a timing chart illustrating an operation example of the phase comparator illustrated in FIG. 12. 13 is a timing chart showing another operation example of the phase comparator shown in FIG. 12. 13 is a timing chart showing another operation example of the phase comparator shown in FIG. 12.

Explanation of symbols

10 Comparison Unit 20 Hold Signal Generation Unit 30, 50 Hold Circuit 40 Clock Synchronization Signal Generation Unit CMP Comparison Signal REF Reference Signal

Claims (5)

A comparator that compares phases of the first input signal and the second input signal and outputs a phase relationship between the first input signal and the second input signal;
A first holding unit that receives and outputs a phase comparison result output from the comparison unit as a third input signal;
A first signal generation unit that determines whether or not a phase comparison result by the comparison unit is fixed based on an output of the comparison unit, and outputs a first control signal when it is determined that the phase comparison result is fixed And
The phase comparator according to claim 1, wherein the first holding unit holds the third input signal during a period in which the first control signal is output. The first holding part is
When the first control signal is not output and the output of the comparison unit is a predetermined output, the third input signal is held,
When the first control signal is not output and the output of the comparison unit is not the predetermined output, the phase comparison result output from the comparison unit is captured as the third input signal. The phase comparator according to claim 1.   The phase comparator according to claim 2, wherein the first signal generator detects that the predetermined output is output from the comparator and stops the first control signal. A second holding unit that receives and outputs the output of the first holding unit as a fourth input signal;
A second signal generation unit that detects that the phase comparison result by the comparison unit is fixed and stops the second control signal based on the second input signal ;
The phase comparator according to claim 1, wherein the second holding unit holds the fourth input signal during a period in which the second control signal is output. The phase comparator according to any one of claims 1 to 4,
A plurality of delay elements for delaying the comparison signal;
A plurality of delay elements for delaying the reference signal;
A set of the comparison signal and the reference signal having different delay amounts for each set is input to each phase comparator with the comparison signal as the first input signal and the reference signal as the second input signal. And measuring the phase difference between the comparison signal and the reference signal based on the output of the phase comparator.

Images