JP3806476B2 - Receiver circuit for digital broadcasting - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a receiving circuit that receives a digital broadcast signal from a satellite, and more particularly to detection of electric field strength of a received signal.
[0002]
[Prior art]
In a receiver that receives a digital broadcast using a broadcast satellite or a new communication satellite, generally, the electric field strength of a received signal is detected in order to check whether the antenna is correctly oriented in the direction of the satellite. In the future, it is expected that there will be more opportunities to receive signals from multiple satellites with one antenna.In this case, in order to monitor whether the antenna is pointing in the correct direction by automatically selecting an arbitrary satellite, Intensity detection becomes essential.
[0003]
Further, when a satellite broadcast receiver is mounted on a mobile body, it is necessary to automatically track with an antenna, and in this case also, detection of electric field strength is indispensable.
Such detection of the electric field strength has been conventionally realized with a configuration as shown in FIG. That is, the noise level in the no-signal band of the IF signal is extracted by the band pass filter 1 and converted to a DC level by the level detection circuit 2. Further, the DC signal is equivalently output with a C / N ratio characteristic using the log amplifier 3 to detect the electric field strength.
[0004]
[Problems to be solved by the invention]
Since conventional electric field strength detection has been realized using an analog circuit, the C / N ratio detection characteristics may be shifted due to variations in elements, or the characteristics of the log amp itself may not match the original C / N ratio characteristics. Therefore, there was a problem in detection accuracy. For this reason, finally, correction had to be performed by a microcomputer or the like.
[0005]
[Means for Solving the Problems]
The present invention relates to a digital broadcast receiving circuit comprising a digital demodulator that demodulates a digital modulation signal and an error detection and correction unit that performs error detection and error correction on the demodulated data from the demodulator. An electric field strength detection circuit comprising: an error rate calculator that calculates a bit error rate based on an error detection signal from; and an error rate / C / N ratio converter that converts the calculated bit error rate into a C / N ratio. It is characterized by having.
[0006]
The present invention further includes a detection sensitivity controller for detecting that the calculated bit error rate is lower than a predetermined value and outputting a switching signal, and the digital demodulator is responsive to the switching signal. An AD converter having a reduced resolution is provided.
In the present invention, the error rate / C / N ratio converter includes a first conversion table indicating a correspondence between an error rate and a C / N ratio at a normal resolution of the AD converter, and the AD converter. A second conversion table showing correspondence between an error rate at the time of resolution reduction and a C / N ratio, and the first and second conversion tables are switched according to the switching signal.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram showing an embodiment of the present invention, and shows a receiving circuit for digital broadcasting using a satellite. In such digital broadcasting, digital data is normally modulated and transmitted by a method such as QPSK or QAM, and the receiving circuit first digitally demodulates the digital modulation signal input by the digital demodulator 4. The demodulated data is input to the error detector / corrector 5, where an error generated in the transmission process or the like is detected, and the error is corrected and sent to a subsequent circuit.
[0008]
The above configuration is a basic configuration of the receiving circuit, and further includes the following configuration for detecting the electric field strength.
That is, an error counter 6 that counts error detection signals from the error detection corrector 5 to calculate a bit error rate, and an error rate / C / N ratio converter 7 that converts the calculated bit error rate into a C / N ratio. The field strength detection circuit 8 is configured by these. The error rate / C / N ratio converter 7 is composed of a ROM in which the C / N ratio with respect to the bit error rate is stored in advance, and specifically stores discrete data having characteristics shown by a solid line in FIG. . Then, by inputting the bit error rate as the ROM address, the corresponding C / N ratio is output as data.
[0009]
Thus, with the above configuration, a C / N ratio corresponding to the bit error rate of the received digital modulation signal is obtained, and detection of the electric field strength of the received signal is realized.
By the way, referring to the characteristics of the solid line in FIG. 5, when the calculated bit error rate is lowered to about 10 −8, the change in the C / N ratio becomes minute, which becomes the detection limit. However, in order to confirm whether the antenna is pointing in the direction of the satellite accurately, it is necessary to detect even a lower bit error rate. In addition, when the bit error rate is lowered in this way, the bit error rate calculation time itself becomes a problem. For example, assuming a digital data receiver with a transmission rate of 50 Mbps, a bit error rate calculation time of about 2 seconds is required when the bit error rate is about 10 −8. If the calculation time of the bit error rate becomes too long, the electric field strength detection response falls and the antenna direction control cannot be performed well.
[0010]
Therefore, in the present embodiment, when the calculated bit error rate is lower than a predetermined value, the apparent error rate is reduced so that a high C / N ratio can be detected.
That is, as shown in FIG. 1, first, a detection sensitivity controller 9 is provided for outputting a switching signal when the bit error rate calculated by the error counter 6 is lower than a predetermined value. Since the input signal is an analog signal, the digital demodulator 4 includes an AD converter 40 for AD conversion. Therefore, the apparent bit error rate is lowered by lowering the resolution of the AD converter 40 by the switching signal from the detection sensitivity controller 9. In this way, even if the actual bit error rate is so low that it cannot be measured, the resolution of the AD converter 40 is reduced, so that errors increase and the apparent bit error rate increases.
[0011]
The relationship between the apparent bit error rate when the resolution of the AD converter 40 is reduced and the actual C / N ratio is the characteristic indicated by the broken line in FIG. 5, and the C / N ratio with respect to the bit error rate in this characteristic. Are stored in the second ROM table 71. Further, the first ROM table 70 similarly stores discrete data of the C / N ratio with respect to the bit error rate for the characteristics indicated by the solid line in FIG. The error rate / C / N ratio converter 7 switches from the first ROM table 70 to the second ROM table 71 when a switching signal is input.
[0012]
Therefore, when the bit error rate calculated by the error counter 6 is higher than a predetermined value, no switching signal is generated from the detection sensitivity controller 9, and therefore the resolution of the AD converter in the digital demodulator 4 is normal. The full counter state is entered, and the actual bit error rate itself is input from the error counter 6 to the error rate / C / N ratio converter 7. When the switching signal is not generated, the first ROM table 70 is selected, so that the error rate / C / N ratio converter 7 actually corresponds to the actual bit error rate according to the characteristic shown by the solid line in FIG. The C / N ratio is output.
[0013]
On the other hand, when the bit error rate calculated by the error counter 6 is lower than a predetermined value, a switching signal is generated from the detection sensitivity controller 9, and the resolution of the AD converter in the digital demodulator 4 is lowered by this signal. In this state, an apparent bit error rate higher than the actual bit error rate is output from the error counter 6, and this is input to the error rate / C / N ratio converter 7. When the switching signal is generated, switching from the first ROM table 70 to the second ROM table is performed, so that the error rate / C / N ratio converter 7 uses the apparent bit according to the characteristics shown by the broken line in FIG. The actual C / N ratio corresponding to the error rate is output. In this case, the calculation time of the bit error rate is the same as that when the first ROM table 70 is used, and the detection response does not deteriorate.
[0014]
As described above, a wide range of C / N ratios can be detected.
Here, a specific configuration of the digital demodulation circuit will be described with reference to FIGS. FIG. 3 shows a QPSK demodulation circuit which is currently mainstream in satellite broadcasting, and includes an AD converter 10 that AD converts an analog QPSK modulation signal, and multipliers 110 and 111, and outputs the AD converter 10 by quadrature detection. The quadrature detector 11 and the low-pass filters 12 and 13 connected to the multipliers 110 and 111, respectively. The resolution of the AD converter 10 changes according to the switching signal from the detection sensitivity controller 9. The demodulator shown in FIG. 4 first performs quadrature detection on the analog QPSK modulation signal by the quadrature detector 14 and then outputs the outputs of the multipliers 140 and 141 in the quadrature detector 14 by AD converters 15 and 16 respectively. These two AD converters 15 and 16 are configured such that the resolution changes in accordance with the switching signal from the detection sensitivity controller 9.
[0015]
Next, a configuration for changing the resolution in the AD converter 10 is shown in FIG. A similar configuration may be used for the AD converters 15 and 16.
Here, multiplexers 101 and 102 for selecting either the lower bits or the fixed value “0” are provided for the lower two bits of the output of the AD conversion unit 100, and the switching signal from the detection sensitivity controller 9 is provided. When no switching occurs, the lower bit is passed as it is, and when the switching signal is generated, the fixed value “0” is passed. In other words, when the switching signal is generated, the resolution of the AD converter 10 is lowered by fixing the lower bits of the AD converter 100 to “0”, thereby increasing the apparent error rate. Therefore, it is possible to detect the C / N ratio over a wide range as described above.
[0016]
【The invention's effect】
According to the present invention, since the detection of the electric field strength is realized using a digital circuit, it is not affected at all by the variation of the element as in the prior art, and the electric field strength can be surely matched with the original C / N characteristics. Detection is possible, and correction processing by the microcomputer is not necessary. In addition, the electric field strength detection circuit can be on-chip in the digital demodulator and the baseband signal processing IC. Furthermore, it is possible to detect the C / N ratio over a wide range without deteriorating the electric field strength detection response.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.
FIG. 2 is a block diagram showing a specific configuration of an AD converter in the embodiment.
FIG. 3 is a block diagram showing a specific configuration of a digital demodulator in the embodiment.
FIG. 4 is a block diagram showing another specific configuration of the digital demodulator in the embodiment.
FIG. 5 is a characteristic diagram showing a relationship between a bit error rate and a C / N ratio in the embodiment.
FIG. 6 is a block diagram showing a configuration of a conventional electric field strength detection circuit.
[Explanation of symbols]
4 Digital Demodulator 5 Error Detection Corrector 6 Error Counter 7 Error Rate / C / N Ratio Converter 8 Electric Field Strength Detection Circuit 9 Detection Sensitivity Controller 10, 15, 16 AD Converter 100 AD Converter 101, 102 Multiplexer

Claims (4)

In a digital broadcast receiving circuit comprising a digital demodulator having a function for AD-converting a digital modulation signal , and an error detection and correction unit that performs error detection and error correction on demodulated data from the demodulator,
Field strength detection with an error rate calculator for calculating a bit error rate based on the error detection signal from said error detecting and correcting unit, the error rate · C / N ratio converter for converting the bit error rate in the C / N ratio Circuit,
A detection sensitivity controller that detects that the bit error rate is lower than a predetermined value and outputs a switching signal , and
The digital demodulator has a digital broadcast receiving circuit in which the resolution of the AD conversion function is lowered according to the switching signal. The error rate / C / N ratio converter stores in advance the correspondence between the bit error rate and the C / N ratio, inputs the bit error rate as an address, and outputs the corresponding C / N ratio as data digital broadcast receiving circuit according to claim 1, further comprising a. The error rate / C / N ratio converter includes a first conversion table indicating a correspondence between an error rate at the normal resolution of the AD converter and a C / N ratio, and an error rate at the time of the resolution reduction of the AD converter. and a second conversion table indicating the correspondence between C / N ratio, characterized in that said switching the first and second conversion table in accordance with the switching signal according to claim 1 digital broadcast receiving circuit according . 2. The digital broadcast receiving circuit according to claim 1 , wherein said AD converter has fixing means for fixing a lower bit of output data to a predetermined value in accordance with said switching signal in order to reduce resolution.

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