JP3804336B2 - Pulse width control circuit and electric / optical conversion circuit having pulse width control function - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a pulse width control circuit and an electric / optical conversion circuit, and in particular, a small and low-cost pulse width control circuit that outputs a signal with a constant duty ratio even when an input signal with a varying duty ratio is received, and the above-mentioned The present invention relates to an electrical / optical conversion circuit to which a pulse width control technique is applied.
[0002]
In the signal transmission apparatus, the logic level “1” and the logic level “0” are alternately repeated (that is, the code rate of the logic level “1” and the logic level “0”) in order to be able to stably identify the logic level. In this case, the design is performed on the assumption that the duration of the logical level “1” is equal to the duration of the logical level “0”, that is, the duty ratio is 50%.
[0003]
Even if the rate of the logic level “1” code (referred to as a normal mark) and the logic level “0” code (referred to as a normal space) deviate from 50%, within a predetermined time In the case of a code that maintains a mark rate of 50%, the duration of one mark and the duration of one space are required to be the same as when the mark and space are alternately repeated.
[0004]
However, since the rise time and the fall time of the pulse signal are usually not zero, and the rise time and the fall time are usually not equal, the duty ratio is changed due to the fluctuation of the threshold value of the identification circuit used in the signal transmission device. May fluctuate.
[0005]
Once the duty ratio fluctuates, the signal is transmitted while the fluctuation is preserved. As a result, in the subsequent signal transmission apparatus, the identification timing margin decreases, the identification error of the logic level of the signal increases, and the signal transmission quality decreases.
[0006]
Moreover, when a signal with a duty ratio fluctuating as described above is input to the electrical / optical conversion circuit, the duty ratio also remains fluctuating in the optical signal, and at the same time, automatic power control (Automatic Power Control: The amplitude of the light pulse varies.
[0007]
Accordingly, it is strongly desired to realize a pulse width control circuit that outputs a signal with a constant duty ratio even when an input signal with a varying duty ratio is received, and an electric / optical conversion circuit to which the pulse width control technique is applied.
[0008]
[Prior art]
FIG. 14 shows an example of a conventional pulse width adjustment circuit.
[0009]
In FIG. 14, 50 is a buffer amplifier, 51 is an integration circuit, and 52 is an artificial adjustment circuit for the pulse width.
[0010]
The integrating circuit 51 includes a resistor 51-1 and a capacitor 51-2. The pulse width adjusting circuit 52 includes a DC blocking capacitor 52-1, a resistor 52-2, a variable resistor 52-3, and an inverter 52-4. Composed.
[0011]
In the configuration of FIG. 14, the pulse width is artificially adjusted as follows.
[0012]
That is, the input signal is supplied to the integration circuit 51 via the buffer amplifier 50, and converted from a pulse waveform to an exponential function charge / discharge waveform.
[0013]
The output of the integrating circuit 51 is supplied to the pulse width adjusting circuit 52. First, the DC component is cut off by the DC blocking capacitor 52-1, and then the component consisting of the resistor 52-2 and the variable resistor 52-3. The DC component is again superimposed by the pressure circuit.
[0014]
The output of the voltage dividing circuit is applied to the inverter 52-4. The inverter 52-4 has a specific threshold value for discriminating between the logic level “1” and the logic level “0”.
[0015]
On the other hand, the level of the waveform input to the inverter 52-4 can be artificially adjusted by the voltage dividing circuit.
[0016]
Therefore, the pulse width at the output terminal of the inverter 52-4 can be artificially adjusted to a predetermined value based on the relationship between the DC level superimposed by the voltage dividing circuit and the threshold value of the inverter 52-4.
[0017]
FIG. 15 shows an example of a conventional electric / optical conversion circuit.
[0018]
In FIG. 15, 50 is a buffer amplifier, 51 is an integration circuit, and 52 is an artificial adjustment circuit for the pulse width. The integrating circuit 51 includes a resistor 51-1 and a capacitor 51-2, and the artificial adjustment circuit 52 for the pulse width includes a DC blocking capacitor 52-1, a resistor 52-2, a variable resistor 52-3, an inverter. 52-4. The above-described components constitute the conventional pulse width adjustment circuit shown in FIG.
[0019]
Further, 53 is a laser diode drive circuit (indicated as an LD drive circuit in the figure), 54 is a laser diode, 55 is a photo diode that electrically converts back light of the laser diode again, and 56 is the laser diode. A resistor 57 for converting the current output from the photodiode 55 into a voltage is an automatic optical power control circuit (also abbreviated as an APC circuit in many cases).
[0020]
The output of the pulse width adjusting circuit in FIG. 15, that is, the output of the inverter 52-4 is supplied to the laser diode driving circuit 53, and the laser diode 54 is driven to convert the electrical signal into an optical signal.
[0021]
A part of the output light of the laser diode 54, which is usually called back light, is supplied to the photo diode 55 and converted again into electrical power, and is converted into voltage by the resistor 56.
[0022]
The voltage-converted signal by the resistor 56 is guided to the automatic optical power control circuit 57, and after a mean value detection or peak detection, a difference voltage from the reference voltage is generated, and the laser diode drive is generated by the voltage. The bias current of the circuit 53 is controlled to keep the optical output power of the laser diode 54 constant.
[0023]
[Problems to be solved by the invention]
In the conventional pulse width adjustment circuit shown in FIG. 14, the level of the waveform input to the inverter 52-4 is artificially adjusted by the variable resistor 52-3 to obtain a threshold value unique to the inverter 52-4. The pulse width is artificially adjusted. In other words, the variable resistor is an essential component in the configuration of FIG.
[0024]
However, since the shape of the variable resistor is large and the variable mechanism is not compatible with an integrated circuit, the shape of the field width artificial adjustment circuit in FIG. 14 is large. Further, since the above-described artificial adjustment work is necessary, the pulse width adjustment circuit of FIG. 14 increases the man-hours for adjustment and increases the price of the pulse width adjustment circuit.
[0025]
Similarly, in the electrical / optical conversion circuit of FIG. 15, the circuit shape increases and the price increases.
[0026]
In view of such problems, the present invention is a small and low-cost pulse width control circuit that outputs a signal with a constant duty ratio even when an input signal with a varying duty ratio is received, and an electric / An object is to provide an optical conversion circuit.
[0027]
[Means for Solving the Problems]
The basic configuration of the pulse width control circuit according to the present invention is that the input signal is passed through a low-pass filter to convert the pulse waveform into a waveform whose level gradually increases / decreases, and the waveform whose level gradually increases / decreases is CMOS non-inverter. (Complementary Metal-Oxide Semiconductor Non-Invertor), the output of the CMOS non-inverter is supplied to an automatic level control circuit, and the voltage obtained by detecting the average value of the output of the automatic level control circuit is supplied to the non-inverting compression amplifier. The non-inverting compression amplifier is supplied to the inverting input terminal of the non-inverting compression amplifier with a voltage half the output of the non-inverting compression amplifier as a reference voltage, and the output of the non-decision compression amplifier is supplied to the power source of the CMOS non-inverter. It is the structure supplied as a voltage.
[0028]
According to the basic configuration of the pulse width control circuit of the present invention, when the duty ratio of the input signal varies, the fluctuation of the pulse width of the input signal is suppressed by the following operation.
[0029]
Here, description will be made assuming that the pulse width of the input signal is increased. When the pulse field of the input signal increases, the power supply voltage of the CMOS non-inverter is the voltage before the pulse width fluctuates at this moment, and the threshold value is also the threshold value before the pulse width fluctuates.・ The output pulse width of the inverter is expanded.
[0030]
Accordingly, the output pulse width of the automatic level control circuit is widened, and the output of the average value detection circuit is also increased.
[0031]
Since the output of the average value detection circuit is supplied to the non-inverting input terminal of the non-inverting compression amplifier, the output voltage of the non-inverting compression amplifier also increases.
[0032]
Since the output voltage of the non-inverting compression amplifier is supplied to the CMOS non-inverter as a power supply voltage, the discrimination threshold of the CMOS non-inverter is also increased, and the output pulse width of the CMOS non-inverter is narrowed.
[0033]
Accordingly, the output pulse width of the automatic level control circuit is also narrowed. By the way, since the output of the CMOS non-inverter is controlled to have a constant amplitude by the automatic level control circuit, the output obtained by detecting the average value of the output of the automatic level control circuit is lowered.
[0034]
Accordingly, the output voltage of the non-inverting compression amplifier is lowered, the discrimination threshold value of the CMOS non-inverter is also lowered, and control is performed so that the width of the output pulse of the CMOS non-inverter is widened.
[0035]
Further, since ½ of the output voltage of the non-inverting compression amplifier is supplied as a reference voltage to the inverting input terminal of the non-inverting compression amplifier, the output of the average value detection circuit and the output voltage of the non-inverting compression amplifier are fed by the feedback. Control is performed so that ½ of the code finally matches.
[0036]
That is, in the CMOS non-inverter, the discrimination threshold is ½ of the power supply voltage, but control is performed so that the discrimination threshold is equal to the average value of the signal. This indicates that fluctuations in the pulse width of the signal are suppressed.
[0037]
In the above description, it is assumed that the pulse width of the input signal is widened. However, even when the pulse width of the input signal is narrowed, fluctuations in the pulse width are similarly suppressed.
[0038]
In this way, even if the pulse width of the input signal varies, the variation in the pulse width is suppressed in the output signal.
[0039]
In addition, artificial adjustment of a variable element such as a variable resistor is not required in the control of the pulse width. Therefore, a small and inexpensive pulse width control circuit can be obtained.
[0040]
In addition, it is possible to reduce the size and price of an electric / optical conversion circuit in which the pulse width control circuit is applied to an input circuit.
[0041]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a first embodiment of the present invention.
[0042]
In FIG. 1, 1 is a low-pass filter, 2 is a CMOS non-inverter, 3 is an automatic level control circuit, 4 is an average value detection circuit, 5 is a voltage dividing circuit, and 6 is a non-inverting compression amplifier.
[0043]
The CMOS non-inverter 2 includes a P-CH type MOS transistor 2-1, an N-CH type MOS transistor 2-2, a P-CH type MOS transistor 2-3, and an N-CH type MOS transistor 2-4. The voltage dividing circuit 5 includes a resistor 5-1 and a resistor 5-2.
[0044]
Furthermore, as shown in FIG. 11, the average value detection circuit 4 may be configured by a circuit having a resistor in the series branch and a capacitor in the parallel branch. If the time constant is set longer than the time for defining the mark rate of the signal, the correct average value of the signal can be obtained even if the microscopic rate of the mark and space fluctuates.
[0045]
In the configuration of FIG. 1, an input signal is passed through the low-pass filter 1 and converted from a pulse waveform to a waveform in which a high-frequency component whose level gradually increases / decreases is attenuated, and the low-pass filter 1 The output is supplied to the complementary metal-oxide semiconductor non-invertor (CMOS) 2, the output of the CMOS non-inverter 2 is supplied to the automatic level control circuit 3, and the output of the automatic level control circuit 3 is supplied. The voltage detected by the average value detection circuit 4 is supplied to the non-inverting input terminal of the non-inverting compression amplifier 6, and the inverting input terminal of the non-inverting compression amplifier 6 is ½ of the output of the non-inverting compression amplifier 6. A voltage is supplied as a reference voltage, and an output of the non-inverting compression amplifier 6 is supplied as a power supply voltage for the CMOS non-inverter 2. The output of the automatic level control circuit 3 is used as the output of the pulse width control circuit.
[0046]
2 is a diagram for explaining the operation of the configuration of FIG. 1. FIG. 2 (a) shows the input of the low-pass filter, FIG. 2 (b) shows the output of the CMOS non-inverter, and FIG. The output of the automatic level control circuit is shown.
[0047]
Hereinafter, the operation of the configuration of FIG. 1 will be described with reference to FIGS. 1 and 2.
[0048]
A signal indicated by a thin solid line in FIG. 2A is a signal having a normal pulse width, and a signal indicated by a thick solid line is a signal having a wide pulse width. Here, it is assumed that a signal indicated by a thick solid line in FIG. 2A is input to the low-pass filter 1 in FIG.
[0049]
2 (b) shows the output of the low-pass filter 1 when the signal indicated by the thick solid line in FIG. 2 (a) is input, corresponding to the characteristics of the low-pass filter 1. FIG. A waveform with suppressed high-frequency components. If the low-pass filter 1 is constituted by an integrating circuit as shown in FIG. 14, the rising waveform in FIG. 2 (b) is an exponential function that increases the amplitude by the charging time constant of the integrating circuit. The falling waveform becomes an exponential function that decreases the amplitude by the discharge time constant of the integration circuit.
[0050]
The waveform of FIG. 2B is input to the CMOS non-inverter 2 of FIG. The discrimination threshold of the CMOS non-inverter 2 is equal to ½ of the power supply voltage supplied at this moment. If this is equal to the threshold value 1 in FIG. 2 (b), the output of the CMOS non-inverter 2 becomes a logic level “1” when the amplitude of the waveform in FIG. When the amplitude of the waveform of 2 (b) is smaller than the threshold value 1, the waveform becomes a logic level “0”. Since this is supplied to the CMOS non-inverter 2 of FIG. 1, even in the output waveform of the CMOS non-inverter, the pulse width becomes wider than a predetermined value.
[0051]
Since the output of the CMOS non-inverter 2 is supplied to the automatic level control circuit 3 of FIG. 1, the output of the automatic level control circuit 3 has a waveform in which the amplitude is constant and the pulse width is wider than the internal value. This is shown by a thick solid line waveform in FIG.
[0052]
Since the thick solid line waveform in FIG. 2 (c) is supplied to the average value detection circuit 4 in FIG. 1, the output of the average value detection circuit 4 rises.
[0053]
Since the output of the average value detection circuit 4 is supplied to the non-inverting input terminal of the non-inverting compression amplifier 6 of FIG. 1, the output voltage of the non-inverting compression amplifier 6 also rises.
[0054]
The output voltage of the non-inverting compression amplifier 6 is supplied to the CMOS non-inverter 2 as a power supply voltage. By the way, since the identification threshold value of the CMOS non-inverter 2 is ½ of the power supply voltage supplied to the CMOS non-inverter 2, the identification threshold value of the CMOS non-inverter 2 also increases, and the CMOS non-inverter 2 The width of the output pulse 2 is reduced.
[0055]
Accordingly, the output pulse width of the automatic level control circuit 3 is also narrowed. This is shown by the thin solid line waveform in FIG.
[0056]
By the way, since the output of the CMOS non-inverter 2 is controlled to a constant amplitude by the automatic level control circuit 3, the voltage obtained by detecting the average value of the output of the automatic level control circuit 3 by the average value detection circuit 4 of FIG. descend.
[0057]
Accordingly, the output voltage of the non-inverting compression amplifier 6 is lowered, the discrimination threshold value of the CMOS non-inverter 2 is also lowered, and control is performed so that the output pulse width of the CMOS non-inverter 2 is widened.
[0058]
Further, since ½ of the output voltage of the non-inverting compression amplifier 6 is supplied as a reference voltage to the inverting input terminal of the non-inverting compression amplifier 6, the output of the average value detection circuit 4 and the non-inverting compression amplifier are fed by the feedback. Control is performed so that ½ of the output voltage of 6 finally matches.
[0059]
That is, control is performed so that the discrimination threshold of the CMOS non-inverter 2 is equal to the average value of the signal. This means that fluctuations in the direction in which the pulse width of the signal widens is suppressed.
[0060]
In the above description, it is assumed that the pulse width of the input signal is widened. However, even when the pulse width of the input signal is narrowed, fluctuations in the pulse width are similarly suppressed.
[0061]
In this manner, even if the pulse width of the input signal varies, the variation in the pulse width is suppressed in the output signal.
[0062]
In addition, artificial adjustment of a variable element such as a variable resistor is not required in the control of the pulse width. Therefore, a small and inexpensive pulse width control circuit can be obtained.
[0063]
FIG. 3 shows a second embodiment of the present invention.
[0064]
In FIG. 3, 1 is a low-pass filter, 2 is a CMOS non-inverter, 3 is an automatic level control circuit, 4 is an average value detection circuit, 6 is a non-inverting compression amplifier, 7 is a peak detection circuit, and 8 is a direct current. It is a blocking capacitor.
[0065]
The CMOS non-inverter 2 includes a P-CH type MOS transistor 2-1, an N-CH type MOS transistor 2-2, a P-CH type MOS transistor 2-3, and an N-CH type MOS transistor 2-4. Composed.
[0066]
Furthermore, as shown in FIG. 11, the average value detection circuit 4 may be configured by a circuit having a resistor in the series branch and a capacitor in the parallel branch. If the time constant is set longer than the time for defining the mark rate of the signal, the correct average value of the signal can be obtained even if the microscopic rate of the mark and space fluctuates.
[0067]
Further, the configuration of the peak detection circuit 7 may be a circuit having a diode in the serial branch and a capacitor in the parallel branch, as shown in FIG.
[0068]
In the configuration of FIG. 3, an input signal is passed through the low-pass filter 1 to convert a pulse waveform into a waveform in which a high-frequency component is attenuated, and the output of the low-pass filter 1 is converted to the CMOS non-pass filter 1. Supply to the inverter 2, supply the output of the CMOS non-inverter 2 to the automatic level control circuit 3, divide the output of the automatic level control circuit 3 into two, and supply one to the average value detection circuit 4 The other is supplied to the peak detection circuit 7 through the DC blocking capacitor 8, and the output of the average value detection circuit 4 is supplied to the non-inverting input terminal of the non-inverting compression amplifier 6. The output is supplied to the inverting input terminal of the non-inverting compression amplifier 6, and the output of the non-inverting compression amplifier 6 is supplied to the CMOS non-inverter 2 as a power supply voltage.
[0069]
Here, description will be made assuming that the pulse width of the input signal is widened.
[0070]
When the input signal passes through the low-pass filter 1, the high frequency component is attenuated and converted into a waveform whose level gradually increases / decreases. This waveform is identified by the identification threshold value of the CMOS non-inverter 2 and returned to a pulse waveform.
[0071]
Now, since it is assumed that the pulse width of the input signal is widened, the pulse width at the output of the CMOS non-inverter 2 is also widened. Therefore, the pulse width is wide at the output of the automatic level control circuit 3 as well. Become.
[0072]
Since the output of the automatic level control circuit 3 is supplied to the average value detection circuit 4, the output of the average value detection circuit 4 rises, and therefore the output of the non-inverting compression amplifier 6 also rises.
[0073]
Along with this, the discrimination threshold of the CMOS non-inverter 2 rises, so that the pulse width of the output waveform of the CMOS non-inverter 2 changes in the direction of narrowing.
[0074]
Therefore, the average value of the output of the automatic level control circuit 3 is lowered and the output of the non-inverting compression amplifier 6 is also lowered, so that the discrimination threshold value of the CMOS non-inverter 2 is lowered.
[0075]
As a result, control is performed in the direction in which the pulse width becomes wider in the output waveform of the CMOS non-inverter.
[0076]
Further, a signal obtained by cutting off the direct current output from the automatic level control circuit 3 is supplied to the peak detection circuit 7. Therefore, the output of the peak detection circuit 7 becomes a voltage that is ½ of the output amplitude of the automatic level control circuit 4.
[0077]
That is, control is performed so that the discrimination threshold of the CMOS non-inverter 2 is equal to the average value of the signal. This means that fluctuations in the direction in which the pulse width of the signal widens is suppressed.
[0078]
In the above description, it is assumed that the pulse width of the input signal is widened. However, even when the pulse width of the input signal is narrowed, fluctuations in the pulse width are similarly suppressed.
[0079]
In this way, even if the pulse width of the input signal varies, the variation in the pulse width is suppressed in the output signal.
[0080]
In addition, artificial adjustment of a variable element such as a variable resistor is not required in the control of the pulse width. Therefore, a small and inexpensive pulse width control circuit can be obtained.
[0081]
FIG. 4 shows a third embodiment of the present invention.
[0082]
In FIG. 4, 1 is a low-pass filter, 2 is a CMOS non-inverter, 3 is an automatic level control circuit, 4 is an average value detection circuit, 5 is a voltage dividing circuit, 6 is a non-inverting compression amplifier, and 8 is a direct current. A cutoff capacitor 9 is a second average value detection circuit.
[0083]
The CMOS non-inverter 2 includes a P-CH type MOS transistor 2-1, an N-CH type MOS transistor 2-2, a P-CH type MOS transistor 2-3, and an N-CH type MOS transistor 2-4. The voltage dividing circuit 5 includes a resistor 5-1 and a resistor 5-2.
[0084]
Further, the configuration of the average value detection circuit 4 and the second average value detection circuit 9 may be configured by a circuit having a resistor in the serial branch and a capacitor in the parallel branch, as shown in FIG. If the time constant is set longer than the time for defining the mark rate of the signal, the correct average value of the signal can be obtained even if the microscopic rate of the mark and space fluctuates.
[0085]
In the configuration of FIG. 4, an input signal is passed through the low-pass filter 1 to convert a pulse waveform into a waveform in which a high-frequency component is attenuated, and the output of the low-pass filter 1 is converted into the CMOS non-pass filter 1. Supply to the inverter 2, supply the output of the CMOS non-inverter 2 to the automatic level control circuit 3, divide the output of the automatic level control circuit 3 into two, and supply one to the average value detection circuit 4 The other is supplied to the second average value detection circuit 9 via the DC blocking capacitor 8 and the voltage dividing circuit 5, and the output of the average value detection circuit 4 is supplied to the non-inverting input terminal of the non-inverting compression amplifier 6. And the output of the second average value detection circuit 9 is supplied to the inverting input terminal of the non-inverting compression amplifier 6, and the output of the non-inverting compression amplifier 6 is supplied to the CMOS non-inverter 2 as a power supply voltage. , Also supplied to one end of the voltage dividing circuit 5 That.
[0086]
Here, description will be made assuming that the pulse width of the input signal is widened.
[0087]
When the input signal passes through the low-pass filter 1, the high frequency component is attenuated and converted into a waveform whose level gradually increases / decreases. This waveform is identified by the identification threshold value of the CMOS non-inverter 2 and returned to a pulse waveform.
[0088]
Now, since it is assumed that the pulse width of the input signal is widened, the pulse width at the output of the CMOS non-inverter 2 is also widened. Therefore, the pulse width is wide at the output of the automatic level control circuit 3 as well. Become.
[0089]
Since the output of the automatic level control circuit 3 is supplied to the average value detection circuit 4, the output of the average value detection circuit 4 rises, and therefore the output of the non-inverting compression amplifier 6 also rises.
[0090]
Along with this, the discrimination threshold of the CMOS non-inverter 2 rises, so that the pulse width of the output waveform of the CMOS non-inverter 2 changes in the direction of narrowing.
[0091]
Therefore, the average value of the output of the automatic level control circuit 3 is lowered and the output of the non-inverting compression amplifier 6 is also lowered, so that the discrimination threshold value of the CMOS non-inverter 2 is lowered.
[0092]
As a result, control is applied in the direction in which the pulse width becomes wider in the output waveform of the CMOS non-inverter 2.
[0093]
Further, a signal obtained by superimposing a voltage obtained by dividing the output of the non-inverting compression amplifier 6 by the voltage dividing circuit 5 on the signal obtained by cutting off the direct current of the output of the automatic level control circuit 3 is supplied to the second average value detection circuit 9. Supplied. Therefore, the output of the second average value detection circuit 9 becomes a voltage that is ½ of the output amplitude of the non-inverting compression amplifier 6.
[0094]
That is, control is performed so that the discrimination threshold of the CMOS non-inverter 2 is equal to the average value of the signal. This means that fluctuations in the direction in which the pulse width of the signal widens is suppressed.
[0095]
In the above description, it is assumed that the pulse width of the input signal is widened. However, even when the pulse width of the input signal is narrowed, fluctuations in the pulse width are similarly suppressed.
[0096]
In this way, even if the pulse width of the input signal varies, the variation in the pulse width is suppressed in the output signal.
[0097]
In addition, artificial adjustment of a variable element such as a variable resistor is not required in the control of the pulse width. Therefore, a small and inexpensive pulse width control circuit can be obtained.
[0098]
Also in the configuration of FIG. 4, the output of the second average value detection circuit 9 is equal to ½ of the output of the non-inverted compression amplifier 6. Therefore, the operation is basically the same as that of the configuration of FIG. Even when the characteristics of the average value detection circuit 4 and the second average value detection circuit 9 have errors from the characteristics of the ideal average value detection circuit, these errors can be canceled out.
[0099]
FIG. 5 is a modification of the first embodiment of the present invention.
[0100]
In FIG. 5, 1 is a low-pass filter, 2a is a CMOS inverter, 3 is an automatic level control circuit, 4 is an average value detection circuit, 5 is a voltage dividing circuit, 6 is a non-inverting compression amplifier, and 7 is a peak detection circuit. , 16 is a differential amplifier whose absolute value of voltage gain is 1 on both the inverting side and the non-inverting side.
[0101]
The CMOS inverter 2a is composed of a P-CH type MOS transistor 2-1 and an N-CH type MOS transistor 2-2, and the voltage dividing circuit 5 is composed of a resistor 5-1 and a resistor 5-2. .
[0102]
Furthermore, as shown in FIG. 11, the average value detection circuit 4 may be configured by a circuit having a resistor in the series branch and a capacitor in the parallel branch. If the time constant is set longer than the time for defining the mark rate of the signal, the correct average value of the signal can be obtained even if the microscopic rate of the mark and space fluctuates.
[0103]
Further, the configuration of the peak detection circuit 7 may be a circuit having a diode in the serial branch and a capacitor in the parallel branch, as shown in FIG.
[0104]
The differential amplifier 16 having an absolute value of voltage gain of 1 on both the inverting side and the non-inverting side forms a voltage follower by an operational amplifier and divides the voltage by 1/2 on the non-inverting input terminal side of the voltage follower. This can be realized by connecting a circuit.
[0105]
In the configuration of FIG. 5, the input signal is passed through the low-pass filter 1 to convert the pulse waveform into a waveform in which the level at which the high-frequency component is attenuated gradually increases / decreases, and the low-pass filter 1 The output is supplied to a CMOS inverter (Complementary Metal-Oxide Semiconductor Invertor) 2a, the output of the CMOS inverter 2a is supplied to the automatic level control circuit 3, and the output of the automatic level control circuit 3 is supplied to the average value detection circuit 4 And the peak detection circuit 7 detects the peak value, supplies the output of the average value detection circuit 4 to the inverting input terminal of the differential amplifier 16, and outputs the output of the peak detection circuit to the differential amplifier. The non-inverting input terminal is supplied, the output of the differential amplifier 16 is supplied to the non-inverting input terminal of the non-inverting compression amplifier 6, and the non-inverting input terminal of the non-inverting compression amplifier 6 is supplied to the non-inverting input terminal by the voltage dividing circuit 5. Rolling a half voltage of the output of the compression amplifier 6 and supplied as a reference voltage, and supplies the output of the non-determination compression amplifier 6 as a power supply voltage of the CMOS inverter 2a. The output of the automatic level control circuit 3 is used as the output of the pulse width control circuit.
[0106]
When the output of the low-pass filter 1 is supplied to the CMOS inverter 2a, the output of the average value detection circuit 4 decreases as the duty ratio of the input signal increases.
[0107]
When the output of the average value circuit 4 is supplied directly to the non-inverting input terminal of the non-inverting compression amplifier 6, the threshold value of the CMOS inverter 2a is lowered, the output of the average value detecting circuit is further lowered, and the duty ratio of the signal is reduced. It is impossible to control to restore
[0108]
The above control is possible when the power supply voltage of the CMOS inverter can be increased when the duty ratio of the input signal is increased. For this reason, it seems that the polarity of the compression amplifier may be reversed at first glance.
[0109]
However, when the polarity of the compression amplifier is simply reversed, positive feedback is applied to the compression amplifier by the voltage dividing circuit 5, making it impossible to obtain a stable operation.
[0110]
Therefore, the peak detection circuit 7 and the differential amplifier 16 are provided to generate a voltage obtained by subtracting the output of the average value detection circuit 4 from the output of the peak detection circuit 7, and the ratio of the ratio inverting compression amplifier 6. When supplied to the inverting input terminal, when the duty ratio of the input voltage increases in the configuration of FIG. 1, the same voltage as that supplied to the ratio inverting input terminal of the ratio inverting compression amplifier 6 can be supplied. The ratio can be controlled.
[0111]
Therefore, although the configuration for controlling the duty ratio of a signal using a CMOS non-inverter in FIG. 1 has been shown, the same can be achieved using a CMOS inverter.
[0112]
That is, the technique shown in FIGS. 1 and 5 essentially includes a CMOS gate for identifying a signal waveform in which a high frequency component of an input signal waveform is attenuated, and an average value detection for detecting an average value of the output waveform of the CMOS gate. A non-inverting compression circuit that receives a voltage half of its output at its inverting input terminal, receives a change in the output of the average value detection circuit at its non-inverting input terminal, and supplies the output to the CMOS gate as a power supply voltage It can be said that the pulse width control circuit includes an amplifier.
[0113]
Needless to say, the technique shown in the configuration of FIG. 5 can also be applied to the configurations of FIGS. 3 and 4.
[0114]
1, 3, 4, and 5, consistently, the output of the CMOS gate is supplied to the automatic level control circuit, and the output of the automatic level control circuit is supplied to the average value detection circuit or the peak detection circuit. The configuration to supply to has been shown. However, the present invention is not limited to the above configuration, and the pulse width can be controlled by a configuration in which the output of the CMOS gate is directly supplied to the average value detection circuit or the peak detection circuit. This is clear if the operation of the pulse width control already described is confirmed with respect to the above-mentioned configuration, but if it is dared to add, if the duty ratio of the input signal changes and enters the control operation of the duty ratio, the CMOS gate This is because the average value detection circuit 4 can always detect the change in the average value of the output of the CMOS gate.
[0115]
In the case of the above configuration, since the logic level of the output of the CMOS gate can vary depending on the input pulse width while the duty ratio is controlled, the CMOS gate and the average value detection circuit or the peak detection circuit It is desirable that an automatic level control circuit is arranged after the connection point of the above and the output of the automatic level control circuit is used as the output of the pulse width control circuit.
[0116]
FIG. 6 shows a fourth embodiment of the present invention.
[0117]
In FIG. 6, 1 is a low-pass filter, 2 is a CMOS non-inverter, 3 is an automatic level control circuit, 5a is a voltage dividing circuit, and 10 is a buffer amplifier.
[0118]
The CMOS non-inverter 2 includes a P-CH type MOS transistor 2-1, an N-CH type MOS transistor 2-2, a P-CH type MOS transistor 2-3, and an N-CH type MOS transistor 2-4. The voltage dividing circuit 5a includes a resistor 5-1 and a resistor 5-3 having temperature characteristics.
[0119]
In the configuration of FIG. 6, an input signal is passed through the low-pass filter 1 to convert a pulse waveform into a waveform in which a high-frequency component is attenuated, and the output of the low-pass filter 1 is converted to the CMOS non-inverter. 2 is supplied to the CMOS non-inverter 2 through the buffer amplifier 10 as a power supply voltage.
[0120]
When the temperature characteristic of the pulse width of the input signal to the configuration of FIG. 6 has a positive coefficient, fluctuation of the pulse width can be suppressed by applying a resistor having a positive temperature coefficient as the resistor 5-3. .
[0121]
This is because it is assumed that the temperature coefficient of the resistor 5-3 is positive. Therefore, when the temperature rises, the power supply voltage supplied to the CMOS non-inverter 2 rises, and the CMOS non-inverter accordingly. The identification threshold of 2 also increases. As a result, the pulse width at the output of the CMOS non-inverter 2 becomes narrow, and the spread of the pulse width of the input signal is suppressed.
[0122]
When the temperature decreases, the power supply voltage supplied to the CMOS non-inverter 2 also decreases, and the discrimination threshold of the CMOS non-inverter 2 also decreases accordingly. As a result, the pulse width at the output of the CMOS non-inverter 2 is widened, and the narrowing of the pulse width of the input signal can be suppressed.
[0123]
Conversely, when the temperature characteristic of the pulse width of the input signal to the configuration of FIG. 6 has a negative coefficient, fluctuation of the pulse width is suppressed by applying a resistor having a negative temperature coefficient as the resistor 5-3. be able to.
[0124]
Because it is assumed that the temperature coefficient of the resistor 5-3 is negative, the power supply voltage supplied to the CMOS non-inverter 2 decreases as the temperature rises, and the CMOS non-inverter is accordingly reduced. The identification threshold of 2 also falls. As a result, the pulse width at the output of the CMOS non-inverter 2 becomes wider, and the narrowing of the pulse width of the input signal is suppressed.
[0125]
When the temperature falls, the power supply voltage supplied to the CMOS non-inverter 2 rises, and the discrimination threshold of the CMOS non-inverter 2 rises accordingly. As a result, the pulse width at the output of the CMOS non-inverter 2 becomes narrow, and the spread of the pulse width of the input signal can be suppressed.
[0126]
In this way, even if there is a temperature fluctuation in the pulse width of the input signal, the fluctuation in the pulse width is suppressed in the output signal.
[0127]
In addition, artificial adjustment of a variable element such as a variable resistor is not required in the control of the pulse width. Therefore, a small and inexpensive pulse width control circuit can be obtained.
[0128]
The advantage of the configuration of FIG. 6 is that the circuit configuration is simplified in a feed-forward type pulse width control circuit.
[0129]
If the voltage having the temperature coefficient is generated by a circuit that combines a plurality of resistors having the temperature coefficient instead of the simple voltage dividing circuit as shown in FIG. 6, the accuracy of the pulse width control can be improved.
[0130]
FIG. 7 is a modification of the fourth embodiment of the present invention.
[0131]
In FIG. 7, 1 is a low-pass filter, 2a is a CMOS inverter, 3 is an automatic level control circuit, 5a is a voltage dividing circuit, and 10 is a buffer amplifier.
[0132]
The CMOS inverter 2a includes a P-CH type MOS transistor 2-1 and an N-CH type MOS transistor 2-2. The voltage dividing circuit 5a includes a resistor 5-1 and a resistor 5-3 having temperature characteristics. Consists of.
[0133]
In the configuration of FIG. 7, an input signal is passed through the low-pass filter 1 to convert a pulse waveform into a waveform in which high-frequency components are attenuated, and the output of the low-pass filter 1 is sent to the CMOS inverter 2a. The voltage having a temperature characteristic supplied and burned out by the voltage dividing circuit 5a is supplied to the CMOS inverter 2a through the buffer amplifier 10 as a power supply voltage.
[0134]
When the temperature characteristic of the pulse width of the input signal to the configuration of FIG. 7 has a positive coefficient, fluctuation of the pulse width can be suppressed by applying a resistor having a positive temperature coefficient as the resistor 5-3. .
[0135]
This is because it is assumed that the temperature coefficient of the resistor 5-3 is positive. Therefore, when the temperature rises, the power supply voltage supplied to the CMOS inverter 2a rises, and the discrimination threshold of the CMOS inverter 2a increases accordingly. Also rises. As a result, the pulse width at the output of the CMOS inverter 2a becomes narrow, and the spread of the pulse width of the input signal is suppressed.
[0136]
When the temperature decreases, the power supply voltage supplied to the CMOS inverter 2a also decreases, and the identification threshold value of the CMOS inverter 2a also decreases accordingly. As a result, the pulse width at the output of the CMOS inverter 2a is widened, and the narrowing of the pulse width of the input signal can be suppressed.
[0137]
Conversely, when the temperature characteristic of the pulse width of the input signal to the configuration of FIG. 7 has a negative coefficient, fluctuation of the pulse width can be suppressed by applying a resistor having a negative temperature coefficient as the resistor 5-3. be able to.
[0138]
This is because it is assumed that the temperature coefficient of the resistor 5-3 is negative. Therefore, when the temperature rises, the power supply voltage supplied to the CMOS inverter 2a decreases, and the discrimination threshold of the CMOS inverter 2a is accordingly increased. Also descends. As a result, the pulse width at the output of the CMOS inverter 2a becomes wider, and the narrowing of the pulse width of the input signal is suppressed.
[0139]
When the temperature decreases, the power supply voltage supplied to the CMOS inverter 2a increases, and the identification threshold value of the CMOS inverter 2a also increases accordingly. As a result, the pulse width at the output of the CMOS inverter 2a becomes narrow, and the spread of the pulse width of the input signal can be suppressed.
[0140]
In this way, even if there is a temperature fluctuation in the pulse width of the input signal, the fluctuation in the pulse width is suppressed in the output signal.
[0141]
In addition, artificial adjustment of a variable element such as a variable resistor is not required in the control of the pulse width. Therefore, a small and inexpensive pulse width control circuit can be obtained.
[0142]
The advantage of the configuration of FIG. 7 is that the circuit configuration is simplified in a feed-forward type pulse width control circuit.
[0143]
If the voltage having the temperature coefficient is generated by a circuit combining a plurality of resistors having the temperature coefficient instead of the simple voltage dividing circuit as shown in FIG. 7, the accuracy of the pulse width control can be improved.
[0144]
The configuration of FIG. 6 and the configuration of FIG. 7 are essentially the same except that the CMOS non-inverter and the CMOS inverter are different and the temperature coefficient of the resistor having the temperature coefficient is different. 6 and 7 is a pulse width control circuit that receives a voltage having a temperature coefficient as a power supply voltage and controls the pulse width by a CMOS gate that identifies a waveform in which a high frequency component of an input signal waveform is attenuated. It can be said that there is.
[0145]
FIG. 8 shows a configuration of an electric / optical conversion circuit according to the fifth embodiment of the present invention, which is a combination of the pulse width control circuit having the configuration of FIG. 1 and the electric / optical conversion circuit.
[0146]
In FIG. 8, 1 is a low-pass filter, 2 is a CMOS non-inverter, 3 is an automatic level control circuit, 4 is an average value detection circuit, 5 is a voltage dividing circuit, and 6 is a non-inverting compression amplifier.
[0147]
The CMOS non-inverter 2 includes a P-CH type MOS transistor 2-1, an N-CH type MOS transistor 2-2, a P-CH type MOS transistor 2-3, and an N-CH type MOS transistor 2-4. The voltage dividing circuit 5 includes a resistor 5-1 and a resistor 5-2.
[0148]
Furthermore, as shown in FIG. 11, the average value detection circuit 4 may be configured by a circuit having a resistor in the series branch and a capacitor in the parallel branch. If the time constant is set longer than the time for defining the mark rate of the signal, the correct average value of the signal can be obtained even if the microscopic rate of the mark and space fluctuates.
[0149]
Then, the pulse width control circuit shown in FIG.
[0150]
Next, 11 is a laser diode drive circuit (indicated as an LD drive circuit in the figure, and so on), 12 is a laser diode that converts an electrical signal into an optical signal, and 13 is the laser diode. Photodiode which receives back light which is a part of the output light of 12 and converts it again into electric power, 14 is a resistor which converts the output current of the photodiode 13 into voltage, and 15 is the power of the output light of the laser diode Is an automatic optical power control circuit for controlling
[0151]
The automatic optical power control circuit 15 includes, as shown in FIG. 13, an average value detection circuit or a peak detection circuit that converts a voltage obtained by converting a current generated by photo / electric conversion by a photo diode PD into a direct current. The voltage V output when the average value detection circuit or the peak detection circuit is in the reference state _REF Is received at the non-inverting input terminal, the output of the average value detection circuit or the peak detection circuit is received at the inverting input terminal, and the output is supplied to a laser diode driving circuit (denoted as an LD driving circuit in the figure). What is necessary is just to comprise by an inverting compression amplifier.
[0152]
In the configuration of FIG. 8, a signal whose pulse width is controlled by the configuration of FIG. 1 is supplied to the laser diode drive circuit 11 and converted into an optical signal by the laser diode 12 subjected to automatic optical power control.
[0153]
Therefore, the pulse width of the output light of the laser diode 12 is also controlled, and it is possible to prevent the fluctuation of the pulse width from being transmitted as it is to the subsequent circuit.
[0154]
In addition, artificial adjustment of a variable element such as a variable resistor is not required in the control of the pulse width. Therefore, it is possible to obtain a small and inexpensive electric / optical conversion circuit.
[0155]
In FIG. 8, the electric / optical conversion circuit in which the pulse width control circuit of FIG. 1 and the electric / optical conversion circuit are combined has been described. This combination is the same as the pulse width control circuit and the electric / optical conversion circuit of FIGS. Needless to say, this is also possible.
[0156]
FIG. 9 shows a sixth embodiment of the present invention.
[0157]
In FIG. 9, 1 is a low-pass filter, 2 is a CMOS non-inverter, 6 is a non-inverting compression amplifier, 7 is a peak detection circuit, 11 is a laser diode drive circuit, 12 is a laser diode, and 13 is a photo diode. A diode, 14 is a resistor, and 15 is an automatic optical power control circuit.
[0158]
The CMOS non-inverter 2 includes a P-CH type MOS transistor 2-1, an N-CH type MOS transistor 2-2, a P-CH type MOS transistor 2-3, and an N-CH type MOS transistor 2-4. Composed.
[0159]
Furthermore, as shown in FIG. 12, the peak detection circuit 7 may be configured by a circuit having a diode in the serial branch and a capacitor in the parallel branch.
[0160]
In the configuration of FIG. 9, an input signal is passed through the low-pass filter 1 to convert a pulse waveform into a waveform in which a high-frequency component is attenuated, and the output of the low-pass filter 1 is converted to the CMOS non-inverter. 2, the output of the CMOS non-inverter 2 is supplied to the laser diode drive circuit 11, and the laser diode 12 is driven to convert an electrical signal into an optical signal. Then, the back light, which is a part of the output light of the laser diode 12, is received by the photo diode 13 and is electrically converted, and voltage is converted by the resistor 14.
[0161]
The terminal voltage of the resistor 14 is supplied to the automatic optical power control circuit 15 on the one hand to control the output light level of the laser diode 12 to be constant. Further, the terminal voltage of the resistor 14 is supplied to the peak detection circuit 7 on the other side, and the output of the peak detection circuit 7 is supplied to the reference voltage V at the inverting input terminal. _REF Is supplied to the inverting input terminal of the non-inverting compression amplifier 6 and the output of the non-inverting compression amplifier 6 is supplied to the CMOS non-inverter 2 as a power supply voltage.
[0162]
Now, the operation of the configuration of FIG. 9 will be described assuming that the pulse width of the input signal is widened.
[0163]
When the pulse width of the input signal is widened, the pulse width of the signal in which the high frequency component is attenuated by the CMOS non-inverter 2 is widened. With this signal, the laser diode drive circuit 11 drives the laser diode 12 subjected to automatic optical power control, so that the pulse amplitude of the output light of the laser diode 12 is lowered.
[0164]
Accordingly, since the terminal voltage of the resistor 14 also decreases, the non-inverting compression amplifier 6 supplies a low power supply voltage to the CMOS non-inverter 2. Since the power supply voltage is lowered, the discrimination threshold value of the CMOS non-inverter 2 is also lowered, and the pulse width of the CMOS inverter 2a is controlled to be narrowed.
[0165]
The reference voltage V supplied to the non-inverting input terminal of the non-inverting compression amplifier 6 _REF And the control works so that the output voltage of the peak detection circuit 7 becomes equal, and the level of each part of the configuration of FIG. 9 is stabilized.
[0166]
Then, even if the pulse width of the input signal is narrowed, the control is similarly performed so as to suppress the narrowing of the pulse width.
[0167]
In this manner, the pulse width of the output light can be kept constant even if the pulse width of the input signal varies due to the configuration of FIG.
[0168]
In addition, artificial adjustment of a variable element such as a variable resistor is not required in the control of the pulse width. Therefore, it is possible to obtain a small and inexpensive electric / optical conversion circuit.
[0169]
The advantage of the configuration of FIG. 9 is that a circuit for performing electrical / optical conversion is included in a loop for performing pulse width control, so that there is an individual difference in the threshold value of the output characteristics of the laser diode. This is because the pulse width of the output light of the diode can be kept constant.
[0170]
FIG. 10 is a modification of the sixth embodiment of the present invention.
[0171]
In FIG. 10, 1 is a low-pass filter, 2a is a CMOS inverter, 6a is an inverting compression amplifier, 7 is a peak detection circuit, 11 is a laser diode drive circuit, and 12 is a laser that converts an electrical signal into an optical signal. A diode, 13 is a photodiode that receives back light, which is a part of the output light of the laser diode 12, and converts it again, 14 is a resistor that converts the output current of the photodiode 13 to voltage, and 15 is the laser. An automatic optical power control circuit that controls the power of the output light of the diode 12.
[0172]
The CMOS inverter 2a includes a P-CH type MOS transistor 2-1 and an N-CH type MOS transistor 2-2.
[0173]
Furthermore, as shown in FIG. 12, the peak detection circuit 7 may be configured by a circuit having a diode in the serial branch and a capacitor in the parallel branch.
[0174]
Finally, as shown in FIG. 13, the automatic optical power control circuit receives an average value detection circuit or peak detection circuit and a reference voltage output by the average value detection circuit or peak detection circuit in a reference state at an inverting input terminal, The inverting compression amplifier receives the output voltage of the average value detection circuit or peak detection circuit at a non-inverting input terminal, and the bias current of the laser diode driving circuit is controlled by the output voltage of the inverting compression amplifier.
[0175]
In the configuration of FIG. 10, an input signal is passed through the low-pass filter 1 to be converted into a signal in which a high-frequency component is suppressed, and an output signal of the low-pass filter 1 is supplied to the CMOS inverter 2a. The output of the CMOS inverter 2a is supplied to the laser diode drive circuit 11, and the laser diode 12 converts an electrical signal into an optical signal.
[0176]
Back light, which is a part of the output light of the laser diode 12, is converted again into an electric signal by the photo diode 13 and converted into a voltage by the resistor 14.
[0177]
The terminal voltage of the resistor 14 is divided into two, and one is supplied to the automatic optical power control circuit 15 to control the bias current of the laser diode drive circuit 11 to control the output power of the laser diode 12 to be constant. To do.
[0178]
At the same time, the terminal voltage of the resistor 14 is supplied to the peak detection circuit 7, and the output voltage of the peak detection circuit 7 is supplied as the power supply voltage of the CMOS inverter 2a.
[0179]
Assume that the pulse width of the input electrical signal is now wide. At this time, the pulse width of the output signal of the CMOS inverter 2a becomes narrow, and this signal is supplied to the laser diode drive circuit 11 to drive the laser diode 12.
[0180]
By the way, since the laser diode 12 is subjected to automatic optical power control, when the input pulse width of the laser diode driving circuit 11 becomes narrow, the power of the output light of the laser diode 12 is kept constant. Control is applied in the direction of increasing the amplitude of the output light of the laser diode 12.
[0181]
Accordingly, the output voltage of the peak detection circuit 7 also changes in the increasing direction. Since this voltage is supplied to the non-inverting input terminal of the inverting compression amplifier 6a and the output of the inverting compression amplifier 6a is supplied as a power supply voltage to the CMOS inverter 2a, the discrimination threshold of the CMOS inverter 2a also increases, Control is applied in the direction in which the pulse width of the output signal of the CMOS inverter 2a becomes narrower.
[0182]
In this way, even if the pulse width of the input signal is widened, the spread of the pulse width of the output light of the laser diode 12 is suppressed.
[0183]
Similarly, even if the pulse width of the input signal is narrowed, the narrowing of the pulse width of the output light of the laser diode 12 is suppressed.
[0184]
Therefore, even if the pulse width of the input signal varies due to the configuration of FIG. 10, the variation in the pulse width of the optical signal output from the laser diode is suppressed.
[0185]
In addition, artificial adjustment of a variable element such as a variable resistor is not required in the control of the pulse width. Therefore, it is possible to obtain a small and inexpensive electric / optical conversion circuit.
[0186]
The advantage of the configuration of FIG. 10 is that a circuit for performing electrical / optical conversion is included in a loop for performing pulse width control, so that there is an individual difference in the threshold value of the output characteristics of the laser diode. This is in that the pulse width of the output light of the diode can be kept constant.
[0187]
The configuration of FIG. 9 and the configuration of FIG. 10 are essentially the same, although the CMOS non-inverter and the CMOS inverter are different and the non-inverting compression amplifier and the inverting compression amplifier are different. 9 and FIG. 10, the CMOS gate for identifying the signal waveform obtained by attenuating the high frequency component of the input signal waveform, the laser diode driving circuit for receiving the output of the CMOS gate, and the laser diode driving circuit. A laser diode that is driven by the laser to convert an electrical signal into an optical signal, a photo diode that electrically converts the back light of the laser diode, and a voltage obtained by voltage-converting the output current of the photo diode An automatic optical power control circuit for controlling the bias of the driving circuit to perform automatic optical power control on the laser diode, and detecting a peak value of a voltage obtained by converting the output current of the photo diode, and depending on the detected peak value An electric / optical conversion circuit including a peak detection circuit for controlling a power supply voltage of the CMOS gate; It can be said that.
[0188]
【The invention's effect】
As described above in detail, according to the present invention, a small and low-cost pulse width control circuit that outputs a signal having a constant pulse width even when an input signal with a varying pulse width is received can be obtained. A small and inexpensive electric / optical conversion circuit can be obtained.
[Brief description of the drawings]
FIG. 1 is a first embodiment of the present invention.
FIG. 2 is a diagram for explaining the operation of the configuration of FIG. 1;
FIG. 3 shows a second embodiment of the present invention.
FIG. 4 is a third embodiment of the present invention.
FIG. 5 shows a modification of the first embodiment of the present invention.
FIG. 6 shows a fourth embodiment of the present invention.
FIG. 7 shows a modification of the fourth embodiment of the present invention.
FIG. 8 shows a fifth embodiment of the present invention.
FIG. 9 shows a sixth embodiment of the present invention.
FIG. 10 shows a modification of the sixth embodiment of the present invention.
FIG. 11 shows an example of an average value detection circuit.
FIG. 12 shows an example of a peak detection circuit.
FIG. 13 shows an example of an automatic optical power control circuit.
FIG. 14 shows an example of a conventional pulse width control circuit.
FIG. 15 shows an example of a conventional electric / optical conversion circuit.
[Explanation of symbols]
1 Low-pass filter (LPF)
2 CMOS non-inverter
2a CMOS inverter
2-1 P-CH type MOS transistor
2-2 N-CH type MOS transistor
2-3 P-CH type MOS transistor
2-4 N-CH MOS transistor
3 Automatic level control circuit (ALC circuit)
4 Average value detection circuit
5 Voltage divider circuit
5a Voltage divider circuit
5-1 Resistance
5-2 Resistance
5-3 Resistance with temperature characteristics
6 Non-inverting compression amplifier
6a Inverting compression amplifier
7 Peak detection circuit
8 DC blocking capacitor
9 Second average value detection circuit
10 Buffer amplifier
11 Laser diode drive circuit (LD drive circuit)
12 Laser diode
13 Photo diode
14 Resistance
15 Automatic optical power control circuit (APC circuit)
16 Differential amplifier
50 buffer amplifier
51 Integration circuit
51-1 Resistance
51-2 Capacitor
52 Artificial adjustment circuit of pulse width
52-1 DC blocking capacitor
52-2 Resistance
52-3 Variable resistance
52-4 Inverter
53 Laser diode drive circuit (LD drive circuit)
54 Laser diode
55 Photo diode
56 Resistance
57 Automatic optical power control circuit (APC circuit)

Claims (5)

A low-pass filter that suppresses high-frequency components of the input signal ;
A CMOS gate for inputting the output of the low-pass filter ;
An automatic level control circuit for supplying an output of the CMOS gate and outputting an output voltage having a constant amplitude;
An average value detection circuit for detecting an average value of the output voltage of the automatic level control circuit ;
A non-inverting amplifier that receives a voltage half of its own output at its inverting input terminal, receives the output of the average value detection circuit at its non-inverting input terminal, and supplies its own output as a power supply voltage to the CMOS gate; A pulse width control circuit characterized by that. A low-pass filter that suppresses high-frequency components of the input signal ;
A CMOS gate for inputting the output of the low-pass filter ;
An automatic level control circuit for supplying an output of the CMOS gate and outputting an output voltage having a constant amplitude;
An average value detection circuit for detecting an average value of the output voltage of the automatic level control circuit ;
A peak detection circuit for detecting a peak value of a signal obtained by cutting off a DC component of the output of the CMOS gate;
A non-inverting amplifier that receives the output of the average value detection circuit at a non-inverting input terminal, receives the output of the peak detection circuit at an inverting input terminal, and supplies its own output as a power supply voltage to the CMOS gate. A pulse width control circuit. A low-pass filter that suppresses high-frequency components of the input signal ;
A CMOS gate for inputting the output of the low-pass filter ;
An automatic level control circuit for supplying an output of the CMOS gate and outputting an output voltage having a constant amplitude;
An average value detection circuit for detecting an average value of the output voltage of the automatic level control circuit ;
The output of the average value detection circuit is received at a non-inverting input terminal, and its own output is supplied as a power supply voltage to the CMOS gate, and also supplied to a 1/2 voltage dividing circuit that generates a voltage half that of its own output. A non-inverting amplifier that
A second average value detection circuit for detecting an average value of a signal obtained by superimposing the output of the 1/2 voltage dividing circuit on a signal obtained by cutting off the DC component of the output of the CMOS gate and supplying the average value to the inverting input terminal of the non-inverting amplifier And a pulse width control circuit. A pulse width control circuit according to any one of claims 1 to 3,
A laser diode drive circuit receiving the output of the pulse width control circuit;
A laser diode driven by the laser diode drive circuit to convert an electrical signal into an optical signal;
A photodiode for converting the back light of the laser diode into an electrical signal;
And an automatic optical power control circuit for controlling a bias of the laser diode driving circuit by a voltage obtained by converting the output current of the photo diode into a voltage, and applying automatic optical power control to the laser diode. Electrical / optical conversion circuit with width control function. A low-pass filter that suppresses high-frequency components of the input signal ;
A CMOS gate for inputting the output of the low-pass filter ;
A laser diode drive circuit receiving the output of the CMOS gate;
A laser diode driven by the laser diode drive circuit to convert an electrical signal into an optical signal;
A photodiode for converting the back light of the laser diode into an electrical signal;
An automatic optical power control circuit for controlling the bias of the laser diode driving circuit by a voltage obtained by converting the output current of the photo diode to perform automatic optical power control on the laser diode, and an output current of the photo diode A peak detection circuit for detecting a peak value of the voltage converted voltage;
An electric / optical conversion circuit having a pulse width control function, comprising: a non-inverting amplifier that supplies its own output based on the detected peak value as a power supply voltage of the CMOS gate.

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