JP2000307390A - Pulse width control circuit and electrical-to-optical transducer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable miniaturization and to keep constant a pulse width at low cost while unnecessitating a circuit for manual control by feeding the fluctuation component of the pulse width back to an input waveform identifying circuit and automatically controlling it. SOLUTION: An input pulse signal is made into a waveform gradually increasing/ decreasing the level through an LPF 1 and supplied through a CMOS non-inverter 2 for waveform identification to an ALC circuit 3 later, a level controlled signal is supplied to the non-inverted input terminal of a non-inverted compression amplifier 6 after detecting the average of a voltage through an average detecting circuit 4, and 1/2 of the output voltage of the amplifier 6 is inputted to an inverted input terminal as a reference voltage. When the pulse width of the input signal is great, the output average value of the average value detecting circuit 4 is increased, the output voltage of the amplifier 6 is increased as well and supplied to the CMOS 2 as a power supply voltage but since an identification threshold is increased as well, the fluctuation in the direction of widening the pulse width is suppressed by control so that the identification threshold and the average of the signal can be made equal. Then, the duty ratio is fixed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse width control circuit and an electro-optical conversion circuit, and more particularly, to a small and low-priced signal that outputs a signal with a constant duty ratio even when an input signal with a varied duty ratio is received. The present invention relates to a simple pulse width control circuit and an electric-optical conversion circuit to which the above-described pulse width control technique is applied.

In a signal transmission device, in order to stably identify a logic level, a logic level "1" and a logic level "0" are alternately repeated (that is, the logic level "1" and the logic level "0" are repeated). Code rate is 50%)
The design is performed on the assumption that the duration of the logic level "1" is equal to the duration of the logic level "0", that is, the duty ratio is 50%.

[0003] Even if the ratio between the code of the logical level "1" (this is called a normal mark) and the code of the logical level "0" (this is called a normal space) deviates from 50%,
In the case of a code that maintains a mark rate of 50% within a predetermined time, the duration of one mark and the duration of one space are required to be the same duration as when the mark and the space are alternately repeated. .

However, since the rise time and the fall time of the pulse signal are usually not 0 and the rise time and the fall time are not equal to each other, the rise and fall times of the discrimination circuit used in the signal transmission device may be changed. The duty ratio may fluctuate.

[0005] Once the duty ratio fluctuates,
The signal is transmitted while the fluctuation is preserved. As a result, in the subsequent signal transmission device, the timing margin of the identification is reduced, the identification error of the logical level of the signal is increased, and the quality of the signal transmission is reduced.

When a signal whose duty ratio fluctuates as described above is input to the electro-optical converter, the duty ratio of the optical signal remains fluctuated, and at the same time, automatic power control (Automatic Power Control) which is normally performed is performed. Control: generally APC) causes the amplitude of the light pulse to fluctuate.

Therefore, a pulse width control circuit that outputs a signal with a constant duty ratio even when receiving an input signal with a varied duty ratio, and an electric / electronic device to which the above-described pulse width control technique is applied.
The realization of a light conversion circuit is strongly desired.

[0008]

FIG. 14 shows an example of a conventional pulse width adjusting circuit.

In FIG. 14, reference numeral 50 denotes a buffer amplifier;
Is an integration circuit, and 52 is a circuit for artificially adjusting the pulse width.

The integrating circuit 51 comprises a resistor 51-1 and a capacitor 51-2. The pulse width adjusting circuit 52 comprises a DC cutoff capacitor 52-1 and a resistor 52-1.
2. It is composed of a variable resistor 52-3 and an inverter 52-4.

In the configuration shown in FIG. 14, the pulse width is artificially adjusted as follows.

That is, the input signal is supplied to the integration circuit 51 via the buffer amplifier 50, and is converted from a pulse waveform into an exponential function charge / discharge waveform.

The output of the integrating circuit 51 is supplied to the pulse width adjusting circuit 52.
-1 cuts off the DC component and then the resistor 52-2
The DC component is superimposed again by the voltage dividing circuit including the variable resistor 52-3.

The output of the voltage dividing circuit is connected to the inverter 52-
4 is applied. The inverter 52-4 has a specific threshold value for distinguishing between the logic level "1" and the logic level "0".

On the other hand, the level of the waveform input to the inverter 52-4 can be artificially adjusted by the voltage dividing circuit.

Therefore, the pulse width at the output terminal of the inverter 52-4 can be artificially adjusted to a predetermined value by the relationship between the DC level superimposed by the voltage dividing circuit and the threshold value of the inverter 52-4. it can.

FIG. 15 shows an example of a conventional electric / optical conversion circuit.

In FIG. 15, reference numeral 50 denotes a buffer amplifier;
Is an integration circuit, and 52 is a circuit for artificially adjusting the pulse width. The integration circuit 51 includes a resistor 51-1 and a capacitor 51-2. The pulse width artificial adjustment circuit 52 includes a DC cutoff capacitor 52-1 and a resistor 52-1.
2. It is composed of a variable resistor 52-3 and an inverter 52-4. The above components constitute the conventional pulse width adjusting circuit shown in FIG.

Further, reference numeral 53 denotes a laser diode driving circuit (denoted as an LD driving circuit in the figure), reference numeral 54 denotes a laser diode, reference numeral 55 denotes a photo diode for converting the back light of the laser diode into electricity again, Reference numeral 56 denotes a resistor for converting the current output from the photodiode 55 into a voltage, and reference numeral 57 denotes an automatic optical power control circuit.
It is often abbreviated as PC circuit. ).

The output of the pulse width adjustment circuit in FIG.
That is, the output of the inverter 52-4 is supplied to the laser diode driving circuit 53, and the laser diode 54
Is driven to convert an electric signal into an optical signal.

Light, which is usually called back light, which is a part of the output light of the laser diode 54, is supplied to the photodiode 55, is again converted into electricity, and is converted into a voltage by the resistor 56.

The signal converted by the resistor 56 is led to the automatic optical power control circuit 57, and after the average value or the peak is detected, a voltage having a difference from the reference voltage is generated. The laser diode 5 by controlling the bias current of the diode drive circuit 53;
The power of the optical output of No. 4 is kept constant.

[0023]

In the conventional pulse width adjusting circuit shown in FIG. 14, the level of the waveform input to the inverter 52-4 is artificially adjusted by the variable resistor 52-3, and The pulse width is artificially adjusted in relation to the threshold value unique to the inverter 52-4. That is, in the configuration of FIG. 14, a variable resistor is an essential component.

However, since the shape of the variable resistor is large and the variable mechanism is not suitable for an integrated circuit, the shape of the artificial adjustment circuit shown in FIG. 14 becomes large. Further, since the above-described artificial adjustment work is required, the pulse width adjustment circuit of FIG. 14 increases the number of artificial adjustment steps and increases the price of the pulse width adjustment circuit.

Similarly, in the electric / optical conversion circuit shown in FIG. 15, the circuit size is increased and the price is increased.

In view of the above problems, the present invention employs a small and inexpensive pulse width control circuit that outputs a signal with a constant duty ratio even when an input signal with a varied duty ratio is received, and applies the above-described pulse width control technology. It is an object of the present invention to provide an electric-optical conversion circuit that performs the following.

[0027]

According to the basic structure of the pulse width control circuit of the present invention, an input signal is passed through a low-pass filter to convert a pulse waveform from a pulse waveform to a waveform whose level gradually increases / decreases, and the level gradually increases. / Complementary Metal-Oxide Semiconductor Non-Inver
tor), the output of the CMOS non-inverter is supplied to an automatic level control circuit, and the voltage obtained by detecting the average value of the output of the automatic level control circuit is supplied to the non-inverting input terminal of a non-inverting compression amplifier. A voltage which is 1/2 of the output of the non-inverting compression amplifier is supplied to the inverting input terminal of the inverting compression amplifier as a reference voltage.
In this configuration, the power is supplied as the power supply voltage of the S non-inverter.

According to the basic configuration of the pulse width control circuit of the present invention, when the duty ratio of the input signal fluctuates, the fluctuation of the pulse width of the input signal is suppressed by the following operation.

Here, the description will be made on the assumption that the pulse width of the input signal becomes large. When the pulse field of the input signal increases, at this moment, the power supply voltage of the CMOS non-inverter is the voltage before the pulse width fluctuates, and the threshold is also the threshold before the pulse width fluctuates.・
The width of the output pulse of the inverter increases.

Therefore, the width of the output pulse of the automatic level control circuit also increases, and the output of the average value detection circuit also increases.

Since the output of the average value detection circuit is supplied to the non-inverting input terminal of the non-inverting compression amplifier, the output voltage of the non-inverting compression amplifier also increases.

The output voltage of the non-inverting compression amplifier is
Since the power supply voltage is supplied to the S non-inverter, the identification threshold value of the CMOS non-inverter also increases,
The width of the output pulse of the CMOS non-inverter is reduced.

Therefore, the width of the output pulse of the automatic level control circuit also becomes narrow. Since the output of the CMOS non-inverter is controlled to have a constant amplitude by the automatic level control circuit, the output of the automatic level control circuit whose average value is detected decreases.

Accordingly, control is performed so that the output voltage of the non-inverting compression amplifier decreases, the identification threshold value of the CMOS non-inverter decreases, and the width of the output pulse of the CMOS non-inverter increases.

Further, the output voltage of the non-inverting compression amplifier is 1
/ 2 is supplied as a reference voltage to the inverting input terminal of the non-inverting compression amplifier.
Is controlled so that finally matches.

That is, in the CMOS non-inverter, the discrimination threshold is 電源 of the power supply voltage, but control is performed so that the discrimination threshold is equal to the average value of the signal. This indicates that the fluctuation of the pulse width of the signal is suppressed.

The above description has been made on the assumption that the pulse width of the input signal is widened. However, even if the pulse width of the input signal is narrowed, the fluctuation of the pulse width is similarly suppressed.

As described above, even if the pulse width of the input signal fluctuates, the fluctuation of the pulse width is suppressed in the output signal.

Further, in the control of the pulse width, no artificial adjustment of a variable element such as a variable resistor is required. Therefore, a small and inexpensive pulse width control circuit can be obtained.

Also, the size and cost of an electric / optical conversion circuit in which the above-mentioned pulse width control circuit is applied to an input circuit can be reduced.

[0041]

FIG. 1 shows a first embodiment of the present invention.

In FIG. 1, 1 is a low-pass filter, 2 is a CMOS non-inverter, 3 is an automatic level control circuit,
4 is an average value detection circuit, 5 is a voltage dividing circuit, and 6 is a non-inverting compression amplifier.

Further, the CMOS non-inverter 2 has P
-CH type MOS transistor 2-1, N-CH type MOS
Transistor 2-2, P-CH type MOS transistor 2
-3 and an N-CH type MOS transistor 2-4, and the voltage dividing circuit 5 is constituted by a resistor 5-1 and a resistor 5-2.

Further, the configuration of the average value detection circuit 4 is shown in FIG.
As shown in FIG. 1, a circuit having a resistor in the series branch and a capacitor in the parallel branch may be used. If the time constant is set longer than the time that defines the mark ratio of the signal, a correct average value of the signal can be obtained even if the microscopic ratio between the mark and the space fluctuates.

In the configuration shown in FIG. 1, an input signal is passed through the low-pass filter 1 to convert a pulse waveform from a pulse waveform into a waveform in which a high-frequency component whose level is gradually increased / decreased is attenuated. The output of the device 1 is the CMOS non-inverter (Comp
lementary Metal-Oxide Semiconductor Non-Invertor)
2, the output of the CMOS non-inverter 2 is supplied to the automatic level control circuit 3, and the output of the automatic level control circuit 3 is detected by the average value detection circuit 4 as an average value. 6 is supplied to a non-inverting input terminal of the non-inverting compression amplifier 6, and a voltage of 1/2 of the output of the non-inverting compression amplifier 6 is supplied to the inverting input terminal of the non-inverting compression amplifier 6 as a reference voltage. CMOS non-
It is supplied as the power supply voltage of the inverter 2. Then, the output of the automatic level control circuit 3 is used as the output of the pulse width control circuit.

FIG. 2 is a diagram for explaining the operation of the configuration of FIG. 1. FIG. 2A shows the input of the low-pass filter, FIG. 2B shows the output of the CMOS non-inverter, and FIG. (C) shows the output of the automatic level control circuit.

Hereinafter, the operation of the configuration shown in FIG. 1 will be described with reference to FIGS.

In FIG. 2A, a signal indicated by a thin solid line is a signal having a normal pulse width, and a signal indicated by a thick solid line is a signal having a wide pulse width. Here, it is assumed that the signal indicated by the thick solid line in FIG. 2A is input to the low-pass filter 1 in FIG.

FIG. 2B shows the output of the low-pass filter 1 when the signal indicated by the thick solid line in FIG.
The waveform has a high-frequency component suppressed corresponding to the characteristics of the low-pass filter 1. If the low-pass filter 1 is constituted by an integrating circuit as shown in FIG.
The rising waveform in (b) is an exponential function for increasing the amplitude by the charging time constant of the integrating circuit, and the falling waveform is an exponential function for decreasing the amplitude by the discharging time constant of the integrating circuit.

The waveform shown in FIG.
Input to the inverter 2. The identification threshold of the CMOS non-inverter 2 is equal to one half of the power supply voltage supplied at this moment. Assuming that this is equal to the threshold value 1 in FIG. 2B, the output of the CMOS non-inverter 2 becomes a logical level "1" when the amplitude of the waveform in FIG. When the amplitude of the waveform 2 (b) is smaller than the threshold value 1, the waveform becomes a logical level “0”. Since this is supplied to the CMOS non-inverter 2 of FIG. 1, the pulse width of the output waveform of the CMOS non-inverter becomes wider than a predetermined value.

Since the output of the CMOS non-inverter 2 is supplied to the automatic level control circuit 3 of FIG. 1, the output of the automatic level control circuit 3 has a constant amplitude and a pulse width wider than the internal value. Becomes This is shown by a thick solid waveform in FIG.

The waveform indicated by the thick solid line in FIG. 2C is supplied to the average value detection circuit 4 in FIG. 1, so that the output of the average value detection circuit 4 rises.

Since the output of the average value detection circuit 4 is supplied to the non-inverting input terminal of the non-inverting compression amplifier 6 of FIG. 1, the output voltage of the non-inverting compression amplifier 6 also increases.

The output voltage of the non-inverting compression amplifier 6 is
It is supplied to the OS non-inverter 2 as a power supply voltage. Incidentally, since the identification threshold value of the CMOS non-inverter 2 is １ ／ of the power supply voltage supplied to the CMOS non-inverter 2, the identification threshold value of the CMOS non-inverter 2 also increases, and 2, the width of the output pulse becomes narrow.

Therefore, the width of the output pulse of the automatic level control circuit 3 also becomes narrow. This is shown by a thin solid line waveform in FIG.

Incidentally, the CMOS non-inverter 2
Is controlled to have a constant amplitude by the automatic level control circuit 3, so that the average value of the output of the automatic level control circuit 3 detected by the average value detection circuit 4 in FIG.

Therefore, the output voltage of the non-inverting compression amplifier 6 is reduced, the discrimination threshold of the CMOS non-inverter 2 is also reduced, and control is performed so that the width of the output pulse of the CMOS non-inverter 2 is widened.

Further, since half of the output voltage of the non-inverting compression amplifier 6 is supplied to the inverting input terminal of the non-inverting compression amplifier 6 as a reference voltage, the output of the average value detecting circuit 4 and the non-inverting Control is performed so that 1/2 of the output voltage of the inverting compression amplifier 6 finally matches.

That is, control is performed so that the identification threshold value of the CMOS non-inverter 2 is equal to the average value of the signal. This indicates that the fluctuation in the direction in which the pulse width of the signal is expanded is suppressed.

The above description has been made on the assumption that the pulse width of the input signal is wide. However, even if the pulse width of the input signal becomes narrow, the fluctuation of the pulse width is similarly suppressed.

As described above, even if the pulse width of the input signal fluctuates, the fluctuation of the pulse width is suppressed in the output signal.

Further, in the control of the pulse width, no artificial adjustment of a variable element such as a variable resistor is required. Therefore, a small and inexpensive pulse width control circuit can be obtained.

FIG. 3 shows a second embodiment of the present invention.

In FIG. 3, 1 is a low-pass filter, 2 is a CMOS non-inverter, 3 is an automatic level control circuit,
4 is an average value detection circuit, 6 is a non-inverting compression amplifier, 7 is a peak detection circuit, and 8 is a DC cutoff capacitor.

The CMOS non-inverter 2 has a P
-CH type MOS transistor 2-1, N-CH type MOS
Transistor 2-2, P-CH type MOS transistor 2
-3 and an N-CH type MOS transistor 2-4.

Further, the configuration of the average value detection circuit 4 is shown in FIG.
As shown in FIG. 1, a circuit having a resistor in the series branch and a capacitor in the parallel branch may be used. If the time constant is set longer than the time that defines the mark ratio of the signal, a correct average value of the signal can be obtained even if the microscopic ratio between the mark and the space fluctuates.

The configuration of the peak detection circuit 7 is shown in FIG.
As shown in the above, a circuit having a diode in the series branch and a capacitor in the parallel branch may be used.

In the configuration of FIG. 3, an input signal is passed through the low-pass filter 1 to convert a pulse waveform into a waveform in which high-frequency components are attenuated, and the output of the low-pass filter 1 is applied to the low-pass filter 1. C
The CMOS non-inverter 2 is supplied to the
The output of the inverter 2 is supplied to the automatic level control circuit 3, the output of the automatic level control circuit 3 is divided into two, and one is supplied to the average value detection circuit 4 and the other is supplied to the DC cutoff capacitor 8. The output of the average value detection circuit 4 is supplied to a non-inverting input terminal of the non-inverting compression amplifier 6, and the output of the peak detecting circuit 7 is supplied to an inverting input terminal of the non-inverting compression amplifier 6. And the output of the non-inverting compression amplifier 6 is supplied to the CMOS non-inverter 2 as a power supply voltage.

Here, the description will be made on the assumption that the pulse width of the input signal is widened.

When the input signal passes through the low-pass filter 1, the high-frequency component is attenuated and converted into a waveform whose level gradually increases / decreases. This waveform is identified by the identification threshold of the CMOS non-inverter 2 and returned to a pulse waveform.

Now, it is assumed that the pulse width of the input signal is widened, so that the pulse width at the output of the CMOS non-inverter 2 is also widened. Wider.

Since the output of the automatic level control circuit 3 is supplied to the average value detection circuit 4, the output of the average value detection circuit 4 rises, and the output of the non-inverting compression amplifier 6 also rises.

Accordingly, the identification threshold value of the CMOS non-inverter 2 rises, so that the pulse width of the output waveform of the CMOS non-inverter 2 changes in a narrowing direction.

Therefore, the average value of the output of the automatic level control circuit 3 decreases, and the output of the non-inverting compression amplifier 6 also changes in the decreasing direction.
Is reduced.

As a result, the pulse width of the output waveform of the CMOS non-inverter is controlled to be increased.

Further, a signal obtained by cutting off the direct current of the output of the automatic level control circuit 3 is supplied to the peak detection circuit 7.
Therefore, the output of the peak detection circuit 7 is a voltage that is １ ／ of the output amplitude of the automatic level control circuit 4.

That is, control is performed so that the identification threshold value of the CMOS non-inverter 2 and the average value of the signals become equal. This indicates that the fluctuation in the direction in which the pulse width of the signal is expanded is suppressed.

The above description has been made on the assumption that the pulse width of the input signal is wide. However, even if the pulse width of the input signal becomes narrow, the fluctuation of the pulse width is similarly suppressed.

As described above, even if the pulse width of the input signal fluctuates, the fluctuation of the pulse width is suppressed in the output signal.

Further, in the control of the pulse width, no artificial adjustment of a variable element such as a variable resistor is required. Therefore, a small and inexpensive pulse width control circuit can be obtained.

FIG. 4 shows a third embodiment of the present invention.

In FIG. 4, 1 is a low-pass filter, 2 is a CMOS non-inverter, 3 is an automatic level control circuit,
Reference numeral 4 denotes an average value detection circuit, 5 denotes a voltage dividing circuit, 6 denotes a non-inverting compression amplifier, 8 denotes a DC cutoff capacitor, and 9 denotes a second average value detection circuit.

The CMOS non-inverter 2 has a P
-CH type MOS transistor 2-1, N-CH type MOS
Transistor 2-2, P-CH type MOS transistor 2
-3 and an N-CH type MOS transistor 2-4, and the voltage dividing circuit 5 is constituted by a resistor 5-1 and a resistor 5-2.

Further, as shown in FIG. 11, the average value detection circuit 4 and the second average value detection circuit 9 may be constituted by a circuit having a resistor in the series branch and a capacitor in the parallel branch. If the time constant is set longer than the time that defines the mark ratio of the signal, a correct average value of the signal can be obtained even if the microscopic ratio between the mark and the space fluctuates.

In the configuration of FIG. 4, an input signal is passed through the low-pass filter 1 to convert a pulse waveform from a pulse waveform to a waveform in which high-frequency components are attenuated, and the output of the low-pass filter 1 is applied to the low-pass filter 1. C
The CMOS non-inverter 2 is supplied to the
The output of the inverter 2 is supplied to the automatic level control circuit 3, the output of the automatic level control circuit 3 is divided into two, and one is supplied to the average value detection circuit 4, and the other is connected to the DC cutoff capacitor 8. The second average value is supplied to the second average value detection circuit 9 via the voltage dividing circuit 5, and the output of the average value detection circuit 4 is supplied to the non-inversion input terminal of the non-inversion compression amplifier 6. The output of the detection circuit 9 is supplied to the inverting input terminal of the non-inverting compression amplifier 6, and the output of the non-inverting compression amplifier 6 is supplied to the CM.
The power is supplied to the OS non-inverter 2 as a power supply voltage and also to one end of the voltage dividing circuit 5.

Here, the description will be made on the assumption that the pulse width of the input signal is widened.

When the input signal passes through the low-pass filter 1, the high-frequency component is attenuated and converted into a waveform whose level gradually increases / decreases. This waveform is identified by the identification threshold of the CMOS non-inverter 2 and returned to a pulse waveform.

Now, it is assumed that the pulse width of the input signal is widened, so that the pulse width at the output of the CMOS non-inverter 2 is also widened. Wider.

Since the output of the automatic level control circuit 3 is supplied to the average value detection circuit 4, the output of the average value detection circuit 4 increases, and the output of the non-inverting compression amplifier 6 also increases.

As the identification threshold value of the CMOS non-inverter 2 increases, the pulse width of the output waveform of the CMOS non-inverter 2 changes in a narrowing direction.

Therefore, the average value of the output of the automatic level control circuit 3 decreases, and the output of the non-inverting compression amplifier 6 also changes in the decreasing direction.
Is reduced.

As a result, the pulse width of the output waveform of the CMOS non-inverter 2 is controlled to be increased.

Further, a signal obtained by superimposing a voltage obtained by dividing the output of the non-inverting compression amplifier 6 by the voltage dividing circuit 5 on a signal from which the direct current is cut off from the output of the automatic level control circuit 3 is used to detect the second average value. It is supplied to the circuit 9. Accordingly, the output of the second average value detection circuit 9 is equal to one of the output amplitude of the non-inverting compression amplifier 6.
/ 2 voltage.

That is, control is performed so that the identification threshold value of the CMOS non-inverter 2 is equal to the average value of the signal. This indicates that the fluctuation in the direction in which the pulse width of the signal is expanded is suppressed.

Although the above description has been made on the assumption that the pulse width of the input signal is wide, the fluctuation of the pulse width is similarly suppressed even if the pulse width of the input signal becomes narrow.

As described above, even if the pulse width of the input signal fluctuates, the fluctuation of the pulse width is suppressed in the output signal.

Further, in the control of the pulse width, no artificial adjustment of a variable element such as a variable resistor is required. Therefore, a small and inexpensive pulse width control circuit can be obtained.

Also in the configuration of FIG. 4, the output of the second average value detection circuit 9 is equal to one half of the output of the non-inverting compression amplifier 6, so that the operation is basically the same as that of the configuration of FIG. However, even when the characteristics of the average value detection circuit 4 and the second average value detection circuit 9 have errors from the characteristics of the ideal average value detection circuit, those errors can be canceled. .

FIG. 5 is a modification of the first embodiment of the present invention.

In FIG. 5, 1 is a low-pass filter, 2a
Is a CMOS inverter, 3 is an automatic level control circuit, 4 is an average value detecting circuit, 5 is a voltage dividing circuit, 6 is a non-inverting compression amplifier, 7 is a peak detecting circuit, 16 is an absolute voltage gain on both inverting and non-inverting sides. This is a differential amplifier having a value of 1.

The CMOS inverter 2a has a PC
The voltage dividing circuit 5 includes an H-type MOS transistor 2-1 and an N-CH type MOS transistor 2-2. The voltage dividing circuit 5 includes a resistor 5-1 and a resistor 5-2.

Further, the configuration of the average value detection circuit 4 is shown in FIG.
As shown in FIG. 1, a circuit having a resistor in the series branch and a capacitor in the parallel branch may be used. If the time constant is set longer than the time that defines the mark ratio of the signal, a correct average value of the signal can be obtained even if the microscopic ratio between the mark and the space fluctuates.

The configuration of the peak detection circuit 7 is shown in FIG.
As shown in the above, a circuit having a diode in the series branch and a capacitor in the parallel branch may be used.

The differential amplifier 16 in which the absolute value of the voltage gain is 1 on both the inverting side and the non-inverting side forms a voltage follower by an operational amplifier, and 1 / is connected to the non-inverting input terminal side of the voltage follower. This can be realized by connecting a two-divider circuit.

In the configuration shown in FIG. 5, the input signal is passed through the low-pass filter 1 to convert the pulse waveform from a pulse waveform into a waveform in which the level in which the high-frequency component is attenuated gradually increases / decreases. Output of the CMOS inverter (Complement)
ary Metal-Oxide Semiconductor Invertor) 2a, the output of the CMOS inverter 2a is supplied to the automatic level control circuit 3, and the output of the automatic level control circuit 3 is averaged by the average value detection circuit 4. A peak is detected by the peak detection circuit 7, and an output of the average value detection circuit 4 is supplied to an inverting input terminal of the differential amplifier 16,
An output of the peak detection circuit is supplied to a non-inverting input terminal of the differential amplifier, an output of the differential amplifier 16 is supplied to a non-inverting input terminal of the non-inverting compression amplifier 6, and an inverting input terminal of the non-inverting compression amplifier 6 is supplied. The voltage dividing circuit 5 supplies a voltage of 1/2 of the output of the non-inverting compression amplifier 6 to the terminal as a reference voltage, and supplies the output of the non-judgmenting compression amplifier 6 as a power supply voltage of the CMOS inverter 2a. Then, the output of the automatic level control circuit 3 is used as the output of the pulse width control circuit.

When the output of the low-pass filter 1 is supplied to the CMOS inverter 2a, the output of the average detection circuit 4 decreases as the duty ratio of the input signal increases.

When the output of the average value circuit 4 is supplied directly to the non-inverting input terminal of the non-inverting compression amplifier 6, the threshold value of the CMOS inverter 2a decreases, and the output of the average value detecting circuit further decreases, and the signal It is not possible to control the duty ratio to return to the original.

The above control can be performed when the power supply voltage of the CMOS inverter can be increased when the duty ratio of the input signal is increased. At first glance, it seems that the polarity of the compression amplifier should be reversed.

However, if the polarity of the compression amplifier is simply reversed, positive feedback is applied to the compression amplifier by the voltage dividing circuit 5, making it impossible to obtain a stable operation.

Therefore, the peak detection circuit 7 and the differential amplifier 16 are provided to generate a voltage obtained by subtracting the output of the average value detection circuit 4 from the output of the peak detection circuit 7 to generate the voltage of the ratio inversion compression amplifier. 6, the same voltage as that supplied to the ratio inversion input terminal of the ratio inversion compression amplifier 6 can be supplied when the duty ratio of the input voltage is increased in the configuration of FIG. It is possible to control the duty ratio of the signal.

Therefore, although the configuration for controlling the duty ratio of a signal using a CMOS non-inverter has been shown in FIG. 1, the same can be achieved by using a CMOS inverter.

That is, the techniques shown in FIGS. 1 and 5 essentially detect a CMOS gate for identifying a signal waveform in which the high-frequency component of the input signal waveform is attenuated, and detect an average value of the output waveform of the CMOS gate. The average value detection circuit receives a voltage of one half of its own output at an inverting input terminal, receives a change in the output of the average value detection circuit at a non-inverting input terminal, and outputs the output to the CMO.
It can be said that the pulse width control circuit includes a non-inverting compression amplifier that supplies a power supply voltage to the S gate.

The technique shown in the configuration of FIG.
Needless to say, the present invention can be applied to the configuration of FIG.

Now, in the constructions of FIGS. 1, 3, 4 and 5, the output of the CMOS gate is supplied to the automatic level control circuit, and the output of the automatic level control circuit is averaged or detected. The configuration for supplying to the peak detection circuit has been described. However, the present invention is not limited to the above configuration, and the pulse width can be controlled by a configuration in which the output of the CMOS gate is directly supplied to the average value detection circuit or the peak detection circuit. This is clear when the operation of the pulse width control described above is confirmed for the above-described configuration, but it is daringly added that at the moment when the duty ratio of the input signal changes and the control operation of the duty ratio starts, the CMOS gate is operated. Is determined by the predetermined voltage supplied by the non-inverting compression amplifier 6, so that the average value detection circuit 4 can always detect a change in the average value of the output of the CMOS gate.

In the above configuration, since the logic level of the output of the CMOS gate can fluctuate depending on the input pulse width while the duty ratio is being controlled, the CMOS gate and the average value detection circuit or the peak value can be changed. It is preferable that an automatic level control circuit is arranged after a connection point with the detection circuit, and an output of the automatic level control circuit is used as an output of the pulse width control circuit.

FIG. 6 shows a fourth embodiment of the present invention.

In FIG. 6, 1 is a low-pass filter, 2 is a CMOS non-inverter, 3 is an automatic level control circuit,
5a is a voltage dividing circuit, and 10 is a buffer amplifier.

The CMOS non-inverter 2 has a P
-CH type MOS transistor 2-1, N-CH type MOS
Transistor 2-2, P-CH type MOS transistor 2
-3 and an N-CH type MOS transistor 2-4, and the voltage dividing circuit 5a includes a resistor 5-1 and a resistor 5-3 having a temperature characteristic.

In the configuration shown in FIG. 6, an input signal is passed through the low-pass filter 1 to convert a pulse waveform into a waveform in which high-frequency components are attenuated, and the output of the low-pass filter 1 is applied to the CMOS.
The voltage is supplied to the non-inverter 2, and the voltage having a temperature characteristic generated by the voltage dividing circuit 5a is supplied to the CMOS non-inverter 2 via the buffer amplifier 10 as a power supply voltage.

When the temperature characteristic of the pulse width of the input signal to the configuration shown in FIG. 6 has a positive coefficient, the variation of the pulse width is suppressed by applying a resistor having a positive temperature coefficient as the resistor 5-3. be able to.

The reason is that it is assumed that the temperature coefficient of the resistor 5-3 is positive.
The power supply voltage supplied to the OS non-inverter 2 increases, and accordingly, the identification threshold of the CMOS non-inverter 2 also increases. As a result, the pulse width of the output of the CMOS non-inverter 2 becomes narrower, and the pulse width of the input signal is suppressed from expanding.

When the temperature decreases, the power supply voltage supplied to the CMOS non-inverter 2 also decreases, and accordingly, the identification threshold of the CMOS non-inverter 2 also decreases. As a result, the pulse width at the output of the CMOS non-inverter 2 becomes wide, and the narrowing of the pulse width of the input signal can be suppressed.

Conversely, in the case where the temperature characteristic of the pulse width of the input signal to the configuration of FIG. 6 has a negative coefficient, if a resistor having a negative temperature coefficient is applied as the resistor 5-3, the pulse width variation may occur. Can be suppressed.

The reason is that the temperature coefficient of the resistor 5-3 is assumed to be negative.
The power supply voltage supplied to the OS non-inverter 2 decreases, and accordingly, the identification threshold of the CMOS non-inverter 2 also decreases. As a result, the pulse width at the output of the CMOS non-inverter 2 is increased, and the narrowing of the pulse width of the input signal is suppressed.

When the temperature decreases, the power supply voltage supplied to the CMOS non-inverter 2 increases, and accordingly, the identification threshold value of the CMOS non-inverter 2 also increases. As a result, the pulse width at the output of the CMOS non-inverter 2 becomes narrow, and the spread of the pulse width of the input signal can be suppressed.

As described above, even if the pulse width of the input signal has a temperature fluctuation, the fluctuation of the pulse width is suppressed in the output signal.

Further, in the control of the pulse width, no artificial adjustment of a variable element such as a variable resistor is required. Therefore, a small and inexpensive pulse width control circuit can be obtained.

The advantage of the configuration shown in FIG.
An advantage is that the circuit configuration is simplified with a forward type pulse width control circuit.

Note that if a voltage having a temperature coefficient is generated by a circuit combining a plurality of resistors having a temperature coefficient instead of a simple voltage dividing circuit as shown in FIG. 6, the accuracy of pulse width control can be improved.

FIG. 7 shows a modification of the fourth embodiment of the present invention.

In FIG. 7, 1 is a low-pass filter, 2a
Is a CMOS inverter, 3 is an automatic level control circuit, 5a
Is a voltage dividing circuit, and 10 is a buffer amplifier.

The CMOS inverter 2a has a PC
The voltage dividing circuit 5a includes an H-type MOS transistor 2-1 and an N-CH type MOS transistor 2-2. The voltage dividing circuit 5a includes a resistor 5-1 and a resistor 5-3 having a temperature characteristic.

In the configuration of FIG. 7, the input signal is passed through the low-pass filter 1 to convert a pulse waveform into a waveform in which high-frequency components are attenuated, and the output of the low-pass filter 1 is applied to the CMOS.
The voltage having a temperature characteristic, which is supplied to the inverter 2a and burned out by the voltage dividing circuit 5a, is supplied to the CM through the buffer amplifier 10.
It is supplied as a power supply voltage to the OS inverter 2a.

When the temperature characteristic of the pulse width of the input signal to the configuration of FIG. 7 has a positive coefficient, the variation of the pulse width is suppressed by applying a resistor having a positive temperature coefficient as the resistor 5-3. be able to.

The reason is that it is assumed that the temperature coefficient of the resistor 5-3 is positive.
The power supply voltage supplied to the OS inverter 2a increases, and accordingly, the identification threshold of the CMOS inverter 2a also increases. As a result, the pulse width at the output of the CMOS inverter 2a becomes narrow, and the expansion of the pulse width of the input signal is suppressed.

When the temperature decreases, the power supply voltage supplied to the CMOS inverter 2a also decreases, and accordingly, the identification threshold of the CMOS inverter 2a also decreases. As a result, the pulse width at the output of the CMOS inverter 2a is widened, and the narrowing of the pulse width of the input signal can be suppressed.

Conversely, in the case where the temperature characteristic of the pulse width of the input signal to the configuration of FIG. 7 has a negative coefficient, if a resistor having a negative temperature coefficient is applied as the resistor 5-3, the pulse width variation may occur. Can be suppressed.

Since it is assumed that the temperature coefficient of the resistor 5-3 is negative, when the temperature rises, the CM
The power supply voltage supplied to the OS inverter 2a decreases, and accordingly, the identification threshold of the CMOS inverter 2a also decreases. As a result, the pulse width at the output of the CMOS inverter 2a is widened, and the narrowing of the pulse width of the input signal is suppressed.

When the temperature decreases, the power supply voltage supplied to the CMOS inverter 2a increases, and accordingly, the identification threshold of the CMOS inverter 2a also increases. As a result, the pulse width at the output of the CMOS inverter 2a becomes narrow, and the spread of the pulse width of the input signal can be suppressed.

As described above, even if the pulse width of the input signal has a temperature fluctuation, the fluctuation of the pulse width is suppressed in the output signal.

Further, in the control of the pulse width, no artificial adjustment of a variable element such as a variable resistor is required. Therefore, a small and inexpensive pulse width control circuit can be obtained.

The advantage of the configuration shown in FIG.
An advantage is that the circuit configuration is simplified with a forward type pulse width control circuit.

If a voltage having a temperature coefficient is generated by a circuit combining a plurality of resistors having a temperature coefficient instead of a simple voltage dividing circuit as shown in FIG. 7, the accuracy of pulse width control can be improved.

The configuration shown in FIG. 6 and the configuration shown in FIG.
The difference between the S non-inverter and the CMOS inverter is that only the positive and negative of the temperature coefficient of the resistor having the temperature coefficient are different.
The configuration is essentially the same. That is, the configuration of FIGS. 6 and 7 is a pulse width control circuit that receives a voltage having a temperature coefficient as a power supply voltage and controls a pulse width by a CMOS gate that identifies a waveform in which a high-frequency component of an input signal waveform is attenuated. It can be said that there is.

FIG. 8 shows a fifth embodiment of the present invention, which shows a configuration of an electrical / optical conversion circuit obtained by combining the pulse width control circuit having the configuration of FIG. 1 and an electrical / optical conversion circuit.

In FIG. 8, 1 is a low-pass filter, 2 is a CMOS non-inverter, 3 is an automatic level control circuit,
4 is an average value detection circuit, 5 is a voltage dividing circuit, and 6 is a non-inverting compression amplifier.

The CMOS non-inverter 2 has a P
-CH type MOS transistor 2-1, N-CH type MOS
Transistor 2-2, P-CH type MOS transistor 2
-3 and an N-CH type MOS transistor 2-4, and the voltage dividing circuit 5 is constituted by a resistor 5-1 and a resistor 5-2.

Further, the configuration of the average value detection circuit 4 is shown in FIG.
As shown in FIG. 1, a circuit having a resistor in the series branch and a capacitor in the parallel branch may be used. If the time constant is set longer than the time that defines the mark ratio of the signal, a correct average value of the signal can be obtained even if the microscopic ratio between the mark and the space fluctuates.

The above components constitute the pulse width control circuit shown in FIG.

Next, reference numeral 11 denotes a laser diode drive circuit (in the figure, this is referred to as an LD drive circuit; the same applies hereinafter), reference numeral 12 denotes a laser diode for converting an electric signal into an optical signal, and reference numeral 13 denotes the laser diode. Photodiode which receives back light which is a part of output light of laser diode 12 and converts it again, 14 is a resistor which converts the output current of photodiode 13 into voltage, and 15 is the output of laser diode 12 This is an automatic optical power control circuit for controlling the optical power.

Note that the automatic optical power control circuit 15
As shown in FIG. 3, an average value detection circuit or a peak detection circuit for converting a voltage obtained by voltage-converting a current generated by photo-electric conversion by the photodiode PD into a direct current, and the average value detection circuit or the peak detection circuit The voltage V _REF output in the reference state is received at the non-inverting input terminal, the output of the average value detecting circuit or the peak detecting circuit is received at the inverting input terminal, and the output is output from the laser diode driving circuit (LD driving circuit in FIG. ) May be provided by an inverting compression amplifier that supplies the signal.

In the configuration shown in FIG. 8, a signal whose pulse width is controlled by the configuration shown in FIG. 1 is supplied to the laser diode driving circuit 11 to perform automatic light power control on the laser diode.
The light is converted into an optical signal by the diode 12.

Therefore, the pulse width of the output light of the laser diode 12 is also controlled, and it is possible to prevent the fluctuation of the pulse width from being transmitted to the subsequent circuit as it is.

Further, in the control of the pulse width, it is not necessary to manually adjust a variable element such as a variable resistor. Therefore, it is possible to obtain a small and inexpensive electric / optical conversion circuit.

In FIG. 8, the electric / optical conversion circuit in which the pulse width control circuit of FIG. 1 and the electric / optical conversion circuit are combined has been described. This combination is equivalent to the pulse width control circuit of FIG. It goes without saying that a light conversion circuit is also possible.

FIG. 9 shows a sixth embodiment of the present invention.

In FIG. 9, 1 is a low-pass filter, 2 is a CMOS non-inverter, 6 is a non-inverting compression amplifier, 7
Is a peak detection circuit, 11 is a laser diode drive circuit, 12 is a laser diode, 13 is a photodiode, 14 is a resistor, and 15 is an automatic optical power control circuit.

The CMOS non-inverter 2 has a P
-CH type MOS transistor 2-1, N-CH type MOS
Transistor 2-2, P-CH type MOS transistor 2
-3, an N-CH type MOS transistor 2-4.

Further, the configuration of the peak detection circuit 7 is shown in FIG.
As shown in FIG. 2, a circuit having a diode in the series branch and a capacitor in the parallel branch may be used.

In the configuration of FIG. 9, an input signal is passed through the low-pass filter 1 to convert a pulse waveform into a waveform in which high-frequency components are attenuated, and the output of the low-pass filter 1 is applied to the CMOS.
The output of the CMOS non-inverter 2 is supplied to the non-inverter 2, and the output of the CMOS non-inverter 2 is supplied to the laser diode drive circuit 11. The laser diode 12 is driven to convert an electric signal into an optical signal. And the laser diode 12
The back light, which is a part of the output light, is received by the photodiode 13 and converted into electricity, and the resistor 14 converts the voltage.

The terminal voltage of the resistor 14 is supplied to the automatic optical power control circuit 15 to control the output light level of the laser diode 12 at a constant level. The resistance 1
4 is supplied to the peak detection circuit 7 and the output of the peak detection circuit 7 is supplied to the inverting input terminal of the non-inverting compression amplifier 6 to which the reference voltage _VREF is supplied to the inverting input terminal. And the output of the non-inverting compression amplifier 6 is
It is supplied to the MOS non-inverter 2 as a power supply voltage.

Now, the operation of the configuration shown in FIG. 9 will be described assuming that the pulse width of the input signal has become wide.

As the pulse width of the input signal increases, the pulse width of the signal whose high frequency component has been attenuated by the CMOS non-inverter 2 increases. With this signal, the laser diode drive circuit 11 drives the laser diode 12 that has been subjected to the automatic optical power control.
The pulse amplitude of the output light of the laser diode 12 decreases.

Accordingly, since the terminal voltage of the resistor 14 also decreases, the non-inverting compression amplifier 6 supplies a low power supply voltage to the CMOS non-inverter 2. Since the power supply voltage is reduced, the identification threshold value of the CMOS non-inverter 2 is also reduced, and control is performed so that the pulse width of the CMOS inverter 2a is reduced.

The non-inverting input of the non-inverting compression amplifier 6
Reference voltage V supplied to the input terminal _REFAnd the peak detection
The control works so that the output voltages of the circuit 7 become equal, and FIG.
The level of each part of the configuration becomes stable.

Then, even if the pulse width of the input signal is narrowed, control is similarly performed to suppress the narrowing of the pulse width.

As described above, the pulse width of the output light can be kept constant even if the pulse width of the input signal fluctuates by the configuration of FIG.

Further, in the control of the pulse width, it is not necessary to artificially adjust a variable element such as a variable resistor. Therefore, it is possible to obtain a small and inexpensive electric / optical conversion circuit.

An advantage of the configuration shown in FIG. 9 is that since a circuit for performing electrical / optical conversion is included in a loop for performing pulse width control, there is an individual difference in the threshold value of the output characteristic of the laser diode. In this case, the pulse width of the output light from the laser diode can be kept constant.

FIG. 10 is a modification of the sixth embodiment of the present invention.

In FIG. 10, 1 is a low-pass filter, 2
a is a CMOS inverter, 6a is an inverting compression amplifier, 7 is a peak detection circuit, 11 is a laser diode drive circuit,
Reference numeral 12 denotes a laser diode for converting an electric signal into an optical signal, reference numeral 13 denotes a photo diode for receiving back light which is a part of output light of the laser diode 12, and converting the light again, and reference numeral 14 denotes a photo diode for the photo diode 13. A resistance 15 for converting the output current into a voltage is an automatic optical power control circuit for controlling the power of the output light of the laser diode 12.

The CMOS inverter 2a has a PC
It is composed of an H-type MOS transistor 2-1 and an N-CH type MOS transistor 2-2.

Further, the configuration of the peak detection circuit 7 is shown in FIG.
As shown in FIG. 2, a circuit having a diode in the series branch and a capacitor in the parallel branch may be used.

Finally, the automatic optical power control circuit shown in FIG.
As described above, an average value detection circuit or a peak detection circuit, and a reference voltage output by the average value detection circuit or the peak detection circuit in a reference state is received at an inverting input terminal, and the output voltage of the average value detection circuit or the peak detection circuit is received. It is constituted by an inverting compression amplifier received at a non-inverting input terminal, and configured to control a bias current of the laser diode driving circuit by an output voltage of the inverting compression amplifier.

In the configuration shown in FIG. 10, the input signal is passed through the low-pass filter 1 to be converted into a signal in which high-frequency components are suppressed.
An output signal of the low-pass filter 1 is supplied to the CMOS inverter 2a, an output of the CMOS inverter 2a is supplied to the laser diode driving circuit 11, and an electric signal is converted into an optical signal by the laser diode 12. Convert.

The back light, which is a part of the output light of the laser diode 12, is converted into an electric signal again by the photo diode 13 and converted into a voltage by the resistor 14.

The terminal voltage of the resistor 14 is divided into two, and one is supplied to the automatic optical power control circuit 15 to control the bias current of the laser diode drive circuit 11 to reduce the output power of the laser diode 12. Control to constant.

At the same time, the terminal voltage of the resistor 14 is supplied to the peak detection circuit 7, and the output voltage of the peak detection circuit 7 is supplied as the power supply voltage of the CMOS inverter 2a.

Now, it is assumed that the pulse width of the input electric signal is widened. At this time, the pulse width of the output signal of the CMOS inverter 2a becomes narrow, and this signal is supplied to the laser diode drive circuit 11 to drive the laser diode 12.

Since the laser diode 12 is subjected to automatic optical power control, when the input pulse width of the laser diode drive circuit 11 becomes narrow, the power of the output light from the laser diode 12 is kept constant. Therefore, control is performed in a direction in which the amplitude of the output light of the laser diode 12 is increased.

Therefore, the output voltage of the peak detection circuit 7 also changes in a rising direction. This voltage is supplied to the non-inverting input terminal of the inverting compression amplifier 6a.
Since the output of the CMOS inverter 2a is supplied to the CMOS inverter 2a as a power supply voltage, the identification threshold of the CMOS inverter 2a also increases, and control is performed in the direction in which the pulse width of the output signal of the CMOS inverter 2a becomes narrow.

As described above, even if the pulse width of the input signal is widened, the spread of the pulse width of the output light from the laser diode 12 is suppressed.

Similarly, even if the pulse width of the input signal becomes narrow, the narrowing of the pulse width of the output light of the laser diode 12 is suppressed.

Therefore, even if the pulse width of the input signal fluctuates according to the configuration of FIG. 10, the fluctuation of the pulse width of the optical signal output from the laser diode is suppressed.

Further, in the control of the pulse width, no artificial adjustment of a variable element such as a variable resistor is required. Therefore, it is possible to obtain a small and inexpensive electric / optical conversion circuit.

The advantage of the configuration shown in FIG. 10 is that the threshold for the output characteristics of the laser diode has individual differences because the circuit for performing the electrical / optical conversion is included in the loop for performing the pulse width control. In this case, the pulse width of the output light from the laser diode can be kept constant.

The configuration shown in FIG. 9 and the configuration shown in FIG.
OS non-inverter and CMOS inverter are different,
Although the non-inverting compression amplifier and the inverting compression amplifier are different, they have essentially the same configuration. That is, the configuration of FIGS. 9 and 10 includes a CMOS gate for identifying a signal waveform obtained by attenuating a high-frequency component of an input signal waveform, a laser diode driving circuit receiving an output of the CMOS gate, and the laser diode driving circuit. A laser diode driven by the laser diode to convert an electric signal into an optical signal, a photo diode for electrically converting the back light of the laser diode, and a voltage obtained by converting the output current of the photo diode into a voltage. An automatic optical power control circuit for controlling the bias of the drive circuit to perform automatic optical power control on the laser diode; and detecting a peak value of a voltage obtained by converting the output current of the photodiode into a voltage, and detecting the peak value based on the detected peak value. A peak detection circuit for controlling a power supply voltage of the CMOS gate. It can be said that.

[0188]

As described above in detail, according to the present invention, it is possible to obtain a small and inexpensive pulse width control circuit which outputs a signal having a constant pulse width even when an input signal having a varied pulse width is received. A small and inexpensive electric / optical conversion circuit to which the width control technology is applied can be obtained.

[Brief description of the drawings]

FIG. 1 shows a first embodiment of the present invention.

FIG. 2 is a view for explaining the operation of the configuration of FIG. 1;

FIG. 3 shows a second embodiment of the present invention.

FIG. 4 shows a third embodiment of the present invention.

FIG. 5 is a modification of the first embodiment of the present invention.

FIG. 6 shows a fourth embodiment of the present invention.

FIG. 7 is a modification of the fourth embodiment of the present invention.

FIG. 8 shows a fifth embodiment of the present invention.

FIG. 9 shows a sixth embodiment of the present invention.

FIG. 10 is a modification of the sixth embodiment of the present invention.

FIG. 11 shows an example of an average value detection circuit.

FIG. 12 illustrates an example of a peak detection circuit.

FIG. 13 shows an example of an automatic optical power control circuit.

FIG. 14 shows an example of a conventional pulse width control circuit.

FIG. 15 shows an example of a conventional electric / optical conversion circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Low-pass filter (LPF) 2 CMOS non-inverter 2a CMOS inverter 2-1 P-CH type MOS transistor 2-2 N-CH type MOS transistor 2-3 P-CH type MOS transistor 2-4 N- CH type MOS transistor 3 Automatic level control circuit (ALC circuit) 4 Average value detecting circuit 5 Voltage dividing circuit 5a Voltage dividing circuit 5-1 Resistance 5-2 Resistance 5-3 Resistance having temperature characteristic 6 Non-inverting compression amplifier 6a Inverting compression Amplifier 7 Peak detection circuit 8 DC cut-off capacitor 9 Second average value detection circuit 10 Buffer amplifier 11 Laser diode drive circuit (LD drive circuit) 12 Laser diode 13 Photodiode 14 Resistance 15 Automatic optical power control circuit (APC circuit) ) 16 differential amplifier 50 buffer amplifier 51 integrating circuit 51-1 resistor 51 -2 Capacitor 52 Artificial adjustment circuit of pulse width 52-1 DC blocking capacitor 52-2 Resistance 52-3 Variable resistance 52-4 Inverter 53 Laser diode drive circuit (LD drive circuit) 54 Laser diode 55 Photo diode 56 resistor 57 automatic optical power control circuit (APC circuit)

Claims (6)

[Claims] A CMOS gate for identifying a signal waveform obtained by attenuating a high-frequency component of an input signal waveform; an average value detection circuit for detecting an average value of an output waveform of the CMOS gate; A non-inverting compression amplifier receiving a voltage at an inverting input terminal, receiving a change in the output of the average value detection circuit at a non-inverting input terminal, and supplying an output to the CMOS gate as a power supply voltage. Control circuit. 2. A CMOS gate for identifying a signal waveform obtained by attenuating a high-frequency component of an input signal waveform, an average value detection circuit for detecting an average value of an output waveform of the CMOS gate, and a DC component of an output of the CMOS gate. A peak detection circuit for detecting a peak value of a waveform obtained by cutting off the peak value, a change in the output of the average value detection circuit to a non-inverting input terminal, an output from the peak detecting circuit to an inverting input terminal, and an output to the CMOS gate. And a non-inverting compression amplifier for supplying a power supply voltage to the pulse width control circuit. 3. A CMOS gate for identifying a signal waveform obtained by attenuating a high-frequency component of an input signal waveform, an average value detection circuit for detecting an average value of an output waveform of the CMOS gate, and an output of the average value detection circuit. The non-inverting input terminal receives the change, supplies the output to the CMOS gate as a power supply voltage, and supplies the non-inverting compression amplifier to the 1/2 voltage dividing circuit. A second average value detection circuit for detecting an average value of a signal obtained by superimposing an output of the 1/2 voltage dividing circuit and supplying the average value to an inverting input terminal of the non-inverting compression amplifier. . 4. A pulse width control circuit comprising a CMOS gate for receiving a voltage having a temperature coefficient as a power supply voltage and identifying a signal waveform obtained by attenuating a high-frequency component of an input signal waveform. 5. The pulse width control circuit according to claim 1, a laser diode drive circuit receiving an output of the pulse width control circuit, and a laser diode drive circuit driven by the laser diode drive circuit. A laser diode for converting an electric signal to an optical signal, a photodiode for electrically converting the back light of the laser diode, and a bias for the laser diode driving circuit by a voltage obtained by converting the output current of the photodiode to a voltage An automatic optical power control circuit for controlling the laser diode to perform automatic optical power control on the laser diode. 6. A CMOS gate for identifying a signal waveform obtained by attenuating a high-frequency component of an input signal waveform, a laser diode driving circuit receiving an output of the CMOS gate, and an electric signal driven by the laser diode driving circuit. A laser diode that converts light into an optical signal, a photo diode that electrically converts back light of the laser diode, and a bias of the laser diode drive circuit controlled by a voltage obtained by converting the output current of the photo diode into a voltage. An automatic optical power control circuit for performing automatic optical power control on the laser diode; and detecting a peak value of a voltage obtained by converting the output current of the photo diode into a voltage, and determining a power supply voltage of the CMOS gate based on the detected peak value. An electric / optical conversion circuit, comprising: a peak detection circuit for controlling.