JP3800393B2 - PWM inverter output voltage compensation method - Google Patents

Description

【００１４】
【数２】

【００１５】
【数３】

【００１６】
上記各数式において、Ｅ_dcは直流電源１の電圧、ｖ_ce(sat)はＩＧＢＴの順電圧降下量、ｖ_dはＦＷＤの順電圧降下量である。
また、ｔ_on＝ｔ₁＋ｔ₃、ｔ_off＝ｔ₂である。
【００１７】
数式２及び数式３の右辺第２項は、ＩＧＢＴ及びＦＷＤの順電圧降下によって生じる、理想の相電圧値に対する誤差であるから、これらの電圧を補償量として補償すれば良い。そして、数式２及び数式３の右辺第２項の演算に必要な各値は、予め設定された設定値または検出値を用いれば良い。補償量の演算手段としては、以下の手段がある。
まず、演算に必要な変数は、ｖ_ce(sat)，ｖ_d，ｔ_on，ｔ_off，Ｔ_cと電流ｉの極性である。Ｔ_cは搬送波の周期なので設定値を用い、電流極性は相電流の極性検出結果を用いる。残る４変数に設定値または検出値を使うとすると、次の５通りとなる。
【００１８】
（１）第１の補償量演算手段：ｖ_ce(sat)＝ｖ_dとし、ｖ_ce(sat)，ｖ_d，ｔ_on，ｔ_offには全て設定値を使って演算する。
数式２、数式３の右辺第２項に前述の条件を入れると、補償量はｉ＞０の場合には数式４となり、ｉ＜０の場合には数式５となる。つまり、補償量は相電流の極性によって決まることになる。
【００１９】
【数４】

【００２０】
【数５】

【００２１】
（２）第２の補償量演算手段：ｖ_ce(sat)，ｖ_d，ｔ_on，ｔ_offには全て設定値を使って演算する。
（３）第３の補償量演算手段：ｖ_ce(sat)，ｖ_dには設定値、ｔ_on，ｔ_offには検出値を使って演算する。
（４）第４の補償量演算手段：ｖ_ce(sat)，ｖ_dには検出値、ｔ_on，ｔ_offには設定値を使って演算する。
（５）第５の補償量演算手段：ｖ_ce(sat)，ｖ_d，ｔ_on，ｔ_offには全て検出値を使って演算する。
【００２２】
次に、相電流の極性検出手段について述べる。
（１）第１の極性検出手段：相電流を電流検出器により検出し、比較器によりゼロと比較して（つまり相電流の正負により）極性を検出する。
【００２３】
また、図１６に示した補正演算部３３Ａはゲート信号のパルス幅を補正するための演算部であり、「各アームのオン検出信号」を生成している。従って、これらのオン検出信号から相電流の極性を検出する手段を以下に説明する。なお、以下の電流極性検出手段を第２の極性検出手段、第３の極性検出手段とする。
【００２４】
（２）第２の極性検出手段：図１８に、第２の極性検出手段の動作原理図を示す。この図において、（ａ）は主回路１アーム分の回路図、（ｂ）は相電流極性とアーム電圧の挙動を示している。
これらの図において、相電流が上アームから負荷へ流れる方向を正と定義すると、相電流が正の場合に上アームゲート信号の立ち上がり時点（以下、オン信号という）でのアーム電圧ｖは負である（図１８（ｂ）の▲１▼）。この理由は、デッドタイムｔ_d中のアーム電圧ｖは上アームのＦＷＤがオンしているか、下アームのＦＷＤがオンしているかにより決まるため、電流極性に依存する。つまり、自アーム（着目しているアーム）のゲート信号のオン時点で上アームまたは下アームのＦＷＤのどちらがオンしているかを検出して自アームの電圧ｖの正負を知ることができれば、相電流極性が判別できることになる。
【００２５】
（３）第３の極性検出手段：図１９に、第３の極性検出手段の動作原理図を示す。この図において、（ａ）は相電流とアーム電圧の挙動、（ｂ）は相電流と誤差量との関係、（ｃ）はＦＷＤの等価回路を示す。
図１９（ａ）により、デッドタイム中の相電流とアーム電圧の挙動を説明する。デッドタイム中のアーム電圧ｖは、第２の極性検出手段の項でも述べたが、相電流ｉの極性に依存する。更に、アーム電圧ｖは相電流の大きさにも依存する。
【００２６】
ここで、ＦＷＤの等価回路は、図１９（ｃ）に示すようにオン抵抗Ｒ_onと接合容量Ｃ_jとの並列回路であるので、デッドタイム中の電圧変化（以下、ｄｖ／ｄｔという）はこの接合容量Ｃ_jを相電流ｉで充電して行く速度で決まる。つまり、電流ｉが小さい時は充電速度が遅くなるためｄｖ／ｄｔは小さくなる。その逆に、電流ｉが大きい時は充電速度が早くなり、ｄｖ／ｄｔは大きくなる。更に、電流極性によりアーム電圧ｖの変化点が変化する。
よって、図１９（ａ）に示すように、デッドタイム中のアーム電圧ｖの変化は電流ｉの極性と大きさとに依存する。つまり、デッドタイム中のアーム電圧ｖが相電流ｉに依存することは、図１９（ｂ）に示すようにデッドタイム中の誤差量ε_rが相電流ｉに依存することを意味する。逆の見方をすれば、誤差量ε_rから相電流ｉの極性が判ることになる。
【００２７】
そこで、誤差量ε_rの検出方法を説明する。図１９（ａ）において、デッドタイム中のアーム電圧ｖの変化は、ＦＷＤの接合容量Ｃ_jが定電流充電されたとすると一定となり、その大きさは電流ｉに比例することになる。そこで、上下アームのオン状態を個別に検出し、これらのオン検出パルスの時間差をカウンタで計測すれば誤差量ε_rを検出することができる。図１９（ｂ）の原理図によれば、検出した誤差量ε_rの大きさをデッドタイムの半分ｔ_d／２の時間で決まる誤差量の大きさと比較することにより、相電流ｉの極性を判定することができる。
【００２８】
最後に、誤差量に相当する電圧信号に補償量を重畳した値をアップダウンカウンタへ再設定する手段を述べる。
図２０に、アップダウンカウンタの再設定方法を示す。この図の（ａ）はｉ＞０（電流極性が正）、（ｂ）はｉ＜０（電流極性が負）の場合を示す。
図２０（ａ），（ｂ）において、デッドタイムによる誤差量はＰＷＭ指令パルスが変化してから該当アームのゲート信号の極性がＰＷＭ指令パルスの極性と同じになるまでの時間となるので、この誤差量の検出終了タイミングはＰＷＭ指令パルスの極性と該当アームゲート信号の極性とが一致したことで判る。よって、ＰＷＭ指令パルスの極性と該当アームゲート信号の極性との一致を検出した後に、誤差量に相当する電圧信号に補償量を重畳し、その後、この「誤差量＋補償量」をアップダウンカウンタの初期値として再設定すれば良い。
【００２９】
すなわち本発明は、請求項１に示すように、ＰＷＭインバータのＰＷＭ指令パルスと各相アームの半導体スイッチング素子の駆動パルスとの間に保有されたデッドタイムに起因するインバータ出力電圧の誤差電圧を補償するために、ＰＷＭ指令パルスのエッジ変化から半導体スイッチング素子のオン検出パルスのエッジ変化までのパルスの積算値を誤差量とし、この誤差量を用いてＰＷＭ指令パルスを補正するようにしたＰＷＭインバータの出力電圧補償方法において、ＰＷＭインバータの相電流極性に応じてＰＷＭインバータを構成する半導体素子の順電圧降下量に基づく補償量を演算し、この補償量を前記誤差量に相当する電圧信号に重畳してＰＷＭ指令パルスを補正することを特徴とする。
そして、相電流極性の検出手段として第１〜第３の極性検出手段を含み、補償量演算手段として第１〜第５の補償量演算手段を含むものである。
このように構成される本発明によれば、デッドタイム中の誤差量に相当する電圧信号に素子順電圧降下量を補償する補償量を搬送波の周期で重畳することにより、高速な順電圧降下補償が可能になる。
【００３０】
【発明の実施の形態】
以下、図に沿って本発明の実施形態を説明する。
まず、請求項１、請求項２に該当する第１実施形態を図１に示す。図１において、直流電源１はスイッチング部Ｔ１〜Ｔ６からなる三相のＰＷＭインバータ２の直流側に接続され、インバータ２はＵ相補正回路３から出力されるＵ相ゲート信号、Ｖ相補正回路４から出力されるＶ相ゲート信号、Ｗ相補正回路５から出力されるＷ相ゲート信号により駆動されて直流電源１の電圧を交流電圧に変換する。
インバータ２の交流出力側に設けられた電流検出器２９，３０，３１の出力は、それぞれ該当相の補正回路３〜５に入力される。ここでは、便宜上、Ｕ相補正回路３に着目してその構成及び動作を以下に説明する。なお、図１６と同一の構成要素には同一の参照符号を付してある。
【００３１】
補正回路３は、補正演算部３３、電流極性検出手段２７Ａ、エッジ検出回路１９Ａ、スイッチ２３、乗算器２４、加算器２５、オンディレー回路９、ゲート駆動回路１０により構成される。
なお、前記電流極性検出手段２７Ａは前述した第１の極性検出手段に該当し、電流検出器２９により検出した相電流を比較器２８によりゼロと比較して相電流の極性を検出する。
【００３２】
まず、補正演算部３３の動作を説明する。インバータ２のＵ相アーム電圧は、上アームオン検出器１１及び下アームオン検出器１２に入力され、それぞれオン時にHighレベルとなる上アームオン検出信号Ｔ₁ ^ist及び下アームオン検出信号Ｔ₄ ^istを得る。これらのオン検出信号は、上アーム及び下アームの両方のオフ・オフ区間を検出するためのオフ・オフ区間検出回路１５とデータセレクタ１３とに入力される。
データセレクタ１３では、ＰＷＭ指令パルスＰＷＭ_U ^*が上アームオン指令（Highレベル）の時に上アームオン検出信号Ｔ₁ ^istを選択し、下アームオン指令（Lowレベル）の時に下アームオン検出信号Ｔ₄ ^istを選択して出力する。そして、データセレクタ１３の出力信号はデータセレクタ１４に入力され、オフ・オフ区間検出回路１５からのオフ・オフ区間検出信号はデータセレクタ１４及びデータセレクタ１６に入力されている。
【００３３】
データセレクタ１４では、上下アームのオフ・オフ区間中はＰＷＭ指令パルスＰＷＭ_U ^*の反転信号を選択し、上下アームの何れか一方がオンしている時はデータセレクタ１３の出力信号を選択する。
一方、発振器１７の出力信号（搬送波）は１／２分周器１８及びデータセレクタ１６に入力され、１／２分周器１８の出力信号はデータセレクタ１６へ入力されている。
データセレクタ１６は、オフ・オフ区間検出信号に基づいて、オフ・オフ区間中は１／２分周器１８の出力信号を選択し、上下アームの何れか一方がオンしている時は発振器１７の出力信号を選択して出力する。
【００３４】
データセレクタ１４の出力信号及びデータセレクタ１６の出力信号は、パルス差分検出回路６へ入力される。
パルス差分検出回路６では、オフ・オフ区間中（すなわち、データセレクタ１４によりＰＷＭ指令パルスＰＷＭ_U ^*の反転信号が選択されて出力され、かつ、データセレクタ１６により１／２分周器１８の出力信号が選択されて出力されているとき）は前記１／２分周器１８の出力信号（正規のクロックの１／２の周波数を有する信号）とＰＷＭ指令パルスＰＷＭ_U ^*の反転信号とから誤差電圧に相当する量のクロックを得るとともに、上下アームの何れか一方がオンしている時（すなわち、データセレクタ１４によりデータセレクタ１３の出力信号が選択されて出力され、かつ、データセレクタ１６により発振器１７の出力信号が選択されて出力されているとき）は発振器１７の出力信号（正規のクロック）と自アームのオン検出信号とから、誤差量に相当する数のクロックを得る。そして、これらのクロックをロードタイプアップダウンカウンタ７により積算する。
更に、アップダウンカウンタ７の積算結果によりフリップフロップ８をセット／リセットし、デッドタイムに起因する誤差量を搬送波の周期内で補正したＰＷＭ指令パルスを得る。
【００３５】
一方、電流検出器２９により検出した相電流は電流極性検出手段２７Ａに入力され、比較器２８によりゼロと比較して相電流極性が検出される。
第１の補償量演算手段として前述したように、数式４，数式５によれば電流極性に応じて補償量がｖ_ce(sat)または−ｖ_ce(sat)となる。従って、比較器２８から出力される電流極性に応じスイッチ２３を「１」または「−１」に切り替えて乗算器２４により素子（ＩＧＢＴ）の順電圧降下量（ｖ_ce(sat)）に乗算し、その結果（ｖ_ce(sat)または−ｖ_ce(sat)）を補償量とする。この補償量を、ロードタイプアップダウンカウンタ７により積算した誤差量に対し加算器２５により重畳する。
【００３６】
この加算器２５の出力信号は、エッジ検出器１９Ａから出力されるタイミング信号により、ロードタイプアップダウンカウンタ７に再設定される。
なお、エッジ検出器１９Ａは、ＰＷＭ指令パルスＰＷＭ_U ^*の極性とデータセレクタ１４の出力信号（上アームまたは下アームのオン検出信号すなわちゲート信号）の極性とが一致したことを検出して誤差量の検出終了を認識し、タイミング信号を出力する。この再設定タイミング信号により、アップダウンカウンタ７では加算器２５の出力信号である「誤差量＋補償量」を初期値として再設定する。
【００３７】
これらの動作により、補正演算部３３からは素子順電圧降下量を含んだ補正後のＰＷＭ指令パルスが出力される。この指令パルスはオンディレー回路９に入力され、上下アームの半導体スイッチング素子に対するゲート信号が生成される。これらのゲート信号はゲート駆動回路１０へ入力され、インバータ２のＵ相を駆動するゲート信号となる。
【００３８】
次に、請求項１、請求項３に該当する本発明の第２実施形態を図２に示す。
第１実施形態と重複する部分は割愛し、異なる部分のみを説明すると、異なる部分は補正回路３〜５における電流極性検出手段にある。Ｕ相補正回路３において、電流極性検出手段２７Ｂは前述した第２の極性検出手段に相当し、自アームのオン信号によって自アームの電圧の正負を判別し、電流極性を判別する。
【００３９】
具体的には、上アームオン検出回路１１、下アームオン検出回路１２から出力される上アームオン検出信号、下アームオン検出信号は、上アーム基準でのＦＷＤモード検出器２０と下アーム基準でのＦＷＤモード検出器２１とにそれぞれ入力される。
各ＦＷＤモード検出器２０，２１には該当アームのゲート信号も入力されており、これらのゲート信号の立ち上がりで上アームオン検出信号、下アームオン検出信号をラッチする。すなわち、上アーム基準でのＦＷＤモード検出器２０は、上アームゲート信号の立ち上がりで上アームオン検出信号をラッチすることにより上アームのＦＷＤのオンオフ状態を検出し、下アーム基準でのＦＷＤモード検出器２１は、下アームゲート信号の立ち上がりで下アームオン検出信号をラッチすることにより下アームのＦＷＤのオンオフ状態を検出する。
【００４０】
上アームまたは下アームのＦＷＤのオンオフ状態は、デッドタイムにおけるアーム電圧のレベルに対応しており、図１８に示したごとくアーム電圧のレベルから電流極性を判別することができる。
フリップフロップ２２は、各ＦＷＤモード検出器２０，２１によりラッチされた上アームまたは下アームのＦＷＤのオンオフ状態（アーム電圧のレベル）からＵ相の電流極性を検出する。この電流極性に応じた補償量の決定方法は第１実施形態と同一であり、前述した第１の演算手段によりスイッチ２３、乗算器２４を介して補償量ｖ_ce(sat)または−ｖ_ce(sat)を演算し、加算器２５によりロードタイプアップダウンカウンタ７からの誤差量に重畳して補償動作を行う。
【００４１】
次に、請求項１、請求項４に該当する本発明の第３実施形態を図３に示す。
第１実施形態と重複する部分は割愛し、異なる部分のみ説明すると、この実施形態でも、補正回路３〜５における電流極性検出手段が異なっている。
Ｕ相補正回路３において、電流極性検出手段２７Ｃは前述した第３の極性検出手段に相当しており、この電流極性検出手段２７Ｃは、エッジ検出回路１９Ｂから出力されるタイミング信号によってロードタイプアップダウンカウンタ７の出力信号をラッチするデータラッチ３２と、その出力信号とデッドタイムｔ_dの１／２の期間である期間信号ｔ_d／２及びフリップフロップ８の出力信号が入力される比較器２８とから構成されている。
【００４２】
アップダウンカウンタ７により積算した誤差量は、誤差量検出終了を検出するエッジ検出回路１９Ｂの出力信号により、データラッチ３２にラッチされる。比較器２８では、ラッチされた誤差量とｔ_d／２における誤差量（期間信号ｔ_d／２及びフリップフロップ８の出力信号から算出される）とを比較し、更にＰＷＭ指令パルスＰＷＭ_U ^*の極性を参照して電流極性を判別する。この電流極性に応じた補償量の決定方法は第１実施形態と同一であり、前述した第１の演算手段によりスイッチ２３、乗算器２４を介して補償量ｖ_ce(sat)または−ｖ_ce(sat)を演算し、加算器２５によりアップダウンカウンタ７からの誤差量に重畳して補償動作を行う。
なお、ロード信号発生器３６は、エッジ検出回路１９Ｂからのタイミング信号及び比較器２８からの相電流極性に基づいてアップダウンカウンタ７に対する再設定タイミング信号を生成し、出力する。
【００４３】
請求項５、請求項６に該当する本発明の第４実施形態を、図４に示す。
この実施形態が第１実施形態と異なるのは補償量演算手段３４を有する点である。この演算手段３４は前述した第２の補償量演算手段に該当し、ｖ_ce(sat)，ｖ_d，ｔ_on，ｔ_offに全て設定値を用いて補償量を演算する。
補償量演算手段３４には、Ｕ相電圧設定値ｖ_U ^*と、直流電圧検出器３７によって検出した直流電圧Ｅ_dcと、搬送波周期設定値Ｔ_c ^*と、半導体スイッチング素子（ＩＧＢＴ）の順電圧降下量設定値ｖ_ce ^*と、ＦＷＤの順電圧降下量設定値ｖ_d ^*と、電流極性検出手段２７Ａ（比較器２８）からの電流極性とが入力されている。
【００４４】
ここでは、前述の数式２及び数式３の右辺第２項をｖ_ce(sat)＝ｖ_ce ^*，ｖ_d＝ｖ_d ^*，Ｔ_c＝Ｔ_c ^*，ｔ_on＝ｖ^*／Ｅ_dc，ｔ_off＝Ｔ_c ^*−ｔ_onとして、補償量演算手段３４が補償量を演算する。なお、ｔ_on＝ｖ^*／Ｅ_dcとする理由は、ｖ^*を規定直流電圧Ｅ_dc ^*における出力電圧指令値としているので、直流電圧の変動を補償するためである。
補償量演算手段３４により演算された補償量は乗算器２４に入力され、電流極性に応じてスイッチ２３により選択された「１」または「−１」が乗じられて加算器２５に入力される。以後の動作は第１〜第３実施形態と同様である。
【００４５】
請求項５、請求項７に該当する本発明の第５実施形態を、図５に示す。この実施形態は、第２実施形態における補正回路３と第４実施形態における補償量演算手段３４及び直流電圧検出器３７とを組み合わせたものである。
すなわち、電流極性検出手段２７Ｂとしては第２の極性検出手段を用い、自アームのオン信号により自アームの電圧の正負を判別して電流極性を判別する。また、補償量演算手段としては第２の補償量演算手段を用い、ｖ_ce(sat)，ｖ_d，ｔ_on，ｔ_offに全て設定値を用いて補償量を演算する。
【００４６】
請求項５、請求項８に該当する本発明の第６実施形態を、図６に示す。この実施形態は、第３実施形態における補正回路３と第４実施形態における補償量演算手段３４及び直流電圧検出器３７とを組み合わせたものである。
すなわち、電流極性検出手段としては第３の極性検出手段を用いることとし、この電流極性検出手段２７Ｃは、データラッチ３２と比較器２８とから構成されており、比較器２８では、ラッチされたロードタイプアップダウンカウンタ７の積算誤差量とｔ_d／２における誤差量とを比較し、更に、ＰＷＭ指令パルスＰＷＭ_U ^*の極性を参照して電流極性を判別する。
また、補償量演算手段としては第２の補償量演算手段を用い、ｖ_ce(sat)，ｖ_d，ｔ_on，ｔ_offに全て設定値を用いて補償量を演算する。
【００４７】
請求項９、請求項１０に該当する本発明の第７実施形態を、図７に示す。
第４実施形態と重複する部分は割愛し、異なる部分のみを説明すると、この実施形態では補償量演算手段３５が異なっている。この演算手段３５は前述した第３の補償量演算手段に該当しており、ｖ_ce(sat)，ｖ_dには設定値、ｔ_on，ｔ_offには検出値を使って補償量を演算する。なお、電流極性検出手段２７Ａは第１の極性検出手段であり、検出した相電流を比較器２８によりゼロと比較して電流極性が検出される。
【００４８】
補償量演算手段３５では、数式２、数式３の右辺第２項をｖ_ce(sat)＝ｖ_ce ^*，ｖ_d＝ｖ_d ^*，Ｔ_c＝Ｔ_c ^*とし、更にｔ_on，ｔ_offは、上アームオン検出回路１１、下アームオン検出回路１２から出力される上アームオン検出信号、下アームオン検出信号を内部のカウンタ等（図示せず）に入力してオン幅、オフ幅を測定することにより求める。これらのｖ_ce(sat)，ｖ_d，Ｔ_c，ｔ_on，ｔ_offを用い、電流極性に応じて数式２、数式３の右辺第２項により補償量を演算する。
以後の動作は第４実施形態と同様である。
【００４９】
請求項９、請求項１１に該当する本発明の第８実施形態を、図８に示す。
第７実施形態と異なる部分は電流極性検出手段２７Ｂであり、ＦＷＤモード検出器２０，２１及びフリップフロップ２２により自アームのオン信号により自アームの電圧の正負を判別し、電流極性を判別する。この検出手段は第２の極性検出手段２に該当する。なお、補償量演算手段３５は第７実施形態と同様に前述した第３の補償量演算手段に相当する。
【００５０】
請求項９、請求項１２に該当する本発明の第９実施形態を、図９に示す。
第７実施形態と異なる部分は電流極性検出手段２７Ｃであり、データラッチ３２及び比較器２８により第３の極性検出手段が構成されている。この電流極性検出手段２７Ｃにおいて、データラッチ３２によりラッチされたロードタイプアップダウンカウンタ７の積算誤差量とｔ_d／２における誤差量とを比較器２８により比較し、更にＰＷＭ指令パルスＰＷＭ_U ^*の極性を参照して電流極性を判別する。
補償量演算手段３５は、第７実施形態と同様に第３の補償量演算手段に相当しており、ｖ_ce(sat)，ｖ_dは設定値、ｔ_on，ｔ_offは検出値を使って補償量を演算する。
【００５１】
請求項１３、請求項１４に該当する本発明の第１０実施形態を、図１０に示す。
第７実施形態と異なる部分は補償量演算手段３８にある。この演算手段３８は前述の第４の補償量演算手段に該当しており、ｖ_ce(sat)，ｖ_dは検出値、ｔ_on，ｔ_offは設定値を使って補償量を演算する。
図１０において、３９はアームオン電圧検出器であり、直流電源１の両端と各相の上下アームの相互接続点との間に接続され、それぞれのアームのオン時における上アームのオン電圧ｖ_u-Ｕ，ｖ_v-Ｕ，ｖ_w-Ｕ，下アームのオン電圧ｖ_u-Ｄ，ｖ_v-Ｄ，ｖ_w-Ｄが各相の補正回路３〜５にそれぞれ入力されている。
補償量演算手段３８では、数式２、数式３の右辺第２項におけるｖ_ce(sat)，ｖ_dとしてアームオン電圧検出器３７による検出値ｖ_u-Ｕ，ｖ_u-Ｄを用い、これら以外についてはＴ_c＝Ｔ_c ^*，ｔ_on＝ｖ^*／Ｅ_dc，ｔ_off＝Ｔ_c ^*−ｔ_onというように何れも設定値を用いて電流極性に応じた補償量を演算する。そして、この補償量は乗算器２４に入力される。以後の動作は第１〜第９実施形態と同様である。
【００５２】
請求項１３、請求項１５に該当する本発明の第１１実施形態を、図１１に示す。
第１０実施形態と異なる部分は電流極性検出手段であり、本実施形態では、第２の極性検出手段に該当する電流極性検出手段２７Ｂが自アームのオン信号によって自アームの電圧の正負を判別し、電流極性を判別する。
【００５３】
請求項１３、請求項１６に該当する本発明の第１２実施形態を、図１２に示す。
第１０実施形態と異なる部分は電流極性検出手段であり、本実施形態では、第３の極性検出手段に該当する電流極性検出手段２７Ｃにおいて、データラッチ３２によりラッチされたロードタイプアップダウンカウンタ７の積算誤差量とｔ_d／２における誤差量とを比較器２８により比較し、更にＰＷＭ指令パルスＰＷＭ_U ^*の極性を参照して電流極性を判別する。
【００５４】
請求項１７、請求項１８に該当する本発明の第１３実施形態を、図１３に示す。
第１０実施形態と重複する部分は割愛し、異なる部分のみ説明する。異なる部分は補償量演算手段３５であり、この演算手段３５は前述の第５の補償量演算手段に該当する。つまり、補償量演算手段３５は、ｖ_ce(sat)，ｖ_d，ｔ_on，ｔ_offに全て検出値を使って補償量を演算する。
具体的に説明すると、補償量演算手段３５では数式２、数式３の右辺第２項におけるｖ_ce(sat)，ｖ_dとしてアームオン電圧検出器３７による検出値ｖ_u-Ｕ，ｖ_u-Ｄを用いるとともに、Ｔ_c＝Ｔ_c ^*とし、更にｔ_on，ｔ_offについては上アームオン検出回路１１、下アームオン検出回路１２により検出した各オン検出信号を演算手段３５内のカウンタ等（図示せず）に入力してオン幅、オフ幅を測定することにより求める。これらのｖ_ce(sat)，ｖ_d，Ｔ_c，ｔ_on，ｔ_offを用い、電流極性に応じて数式２、数式３の右辺第２項により補償量を演算する。
【００５５】
請求項１７、請求項１９に該当する本発明の第１４実施形態を、図１４に示す。
第１３実施形態と異なる部分は、第２の極性検出手段に該当する電流極性検出手段２７Ｂであり、他の構成は先の実施形態から明らかであるため、説明を省略する。
【００５６】
請求項１７、請求項２０に該当する本発明の第１５実施形態を、図１５に示す。
第１３実施形態と異なる部分は、第３の極性検出手段に該当する電流極性検出手段２７Ｃであり、他の構成は先の実施形態から明らかであるため、説明を省略する。
【００５７】
【発明の効果】
以上のように本発明によれば、総じて、デッドタイムに起因する誤差量に素子順電圧降下量を補償する補償量を搬送波の周期で重畳することにより、高速な補償が可能になり、ＰＷＭインバータの出力電圧波形の歪みを抑制することができる。
【図面の簡単な説明】
【図１】 本発明の第１実施形態を示すブロック図である。
【図２】 本発明の第２実施形態を示すブロック図である。
【図３】 本発明の第３実施形態を示すブロック図である。
【図４】 本発明の第４実施形態を示すブロック図である。
【図５】 本発明の第５実施形態を示すブロック図である。
【図６】 本発明の第６実施形態を示すブロック図である。
【図７】 本発明の第７実施形態を示すブロック図である。
【図８】 本発明の第８実施形態を示すブロック図である。
【図９】 本発明の第９実施形態を示すブロック図である。
【図１０】 本発明の第１０実施形態を示すブロック図である。
【図１１】 本発明の第１１実施形態を示すブロック図である。
【図１２】 本発明の第１２実施形態を示すブロック図である。
【図１３】 本発明の第１３実施形態を示すブロック図である。
【図１４】 本発明の第１４実施形態を示すブロック図である。
【図１５】 本発明の第１５実施形態を示すブロック図である。
【図１６】 従来技術を示すブロック図である。
【図１７】本発明における補償すべき素子順電圧降下量を説明するための図である。
【図１８】本発明における電流極性検出手段の動作原理を説明するための図である。
【図１９】本発明における電流極性検出手段の動作原理を説明するための図である。
【図２０】本発明におけるアップダウンカウンタの再設定方法を説明するための図である。
【符号の説明】
１ 直流電源
２ ＰＷＭインバータ
Ｔ１〜Ｔ６ スイッチング部
Ｕ，Ｖ，Ｗ 交流出力端子
３ Ｕ相補正回路
４ Ｖ相補正回路
５ Ｗ相補正回路
６ パルス差分検出回路
７ ロードタイプアップダウンカウンタ
８ フリップフロップ
９ オンディレー回路
１０ ゲート駆動回路
１１ 上アームオン検出回路
１２ 下アームオン検出回路
１３，１４，１６ データセレクタ
１５ オフ・オフ区間検出回路
１７ 発振器
１８ １／２分周器
１９Ａ，１９Ｂ エッジ検出回路
２０ 上アーム基準ＦＷＤモード検出器
２１ 下アーム基準ＦＷＤモード検出器
２２ フリップフロップ
２３ スイッチ
２４ 乗算器
２５ 加算器
２６ 反転器
２７Ａ，２７Ｂ，２７Ｃ 電流極性検出手段
２８ 比較器
２９，３０，３１ 電流検出器
３２ データラッチ
３３ 補正演算部
３４，３５，３８ 補償量演算手段
３６ ロード信号発生器
３７ 直流電圧検出器
３９ アームオン電圧検出器[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for compensating an output voltage of a PWM inverter that obtains an AC voltage from a DC voltage, and more specifically, a PWM command pulse caused by a dead time provided to prevent simultaneous ON of upper and lower arms of each phase of the PWM inverter, Error voltage due to error from actual drive pulse (ON detection pulse) of upper and lower arms of each phase, loss due to forward voltage drop of semiconductor switching element and freewheeling diode (hereinafter referred to as FWD) constituting main circuit of PWM inverter The present invention relates to an output voltage compensation method for suppressing distortion of an inverter output voltage caused by a voltage.
[0002]
[Prior art]
An error voltage (error between the output voltage command value and the output voltage detection value) generated by an error between the PWM command pulse of the PWM inverter and the ON detection pulse obtained from the ON detection circuit of the semiconductor switching element of each phase upper and lower arms is compensated. A compensation method (hereinafter referred to as a pulse width correction method) will be described based on the prior art of FIG.
[0003]
In FIG. 16, 1 is a DC power source, 2 is a PWM inverter, T1 to T6 are switching units composed of a semiconductor switching element and FWD, U, V, and W are AC output terminals, 3A, 3B, and 3C are U-phase, V 3 is a correction circuit having the same configuration for correcting the phase and W phase gate signals.
[0004]
The configuration of the correction circuit will be described by taking the U-phase correction circuit 3A as an example.
In the U-phase correction circuit 3A, 6 is a PWM command pulse PWM._U ^*The pulse difference detection circuit to which the output signals of the data selectors 14 and 16 are inputted, 7A is an up / down counter for error pulse integration that counts the output signal of the pulse difference detection circuit 6, and 8 is the output signal of the up / down counter 7. A flip-flop to be set / reset, 9 is an on-delay circuit for generating the timing of the gate signals of the upper and lower arms from the corrected PWM command pulse which is the output of the flip-flop 8, and 10 is an output signal of the on-delay circuit 9 Based on this, a gate drive circuit that generates an actual gate signal for the upper and lower arms of the U phase, 11 is an upper arm on detection circuit that detects the on state of the upper arm semiconductor switching element, and 12 is an on state that detects that the lower arm semiconductor switching element is on. Lower arm on detection circuit 13 is on detection circuit 11 or 12 On detection pulse and PWM command pulse PWM output_U ^*And a data selector 15 to which an inversion pulse of the PWM command pulse is input via the inverter 26, detects an off section of the semiconductor switching elements of both the upper and lower arms based on the on detection pulse from each of the on detection circuits 11 and 12. OFF / OFF section detection circuit, 14 is an output signal of the data selector 13 and PWM command pulse PWM_U ^*Is a data selector that selects an inversion pulse of the output signal according to the on / off period detection signal, and 16 is a data that selects the output signal of the oscillator 17 and the output signal of the 1/2 divider 18 according to the off / off period detection signal. It is a selector.
[0005]
Here, the pulse difference detection circuit 6, the up / down counter 7A, the flip-flop 8, the upper arm on detection circuit 11, the lower arm on detection circuit 12, the data selectors 13, 14, and 16, the off / off section detection circuit 15 and the inverter 26 are provided. The correction calculation unit 33A is configured to compensate for an error voltage caused by the dead time.
[0006]
In the correction calculation unit 33A, the data selector 13 controls the PWM command pulse PWM._U ^*Selects and outputs the upper arm on detection signal when is the upper arm on command (High level). The data selector 14 outputs the PWM command pulse PWM when the off / off section detection signal is output._U ^*When either of the upper and lower arms is on, the output signal of the data selector 13 is selected and output.
Based on the off / off period detection signal, the data selector 16 outputs the output signal of the 1/2 frequency divider 18 during the off / off period, and the output signal of the oscillator 17 when either one of the upper and lower arms is on. Select to output.
[0007]
In the pulse difference detection circuit 6, during the off / off period (the data selector 14 causes the PWM command pulse PWM to_U ^*When the inverted signal is selected and the output signal of the 1/2 divider 18 is selected by the data selector 16), the output signal of the 1/2 divider 18 (the oscillator 17 which is a normal clock) Output signal (carrier wave) and a PWM command pulse PWM._U ^*Is obtained from the inverted signal, and when either of the upper and lower arms is on (the output signal of the data selector 13 is selected by the data selector 14 and the data selector 16 When the output signal of the oscillator 17 is selected), an amount of clock corresponding to the error voltage is obtained from the output signal (normal clock) of the oscillator 17 and the ON detection signal of the own arm. These clocks are integrated by the up / down counter 7A.
Further, the flip-flop 8 is set / reset based on the integration result of the up / down counter 7A to obtain a PWM command pulse in which the error voltage caused by the dead time is corrected.
[0008]
That is, the up / down counter 7A has a PWM command pulse PWM._U ^*Error pulses from edge change to upper arm on detection pulse and edge change of lower arm on detection pulse are integrated, and then PWM command pulse PWM_U ^*When the edge change occurs, the output pulse is not changed by the time width of the error pulse accumulated so far (hereinafter referred to as the error amount). For this reason, the output voltage is corrected by a voltage signal corresponding to the amount of error due to the dead time, and the forward voltage drop amount of the constituent elements of the semiconductor switching units T1 to T6 constituting the upper and lower arms cannot be corrected.
[0009]
Here, the constituent elements of the upper and lower arms are switching elements such as IGBT (Insulated Gate Bipolar Transistor), BJT (Bipolar Junction Transistor), MOSFET (MOS Field Effect Transistor), and FWD. In order to compensate, in the pulse width correction method, the element forward voltage drop calculated from the phase current of the inverter is superimposed on the output voltage command value of the inverter.
[0010]
[Problems to be solved by the invention]
Thus, in order to correct the element forward voltage drop amount in the conventional compensation method, the output voltage command value of the inverter must always be manipulated, so that the compensation operation is delayed and the distortion of the voltage waveform cannot be suppressed. there were.
Therefore, the present invention corrects the PWM command pulse by superimposing the compensation amount for compensating the element forward voltage drop amount on the voltage signal corresponding to the error amount without manipulating the output voltage command value of the inverter. It is an object of the present invention to provide an output voltage compensation method that enables compensation and suppresses waveform distortion of the output voltage of the PWM inverter.
[0011]
[Means for Solving the Problems]
First, in order to correct the PWM command pulse by superimposing a compensation amount for compensating the element forward voltage drop amount on the voltage signal corresponding to the error amount, an up / down counter 7A for error pulse integration shown in FIG. After the error pulse is accumulated, and before this counter starts the compensation operation (operation that does not change the output pulse), the value obtained by superimposing the compensation amount on the error pulse integration value is reset in this counter. Just do it.
[0012]
First, the element forward voltage drop amount to be compensated will be described.
FIG. 17A is a connection diagram for one arm of the main circuit, and the switching unit is composed of an IGBT as a semiconductor switching element and an FWD connected in reverse parallel thereto. FIG. 17B shows the phase voltage in the ideal element assuming that the forward voltage drop amount in the IGBT and FWD is zero, FIG. 17C shows the phase voltage when the phase current i> 0, and FIG. The phase voltage when <0 is shown.
Here, as shown in FIGS. 17C and 17D, the actual phase voltage has a value obtained by superimposing the forward voltage drop amount of the element constituting the arm on the phase voltage of the ideal element according to the current polarity. . Therefore, one carrier wave period T shown in FIG._cAverage value of phase voltage in₀Is represented by Equation 1 for an ideal element, Equation 2 for i> 0, and Equation 3 for i <0, as shown below.
[0013]
[Expression 1]

[0014]
[Expression 2]

[0015]
[Equation 3]

[0016]
In the above equations, E_dcIs the voltage of the DC power supply 1, v_{ce (sat)}Is the amount of forward voltage drop of IGBT, v_dIs a forward voltage drop amount of FWD.
T_on= T₁+ T_Three, T_off= T₂It is.
[0017]
Since the second term on the right side of Equation 2 and Equation 3 is an error with respect to the ideal phase voltage value caused by the forward voltage drop of IGBT and FWD, these voltages may be compensated as compensation amounts. Then, as each value necessary for the calculation of the second term on the right side of Equation 2 and Equation 3, a preset setting value or detection value may be used. The compensation amount calculation means includes the following means.
First, the variables required for the operation are v_{ce (sat)}, V_d, T_on, T_off, T_cAnd the polarity of the current i. T_cIs the period of the carrier wave, so the set value is used, and the current polarity is the detection result of the phase current polarity. If setting values or detection values are used for the remaining four variables, the following five types are obtained.
[0018]
(1) First compensation amount calculating means: v_{ce (sat)}= V_dAnd v_{ce (sat)}, V_d, T_on, T_offAll are calculated using the set values.
When the above condition is put in the second term on the right side of Equations 2 and 3, the compensation amount is Equation 4 when i> 0, and Equation 5 when i <0. That is, the compensation amount is determined by the polarity of the phase current.
[0019]
[Expression 4]

[0020]
[Equation 5]

[0021]
(2) Second compensation amount calculating means: v_{ce (sat)}, V_d, T_on, T_offAll are calculated using the set values.
(3) Third compensation amount calculating means: v_{ce (sat)}, V_dIs the set value, t_on, T_offIs calculated using the detected value.
(4) Fourth compensation amount calculating means: v_{ce (sat)}, V_dIs the detected value, t_on, T_offFor the calculation, use the set value.
(5) Fifth compensation amount calculating means: v_{ce (sat)}, V_d, T_on, T_offAll are calculated using the detected values.
[0022]
Next, phase current polarity detection means will be described.
(1) First polarity detection means: a phase current is detected by a current detector, and compared with zero by a comparator (that is, by detecting the polarity of the phase current).
[0023]
Also, the correction calculation unit 33A shown in FIG. 16 is a calculation unit for correcting the pulse width of the gate signal, and generates “ON detection signal of each arm”. Therefore, means for detecting the polarity of the phase current from these on detection signals will be described below. The following current polarity detection means are referred to as second polarity detection means and third polarity detection means.
[0024]
(2) Second polarity detection means: FIG. 18 shows an operation principle diagram of the second polarity detection means. In this figure, (a) is a circuit diagram for one arm of the main circuit, and (b) shows the behavior of phase current polarity and arm voltage.
In these figures, if the direction in which the phase current flows from the upper arm to the load is defined as positive, the arm voltage v at the rising point of the upper arm gate signal (hereinafter referred to as the ON signal) is negative when the phase current is positive. Yes ((1) in FIG. 18B). This is because the dead time t_dSince the middle arm voltage v is determined by whether the FWD of the upper arm is on or the FWD of the lower arm is on, it depends on the current polarity. In other words, if it is possible to detect whether the upper arm or the lower arm FWD is turned on when the gate signal of the own arm (the arm of interest) is turned on and know the positive or negative of the voltage v of the own arm, the phase current The polarity can be determined.
[0025]
(3) Third polarity detection means: FIG. 19 shows an operation principle diagram of the third polarity detection means. In this figure, (a) shows the behavior of the phase current and the arm voltage, (b) shows the relationship between the phase current and the error amount, and (c) shows an equivalent circuit of the FWD.
The behavior of the phase current and arm voltage during the dead time will be described with reference to FIG. The arm voltage v during the dead time depends on the polarity of the phase current i as described in the second polarity detection means. Furthermore, the arm voltage v also depends on the magnitude of the phase current.
[0026]
Here, as shown in FIG. 19C, the equivalent circuit of the FWD is an on-resistance R_onAnd junction capacitance C_jThe voltage change during the dead time (hereinafter referred to as dv / dt) is the junction capacitance C._jIs determined by the speed of charging with the phase current i. That is, when the current i is small, dv / dt is small because the charging speed is slow. On the other hand, when the current i is large, the charging speed increases and dv / dt increases. Furthermore, the changing point of the arm voltage v changes depending on the current polarity.
Therefore, as shown in FIG. 19A, the change in the arm voltage v during the dead time depends on the polarity and magnitude of the current i. That is, the fact that the arm voltage v during the dead time depends on the phase current i indicates that the error amount ε during the dead time as shown in FIG._rIs dependent on the phase current i. In other words, the error amount ε_rThus, the polarity of the phase current i can be determined.
[0027]
Therefore, the error amount ε_rThe detection method of will be described. In FIG. 19A, the change in the arm voltage v during the dead time indicates the junction capacitance C of the FWD._jIs constant and charged, the magnitude is proportional to the current i. Therefore, if the ON state of the upper and lower arms is individually detected and the time difference between these ON detection pulses is measured with a counter, the error amount ε_rCan be detected. According to the principle diagram of FIG. 19B, the detected error amount ε_rIs half the dead time_dThe polarity of the phase current i can be determined by comparing with the amount of error determined by the time of / 2.
[0028]
Finally, means for resetting the value obtained by superimposing the compensation amount on the voltage signal corresponding to the error amount in the up / down counter will be described.
FIG. 20 shows a method for resetting the up / down counter. (A) of this figure shows the case of i> 0 (current polarity is positive), and (b) shows the case of i <0 (current polarity is negative).
In FIGS. 20A and 20B, the amount of error due to the dead time is the time from when the PWM command pulse changes until the polarity of the gate signal of the corresponding arm becomes the same as the polarity of the PWM command pulse. The detection end timing of the error amount can be understood from the fact that the polarity of the PWM command pulse matches the polarity of the corresponding arm gate signal. Therefore, after detecting the coincidence between the polarity of the PWM command pulse and the polarity of the corresponding arm gate signal, the compensation amount is superimposed on the voltage signal corresponding to the error amount, and then this “error amount + compensation amount” is added to the up / down counter. It may be reset as the initial value of.
[0029]
That is, the present invention compensates for an error voltage of the inverter output voltage caused by the dead time held between the PWM command pulse of the PWM inverter and the drive pulse of the semiconductor switching element of each phase arm. In order to achieve this, the integrated value of the pulse from the edge change of the PWM command pulse to the edge change of the ON detection pulse of the semiconductor switching element is used as an error amount, and the PWM command pulse is corrected using this error amount. In the output voltage compensation method, a compensation amount based on the forward voltage drop amount of the semiconductor element constituting the PWM inverter is calculated according to the phase current polarity of the PWM inverter, and this compensation amount is superimposed on the voltage signal corresponding to the error amount. Thus, the PWM command pulse is corrected.
The phase current polarity detection means includes first to third polarity detection means, and the compensation amount calculation means includes first to fifth compensation amount calculation means.
According to the present invention configured as described above, high-speed forward voltage drop compensation is achieved by superimposing the compensation amount for compensating the element forward voltage drop amount on the voltage signal corresponding to the error amount during the dead time in the period of the carrier wave. Is possible.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, FIG. 1 shows a first embodiment corresponding to claims 1 and 2. In FIG. 1, a DC power source 1 is connected to the DC side of a three-phase PWM inverter 2 composed of switching units T1 to T6. The inverter 2 is a U-phase gate signal output from a U-phase correction circuit 3 and a V-phase correction circuit 4. Is driven by the V-phase gate signal output from the W-phase and the W-phase gate signal output from the W-phase correction circuit 5 to convert the voltage of the DC power supply 1 into an AC voltage.
The outputs of the current detectors 29, 30 and 31 provided on the AC output side of the inverter 2 are respectively input to the correction circuits 3 to 5 for the corresponding phases. Here, for convenience, the configuration and operation of the U-phase correction circuit 3 will be described below with a focus on the U-phase correction circuit 3. The same components as those in FIG. 16 are denoted by the same reference numerals.
[0031]
The correction circuit 3 includes a correction calculation unit 33, a current polarity detection means 27A, an edge detection circuit 19A, a switch 23, a multiplier 24, an adder 25, an on-delay circuit 9, and a gate drive circuit 10.
The current polarity detection means 27A corresponds to the first polarity detection means described above, and detects the polarity of the phase current by comparing the phase current detected by the current detector 29 with zero by the comparator 28.
[0032]
First, the operation of the correction calculation unit 33 will be described. The U-phase arm voltage of the inverter 2 is input to the upper arm-on detector 11 and the lower arm-on detector 12, and the upper arm-on detection signal T that is at a high level when turned on.₁ ^istAnd lower arm on detection signal T_Four ^istGet. These on detection signals are input to the off / off section detection circuit 15 and the data selector 13 for detecting the off / off sections of both the upper arm and the lower arm.
In the data selector 13, the PWM command pulse PWM_U ^*Upper arm on detection signal T when is the upper arm on command (High level)₁ ^istWhen the lower arm on command (Low level) is selected, the lower arm on detection signal T_Four ^istSelect to output. The output signal of the data selector 13 is input to the data selector 14, and the off / off period detection signal from the off / off period detection circuit 15 is input to the data selector 14 and the data selector 16.
[0033]
In the data selector 14, the PWM command pulse PWM is applied during the off / off period of the upper and lower arms._U ^*When either one of the upper and lower arms is on, the output signal of the data selector 13 is selected.
On the other hand, the output signal (carrier wave) of the oscillator 17 is input to the 1/2 frequency divider 18 and the data selector 16, and the output signal of the 1/2 frequency divider 18 is input to the data selector 16.
The data selector 16 selects the output signal of the 1/2 frequency divider 18 during the off / off period based on the off / off period detection signal, and when either one of the upper and lower arms is on, the oscillator 17 Output signal is selected and output.
[0034]
The output signal of the data selector 14 and the output signal of the data selector 16 are input to the pulse difference detection circuit 6.
In the pulse difference detection circuit 6, during the off / off period (that is, the PWM command pulse PWM is generated by the data selector 14)._U ^*When the output signal of the 1/2 divider 18 is selected and output by the data selector 16 and the output signal of the 1/2 divider 18 (normal) And a PWM command pulse PWM._U ^*Is obtained from the inverted signal, and when either one of the upper and lower arms is turned on (that is, the output signal of the data selector 13 is selected and output by the data selector 14; and When the output signal of the oscillator 17 is selected and output by the data selector 16), the number of clocks corresponding to the amount of error is calculated from the output signal (regular clock) of the oscillator 17 and the ON detection signal of the own arm. obtain. These clocks are integrated by the load type up / down counter 7.
Further, the flip-flop 8 is set / reset based on the integration result of the up / down counter 7 to obtain a PWM command pulse in which the error amount due to the dead time is corrected within the period of the carrier wave.
[0035]
On the other hand, the phase current detected by the current detector 29 is input to the current polarity detection means 27A, and the phase current polarity is detected by the comparator 28 as compared with zero.
As described above as the first compensation amount calculation means, according to Equations 4 and 5, the compensation amount is v according to the current polarity._{ce (sat)}Or -v_{ce (sat)}It becomes. Accordingly, the switch 23 is switched to “1” or “−1” according to the current polarity output from the comparator 28, and the forward voltage drop amount (v) of the element (IGBT) is changed by the multiplier 24._{ce (sat)}) And the result (v_{ce (sat)}Or -v_{ce (sat)}) Is the compensation amount. This compensation amount is superimposed by the adder 25 on the error amount accumulated by the load type up / down counter 7.
[0036]
The output signal of the adder 25 is reset in the load type up / down counter 7 by the timing signal output from the edge detector 19A.
The edge detector 19A has a PWM command pulse PWM._U ^*Is detected to coincide with the polarity of the output signal of the data selector 14 (the upper arm or lower arm ON detection signal, ie, the gate signal), and the end of detection of the error amount is recognized, and a timing signal is output. Based on this reset timing signal, the up / down counter 7 resets “error amount + compensation amount”, which is an output signal of the adder 25, as an initial value.
[0037]
By these operations, the corrected arithmetic operation unit 33 outputs a corrected PWM command pulse including the element forward voltage drop amount. This command pulse is input to the on-delay circuit 9 to generate gate signals for the upper and lower arm semiconductor switching elements. These gate signals are input to the gate drive circuit 10 and become gate signals for driving the U phase of the inverter 2.
[0038]
Next, FIG. 2 shows a second embodiment of the present invention corresponding to claims 1 and 3.
Parts that overlap with the first embodiment are omitted, and only different parts are described. The different parts are in the current polarity detection means in the correction circuits 3 to 5. In the U-phase correction circuit 3, the current polarity detection unit 27B corresponds to the above-described second polarity detection unit, and determines the current polarity by determining whether the voltage of the own arm is positive or negative based on the ON signal of the own arm.
[0039]
Specifically, the upper arm on detection signal and the lower arm on detection signal output from the upper arm on detection circuit 11 and the lower arm on detection circuit 12 are the FWD mode detector 20 based on the upper arm and the FWD mode detection based on the lower arm, respectively. Are respectively input to the devices 21.
The gate signals of the corresponding arms are also input to the FWD mode detectors 20 and 21, and the upper arm on detection signal and the lower arm on detection signal are latched at the rise of these gate signals. That is, the FWD mode detector 20 based on the upper arm detects the ON / OFF state of the FWD of the upper arm by latching the upper arm ON detection signal at the rising edge of the upper arm gate signal, and detects the FWD mode detector based on the lower arm. 21 detects the ON / OFF state of the FWD of the lower arm by latching the lower arm ON detection signal at the rising edge of the lower arm gate signal.
[0040]
The ON / OFF state of the FWD of the upper arm or the lower arm corresponds to the arm voltage level in the dead time, and the current polarity can be determined from the arm voltage level as shown in FIG.
The flip-flop 22 detects the U-phase current polarity from the ON / OFF state (arm voltage level) of the FWD of the upper arm or the lower arm latched by the FWD mode detectors 20 and 21. The method for determining the compensation amount in accordance with the current polarity is the same as that in the first embodiment, and the compensation amount v is obtained via the switch 23 and the multiplier 24 by the first computing means described above._{ce (sat)}Or -v_{ce (sat)}Is added to the error amount from the load type up / down counter 7 by the adder 25 to perform a compensation operation.
[0041]
Next, FIG. 3 shows a third embodiment of the present invention corresponding to claims 1 and 4.
A portion overlapping with the first embodiment is omitted, and only a different portion will be described. Also in this embodiment, the current polarity detection means in the correction circuits 3 to 5 are different.
In the U-phase correction circuit 3, the current polarity detection means 27C corresponds to the third polarity detection means described above, and this current polarity detection means 27C is loaded type up / down according to the timing signal output from the edge detection circuit 19B. A data latch 32 for latching the output signal of the counter 7, its output signal and dead time t_dPeriod signal t which is a period of 1/2 of_d/ 2 and the comparator 28 to which the output signal of the flip-flop 8 is inputted.
[0042]
The error amount accumulated by the up / down counter 7 is latched in the data latch 32 by the output signal of the edge detection circuit 19B that detects the end of the error amount detection. In the comparator 28, the latched error amount and t_d/ 2 error amount (period signal t_d/ 2 and the output signal of the flip-flop 8) and PWM command pulse PWM_U ^*The polarity of the current is determined with reference to the polarity of the current. The method for determining the compensation amount in accordance with the current polarity is the same as that in the first embodiment, and the compensation amount v is obtained via the switch 23 and the multiplier 24 by the first computing means described above._{ce (sat)}Or -v_{ce (sat)}Is added to the error amount from the up / down counter 7 by the adder 25 to perform a compensation operation.
The load signal generator 36 generates and outputs a reset timing signal for the up / down counter 7 based on the timing signal from the edge detection circuit 19B and the phase current polarity from the comparator 28.
[0043]
FIG. 4 shows a fourth embodiment of the present invention corresponding to claims 5 and 6.
This embodiment is different from the first embodiment in that it has a compensation amount calculation means 34. This calculating means 34 corresponds to the above-mentioned second compensation amount calculating means, and v_{ce (sat)}, V_d, T_on, T_offThe compensation amount is calculated using all the set values.
The compensation amount calculation means 34 has a U-phase voltage set value v_U ^*And the DC voltage E detected by the DC voltage detector 37._dcAnd carrier cycle setting value T_c ^*And the forward voltage drop amount set value v of the semiconductor switching element (IGBT)_ce ^*FWD forward voltage drop setting value v_d ^*And the current polarity from the current polarity detection means 27A (comparator 28).
[0044]
Here, the second term on the right side of Equations 2 and 3 is v_{ce (sat)}= V_ce ^*, V_d= V_d ^*, T_c= T_c ^*, T_on= V^*/ E_dc, T_off= T_c ^*-T_onThe compensation amount calculation means 34 calculates the compensation amount. T_on= V^*/ E_dcThe reason for^*DC voltage E_dc ^*This is because the output voltage command value at is compensated for fluctuations in the DC voltage.
The compensation amount calculated by the compensation amount calculating means 34 is input to the multiplier 24, multiplied by “1” or “−1” selected by the switch 23 according to the current polarity, and input to the adder 25. Subsequent operations are the same as those in the first to third embodiments.
[0045]
5th Embodiment of this invention applicable to Claim 5 and Claim 7 is shown in FIG. This embodiment is a combination of the correction circuit 3 in the second embodiment, the compensation amount calculating means 34 and the DC voltage detector 37 in the fourth embodiment.
That is, as the current polarity detection means 27B, the second polarity detection means is used, and the current polarity is determined by determining whether the voltage of the own arm is positive or negative based on the ON signal of the own arm. Further, as the compensation amount calculation means, the second compensation amount calculation means is used, and v_{ce (sat)}, V_d, T_on, T_offThe compensation amount is calculated using all the set values.
[0046]
A sixth embodiment corresponding to claims 5 and 8 is shown in FIG. In this embodiment, the correction circuit 3 in the third embodiment is combined with the compensation amount calculating means 34 and the DC voltage detector 37 in the fourth embodiment.
That is, the third polarity detection means is used as the current polarity detection means, and this current polarity detection means 27C is composed of the data latch 32 and the comparator 28. In the comparator 28, the latched load Integrated error amount of type up / down counter 7 and t_d/ 2 is compared with the error amount, and further PWM command pulse PWM_U ^*The polarity of the current is determined with reference to the polarity of the current.
Further, as the compensation amount calculation means, the second compensation amount calculation means is used, and v_{ce (sat)}, V_d, T_on, T_offThe compensation amount is calculated using all the set values.
[0047]
FIG. 7 shows a seventh embodiment corresponding to the ninth and tenth aspects of the present invention.
Parts that overlap with the fourth embodiment are omitted, and only different parts are described. In this embodiment, the compensation amount calculation means 35 is different. This calculating means 35 corresponds to the above-described third compensation amount calculating means, and v_{ce (sat)}, V_dIs the set value, t_on, T_offFor this, the compensation value is calculated using the detected value. The current polarity detection means 27A is a first polarity detection means, and the current polarity is detected by comparing the detected phase current with zero by the comparator 28.
[0048]
In the compensation amount calculation means 35, the second term on the right side of Equations 2 and 3 is expressed as v._{ce (sat)}= V_ce ^*, V_d= V_d ^*, T_c= T_c ^*And then t_on, T_offBy inputting the upper arm ON detection signal and the lower arm ON detection signal output from the upper arm ON detection circuit 11 and the lower arm ON detection circuit 12 to an internal counter or the like (not shown), and measuring the ON width and OFF width. Ask. These v_{ce (sat)}, V_d, T_c, T_on, T_offAnd the compensation amount is calculated from the second term on the right side of Equations 2 and 3 according to the current polarity.
Subsequent operations are the same as those in the fourth embodiment.
[0049]
FIG. 8 shows an eighth embodiment of the present invention corresponding to the ninth and eleventh aspects.
The part different from the seventh embodiment is the current polarity detection means 27B, and the FWD mode detectors 20 and 21 and the flip-flop 22 determine the positive / negative of the voltage of the own arm based on the ON signal of the own arm to determine the current polarity. This detection means corresponds to the second polarity detection means 2. The compensation amount calculation means 35 corresponds to the above-described third compensation amount calculation means as in the seventh embodiment.
[0050]
FIG. 9 shows a ninth embodiment of the present invention corresponding to the ninth and twelfth aspects.
The part different from the seventh embodiment is current polarity detection means 27C, and the data latch 32 and the comparator 28 constitute third polarity detection means. In this current polarity detection means 27C, the integrated error amount of the load type up / down counter 7 latched by the data latch 32 and t_dThe error amount at / 2 is compared by the comparator 28, and further the PWM command pulse PWM_U ^*The polarity of the current is determined with reference to the polarity of the current.
The compensation amount calculation means 35 corresponds to the third compensation amount calculation means as in the seventh embodiment, and v_{ce (sat)}, V_dIs the set value, t_on, T_offCalculates the compensation amount using the detected value.
[0051]
A tenth embodiment of the present invention corresponding to claims 13 and 14 is shown in FIG.
A difference from the seventh embodiment resides in the compensation amount calculation means 38. This calculating means 38 corresponds to the above-mentioned fourth compensation amount calculating means, and v_{ce (sat)}, V_dIs the detected value, t_on, T_offCalculates the compensation amount using the set value.
In FIG. 10, 39 is an arm-on voltage detector, which is connected between both ends of the DC power supply 1 and the interconnection point of the upper and lower arms of each phase, and the on-voltage v of the upper arm when each arm is on._u-U, v_v-U, v_w-U, lower arm on-voltage v_u-D, v_v-D, v_w-D is input to the correction circuits 3 to 5 for each phase.
In the compensation amount calculating means 38, v in the second term on the right side of Equations 2 and 3 is used._{ce (sat)}, V_dDetected value v by arm-on voltage detector 37_u-U, v_u-D is used, otherwise T_c= T_c ^*, T_on= V^*/ E_dc, T_off= T_c ^*-T_onIn any case, the compensation amount corresponding to the current polarity is calculated using the set value. This compensation amount is input to the multiplier 24. Subsequent operations are the same as those in the first to ninth embodiments.
[0052]
An eleventh embodiment of the present invention corresponding to claims 13 and 15 is shown in FIG.
The difference from the tenth embodiment is the current polarity detection means. In this embodiment, the current polarity detection means 27B corresponding to the second polarity detection means determines whether the voltage of the own arm is positive or negative based on the ON signal of the own arm. Determine the current polarity.
[0053]
A twelfth embodiment of the present invention corresponding to claims 13 and 16 is shown in FIG.
The difference from the tenth embodiment is the current polarity detection means. In this embodiment, the current type polarity detection means 27C corresponding to the third polarity detection means has the load type up / down counter 7 latched by the data latch 32. Integration error amount and t_dThe error amount at / 2 is compared by the comparator 28, and further the PWM command pulse PWM_U ^*The polarity of the current is determined with reference to the polarity of the current.
[0054]
FIG. 13 shows a thirteenth embodiment of the present invention corresponding to the seventeenth and eighteenth aspects.
Parts that overlap with the tenth embodiment are omitted, and only different parts are described. A different part is the compensation amount calculating means 35, which corresponds to the above-mentioned fifth compensation amount calculating means. That is, the compensation amount calculation means 35 is v_{ce (sat)}, V_d, T_on, T_offAll compensation values are calculated using the detected values.
More specifically, the compensation amount calculator 35 calculates v in the second term on the right side of Equations 2 and 3._{ce (sat)}, V_dDetected value v by arm-on voltage detector 37_u-U, v_u-D and T_c= T_c ^*And then t_on, T_offIs obtained by inputting the respective on detection signals detected by the upper arm on detection circuit 11 and the lower arm on detection circuit 12 to a counter or the like (not shown) in the computing means 35 and measuring the on width and the off width. These v_{ce (sat)}, V_d, T_c, T_on, T_offAnd the compensation amount is calculated from the second term on the right side of Equations 2 and 3 according to the current polarity.
[0055]
FIG. 14 shows a fourteenth embodiment of the present invention corresponding to the seventeenth and nineteenth aspects.
The difference from the thirteenth embodiment is the current polarity detection means 27B corresponding to the second polarity detection means, and the other configuration is clear from the previous embodiment, and thus the description thereof is omitted.
[0056]
A fifteenth embodiment of the present invention corresponding to claims 17 and 20 is shown in FIG.
The difference from the thirteenth embodiment is the current polarity detection means 27C corresponding to the third polarity detection means, and the other configuration is clear from the previous embodiment, and thus the description thereof is omitted.
[0057]
【The invention's effect】
As described above, according to the present invention, it is possible to perform high-speed compensation by superimposing the compensation amount for compensating the element forward voltage drop amount on the error amount due to the dead time in the period of the carrier wave. The distortion of the output voltage waveform can be suppressed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a first embodiment of the present invention.
FIG. 2 is a block diagram showing a second embodiment of the present invention.
FIG. 3 is a block diagram showing a third embodiment of the present invention.
FIG. 4 is a block diagram showing a fourth embodiment of the present invention.
FIG. 5 is a block diagram showing a fifth embodiment of the present invention.
FIG. 6 is a block diagram showing a sixth embodiment of the present invention.
FIG. 7 is a block diagram showing a seventh embodiment of the present invention.
FIG. 8 is a block diagram showing an eighth embodiment of the present invention.
FIG. 9 is a block diagram showing a ninth embodiment of the present invention.
FIG. 10 is a block diagram showing a tenth embodiment of the present invention.
FIG. 11 is a block diagram showing an eleventh embodiment of the present invention.
FIG. 12 is a block diagram showing a twelfth embodiment of the present invention.
FIG. 13 is a block diagram showing a thirteenth embodiment of the present invention.
FIG. 14 is a block diagram showing a fourteenth embodiment of the present invention.
FIG. 15 is a block diagram showing a fifteenth embodiment of the present invention.
FIG. 16 is a block diagram showing a conventional technique.
FIG. 17 is a diagram for explaining an element forward voltage drop amount to be compensated in the present invention.
FIG. 18 is a diagram for explaining the operating principle of the current polarity detection means in the present invention.
FIG. 19 is a diagram for explaining the operating principle of the current polarity detection means in the present invention.
FIG. 20 is a diagram for explaining a method for resetting an up / down counter according to the present invention.
[Explanation of symbols]
1 DC power supply
2 PWM inverter
T1-T6 switching part
U, V, W AC output terminal
3 U-phase correction circuit
4 V-phase correction circuit
5 W phase correction circuit
6 Pulse difference detection circuit
7 Load type up / down counter
8 flip-flops
9 On-delay circuit
10 Gate drive circuit
11 Upper arm on detection circuit
12 Lower arm on detection circuit
13, 14, 16 Data selector
15 OFF / OFF section detection circuit
17 Oscillator
18 1/2 divider
19A, 19B Edge detection circuit
20 Upper arm reference FWD mode detector
21 Lower arm reference FWD mode detector
22 flip-flops
23 switch
24 multiplier
25 Adder
26 Inverter
27A, 27B, 27C Current polarity detection means
28 comparator
29, 30, 31 Current detector
32 Data latch
33 Correction calculation section
34, 35, 38 Compensation amount calculation means
36 Load signal generator
37 DC voltage detector
39 Arm-on voltage detector

Claims (20)

In order to compensate for the error voltage of the inverter output voltage caused by the dead time held between the PWM command pulse of the PWM inverter and the drive pulse of the semiconductor switching element of each phase arm, the semiconductor switching is performed from the edge change of the PWM command pulse. In the output voltage compensation method of the PWM inverter in which the integrated value of the pulse until the edge change of the ON detection pulse of the element is an error amount, and the PWM command pulse is corrected using the error amount,
The compensation amount based on the forward voltage drop amount of the semiconductor elements constituting the PWM inverter is calculated according to the phase current polarity of the PWM inverter, and this compensation amount is superimposed on the voltage signal corresponding to the error amount to correct the PWM command pulse. A method for compensating for an output voltage of a PWM inverter. In the PWM inverter output voltage compensation method according to claim 1,
A method of compensating for an output voltage of a PWM inverter, wherein the phase current polarity is detected from the positive / negative of a phase current detection value of the PWM inverter. In the PWM inverter output voltage compensation method according to claim 1,
A method for compensating an output voltage of a PWM inverter, wherein the phase current polarity is detected based on an on / off state of a semiconductor element of the phase held at a timing when the semiconductor switching element of the phase is turned on. In the PWM inverter output voltage compensation method according to claim 1,
An output voltage compensation method for a PWM inverter, wherein the phase current polarity is detected based on the magnitude of the error amount and the polarity of a PWM command pulse. In the PWM inverter output voltage compensation method according to claim 1,
The amount of compensation is calculated from the detected value of the phase current polarity, the set value of the forward voltage drop of the semiconductor element of the phase, and the set values of the on time and off time of the PWM command pulse within the carrier wave period. A PWM inverter output voltage compensation method characterized by the above. In the PWM inverter output voltage compensation method according to claim 5,
A method of compensating for an output voltage of a PWM inverter, wherein the phase current polarity is detected from the positive / negative of a phase current detection value of the PWM inverter. In the PWM inverter output voltage compensation method according to claim 5,
A method for compensating an output voltage of a PWM inverter, wherein the phase current polarity is detected based on an on / off state of a semiconductor element of the phase held at a timing when the semiconductor switching element of the phase is turned on. In the PWM inverter output voltage compensation method according to claim 5,
An output voltage compensation method for a PWM inverter, wherein the phase current polarity is detected based on the magnitude of the error amount and the polarity of a PWM command pulse. In the PWM inverter output voltage compensation method according to claim 1,
The compensation amount is calculated from the detected value of the phase current polarity, the set value of the forward voltage drop amount of the semiconductor element of the phase, and the detected values of the on time and off time of the PWM command pulse within the carrier wave period. A PWM inverter output voltage compensation method characterized by the above. In the PWM inverter output voltage compensation method according to claim 9,
A method of compensating for an output voltage of a PWM inverter, wherein the phase current polarity is detected from the positive / negative of a phase current detection value of the PWM inverter. In the PWM inverter output voltage compensation method according to claim 9,
A method for compensating an output voltage of a PWM inverter, wherein the phase current polarity is detected based on an on / off state of a semiconductor element of the phase held at a timing when the semiconductor switching element of the phase is turned on. In the PWM inverter output voltage compensation method according to claim 9,
An output voltage compensation method for a PWM inverter, wherein the phase current polarity is detected based on the magnitude of the error amount and the polarity of a PWM command pulse. In the PWM inverter output voltage compensation method according to claim 1,
The compensation amount is calculated from the detected value of the phase current polarity, the detected value of the forward voltage drop of the semiconductor element of the phase, and the set values of the on time and off time of the PWM command pulse within the carrier wave period. A PWM inverter output voltage compensation method characterized by the above. In the PWM inverter output voltage compensation method according to claim 13,
A method of compensating for an output voltage of a PWM inverter, wherein the phase current polarity is detected from the positive / negative of a phase current detection value of the PWM inverter. In the PWM inverter output voltage compensation method according to claim 13,
A method for compensating an output voltage of a PWM inverter, wherein the phase current polarity is detected based on an on / off state of a semiconductor element of the phase held at a timing when the semiconductor switching element of the phase is turned on. In the PWM inverter output voltage compensation method according to claim 13,
An output voltage compensation method for a PWM inverter, wherein the phase current polarity is detected based on the magnitude of the error amount and the polarity of a PWM command pulse. In the PWM inverter output voltage compensation method according to claim 1,
The compensation amount is calculated from a detected value of the phase current polarity, a detected value of the forward voltage drop of the semiconductor element of the phase, and a detected value of the on time and off time of the PWM command pulse in the carrier wave period. A PWM inverter output voltage compensation method characterized by the above. The output voltage compensation method of the PWM inverter according to claim 17,
A method of compensating for an output voltage of a PWM inverter, wherein the phase current polarity is detected from the positive / negative of a phase current detection value of the PWM inverter. The output voltage compensation method of the PWM inverter according to claim 17,
A method for compensating an output voltage of a PWM inverter, wherein the phase current polarity is detected based on an on / off state of a semiconductor element of the phase held at a timing when the semiconductor switching element of the phase is turned on. In the PWM inverter output voltage compensation method according to claim 17,
An output voltage compensation method for a PWM inverter, wherein the phase current polarity is detected based on the magnitude of the error amount and the polarity of a PWM command pulse.

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